1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
2 /* $FreeBSD: src/sys/dev/stge/if_stge.c,v 1.2 2006/08/12 01:21:36 yongari Exp $ */
3 /* $DragonFly: src/sys/dev/netif/stge/if_stge.c,v 1.3 2008/03/10 10:47:57 sephe Exp $ */
6 * Copyright (c) 2001 The NetBSD Foundation, Inc.
9 * This code is derived from software contributed to The NetBSD Foundation
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
42 * Device driver for the Sundance Tech. TC9021 10/100/1000
43 * Ethernet controller.
46 #include "opt_polling.h"
48 #include <sys/param.h>
50 #include <sys/endian.h>
51 #include <sys/kernel.h>
52 #include <sys/malloc.h>
54 #include <sys/module.h>
56 #include <sys/serialize.h>
57 #include <sys/socket.h>
58 #include <sys/sockio.h>
59 #include <sys/sysctl.h>
62 #include <net/ethernet.h>
64 #include <net/if_arp.h>
65 #include <net/if_dl.h>
66 #include <net/if_media.h>
67 #include <net/if_types.h>
68 #include <net/ifq_var.h>
69 #include <net/vlan/if_vlan_var.h>
71 #include <dev/netif/mii_layer/mii.h>
72 #include <dev/netif/mii_layer/miivar.h>
74 #include <bus/pci/pcireg.h>
75 #include <bus/pci/pcivar.h>
77 #include "if_stgereg.h"
78 #include "if_stgevar.h"
80 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
82 /* "device miibus" required. See GENERIC if you get errors here. */
83 #include "miibus_if.h"
86 * Devices supported by this driver.
88 static struct stge_product {
89 uint16_t stge_vendorid;
90 uint16_t stge_deviceid;
91 const char *stge_name;
93 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
94 "Sundance ST-1023 Gigabit Ethernet" },
96 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
97 "Sundance ST-2021 Gigabit Ethernet" },
99 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
100 "Tamarack TC9021 Gigabit Ethernet" },
102 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
103 "Tamarack TC9021 Gigabit Ethernet" },
106 * The Sundance sample boards use the Sundance vendor ID,
107 * but the Tamarack product ID.
109 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
110 "Sundance TC9021 Gigabit Ethernet" },
112 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
113 "Sundance TC9021 Gigabit Ethernet" },
115 { VENDOR_DLINK, DEVICEID_DLINK_DL2000,
116 "D-Link DL-2000 Gigabit Ethernet" },
118 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
119 "Antares Gigabit Ethernet" },
124 static int stge_probe(device_t);
125 static int stge_attach(device_t);
126 static int stge_detach(device_t);
127 static void stge_shutdown(device_t);
128 static int stge_suspend(device_t);
129 static int stge_resume(device_t);
131 static int stge_encap(struct stge_softc *, struct mbuf **);
132 static void stge_start(struct ifnet *);
133 static void stge_watchdog(struct ifnet *);
134 static int stge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
135 static void stge_init(void *);
136 static void stge_vlan_setup(struct stge_softc *);
137 static void stge_stop(struct stge_softc *);
138 static void stge_start_tx(struct stge_softc *);
139 static void stge_start_rx(struct stge_softc *);
140 static void stge_stop_tx(struct stge_softc *);
141 static void stge_stop_rx(struct stge_softc *);
143 static void stge_reset(struct stge_softc *, uint32_t);
144 static int stge_eeprom_wait(struct stge_softc *);
145 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
146 static void stge_tick(void *);
147 static void stge_stats_update(struct stge_softc *);
148 static void stge_set_filter(struct stge_softc *);
149 static void stge_set_multi(struct stge_softc *);
151 static void stge_link(struct stge_softc *);
152 static void stge_intr(void *);
153 static __inline int stge_tx_error(struct stge_softc *);
154 static void stge_txeof(struct stge_softc *);
155 static void stge_rxeof(struct stge_softc *, int);
156 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
157 static int stge_newbuf(struct stge_softc *, int, int);
159 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
162 static void stge_mii_sync(struct stge_softc *);
163 static void stge_mii_send(struct stge_softc *, uint32_t, int);
164 static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *);
165 static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *);
166 static int stge_miibus_readreg(device_t, int, int);
167 static int stge_miibus_writereg(device_t, int, int, int);
168 static void stge_miibus_statchg(device_t);
169 static int stge_mediachange(struct ifnet *);
170 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
172 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
173 static void stge_mbuf_dmamap_cb(void *, bus_dma_segment_t *, int,
175 static int stge_dma_alloc(struct stge_softc *);
176 static void stge_dma_free(struct stge_softc *);
177 static void stge_dma_wait(struct stge_softc *);
178 static void stge_init_tx_ring(struct stge_softc *);
179 static int stge_init_rx_ring(struct stge_softc *);
180 #ifdef DEVICE_POLLING
181 static void stge_poll(struct ifnet *, enum poll_cmd, int);
184 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
185 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
186 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
188 static device_method_t stge_methods[] = {
189 /* Device interface */
190 DEVMETHOD(device_probe, stge_probe),
191 DEVMETHOD(device_attach, stge_attach),
192 DEVMETHOD(device_detach, stge_detach),
193 DEVMETHOD(device_shutdown, stge_shutdown),
194 DEVMETHOD(device_suspend, stge_suspend),
195 DEVMETHOD(device_resume, stge_resume),
198 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
199 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
200 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
206 static driver_t stge_driver = {
209 sizeof(struct stge_softc)
212 static devclass_t stge_devclass;
214 DECLARE_DUMMY_MODULE(if_stge);
215 MODULE_DEPEND(if_stge, miibus, 1, 1, 1);
216 DRIVER_MODULE(if_stge, pci, stge_driver, stge_devclass, 0, 0);
217 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
220 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
222 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
225 * Sync the PHYs by setting data bit and strobing the clock 32 times.
228 stge_mii_sync(struct stge_softc *sc)
232 MII_SET(PC_MgmtDir | PC_MgmtData);
234 for (i = 0; i < 32; i++) {
243 * Clock a series of bits through the MII.
246 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt)
252 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
254 MII_SET(PC_MgmtData);
256 MII_CLR(PC_MgmtData);
265 * Read an PHY register through the MII.
268 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame)
273 * Set up frame for RX.
275 frame->mii_stdelim = STGE_MII_STARTDELIM;
276 frame->mii_opcode = STGE_MII_READOP;
277 frame->mii_turnaround = 0;
280 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl);
289 * Send command/address info.
291 stge_mii_send(sc, frame->mii_stdelim, 2);
292 stge_mii_send(sc, frame->mii_opcode, 2);
293 stge_mii_send(sc, frame->mii_phyaddr, 5);
294 stge_mii_send(sc, frame->mii_regaddr, 5);
300 MII_CLR((PC_MgmtClk | PC_MgmtData));
308 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData;
313 * Now try reading data bits. If the ack failed, we still
314 * need to clock through 16 cycles to keep the PHY(s) in sync.
317 for(i = 0; i < 16; i++) {
326 for (i = 0x8000; i; i >>= 1) {
330 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData)
331 frame->mii_data |= i;
350 * Write to a PHY register through the MII.
353 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame)
357 * Set up frame for TX.
359 frame->mii_stdelim = STGE_MII_STARTDELIM;
360 frame->mii_opcode = STGE_MII_WRITEOP;
361 frame->mii_turnaround = STGE_MII_TURNAROUND;
364 * Turn on data output.
370 stge_mii_send(sc, frame->mii_stdelim, 2);
371 stge_mii_send(sc, frame->mii_opcode, 2);
372 stge_mii_send(sc, frame->mii_phyaddr, 5);
373 stge_mii_send(sc, frame->mii_regaddr, 5);
374 stge_mii_send(sc, frame->mii_turnaround, 2);
375 stge_mii_send(sc, frame->mii_data, 16);
392 * sc_miibus_readreg: [mii interface function]
394 * Read a PHY register on the MII of the TC9021.
397 stge_miibus_readreg(device_t dev, int phy, int reg)
399 struct stge_softc *sc;
400 struct stge_mii_frame frame;
403 sc = device_get_softc(dev);
405 if (reg == STGE_PhyCtrl) {
406 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
407 error = CSR_READ_1(sc, STGE_PhyCtrl);
410 bzero(&frame, sizeof(frame));
411 frame.mii_phyaddr = phy;
412 frame.mii_regaddr = reg;
414 error = stge_mii_readreg(sc, &frame);
417 /* Don't show errors for PHY probe request */
419 device_printf(sc->sc_dev, "phy read fail\n");
422 return (frame.mii_data);
426 * stge_miibus_writereg: [mii interface function]
428 * Write a PHY register on the MII of the TC9021.
431 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
433 struct stge_softc *sc;
434 struct stge_mii_frame frame;
437 sc = device_get_softc(dev);
439 bzero(&frame, sizeof(frame));
440 frame.mii_phyaddr = phy;
441 frame.mii_regaddr = reg;
442 frame.mii_data = val;
444 error = stge_mii_writereg(sc, &frame);
447 device_printf(sc->sc_dev, "phy write fail\n");
452 * stge_miibus_statchg: [mii interface function]
454 * Callback from MII layer when media changes.
457 stge_miibus_statchg(device_t dev)
459 struct stge_softc *sc;
460 struct mii_data *mii;
462 sc = device_get_softc(dev);
463 mii = device_get_softc(sc->sc_miibus);
465 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)
469 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
470 sc->sc_MACCtrl |= MC_DuplexSelect;
471 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0)
472 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
473 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0)
474 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
480 * stge_mediastatus: [ifmedia interface function]
482 * Get the current interface media status.
485 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
487 struct stge_softc *sc;
488 struct mii_data *mii;
491 mii = device_get_softc(sc->sc_miibus);
494 ifmr->ifm_status = mii->mii_media_status;
495 ifmr->ifm_active = mii->mii_media_active;
499 * stge_mediachange: [ifmedia interface function]
501 * Set hardware to newly-selected media.
504 stge_mediachange(struct ifnet *ifp)
506 struct stge_softc *sc;
507 struct mii_data *mii;
510 mii = device_get_softc(sc->sc_miibus);
517 stge_eeprom_wait(struct stge_softc *sc)
521 for (i = 0; i < STGE_TIMEOUT; i++) {
523 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
532 * Read data from the serial EEPROM.
535 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
538 if (stge_eeprom_wait(sc))
539 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
541 CSR_WRITE_2(sc, STGE_EepromCtrl,
542 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
543 if (stge_eeprom_wait(sc))
544 device_printf(sc->sc_dev, "EEPROM read timed out\n");
545 *data = CSR_READ_2(sc, STGE_EepromData);
550 stge_probe(device_t dev)
552 struct stge_product *sp;
553 uint16_t vendor, devid;
555 vendor = pci_get_vendor(dev);
556 devid = pci_get_device(dev);
558 for (sp = stge_products; sp->stge_name != NULL; sp++) {
559 if (vendor == sp->stge_vendorid &&
560 devid == sp->stge_deviceid) {
561 device_set_desc(dev, sp->stge_name);
570 stge_attach(device_t dev)
572 struct stge_softc *sc;
574 uint8_t enaddr[ETHER_ADDR_LEN];
580 sc = device_get_softc(dev);
582 ifp = &sc->arpcom.ac_if;
584 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
586 callout_init(&sc->sc_tick_ch);
590 * Handle power management nonsense.
592 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
593 uint32_t iobase, membase, irq;
595 /* Save important PCI config data. */
596 iobase = pci_read_config(dev, STGE_PCIR_LOIO, 4);
597 membase = pci_read_config(dev, STGE_PCIR_LOMEM, 4);
598 irq = pci_read_config(dev, PCIR_INTLINE, 4);
600 /* Reset the power state. */
601 device_printf(dev, "chip is in D%d power mode "
602 "-- setting to D0\n", pci_get_powerstate(dev));
604 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
606 /* Restore PCI config data. */
607 pci_write_config(dev, STGE_PCIR_LOIO, iobase, 4);
608 pci_write_config(dev, STGE_PCIR_LOMEM, membase, 4);
609 pci_write_config(dev, PCIR_INTLINE, irq, 4);
616 pci_enable_busmaster(dev);
617 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
618 val = pci_read_config(dev, STGE_PCIR_LOMEM, 4);
620 if ((val & 0x01) != 0) {
621 sc->sc_res_rid = STGE_PCIR_LOMEM;
622 sc->sc_res_type = SYS_RES_MEMORY;
624 sc->sc_res_rid = STGE_PCIR_LOIO;
625 sc->sc_res_type = SYS_RES_IOPORT;
627 val = pci_read_config(dev, sc->sc_res_rid, 4);
628 if ((val & 0x01) == 0) {
629 device_printf(dev, "couldn't locate IO BAR\n");
634 sc->sc_res = bus_alloc_resource_any(dev, sc->sc_res_type,
635 &sc->sc_res_rid, RF_ACTIVE);
636 if (sc->sc_res == NULL) {
637 device_printf(dev, "couldn't allocate resource\n");
640 sc->sc_btag = rman_get_bustag(sc->sc_res);
641 sc->sc_bhandle = rman_get_bushandle(sc->sc_res);
643 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
645 RF_ACTIVE | RF_SHAREABLE);
646 if (sc->sc_irq == NULL) {
647 device_printf(dev, "couldn't allocate IRQ\n");
652 sc->sc_rev = pci_get_revid(dev);
654 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
655 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
657 sysctl_ctx_init(&sc->sc_sysctl_ctx);
658 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
659 SYSCTL_STATIC_CHILDREN(_hw),
661 device_get_nameunit(dev),
663 if (sc->sc_sysctl_tree == NULL) {
664 device_printf(dev, "can't add sysctl node\n");
669 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
670 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
671 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
672 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
674 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
675 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
676 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
677 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
679 if ((error = stge_dma_alloc(sc) != 0))
683 * Determine if we're copper or fiber. It affects how we
686 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
691 /* Load LED configuration from EEPROM. */
692 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
695 * Reset the chip to a known state.
697 stge_reset(sc, STGE_RESET_FULL);
700 * Reading the station address from the EEPROM doesn't seem
701 * to work, at least on my sample boards. Instead, since
702 * the reset sequence does AutoInit, read it from the station
703 * address registers. For Sundance 1023 you can only read it
706 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
709 v = CSR_READ_2(sc, STGE_StationAddress0);
710 enaddr[0] = v & 0xff;
712 v = CSR_READ_2(sc, STGE_StationAddress1);
713 enaddr[2] = v & 0xff;
715 v = CSR_READ_2(sc, STGE_StationAddress2);
716 enaddr[4] = v & 0xff;
720 uint16_t myaddr[ETHER_ADDR_LEN / 2];
721 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
722 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
724 myaddr[i] = le16toh(myaddr[i]);
726 bcopy(myaddr, enaddr, sizeof(enaddr));
731 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
732 ifp->if_ioctl = stge_ioctl;
733 ifp->if_start = stge_start;
734 ifp->if_watchdog = stge_watchdog;
735 ifp->if_init = stge_init;
736 #ifdef DEVICE_POLLING
737 ifp->if_poll = stge_poll;
739 ifp->if_mtu = ETHERMTU;
740 ifq_set_maxlen(&ifp->if_snd, STGE_TX_RING_CNT - 1);
741 ifq_set_ready(&ifp->if_snd);
742 /* Revision B3 and earlier chips have checksum bug. */
743 if (sc->sc_rev >= 0x0c) {
744 ifp->if_hwassist = STGE_CSUM_FEATURES;
745 ifp->if_capabilities = IFCAP_HWCSUM;
747 ifp->if_hwassist = 0;
748 ifp->if_capabilities = 0;
750 ifp->if_capenable = ifp->if_capabilities;
753 * Read some important bits from the PhyCtrl register.
755 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
756 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
758 /* Set up MII bus. */
759 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange,
760 stge_mediastatus)) != 0) {
761 device_printf(sc->sc_dev, "no PHY found!\n");
765 ether_ifattach(ifp, enaddr, NULL);
767 /* VLAN capability setup */
768 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
770 if (sc->sc_rev >= 0x0c)
771 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
773 ifp->if_capenable = ifp->if_capabilities;
776 * Tell the upper layer(s) we support long frames.
777 * Must appear after the call to ether_ifattach() because
778 * ether_ifattach() sets ifi_hdrlen to the default value.
780 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
783 * The manual recommends disabling early transmit, so we
784 * do. It's disabled anyway, if using IP checksumming,
785 * since the entire packet must be in the FIFO in order
786 * for the chip to perform the checksum.
788 sc->sc_txthresh = 0x0fff;
791 * Disable MWI if the PCI layer tells us to.
794 if ((cmd & PCIM_CMD_MWRICEN) == 0)
795 sc->sc_DMACtrl |= DMAC_MWIDisable;
800 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, stge_intr, sc,
801 &sc->sc_ih, ifp->if_serializer);
804 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
816 stge_detach(device_t dev)
818 struct stge_softc *sc = device_get_softc(dev);
819 struct ifnet *ifp = &sc->arpcom.ac_if;
821 if (device_is_attached(dev)) {
822 lwkt_serialize_enter(ifp->if_serializer);
826 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
827 lwkt_serialize_exit(ifp->if_serializer);
832 if (sc->sc_sysctl_tree != NULL)
833 sysctl_ctx_free(&sc->sc_sysctl_ctx);
835 if (sc->sc_miibus != NULL)
836 device_delete_child(dev, sc->sc_miibus);
837 bus_generic_detach(dev);
841 if (sc->sc_irq != NULL) {
842 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
845 if (sc->sc_res != NULL) {
846 bus_release_resource(dev, sc->sc_res_type, sc->sc_res_rid,
853 struct stge_dmamap_arg {
854 bus_addr_t stge_busaddr;
858 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
860 struct stge_dmamap_arg *ctx;
865 KASSERT(nseg == 1, ("too many segments %d\n", nseg));
867 ctx = (struct stge_dmamap_arg *)arg;
868 ctx->stge_busaddr = segs[0].ds_addr;
871 struct stge_mbuf_dmamap_arg {
873 bus_dma_segment_t *segs;
877 stge_mbuf_dmamap_cb(void *xarg, bus_dma_segment_t *segs, int nsegs,
878 bus_size_t mapsz __unused, int error)
880 struct stge_mbuf_dmamap_arg *arg = xarg;
888 KASSERT(nsegs <= arg->nsegs,
889 ("too many segments(%d), should be <= %d\n",
893 for (i = 0; i < nsegs; ++i)
894 arg->segs[i] = segs[i];
898 stge_dma_alloc(struct stge_softc *sc)
900 struct stge_dmamap_arg ctx;
901 struct stge_txdesc *txd;
902 struct stge_rxdesc *rxd;
905 /* create parent tag. */
906 error = bus_dma_tag_create(NULL, /* parent */
907 1, 0, /* algnmnt, boundary */
908 STGE_DMA_MAXADDR, /* lowaddr */
909 BUS_SPACE_MAXADDR, /* highaddr */
910 NULL, NULL, /* filter, filterarg */
911 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
913 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
915 &sc->sc_cdata.stge_parent_tag);
917 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
920 /* create tag for Tx ring. */
921 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
922 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
923 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
924 BUS_SPACE_MAXADDR, /* highaddr */
925 NULL, NULL, /* filter, filterarg */
926 STGE_TX_RING_SZ, /* maxsize */
928 STGE_TX_RING_SZ, /* maxsegsize */
930 &sc->sc_cdata.stge_tx_ring_tag);
932 device_printf(sc->sc_dev,
933 "failed to allocate Tx ring DMA tag\n");
937 /* create tag for Rx ring. */
938 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
939 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
940 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
941 BUS_SPACE_MAXADDR, /* highaddr */
942 NULL, NULL, /* filter, filterarg */
943 STGE_RX_RING_SZ, /* maxsize */
945 STGE_RX_RING_SZ, /* maxsegsize */
947 &sc->sc_cdata.stge_rx_ring_tag);
949 device_printf(sc->sc_dev,
950 "failed to allocate Rx ring DMA tag\n");
954 /* create tag for Tx buffers. */
955 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
956 1, 0, /* algnmnt, boundary */
957 BUS_SPACE_MAXADDR, /* lowaddr */
958 BUS_SPACE_MAXADDR, /* highaddr */
959 NULL, NULL, /* filter, filterarg */
960 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
961 STGE_MAXTXSEGS, /* nsegments */
962 MCLBYTES, /* maxsegsize */
964 &sc->sc_cdata.stge_tx_tag);
966 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
970 /* create tag for Rx buffers. */
971 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
972 1, 0, /* algnmnt, boundary */
973 BUS_SPACE_MAXADDR, /* lowaddr */
974 BUS_SPACE_MAXADDR, /* highaddr */
975 NULL, NULL, /* filter, filterarg */
976 MCLBYTES, /* maxsize */
978 MCLBYTES, /* maxsegsize */
980 &sc->sc_cdata.stge_rx_tag);
982 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
986 /* allocate DMA'able memory and load the DMA map for Tx ring. */
987 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
988 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
989 &sc->sc_cdata.stge_tx_ring_map);
991 device_printf(sc->sc_dev,
992 "failed to allocate DMA'able memory for Tx ring\n");
996 ctx.stge_busaddr = 0;
997 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
998 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
999 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1000 if (error != 0 || ctx.stge_busaddr == 0) {
1001 device_printf(sc->sc_dev,
1002 "failed to load DMA'able memory for Tx ring\n");
1005 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
1007 /* allocate DMA'able memory and load the DMA map for Rx ring. */
1008 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
1009 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1010 &sc->sc_cdata.stge_rx_ring_map);
1012 device_printf(sc->sc_dev,
1013 "failed to allocate DMA'able memory for Rx ring\n");
1017 ctx.stge_busaddr = 0;
1018 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
1019 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
1020 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1021 if (error != 0 || ctx.stge_busaddr == 0) {
1022 device_printf(sc->sc_dev,
1023 "failed to load DMA'able memory for Rx ring\n");
1026 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
1028 /* create DMA maps for Tx buffers. */
1029 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1030 txd = &sc->sc_cdata.stge_txdesc[i];
1033 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
1036 device_printf(sc->sc_dev,
1037 "failed to create Tx dmamap\n");
1041 /* create DMA maps for Rx buffers. */
1042 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
1043 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
1044 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
1047 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1048 rxd = &sc->sc_cdata.stge_rxdesc[i];
1051 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
1054 device_printf(sc->sc_dev,
1055 "failed to create Rx dmamap\n");
1065 stge_dma_free(struct stge_softc *sc)
1067 struct stge_txdesc *txd;
1068 struct stge_rxdesc *rxd;
1072 if (sc->sc_cdata.stge_tx_ring_tag) {
1073 if (sc->sc_cdata.stge_tx_ring_map)
1074 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
1075 sc->sc_cdata.stge_tx_ring_map);
1076 if (sc->sc_cdata.stge_tx_ring_map &&
1077 sc->sc_rdata.stge_tx_ring)
1078 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
1079 sc->sc_rdata.stge_tx_ring,
1080 sc->sc_cdata.stge_tx_ring_map);
1081 sc->sc_rdata.stge_tx_ring = NULL;
1082 sc->sc_cdata.stge_tx_ring_map = 0;
1083 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
1084 sc->sc_cdata.stge_tx_ring_tag = NULL;
1087 if (sc->sc_cdata.stge_rx_ring_tag) {
1088 if (sc->sc_cdata.stge_rx_ring_map)
1089 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
1090 sc->sc_cdata.stge_rx_ring_map);
1091 if (sc->sc_cdata.stge_rx_ring_map &&
1092 sc->sc_rdata.stge_rx_ring)
1093 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
1094 sc->sc_rdata.stge_rx_ring,
1095 sc->sc_cdata.stge_rx_ring_map);
1096 sc->sc_rdata.stge_rx_ring = NULL;
1097 sc->sc_cdata.stge_rx_ring_map = 0;
1098 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
1099 sc->sc_cdata.stge_rx_ring_tag = NULL;
1102 if (sc->sc_cdata.stge_tx_tag) {
1103 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1104 txd = &sc->sc_cdata.stge_txdesc[i];
1105 if (txd->tx_dmamap) {
1106 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
1111 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
1112 sc->sc_cdata.stge_tx_tag = NULL;
1115 if (sc->sc_cdata.stge_rx_tag) {
1116 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1117 rxd = &sc->sc_cdata.stge_rxdesc[i];
1118 if (rxd->rx_dmamap) {
1119 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1124 if (sc->sc_cdata.stge_rx_sparemap) {
1125 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1126 sc->sc_cdata.stge_rx_sparemap);
1127 sc->sc_cdata.stge_rx_sparemap = 0;
1129 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
1130 sc->sc_cdata.stge_rx_tag = NULL;
1133 if (sc->sc_cdata.stge_parent_tag) {
1134 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
1135 sc->sc_cdata.stge_parent_tag = NULL;
1142 * Make sure the interface is stopped at reboot time.
1145 stge_shutdown(device_t dev)
1147 struct stge_softc *sc = device_get_softc(dev);
1148 struct ifnet *ifp = &sc->arpcom.ac_if;
1150 lwkt_serialize_enter(ifp->if_serializer);
1152 lwkt_serialize_exit(ifp->if_serializer);
1156 stge_suspend(device_t dev)
1158 struct stge_softc *sc = device_get_softc(dev);
1159 struct ifnet *ifp = &sc->arpcom.ac_if;
1161 lwkt_serialize_enter(ifp->if_serializer);
1163 sc->sc_suspended = 1;
1164 lwkt_serialize_exit(ifp->if_serializer);
1170 stge_resume(device_t dev)
1172 struct stge_softc *sc = device_get_softc(dev);
1173 struct ifnet *ifp = &sc->arpcom.ac_if;
1175 lwkt_serialize_enter(ifp->if_serializer);
1176 if (ifp->if_flags & IFF_UP)
1178 sc->sc_suspended = 0;
1179 lwkt_serialize_exit(ifp->if_serializer);
1185 stge_dma_wait(struct stge_softc *sc)
1189 for (i = 0; i < STGE_TIMEOUT; i++) {
1191 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1195 if (i == STGE_TIMEOUT)
1196 device_printf(sc->sc_dev, "DMA wait timed out\n");
1200 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1202 struct stge_txdesc *txd;
1203 struct stge_tfd *tfd;
1205 struct stge_mbuf_dmamap_arg arg;
1206 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1208 uint64_t csum_flags, tfc;
1210 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1213 arg.nsegs = STGE_MAXTXSEGS;
1215 error = bus_dmamap_load_mbuf(sc->sc_cdata.stge_tx_tag,
1216 txd->tx_dmamap, *m_head,
1217 stge_mbuf_dmamap_cb, &arg,
1219 if (error == EFBIG) {
1220 m = m_defrag(*m_head, MB_DONTWAIT);
1227 error = bus_dmamap_load_mbuf(sc->sc_cdata.stge_tx_tag,
1228 txd->tx_dmamap, *m_head,
1229 stge_mbuf_dmamap_cb, &arg,
1236 } else if (error != 0)
1238 if (arg.nsegs == 0) {
1246 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1247 if (m->m_pkthdr.csum_flags & CSUM_IP)
1248 csum_flags |= TFD_IPChecksumEnable;
1249 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1250 csum_flags |= TFD_TCPChecksumEnable;
1251 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1252 csum_flags |= TFD_UDPChecksumEnable;
1255 si = sc->sc_cdata.stge_tx_prod;
1256 tfd = &sc->sc_rdata.stge_tx_ring[si];
1257 for (i = 0; i < arg.nsegs; i++) {
1258 tfd->tfd_frags[i].frag_word0 =
1259 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1260 FRAG_LEN(txsegs[i].ds_len));
1262 sc->sc_cdata.stge_tx_cnt++;
1264 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1265 TFD_FragCount(arg.nsegs) | csum_flags;
1266 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1267 tfc |= TFD_TxDMAIndicate;
1269 /* Update producer index. */
1270 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1272 /* Check if we have a VLAN tag to insert. */
1273 if (m->m_flags & M_VLANTAG)
1274 tfc |= TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vlantag);
1275 tfd->tfd_control = htole64(tfc);
1277 /* Update Tx Queue. */
1278 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1279 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1282 /* Sync descriptors. */
1283 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1284 BUS_DMASYNC_PREWRITE);
1285 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1286 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1292 * stge_start: [ifnet interface function]
1294 * Start packet transmission on the interface.
1297 stge_start(struct ifnet *ifp)
1299 struct stge_softc *sc;
1300 struct mbuf *m_head;
1305 ASSERT_SERIALIZED(ifp->if_serializer);
1307 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) !=
1311 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) {
1312 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1313 ifp->if_flags |= IFF_OACTIVE;
1317 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1321 * Pack the data into the transmit ring. If we
1322 * don't have room, set the OACTIVE flag and wait
1323 * for the NIC to drain the ring.
1325 if (stge_encap(sc, &m_head)) {
1328 ifp->if_flags |= IFF_OACTIVE;
1334 * If there's a BPF listener, bounce a copy of this frame
1337 BPF_MTAP(ifp, m_head);
1342 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1344 /* Set a timeout in case the chip goes out to lunch. */
1350 * stge_watchdog: [ifnet interface function]
1352 * Watchdog timer handler.
1355 stge_watchdog(struct ifnet *ifp)
1357 ASSERT_SERIALIZED(ifp->if_serializer);
1359 if_printf(ifp, "device timeout\n");
1361 stge_init(ifp->if_softc);
1365 * stge_ioctl: [ifnet interface function]
1367 * Handle control requests from the operator.
1370 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1372 struct stge_softc *sc;
1374 struct mii_data *mii;
1377 ASSERT_SERIALIZED(ifp->if_serializer);
1380 ifr = (struct ifreq *)data;
1384 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1386 else if (ifp->if_mtu != ifr->ifr_mtu) {
1387 ifp->if_mtu = ifr->ifr_mtu;
1392 if ((ifp->if_flags & IFF_UP) != 0) {
1393 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1394 if (((ifp->if_flags ^ sc->sc_if_flags)
1395 & IFF_PROMISC) != 0)
1396 stge_set_filter(sc);
1398 if (sc->sc_detach == 0)
1402 if ((ifp->if_flags & IFF_RUNNING) != 0)
1405 sc->sc_if_flags = ifp->if_flags;
1409 if ((ifp->if_flags & IFF_RUNNING) != 0)
1414 mii = device_get_softc(sc->sc_miibus);
1415 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1418 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1419 if ((mask & IFCAP_HWCSUM) != 0) {
1420 ifp->if_capenable ^= IFCAP_HWCSUM;
1421 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1422 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1423 ifp->if_hwassist = STGE_CSUM_FEATURES;
1425 ifp->if_hwassist = 0;
1427 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1428 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1429 if (ifp->if_flags & IFF_RUNNING)
1430 stge_vlan_setup(sc);
1433 VLAN_CAPABILITIES(ifp);
1437 error = ether_ioctl(ifp, cmd, data);
1445 stge_link(struct stge_softc *sc)
1451 * Update STGE_MACCtrl register depending on link status.
1452 * (duplex, flow control etc)
1454 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1455 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1456 v |= sc->sc_MACCtrl;
1457 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1458 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1459 /* Duplex setting changed, reset Tx/Rx functions. */
1460 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1461 ac |= AC_TxReset | AC_RxReset;
1462 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1463 for (i = 0; i < STGE_TIMEOUT; i++) {
1465 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1468 if (i == STGE_TIMEOUT)
1469 device_printf(sc->sc_dev, "reset failed to complete\n");
1474 stge_tx_error(struct stge_softc *sc)
1480 txstat = CSR_READ_4(sc, STGE_TxStatus);
1481 if ((txstat & TS_TxComplete) == 0)
1484 if ((txstat & TS_TxUnderrun) != 0) {
1487 * There should be a more better way to recover
1488 * from Tx underrun instead of a full reset.
1490 if (sc->sc_nerr++ < STGE_MAXERR)
1491 device_printf(sc->sc_dev, "Tx underrun, "
1493 if (sc->sc_nerr == STGE_MAXERR)
1494 device_printf(sc->sc_dev, "too many errors; "
1495 "not reporting any more\n");
1499 /* Maximum/Late collisions, Re-enable Tx MAC. */
1500 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1501 CSR_WRITE_4(sc, STGE_MACCtrl,
1502 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1512 * Interrupt service routine.
1515 stge_intr(void *arg)
1517 struct stge_softc *sc = arg;
1518 struct ifnet *ifp = &sc->arpcom.ac_if;
1522 ASSERT_SERIALIZED(ifp->if_serializer);
1524 status = CSR_READ_2(sc, STGE_IntStatus);
1525 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1528 /* Disable interrupts. */
1529 for (reinit = 0;;) {
1530 status = CSR_READ_2(sc, STGE_IntStatusAck);
1531 status &= sc->sc_IntEnable;
1534 /* Host interface errors. */
1535 if ((status & IS_HostError) != 0) {
1536 device_printf(sc->sc_dev,
1537 "Host interface error, resetting...\n");
1542 /* Receive interrupts. */
1543 if ((status & IS_RxDMAComplete) != 0) {
1545 if ((status & IS_RFDListEnd) != 0)
1546 CSR_WRITE_4(sc, STGE_DMACtrl,
1550 /* Transmit interrupts. */
1551 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1554 /* Transmission errors.*/
1555 if ((status & IS_TxComplete) != 0) {
1556 if ((reinit = stge_tx_error(sc)) != 0)
1565 /* Re-enable interrupts. */
1566 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1568 /* Try to get more packets going. */
1569 if (!ifq_is_empty(&ifp->if_snd))
1576 * Helper; handle transmit interrupts.
1579 stge_txeof(struct stge_softc *sc)
1581 struct ifnet *ifp = &sc->arpcom.ac_if;
1582 struct stge_txdesc *txd;
1586 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1589 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1590 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1593 * Go through our Tx list and free mbufs for those
1594 * frames which have been transmitted.
1596 for (cons = sc->sc_cdata.stge_tx_cons;;
1597 cons = (cons + 1) % STGE_TX_RING_CNT) {
1598 if (sc->sc_cdata.stge_tx_cnt <= 0)
1600 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1601 if ((control & TFD_TFDDone) == 0)
1603 sc->sc_cdata.stge_tx_cnt--;
1604 ifp->if_flags &= ~IFF_OACTIVE;
1606 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1607 BUS_DMASYNC_POSTWRITE);
1608 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1610 /* Output counter is updated with statistics register */
1613 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1614 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1615 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1617 sc->sc_cdata.stge_tx_cons = cons;
1618 if (sc->sc_cdata.stge_tx_cnt == 0)
1621 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1622 sc->sc_cdata.stge_tx_ring_map,
1623 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1626 static __inline void
1627 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1629 struct stge_rfd *rfd;
1631 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1632 rfd->rfd_status = 0;
1637 * It seems that TC9021's DMA engine has alignment restrictions in
1638 * DMA scatter operations. The first DMA segment has no address
1639 * alignment restrictins but the rest should be aligned on 4(?) bytes
1640 * boundary. Otherwise it would corrupt random memory. Since we don't
1641 * know which one is used for the first segment in advance we simply
1642 * don't align at all.
1643 * To avoid copying over an entire frame to align, we allocate a new
1644 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1645 * prepended into the existing mbuf chain.
1647 static __inline struct mbuf *
1648 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1653 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1654 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1655 m->m_data += ETHER_HDR_LEN;
1658 MGETHDR(n, MB_DONTWAIT, MT_DATA);
1660 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1661 m->m_data += ETHER_HDR_LEN;
1662 m->m_len -= ETHER_HDR_LEN;
1663 n->m_len = ETHER_HDR_LEN;
1664 M_MOVE_PKTHDR(n, m);
1677 * Helper; handle receive interrupts.
1680 stge_rxeof(struct stge_softc *sc, int count)
1682 struct ifnet *ifp = &sc->arpcom.ac_if;
1683 struct stge_rxdesc *rxd;
1684 struct mbuf *mp, *m;
1689 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1690 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1693 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1694 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1695 #ifdef DEVICE_POLLING
1696 if (count >= 0 && count-- == 0)
1700 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1701 status = RFD_RxStatus(status64);
1702 if ((status & RFD_RFDDone) == 0)
1706 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1710 * If the packet had an error, drop it. Note we count
1711 * the error later in the periodic stats update.
1713 if ((status & RFD_FrameEnd) != 0 && (status &
1714 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1715 RFD_RxAlignmentError | RFD_RxFCSError |
1716 RFD_RxLengthError)) != 0) {
1717 stge_discard_rxbuf(sc, cons);
1718 if (sc->sc_cdata.stge_rxhead != NULL) {
1719 m_freem(sc->sc_cdata.stge_rxhead);
1720 STGE_RXCHAIN_RESET(sc);
1725 * Add a new receive buffer to the ring.
1727 if (stge_newbuf(sc, cons, 0) != 0) {
1729 stge_discard_rxbuf(sc, cons);
1730 if (sc->sc_cdata.stge_rxhead != NULL) {
1731 m_freem(sc->sc_cdata.stge_rxhead);
1732 STGE_RXCHAIN_RESET(sc);
1737 if ((status & RFD_FrameEnd) != 0)
1738 mp->m_len = RFD_RxDMAFrameLen(status) -
1739 sc->sc_cdata.stge_rxlen;
1740 sc->sc_cdata.stge_rxlen += mp->m_len;
1743 if (sc->sc_cdata.stge_rxhead == NULL) {
1744 sc->sc_cdata.stge_rxhead = mp;
1745 sc->sc_cdata.stge_rxtail = mp;
1747 mp->m_flags &= ~M_PKTHDR;
1748 sc->sc_cdata.stge_rxtail->m_next = mp;
1749 sc->sc_cdata.stge_rxtail = mp;
1752 if ((status & RFD_FrameEnd) != 0) {
1753 m = sc->sc_cdata.stge_rxhead;
1754 m->m_pkthdr.rcvif = ifp;
1755 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1757 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1759 STGE_RXCHAIN_RESET(sc);
1763 * Set the incoming checksum information for
1766 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1767 if ((status & RFD_IPDetected) != 0) {
1768 m->m_pkthdr.csum_flags |=
1770 if ((status & RFD_IPError) == 0)
1771 m->m_pkthdr.csum_flags |=
1774 if (((status & RFD_TCPDetected) != 0 &&
1775 (status & RFD_TCPError) == 0) ||
1776 ((status & RFD_UDPDetected) != 0 &&
1777 (status & RFD_UDPError) == 0)) {
1778 m->m_pkthdr.csum_flags |=
1781 CSUM_FRAG_NOT_CHECKED);
1782 m->m_pkthdr.csum_data = 0xffff;
1787 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1788 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1789 STGE_RXCHAIN_RESET(sc);
1795 /* Check for VLAN tagged packets. */
1796 if ((status & RFD_VLANDetected) != 0 &&
1797 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1798 VLAN_INPUT_TAG(m, RFD_TCI(status64));
1801 ifp->if_input(ifp, m);
1804 STGE_RXCHAIN_RESET(sc);
1809 /* Update the consumer index. */
1810 sc->sc_cdata.stge_rx_cons = cons;
1811 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1812 sc->sc_cdata.stge_rx_ring_map,
1813 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1817 #ifdef DEVICE_POLLING
1819 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1821 struct stge_softc *sc;
1828 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1830 case POLL_DEREGISTER:
1831 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1834 case POLL_AND_CHECK_STATUS:
1835 sc->sc_cdata.stge_rxcycles = count;
1836 stge_rxeof(sc, count);
1839 if (cmd == POLL_AND_CHECK_STATUS) {
1840 status = CSR_READ_2(sc, STGE_IntStatus);
1841 status &= sc->sc_IntEnable;
1843 if (status & IS_HostError) {
1844 device_printf(sc->sc_dev,
1845 "Host interface error, "
1849 if ((status & IS_TxComplete) != 0 &&
1850 stge_tx_error(sc) != 0)
1856 if (!ifq_is_empty(&ifp->if_snd))
1860 #endif /* DEVICE_POLLING */
1865 * One second timer, used to tick the MII.
1868 stge_tick(void *arg)
1870 struct stge_softc *sc = arg;
1871 struct ifnet *ifp = &sc->arpcom.ac_if;
1872 struct mii_data *mii;
1874 lwkt_serialize_enter(ifp->if_serializer);
1876 mii = device_get_softc(sc->sc_miibus);
1879 /* Update statistics counters. */
1880 stge_stats_update(sc);
1883 * Relcaim any pending Tx descriptors to release mbufs in a
1884 * timely manner as we don't generate Tx completion interrupts
1885 * for every frame. This limits the delay to a maximum of one
1888 if (sc->sc_cdata.stge_tx_cnt != 0)
1891 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1893 lwkt_serialize_exit(ifp->if_serializer);
1897 * stge_stats_update:
1899 * Read the TC9021 statistics counters.
1902 stge_stats_update(struct stge_softc *sc)
1904 struct ifnet *ifp = &sc->arpcom.ac_if;
1906 CSR_READ_4(sc,STGE_OctetRcvOk);
1908 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk);
1910 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
1912 CSR_READ_4(sc, STGE_OctetXmtdOk);
1914 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk);
1916 ifp->if_collisions +=
1917 CSR_READ_4(sc, STGE_LateCollisions) +
1918 CSR_READ_4(sc, STGE_MultiColFrames) +
1919 CSR_READ_4(sc, STGE_SingleColFrames);
1922 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1923 CSR_READ_2(sc, STGE_FramesWEXDeferal);
1929 * Perform a soft reset on the TC9021.
1932 stge_reset(struct stge_softc *sc, uint32_t how)
1939 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1942 ac |= AC_TxReset | AC_FIFO;
1946 ac |= AC_RxReset | AC_FIFO;
1949 case STGE_RESET_FULL:
1952 * Only assert RstOut if we're fiber. We need GMII clocks
1953 * to be present in order for the reset to complete on fiber
1956 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1957 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1958 (sc->sc_usefiber ? AC_RstOut : 0);
1962 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1964 /* Account for reset problem at 10Mbps. */
1967 for (i = 0; i < STGE_TIMEOUT; i++) {
1968 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1973 if (i == STGE_TIMEOUT)
1974 device_printf(sc->sc_dev, "reset failed to complete\n");
1976 /* Set LED, from Linux IPG driver. */
1977 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1978 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1979 if ((sc->sc_led & 0x01) != 0)
1981 if ((sc->sc_led & 0x03) != 0)
1982 ac |= AC_LEDModeBit1;
1983 if ((sc->sc_led & 0x08) != 0)
1985 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1987 /* Set PHY, from Linux IPG driver */
1988 v = CSR_READ_1(sc, STGE_PhySet);
1989 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1990 v |= ((sc->sc_led & 0x70) >> 4);
1991 CSR_WRITE_1(sc, STGE_PhySet, v);
1995 * stge_init: [ ifnet interface function ]
1997 * Initialize the interface.
2000 stge_init(void *xsc)
2002 struct stge_softc *sc = xsc;
2003 struct ifnet *ifp = &sc->arpcom.ac_if;
2004 struct mii_data *mii;
2009 ASSERT_SERIALIZED(ifp->if_serializer);
2011 mii = device_get_softc(sc->sc_miibus);
2014 * Cancel any pending I/O.
2018 /* Init descriptors. */
2019 error = stge_init_rx_ring(sc);
2021 device_printf(sc->sc_dev,
2022 "initialization failed: no memory for rx buffers\n");
2026 stge_init_tx_ring(sc);
2028 /* Set the station address. */
2029 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2030 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2031 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2032 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2035 * Set the statistics masks. Disable all the RMON stats,
2036 * and disable selected stats in the non-RMON stats registers.
2038 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2039 CSR_WRITE_4(sc, STGE_StatisticsMask,
2040 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2041 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2042 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2045 /* Set up the receive filter. */
2046 stge_set_filter(sc);
2047 /* Program multicast filter. */
2051 * Give the transmit and receive ring to the chip.
2053 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2054 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2055 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2056 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2058 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2059 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2060 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2061 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2064 * Initialize the Tx auto-poll period. It's OK to make this number
2065 * large (255 is the max, but we use 127) -- we explicitly kick the
2066 * transmit engine when there's actually a packet.
2068 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2070 /* ..and the Rx auto-poll period. */
2071 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2073 /* Initialize the Tx start threshold. */
2074 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2076 /* Rx DMA thresholds, from Linux */
2077 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2078 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2080 /* Rx early threhold, from Linux */
2081 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2083 /* Tx DMA thresholds, from Linux */
2084 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2085 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2088 * Initialize the Rx DMA interrupt control register. We
2089 * request an interrupt after every incoming packet, but
2090 * defer it for sc_rxint_dmawait us. When the number of
2091 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2092 * deferring the interrupt, and signal it immediately.
2094 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2095 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2096 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2099 * Initialize the interrupt mask.
2101 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2102 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2103 #ifdef DEVICE_POLLING
2104 /* Disable interrupts if we are polling. */
2105 if (ifp->if_flags & IFF_POLLING)
2106 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2109 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2112 * Configure the DMA engine.
2113 * XXX Should auto-tune TxBurstLimit.
2115 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2118 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2119 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2122 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2123 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2126 * Set the maximum frame size.
2128 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2129 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2132 * Initialize MacCtrl -- do it before setting the media,
2133 * as setting the media will actually program the register.
2135 * Note: We have to poke the IFS value before poking
2138 /* Tx/Rx MAC should be disabled before programming IFS.*/
2139 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2141 stge_vlan_setup(sc);
2143 if (sc->sc_rev >= 6) { /* >= B.2 */
2144 /* Multi-frag frame bug work-around. */
2145 CSR_WRITE_2(sc, STGE_DebugCtrl,
2146 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2148 /* Tx Poll Now bug work-around. */
2149 CSR_WRITE_2(sc, STGE_DebugCtrl,
2150 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2151 /* Tx Poll Now bug work-around. */
2152 CSR_WRITE_2(sc, STGE_DebugCtrl,
2153 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2156 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2157 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2158 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2160 * It seems that transmitting frames without checking the state of
2161 * Rx/Tx MAC wedge the hardware.
2167 * Set the current media.
2172 * Start the one second MII clock.
2174 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2179 ifp->if_flags |= IFF_RUNNING;
2180 ifp->if_flags &= ~IFF_OACTIVE;
2184 device_printf(sc->sc_dev, "interface not running\n");
2188 stge_vlan_setup(struct stge_softc *sc)
2190 struct ifnet *ifp = &sc->arpcom.ac_if;
2194 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2195 * MC_AutoVLANuntagging bit.
2196 * MC_AutoVLANtagging bit selects which VLAN source to use
2197 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2198 * bit has priority over MC_AutoVLANtagging bit. So we always
2199 * use TFC instead of STGE_VLANTag register.
2201 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2202 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2203 v |= MC_AutoVLANuntagging;
2205 v &= ~MC_AutoVLANuntagging;
2206 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2210 * Stop transmission on the interface.
2213 stge_stop(struct stge_softc *sc)
2215 struct ifnet *ifp = &sc->arpcom.ac_if;
2216 struct stge_txdesc *txd;
2217 struct stge_rxdesc *rxd;
2221 ASSERT_SERIALIZED(ifp->if_serializer);
2224 * Stop the one second clock.
2226 callout_stop(&sc->sc_tick_ch);
2229 * Reset the chip to a known state.
2231 stge_reset(sc, STGE_RESET_FULL);
2234 * Disable interrupts.
2236 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2239 * Stop receiver, transmitter, and stats update.
2243 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2244 v |= MC_StatisticsDisable;
2245 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2248 * Stop the transmit and receive DMA.
2251 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2252 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2253 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2254 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2257 * Free RX and TX mbufs still in the queues.
2259 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2260 rxd = &sc->sc_cdata.stge_rxdesc[i];
2261 if (rxd->rx_m != NULL) {
2262 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2263 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2264 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2270 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2271 txd = &sc->sc_cdata.stge_txdesc[i];
2272 if (txd->tx_m != NULL) {
2273 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2274 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2275 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2283 * Mark the interface down and cancel the watchdog timer.
2285 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2290 stge_start_tx(struct stge_softc *sc)
2295 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2296 if ((v & MC_TxEnabled) != 0)
2299 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2300 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2301 for (i = STGE_TIMEOUT; i > 0; i--) {
2303 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2304 if ((v & MC_TxEnabled) != 0)
2308 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2312 stge_start_rx(struct stge_softc *sc)
2317 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2318 if ((v & MC_RxEnabled) != 0)
2321 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2322 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2323 for (i = STGE_TIMEOUT; i > 0; i--) {
2325 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2326 if ((v & MC_RxEnabled) != 0)
2330 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2334 stge_stop_tx(struct stge_softc *sc)
2339 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2340 if ((v & MC_TxEnabled) == 0)
2343 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2344 for (i = STGE_TIMEOUT; i > 0; i--) {
2346 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2347 if ((v & MC_TxEnabled) == 0)
2351 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2355 stge_stop_rx(struct stge_softc *sc)
2360 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2361 if ((v & MC_RxEnabled) == 0)
2364 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2365 for (i = STGE_TIMEOUT; i > 0; i--) {
2367 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2368 if ((v & MC_RxEnabled) == 0)
2372 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2376 stge_init_tx_ring(struct stge_softc *sc)
2378 struct stge_ring_data *rd;
2379 struct stge_txdesc *txd;
2383 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2384 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2386 sc->sc_cdata.stge_tx_prod = 0;
2387 sc->sc_cdata.stge_tx_cons = 0;
2388 sc->sc_cdata.stge_tx_cnt = 0;
2391 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2392 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2393 if (i == (STGE_TX_RING_CNT - 1))
2394 addr = STGE_TX_RING_ADDR(sc, 0);
2396 addr = STGE_TX_RING_ADDR(sc, i + 1);
2397 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2398 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2399 txd = &sc->sc_cdata.stge_txdesc[i];
2400 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2403 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2404 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_PREWRITE);
2408 stge_init_rx_ring(struct stge_softc *sc)
2410 struct stge_ring_data *rd;
2414 sc->sc_cdata.stge_rx_cons = 0;
2415 STGE_RXCHAIN_RESET(sc);
2418 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2419 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2420 if (stge_newbuf(sc, i, 1) != 0)
2422 if (i == (STGE_RX_RING_CNT - 1))
2423 addr = STGE_RX_RING_ADDR(sc, 0);
2425 addr = STGE_RX_RING_ADDR(sc, i + 1);
2426 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2427 rd->stge_rx_ring[i].rfd_status = 0;
2430 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2431 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_PREWRITE);
2439 * Add a receive buffer to the indicated descriptor.
2442 stge_newbuf(struct stge_softc *sc, int idx, int waitok)
2444 struct stge_rxdesc *rxd;
2445 struct stge_rfd *rfd;
2447 struct stge_mbuf_dmamap_arg arg;
2448 bus_dma_segment_t segs[1];
2451 m = m_getcl(waitok ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2454 m->m_len = m->m_pkthdr.len = MCLBYTES;
2456 * The hardware requires 4bytes aligned DMA address when JUMBO
2459 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2460 m_adj(m, ETHER_ALIGN);
2464 if (bus_dmamap_load_mbuf(sc->sc_cdata.stge_rx_tag,
2465 sc->sc_cdata.stge_rx_sparemap, m, stge_mbuf_dmamap_cb, &arg,
2466 waitok ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT) != 0) {
2471 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2472 if (rxd->rx_m != NULL) {
2473 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2474 BUS_DMASYNC_POSTREAD);
2475 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2477 map = rxd->rx_dmamap;
2478 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2479 sc->sc_cdata.stge_rx_sparemap = map;
2480 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2481 BUS_DMASYNC_PREREAD);
2484 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2485 rfd->rfd_frag.frag_word0 =
2486 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2487 rfd->rfd_status = 0;
2495 * Set up the receive filter.
2498 stge_set_filter(struct stge_softc *sc)
2500 struct ifnet *ifp = &sc->arpcom.ac_if;
2503 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2504 mode |= RM_ReceiveUnicast;
2505 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2506 mode |= RM_ReceiveBroadcast;
2508 mode &= ~RM_ReceiveBroadcast;
2509 if ((ifp->if_flags & IFF_PROMISC) != 0)
2510 mode |= RM_ReceiveAllFrames;
2512 mode &= ~RM_ReceiveAllFrames;
2514 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2518 stge_set_multi(struct stge_softc *sc)
2520 struct ifnet *ifp = &sc->arpcom.ac_if;
2521 struct ifmultiaddr *ifma;
2527 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2528 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2529 if ((ifp->if_flags & IFF_PROMISC) != 0)
2530 mode |= RM_ReceiveAllFrames;
2531 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2532 mode |= RM_ReceiveMulticast;
2533 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2537 /* clear existing filters. */
2538 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2539 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2542 * Set up the multicast address filter by passing all multicast
2543 * addresses through a CRC generator, and then using the low-order
2544 * 6 bits as an index into the 64 bit multicast hash table. The
2545 * high order bits select the register, while the rest of the bits
2546 * select the bit within the register.
2549 bzero(mchash, sizeof(mchash));
2552 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2553 if (ifma->ifma_addr->sa_family != AF_LINK)
2555 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2556 ifma->ifma_addr), ETHER_ADDR_LEN);
2558 /* Just want the 6 least significant bits. */
2561 /* Set the corresponding bit in the hash table. */
2562 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2566 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2568 mode |= RM_ReceiveMulticastHash;
2570 mode &= ~RM_ReceiveMulticastHash;
2572 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2573 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2574 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2578 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2584 value = *(int *)arg1;
2585 error = sysctl_handle_int(oidp, &value, 0, req);
2586 if (error || !req->newptr)
2588 if (value < low || value > high)
2590 *(int *)arg1 = value;
2596 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2598 return (sysctl_int_range(oidp, arg1, arg2, req,
2599 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2603 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2605 return (sysctl_int_range(oidp, arg1, arg2, req,
2606 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));