sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_polling.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <net/bpf.h>
  72 #include <net/ethernet.h>
  73 #include <net/if.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77 #include <net/if_types.h>
  78 #include <net/ifq_var.h>
  79 #include <net/vlan/if_vlan_var.h>
  80 #include <net/vlan/if_vlan_ether.h>
  81
  82 #include <dev/netif/mii_layer/mii.h>
  83 #include <dev/netif/mii_layer/miivar.h>
  84
  85 #include <bus/pci/pcireg.h>
  86 #include <bus/pci/pcivar.h>
  87
  88 #include "miibus_if.h"
  89
  90 #include <dev/netif/bce/if_bcereg.h>
  91 #include <dev/netif/bce/if_bcefw.h>
  92
  93 /****************************************************************************/
  94 /* BCE Debug Options                                                        */
  95 /****************************************************************************/
  96 #ifdef BCE_DEBUG
  97
  98 static uint32_t bce_debug = BCE_WARN;
  99
 100 /*
 101  *          0 = Never
 102  *          1 = 1 in 2,147,483,648
 103  *        256 = 1 in     8,388,608
 104  *       2048 = 1 in     1,048,576
 105  *      65536 = 1 in        32,768
 106  *    1048576 = 1 in         2,048
 107  *  268435456 = 1 in             8
 108  *  536870912 = 1 in             4
 109  * 1073741824 = 1 in             2
 110  *
 111  * bce_debug_l2fhdr_status_check:
 112  *     How often the l2_fhdr frame error check will fail.
 113  *
 114  * bce_debug_unexpected_attention:
 115  *     How often the unexpected attention check will fail.
 116  *
 117  * bce_debug_mbuf_allocation_failure:
 118  *     How often to simulate an mbuf allocation failure.
 119  *
 120  * bce_debug_dma_map_addr_failure:
 121  *     How often to simulate a DMA mapping failure.
 122  *
 123  * bce_debug_bootcode_running_failure:
 124  *     How often to simulate a bootcode failure.
 125  */
 126 static int      bce_debug_l2fhdr_status_check = 0;
 127 static int      bce_debug_unexpected_attention = 0;
 128 static int      bce_debug_mbuf_allocation_failure = 0;
 129 static int      bce_debug_dma_map_addr_failure = 0;
 130 static int      bce_debug_bootcode_running_failure = 0;
 131
 132 #endif  /* BCE_DEBUG */
 133
 134
 135 /****************************************************************************/
 136 /* PCI Device ID Table                                                      */
 137 /*                                                                          */
 138 /* Used by bce_probe() to identify the devices supported by this driver.    */
 139 /****************************************************************************/
 140 #define BCE_DEVDESC_MAX         64
 141
 142 static struct bce_type bce_devs[] = {
 143         /* BCM5706C Controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 145                 "HP NC370T Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 147                 "HP NC370i Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 149                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 151                 "HP NC371i Multifunction Gigabit Server Adapter" },
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 153                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 154
 155         /* BCM5706S controllers and OEM boards. */
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 157                 "HP NC370F Multifunction Gigabit Server Adapter" },
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 159                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 160
 161         /* BCM5708C controllers and OEM boards. */
 162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 163                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 165                 "HP NC373i Multifunction Gigabit Server Adapter" },
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 167                 "HP NC374m PCIe Multifunction Adapter" },
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 169                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 170
 171         /* BCM5708S controllers and OEM boards. */
 172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 173                 "HP NC373m Multifunction Gigabit Server Adapter" },
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 175                 "HP NC373i Multifunction Gigabit Server Adapter" },
 176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 177                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 179                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 180
 181         /* BCM5709C controllers and OEM boards. */
 182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 183                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 185                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 187                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 188
 189         /* BCM5709S controllers and OEM boards. */
 190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 191                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 193                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 195                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 196
 197         /* BCM5716 controllers and OEM boards. */
 198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 199                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 200
 201         { 0, 0, 0, 0, NULL }
 202 };
 203
 204
 205 /****************************************************************************/
 206 /* Supported Flash NVRAM device data.                                       */
 207 /****************************************************************************/
 208 static const struct flash_spec flash_table[] =
 209 {
 210 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 211 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 212
 213         /* Slow EEPROM */
 214         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 215          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 216          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 217          "EEPROM - slow"},
 218         /* Expansion entry 0001 */
 219         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 222          "Entry 0001"},
 223         /* Saifun SA25F010 (non-buffered flash) */
 224         /* strap, cfg1, & write1 need updates */
 225         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 226          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 227          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 228          "Non-buffered flash (128kB)"},
 229         /* Saifun SA25F020 (non-buffered flash) */
 230         /* strap, cfg1, & write1 need updates */
 231         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 232          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 233          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 234          "Non-buffered flash (256kB)"},
 235         /* Expansion entry 0100 */
 236         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 237          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 238          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 239          "Entry 0100"},
 240         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 241         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 242          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 243          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 244          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 245         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 246         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 247          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 248          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 249          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 250         /* Saifun SA25F005 (non-buffered flash) */
 251         /* strap, cfg1, & write1 need updates */
 252         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 253          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 254          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 255          "Non-buffered flash (64kB)"},
 256         /* Fast EEPROM */
 257         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 258          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 259          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 260          "EEPROM - fast"},
 261         /* Expansion entry 1001 */
 262         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 263          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 264          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 265          "Entry 1001"},
 266         /* Expansion entry 1010 */
 267         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 268          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 269          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 270          "Entry 1010"},
 271         /* ATMEL AT45DB011B (buffered flash) */
 272         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 273          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 274          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 275          "Buffered flash (128kB)"},
 276         /* Expansion entry 1100 */
 277         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 278          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 279          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 280          "Entry 1100"},
 281         /* Expansion entry 1101 */
 282         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 283          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 284          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 285          "Entry 1101"},
 286         /* Ateml Expansion entry 1110 */
 287         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 288          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 289          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 290          "Entry 1110 (Atmel)"},
 291         /* ATMEL AT45DB021B (buffered flash) */
 292         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 293          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 294          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 295          "Buffered flash (256kB)"},
 296 };
 297
 298 /*
 299  * The BCM5709 controllers transparently handle the
 300  * differences between Atmel 264 byte pages and all
 301  * flash devices which use 256 byte pages, so no
 302  * logical-to-physical mapping is required in the
 303  * driver.
 304  */
 305 static struct flash_spec flash_5709 = {
 306         .flags          = BCE_NV_BUFFERED,
 307         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 308         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 309         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 310         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 311         .name           = "5709/5716 buffered flash (256kB)",
 312 };
 313
 314
 315 /****************************************************************************/
 316 /* DragonFly device entry points.                                           */
 317 /****************************************************************************/
 318 static int      bce_probe(device_t);
 319 static int      bce_attach(device_t);
 320 static int      bce_detach(device_t);
 321 static void     bce_shutdown(device_t);
 322
 323 /****************************************************************************/
 324 /* BCE Debug Data Structure Dump Routines                                   */
 325 /****************************************************************************/
 326 #ifdef BCE_DEBUG
 327 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 328 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 329 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 330 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 331 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 332 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 333                                 struct l2_fhdr *) __unused;
 334 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 335 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 336 static void     bce_dump_status_block(struct bce_softc *);
 337 static void     bce_dump_driver_state(struct bce_softc *);
 338 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 339 static void     bce_dump_hw_state(struct bce_softc *);
 340 static void     bce_dump_txp_state(struct bce_softc *);
 341 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 342 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 343 static void     bce_freeze_controller(struct bce_softc *) __unused;
 344 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 345 static void     bce_breakpoint(struct bce_softc *);
 346 #endif  /* BCE_DEBUG */
 347
 348
 349 /****************************************************************************/
 350 /* BCE Register/Memory Access Routines                                      */
 351 /****************************************************************************/
 352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 353 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 354 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
 355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
 356 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 357 static int      bce_miibus_read_reg(device_t, int, int);
 358 static int      bce_miibus_write_reg(device_t, int, int, int);
 359 static void     bce_miibus_statchg(device_t);
 360
 361
 362 /****************************************************************************/
 363 /* BCE NVRAM Access Routines                                                */
 364 /****************************************************************************/
 365 static int      bce_acquire_nvram_lock(struct bce_softc *);
 366 static int      bce_release_nvram_lock(struct bce_softc *);
 367 static void     bce_enable_nvram_access(struct bce_softc *);
 368 static void     bce_disable_nvram_access(struct bce_softc *);
 369 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 370                                      uint32_t);
 371 static int      bce_init_nvram(struct bce_softc *);
 372 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 373 static int      bce_nvram_test(struct bce_softc *);
 374
 375 /****************************************************************************/
 376 /* BCE DMA Allocate/Free Routines                                           */
 377 /****************************************************************************/
 378 static int      bce_dma_alloc(struct bce_softc *);
 379 static void     bce_dma_free(struct bce_softc *);
 380 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 381
 382 /****************************************************************************/
 383 /* BCE Firmware Synchronization and Load                                    */
 384 /****************************************************************************/
 385 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 386 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 387                                  uint32_t, uint32_t);
 388 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 389                                 struct fw_info *);
 390 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
 391 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
 392 static void     bce_start_rxp_cpu(struct bce_softc *);
 393 static void     bce_init_rxp_cpu(struct bce_softc *);
 394 static void     bce_init_txp_cpu(struct bce_softc *);
 395 static void     bce_init_tpat_cpu(struct bce_softc *);
 396 static void     bce_init_cp_cpu(struct bce_softc *);
 397 static void     bce_init_com_cpu(struct bce_softc *);
 398 static void     bce_init_cpus(struct bce_softc *);
 399
 400 static void     bce_stop(struct bce_softc *);
 401 static int      bce_reset(struct bce_softc *, uint32_t);
 402 static int      bce_chipinit(struct bce_softc *);
 403 static int      bce_blockinit(struct bce_softc *);
 404 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 405                                uint32_t *, int);
 406 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 407 static void     bce_probe_pci_caps(struct bce_softc *);
 408 static void     bce_print_adapter_info(struct bce_softc *);
 409 static void     bce_get_media(struct bce_softc *);
 410
 411 static void     bce_init_tx_context(struct bce_softc *);
 412 static int      bce_init_tx_chain(struct bce_softc *);
 413 static void     bce_init_rx_context(struct bce_softc *);
 414 static int      bce_init_rx_chain(struct bce_softc *);
 415 static void     bce_free_rx_chain(struct bce_softc *);
 416 static void     bce_free_tx_chain(struct bce_softc *);
 417
 418 static int      bce_encap(struct bce_softc *, struct mbuf **);
 419 static void     bce_start(struct ifnet *);
 420 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 421 static void     bce_watchdog(struct ifnet *);
 422 static int      bce_ifmedia_upd(struct ifnet *);
 423 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 424 static void     bce_init(void *);
 425 static void     bce_mgmt_init(struct bce_softc *);
 426
 427 static int      bce_init_ctx(struct bce_softc *);
 428 static void     bce_get_mac_addr(struct bce_softc *);
 429 static void     bce_set_mac_addr(struct bce_softc *);
 430 static void     bce_phy_intr(struct bce_softc *);
 431 static void     bce_rx_intr(struct bce_softc *, int);
 432 static void     bce_tx_intr(struct bce_softc *);
 433 static void     bce_disable_intr(struct bce_softc *);
 434 static void     bce_enable_intr(struct bce_softc *, int);
 435
 436 #ifdef DEVICE_POLLING
 437 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 438 #endif
 439 static void     bce_intr(void *);
 440 static void     bce_set_rx_mode(struct bce_softc *);
 441 static void     bce_stats_update(struct bce_softc *);
 442 static void     bce_tick(void *);
 443 static void     bce_tick_serialized(struct bce_softc *);
 444 static void     bce_pulse(void *);
 445 static void     bce_add_sysctls(struct bce_softc *);
 446
 447 static void     bce_coal_change(struct bce_softc *);
 448 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 449 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 450 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 451 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 452 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 453 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 454 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 455 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 456 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 457                                        uint32_t *, uint32_t);
 458
 459 /*
 460  * NOTE:
 461  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 462  * takes 1023 as the TX ticks limit.  However, using 1023 will
 463  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 464  * there is _no_ network activity on the NIC.
 465  */
 466 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 467 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 468 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 469 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 470 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 471 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 472 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 473 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 474
 475 static int      bce_msi_enable = 1;
 476
 477 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 478 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 479 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 480 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 481 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 482 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 483 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 484 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 485 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
 486
 487 /****************************************************************************/
 488 /* DragonFly device dispatch table.                                         */
 489 /****************************************************************************/
 490 static device_method_t bce_methods[] = {
 491         /* Device interface */
 492         DEVMETHOD(device_probe,         bce_probe),
 493         DEVMETHOD(device_attach,        bce_attach),
 494         DEVMETHOD(device_detach,        bce_detach),
 495         DEVMETHOD(device_shutdown,      bce_shutdown),
 496
 497         /* bus interface */
 498         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 499         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 500
 501         /* MII interface */
 502         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 503         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 504         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 505
 506         { 0, 0 }
 507 };
 508
 509 static driver_t bce_driver = {
 510         "bce",
 511         bce_methods,
 512         sizeof(struct bce_softc)
 513 };
 514
 515 static devclass_t bce_devclass;
 516
 517
 518 DECLARE_DUMMY_MODULE(if_bce);
 519 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 520 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 521 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 522
 523
 524 /****************************************************************************/
 525 /* Device probe function.                                                   */
 526 /*                                                                          */
 527 /* Compares the device to the driver's list of supported devices and        */
 528 /* reports back to the OS whether this is the right driver for the device.  */
 529 /*                                                                          */
 530 /* Returns:                                                                 */
 531 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 532 /****************************************************************************/
 533 static int
 534 bce_probe(device_t dev)
 535 {
 536         struct bce_type *t;
 537         uint16_t vid, did, svid, sdid;
 538
 539         /* Get the data for the device to be probed. */
 540         vid  = pci_get_vendor(dev);
 541         did  = pci_get_device(dev);
 542         svid = pci_get_subvendor(dev);
 543         sdid = pci_get_subdevice(dev);
 544
 545         /* Look through the list of known devices for a match. */
 546         for (t = bce_devs; t->bce_name != NULL; ++t) {
 547                 if (vid == t->bce_vid && did == t->bce_did &&
 548                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 549                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 550                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 551                         char *descbuf;
 552
 553                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 554
 555                         /* Print out the device identity. */
 556                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 557                                   t->bce_name,
 558                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 559
 560                         device_set_desc_copy(dev, descbuf);
 561                         kfree(descbuf, M_TEMP);
 562                         return 0;
 563                 }
 564         }
 565         return ENXIO;
 566 }
 567
 568
 569 /****************************************************************************/
 570 /* PCI Capabilities Probe Function.                                         */
 571 /*                                                                          */
 572 /* Walks the PCI capabiites list for the device to find what features are   */
 573 /* supported.                                                               */
 574 /*                                                                          */
 575 /* Returns:                                                                 */
 576 /*   None.                                                                  */
 577 /****************************************************************************/
 578 static void
 579 bce_print_adapter_info(struct bce_softc *sc)
 580 {
 581         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 582
 583         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 584                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 585
 586         /* Bus info. */
 587         if (sc->bce_flags & BCE_PCIE_FLAG) {
 588                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 589                 switch (sc->link_speed) {
 590                 case 1:
 591                         kprintf("2.5Gbps); ");
 592                         break;
 593                 case 2:
 594                         kprintf("5Gbps); ");
 595                         break;
 596                 default:
 597                         kprintf("Unknown link speed); ");
 598                         break;
 599                 }
 600         } else {
 601                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 602                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 603                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 604                     sc->bus_speed_mhz);
 605         }
 606
 607         /* Firmware version and device features. */
 608         kprintf("B/C (%s)", sc->bce_bc_ver);
 609
 610         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 611             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 612                 kprintf("; Flags(");
 613                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 614                         kprintf("MFW[%s]", sc->bce_mfw_ver);
 615                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 616                         kprintf(" 2.5G");
 617                 kprintf(")");
 618         }
 619         kprintf("\n");
 620 }
 621
 622
 623 /****************************************************************************/
 624 /* PCI Capabilities Probe Function.                                         */
 625 /*                                                                          */
 626 /* Walks the PCI capabiites list for the device to find what features are   */
 627 /* supported.                                                               */
 628 /*                                                                          */
 629 /* Returns:                                                                 */
 630 /*   None.                                                                  */
 631 /****************************************************************************/
 632 static void
 633 bce_probe_pci_caps(struct bce_softc *sc)
 634 {
 635         device_t dev = sc->bce_dev;
 636         uint8_t ptr;
 637
 638         if (pci_is_pcix(dev))
 639                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 640
 641         ptr = pci_get_pciecap_ptr(dev);
 642         if (ptr) {
 643                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 644
 645                 sc->link_speed = link_status & 0xf;
 646                 sc->link_width = (link_status >> 4) & 0x3f;
 647                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 648                 sc->bce_flags |= BCE_PCIE_FLAG;
 649         }
 650 }
 651
 652
 653 /****************************************************************************/
 654 /* Device attach function.                                                  */
 655 /*                                                                          */
 656 /* Allocates device resources, performs secondary chip identification,      */
 657 /* resets and initializes the hardware, and initializes driver instance     */
 658 /* variables.                                                               */
 659 /*                                                                          */
 660 /* Returns:                                                                 */
 661 /*   0 on success, positive value on failure.                               */
 662 /****************************************************************************/
 663 static int
 664 bce_attach(device_t dev)
 665 {
 666         struct bce_softc *sc = device_get_softc(dev);
 667         struct ifnet *ifp = &sc->arpcom.ac_if;
 668         uint32_t val;
 669         u_int irq_flags;
 670         int rid, rc = 0, msi_enable;
 671         int i, j;
 672         char env[64];
 673
 674         sc->bce_dev = dev;
 675         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 676
 677         pci_enable_busmaster(dev);
 678
 679         bce_probe_pci_caps(sc);
 680
 681         /* Allocate PCI memory resources. */
 682         rid = PCIR_BAR(0);
 683         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 684                                                  RF_ACTIVE | PCI_RF_DENSE);
 685         if (sc->bce_res_mem == NULL) {
 686                 device_printf(dev, "PCI memory allocation failed\n");
 687                 return ENXIO;
 688         }
 689         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 690         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 691
 692         /* Allocate PCI IRQ resources. */
 693         msi_enable = bce_msi_enable;
 694         ksnprintf(env, sizeof(env), "hw.%s.msi.enable",
 695             device_get_nameunit(dev));
 696         kgetenv_int(env, &msi_enable);
 697
 698         sc->bce_irq_rid = 0;
 699         sc->bce_irq_type = BCE_IRQ_TYPE_LEGACY;
 700         irq_flags = RF_SHAREABLE | RF_ACTIVE;
 701
 702         if (msi_enable) {
 703                 int cpu = -1;
 704
 705                 ksnprintf(env, sizeof(env), "hw.%s.msi.cpu",
 706                     device_get_nameunit(dev));
 707                 kgetenv_int(env, &cpu);
 708                 if (cpu >= ncpus)
 709                         cpu = ncpus - 1;
 710
 711                 if (pci_alloc_msi(dev, &sc->bce_irq_rid, 1, cpu) == 0) {
 712                         irq_flags &= ~RF_SHAREABLE;
 713                         sc->bce_irq_type = BCE_IRQ_TYPE_MSI;
 714                 }
 715         }
 716
 717         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 718             &sc->bce_irq_rid, irq_flags);
 719         if (sc->bce_res_irq == NULL) {
 720                 device_printf(dev, "PCI map interrupt failed\n");
 721                 rc = ENXIO;
 722                 goto fail;
 723         }
 724
 725         /*
 726          * Configure byte swap and enable indirect register access.
 727          * Rely on CPU to do target byte swapping on big endian systems.
 728          * Access to registers outside of PCI configurtion space are not
 729          * valid until this is done.
 730          */
 731         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 732                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 733                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 734
 735         /* Save ASIC revsion info. */
 736         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 737
 738         /* Weed out any non-production controller revisions. */
 739         switch (BCE_CHIP_ID(sc)) {
 740         case BCE_CHIP_ID_5706_A0:
 741         case BCE_CHIP_ID_5706_A1:
 742         case BCE_CHIP_ID_5708_A0:
 743         case BCE_CHIP_ID_5708_B0:
 744         case BCE_CHIP_ID_5709_A0:
 745         case BCE_CHIP_ID_5709_B0:
 746         case BCE_CHIP_ID_5709_B1:
 747 #ifdef foo
 748         /* 5709C B2 seems to work fine */
 749         case BCE_CHIP_ID_5709_B2:
 750 #endif
 751                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 752                               BCE_CHIP_ID(sc));
 753                 rc = ENODEV;
 754                 goto fail;
 755         }
 756
 757         /*
 758          * Find the base address for shared memory access.
 759          * Newer versions of bootcode use a signature and offset
 760          * while older versions use a fixed address.
 761          */
 762         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 763         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 764             BCE_SHM_HDR_SIGNATURE_SIG) {
 765                 /* Multi-port devices use different offsets in shared memory. */
 766                 sc->bce_shmem_base = REG_RD_IND(sc,
 767                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 768         } else {
 769                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 770         }
 771         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 772
 773         /* Fetch the bootcode revision. */
 774         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 775         for (i = 0, j = 0; i < 3; i++) {
 776                 uint8_t num;
 777                 int k, skip0;
 778
 779                 num = (uint8_t)(val >> (24 - (i * 8)));
 780                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 781                         if (num >= k || !skip0 || k == 1) {
 782                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 783                                 skip0 = 0;
 784                         }
 785                 }
 786                 if (i != 2)
 787                         sc->bce_bc_ver[j++] = '.';
 788         }
 789
 790         /* Check if any management firwmare is running. */
 791         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 792         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 793                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 794
 795                 /* Allow time for firmware to enter the running state. */
 796                 for (i = 0; i < 30; i++) {
 797                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 798                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 799                                 break;
 800                         DELAY(10000);
 801                 }
 802         }
 803
 804         /* Check the current bootcode state. */
 805         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
 806             BCE_CONDITION_MFW_RUN_MASK;
 807         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
 808             val != BCE_CONDITION_MFW_RUN_NONE) {
 809                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 810
 811                 for (i = 0, j = 0; j < 3; j++) {
 812                         val = bce_reg_rd_ind(sc, addr + j * 4);
 813                         val = bswap32(val);
 814                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
 815                         i += 4;
 816                 }
 817         }
 818
 819         /* Get PCI bus information (speed and type). */
 820         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 821         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 822                 uint32_t clkreg;
 823
 824                 sc->bce_flags |= BCE_PCIX_FLAG;
 825
 826                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 827                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 828                 switch (clkreg) {
 829                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 830                         sc->bus_speed_mhz = 133;
 831                         break;
 832
 833                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 834                         sc->bus_speed_mhz = 100;
 835                         break;
 836
 837                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 838                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 839                         sc->bus_speed_mhz = 66;
 840                         break;
 841
 842                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 843                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 844                         sc->bus_speed_mhz = 50;
 845                         break;
 846
 847                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 848                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 849                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 850                         sc->bus_speed_mhz = 33;
 851                         break;
 852                 }
 853         } else {
 854                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 855                         sc->bus_speed_mhz = 66;
 856                 else
 857                         sc->bus_speed_mhz = 33;
 858         }
 859
 860         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 861                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 862
 863         /* Reset the controller. */
 864         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 865         if (rc != 0)
 866                 goto fail;
 867
 868         /* Initialize the controller. */
 869         rc = bce_chipinit(sc);
 870         if (rc != 0) {
 871                 device_printf(dev, "Controller initialization failed!\n");
 872                 goto fail;
 873         }
 874
 875         /* Perform NVRAM test. */
 876         rc = bce_nvram_test(sc);
 877         if (rc != 0) {
 878                 device_printf(dev, "NVRAM test failed!\n");
 879                 goto fail;
 880         }
 881
 882         /* Fetch the permanent Ethernet MAC address. */
 883         bce_get_mac_addr(sc);
 884
 885         /*
 886          * Trip points control how many BDs
 887          * should be ready before generating an
 888          * interrupt while ticks control how long
 889          * a BD can sit in the chain before
 890          * generating an interrupt.  Set the default
 891          * values for the RX and TX rings.
 892          */
 893
 894 #ifdef BCE_DRBUG
 895         /* Force more frequent interrupts. */
 896         sc->bce_tx_quick_cons_trip_int = 1;
 897         sc->bce_tx_quick_cons_trip     = 1;
 898         sc->bce_tx_ticks_int           = 0;
 899         sc->bce_tx_ticks               = 0;
 900
 901         sc->bce_rx_quick_cons_trip_int = 1;
 902         sc->bce_rx_quick_cons_trip     = 1;
 903         sc->bce_rx_ticks_int           = 0;
 904         sc->bce_rx_ticks               = 0;
 905 #else
 906         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 907         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 908         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 909         sc->bce_tx_ticks               = bce_tx_ticks;
 910
 911         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 912         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 913         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 914         sc->bce_rx_ticks               = bce_rx_ticks;
 915 #endif
 916
 917         /* Update statistics once every second. */
 918         sc->bce_stats_ticks = 1000000 & 0xffff00;
 919
 920         /* Find the media type for the adapter. */
 921         bce_get_media(sc);
 922
 923         /* Allocate DMA memory resources. */
 924         rc = bce_dma_alloc(sc);
 925         if (rc != 0) {
 926                 device_printf(dev, "DMA resource allocation failed!\n");
 927                 goto fail;
 928         }
 929
 930         /* Initialize the ifnet interface. */
 931         ifp->if_softc = sc;
 932         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 933         ifp->if_ioctl = bce_ioctl;
 934         ifp->if_start = bce_start;
 935         ifp->if_init = bce_init;
 936         ifp->if_watchdog = bce_watchdog;
 937 #ifdef DEVICE_POLLING
 938         ifp->if_poll = bce_poll;
 939 #endif
 940         ifp->if_mtu = ETHERMTU;
 941         ifp->if_hwassist = BCE_IF_HWASSIST;
 942         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 943         ifp->if_capenable = ifp->if_capabilities;
 944         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 945         ifq_set_ready(&ifp->if_snd);
 946
 947         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 948                 ifp->if_baudrate = IF_Gbps(2.5);
 949         else
 950                 ifp->if_baudrate = IF_Gbps(1);
 951
 952         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 953         sc->mbuf_alloc_size  = MCLBYTES;
 954
 955         /* Look for our PHY. */
 956         rc = mii_phy_probe(dev, &sc->bce_miibus,
 957                            bce_ifmedia_upd, bce_ifmedia_sts);
 958         if (rc != 0) {
 959                 device_printf(dev, "PHY probe failed!\n");
 960                 goto fail;
 961         }
 962
 963         /* Attach to the Ethernet interface list. */
 964         ether_ifattach(ifp, sc->eaddr, NULL);
 965
 966         callout_init_mp(&sc->bce_tick_callout);
 967         callout_init_mp(&sc->bce_pulse_callout);
 968
 969         /* Hookup IRQ last. */
 970         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
 971                             &sc->bce_intrhand, ifp->if_serializer);
 972         if (rc != 0) {
 973                 device_printf(dev, "Failed to setup IRQ!\n");
 974                 ether_ifdetach(ifp);
 975                 goto fail;
 976         }
 977
 978         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 979         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 980
 981         /* Print some important debugging info. */
 982         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 983
 984         /* Add the supported sysctls to the kernel. */
 985         bce_add_sysctls(sc);
 986
 987         /*
 988          * The chip reset earlier notified the bootcode that
 989          * a driver is present.  We now need to start our pulse
 990          * routine so that the bootcode is reminded that we're
 991          * still running.
 992          */
 993         bce_pulse(sc);
 994
 995         /* Get the firmware running so IPMI still works */
 996         bce_mgmt_init(sc);
 997
 998         if (bootverbose)
 999                 bce_print_adapter_info(sc);
1000
1001         return 0;
1002 fail:
1003         bce_detach(dev);
1004         return(rc);
1005 }
1006
1007
1008 /****************************************************************************/
1009 /* Device detach function.                                                  */
1010 /*                                                                          */
1011 /* Stops the controller, resets the controller, and releases resources.     */
1012 /*                                                                          */
1013 /* Returns:                                                                 */
1014 /*   0 on success, positive value on failure.                               */
1015 /****************************************************************************/
1016 static int
1017 bce_detach(device_t dev)
1018 {
1019         struct bce_softc *sc = device_get_softc(dev);
1020
1021         if (device_is_attached(dev)) {
1022                 struct ifnet *ifp = &sc->arpcom.ac_if;
1023                 uint32_t msg;
1024
1025                 /* Stop and reset the controller. */
1026                 lwkt_serialize_enter(ifp->if_serializer);
1027                 callout_stop(&sc->bce_pulse_callout);
1028                 bce_stop(sc);
1029                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1030                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1031                 else
1032                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1033                 bce_reset(sc, msg);
1034                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1035                 lwkt_serialize_exit(ifp->if_serializer);
1036
1037                 ether_ifdetach(ifp);
1038         }
1039
1040         /* If we have a child device on the MII bus remove it too. */
1041         if (sc->bce_miibus)
1042                 device_delete_child(dev, sc->bce_miibus);
1043         bus_generic_detach(dev);
1044
1045         if (sc->bce_res_irq != NULL) {
1046                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1047                     sc->bce_res_irq);
1048         }
1049
1050         if (sc->bce_irq_type == BCE_IRQ_TYPE_MSI)
1051                 pci_release_msi(dev);
1052
1053         if (sc->bce_res_mem != NULL) {
1054                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1055                                      sc->bce_res_mem);
1056         }
1057
1058         bce_dma_free(sc);
1059
1060         if (sc->bce_sysctl_tree != NULL)
1061                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1062
1063         return 0;
1064 }
1065
1066
1067 /****************************************************************************/
1068 /* Device shutdown function.                                                */
1069 /*                                                                          */
1070 /* Stops and resets the controller.                                         */
1071 /*                                                                          */
1072 /* Returns:                                                                 */
1073 /*   Nothing                                                                */
1074 /****************************************************************************/
1075 static void
1076 bce_shutdown(device_t dev)
1077 {
1078         struct bce_softc *sc = device_get_softc(dev);
1079         struct ifnet *ifp = &sc->arpcom.ac_if;
1080         uint32_t msg;
1081
1082         lwkt_serialize_enter(ifp->if_serializer);
1083         bce_stop(sc);
1084         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1085                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1086         else
1087                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1088         bce_reset(sc, msg);
1089         lwkt_serialize_exit(ifp->if_serializer);
1090 }
1091
1092
1093 /****************************************************************************/
1094 /* Indirect register read.                                                  */
1095 /*                                                                          */
1096 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1097 /* configuration space.  Using this mechanism avoids issues with posted     */
1098 /* reads but is much slower than memory-mapped I/O.                         */
1099 /*                                                                          */
1100 /* Returns:                                                                 */
1101 /*   The value of the register.                                             */
1102 /****************************************************************************/
1103 static uint32_t
1104 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1105 {
1106         device_t dev = sc->bce_dev;
1107
1108         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1109 #ifdef BCE_DEBUG
1110         {
1111                 uint32_t val;
1112                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1113                 DBPRINT(sc, BCE_EXCESSIVE,
1114                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1115                         __func__, offset, val);
1116                 return val;
1117         }
1118 #else
1119         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1120 #endif
1121 }
1122
1123
1124 /****************************************************************************/
1125 /* Indirect register write.                                                 */
1126 /*                                                                          */
1127 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1128 /* configuration space.  Using this mechanism avoids issues with posted     */
1129 /* writes but is muchh slower than memory-mapped I/O.                       */
1130 /*                                                                          */
1131 /* Returns:                                                                 */
1132 /*   Nothing.                                                               */
1133 /****************************************************************************/
1134 static void
1135 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1136 {
1137         device_t dev = sc->bce_dev;
1138
1139         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1140                 __func__, offset, val);
1141
1142         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1143         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1144 }
1145
1146
1147 /****************************************************************************/
1148 /* Shared memory write.                                                     */
1149 /*                                                                          */
1150 /* Writes NetXtreme II shared memory region.                                */
1151 /*                                                                          */
1152 /* Returns:                                                                 */
1153 /*   Nothing.                                                               */
1154 /****************************************************************************/
1155 static void
1156 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1157 {
1158         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1159 }
1160
1161
1162 /****************************************************************************/
1163 /* Shared memory read.                                                      */
1164 /*                                                                          */
1165 /* Reads NetXtreme II shared memory region.                                 */
1166 /*                                                                          */
1167 /* Returns:                                                                 */
1168 /*   The 32 bit value read.                                                 */
1169 /****************************************************************************/
1170 static u32
1171 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1172 {
1173         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1174 }
1175
1176
1177 /****************************************************************************/
1178 /* Context memory write.                                                    */
1179 /*                                                                          */
1180 /* The NetXtreme II controller uses context memory to track connection      */
1181 /* information for L2 and higher network protocols.                         */
1182 /*                                                                          */
1183 /* Returns:                                                                 */
1184 /*   Nothing.                                                               */
1185 /****************************************************************************/
1186 static void
1187 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1188     uint32_t ctx_val)
1189 {
1190         uint32_t idx, offset = ctx_offset + cid_addr;
1191         uint32_t val, retry_cnt = 5;
1192
1193         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1194             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1195                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1196                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1197
1198                 for (idx = 0; idx < retry_cnt; idx++) {
1199                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1200                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1201                                 break;
1202                         DELAY(5);
1203                 }
1204
1205                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1206                         device_printf(sc->bce_dev,
1207                             "Unable to write CTX memory: "
1208                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1209                             cid_addr, ctx_offset);
1210                 }
1211         } else {
1212                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1213                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1214         }
1215 }
1216
1217
1218 /****************************************************************************/
1219 /* PHY register read.                                                       */
1220 /*                                                                          */
1221 /* Implements register reads on the MII bus.                                */
1222 /*                                                                          */
1223 /* Returns:                                                                 */
1224 /*   The value of the register.                                             */
1225 /****************************************************************************/
1226 static int
1227 bce_miibus_read_reg(device_t dev, int phy, int reg)
1228 {
1229         struct bce_softc *sc = device_get_softc(dev);
1230         uint32_t val;
1231         int i;
1232
1233         /* Make sure we are accessing the correct PHY address. */
1234         if (phy != sc->bce_phy_addr) {
1235                 DBPRINT(sc, BCE_VERBOSE,
1236                         "Invalid PHY address %d for PHY read!\n", phy);
1237                 return 0;
1238         }
1239
1240         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1241                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1242                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1243
1244                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1245                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1246
1247                 DELAY(40);
1248         }
1249
1250         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1251               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1252               BCE_EMAC_MDIO_COMM_START_BUSY;
1253         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1254
1255         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1256                 DELAY(10);
1257
1258                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1259                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1260                         DELAY(5);
1261
1262                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1263                         val &= BCE_EMAC_MDIO_COMM_DATA;
1264                         break;
1265                 }
1266         }
1267
1268         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1269                 if_printf(&sc->arpcom.ac_if,
1270                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1271                           phy, reg);
1272                 val = 0x0;
1273         } else {
1274                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1275         }
1276
1277         DBPRINT(sc, BCE_EXCESSIVE,
1278                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1279                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1280
1281         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1282                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1283                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1284
1285                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1286                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1287
1288                 DELAY(40);
1289         }
1290         return (val & 0xffff);
1291 }
1292
1293
1294 /****************************************************************************/
1295 /* PHY register write.                                                      */
1296 /*                                                                          */
1297 /* Implements register writes on the MII bus.                               */
1298 /*                                                                          */
1299 /* Returns:                                                                 */
1300 /*   The value of the register.                                             */
1301 /****************************************************************************/
1302 static int
1303 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1304 {
1305         struct bce_softc *sc = device_get_softc(dev);
1306         uint32_t val1;
1307         int i;
1308
1309         /* Make sure we are accessing the correct PHY address. */
1310         if (phy != sc->bce_phy_addr) {
1311                 DBPRINT(sc, BCE_WARN,
1312                         "Invalid PHY address %d for PHY write!\n", phy);
1313                 return(0);
1314         }
1315
1316         DBPRINT(sc, BCE_EXCESSIVE,
1317                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1318                 __func__, phy, (uint16_t)(reg & 0xffff),
1319                 (uint16_t)(val & 0xffff));
1320
1321         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1322                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1323                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1324
1325                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1326                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1327
1328                 DELAY(40);
1329         }
1330
1331         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1332                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1333                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1334         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1335
1336         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1337                 DELAY(10);
1338
1339                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1340                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1341                         DELAY(5);
1342                         break;
1343                 }
1344         }
1345
1346         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1347                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1348
1349         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1350                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1351                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1352
1353                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1354                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1355
1356                 DELAY(40);
1357         }
1358         return 0;
1359 }
1360
1361
1362 /****************************************************************************/
1363 /* MII bus status change.                                                   */
1364 /*                                                                          */
1365 /* Called by the MII bus driver when the PHY establishes link to set the    */
1366 /* MAC interface registers.                                                 */
1367 /*                                                                          */
1368 /* Returns:                                                                 */
1369 /*   Nothing.                                                               */
1370 /****************************************************************************/
1371 static void
1372 bce_miibus_statchg(device_t dev)
1373 {
1374         struct bce_softc *sc = device_get_softc(dev);
1375         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1376
1377         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1378                 mii->mii_media_active);
1379
1380 #ifdef BCE_DEBUG
1381         /* Decode the interface media flags. */
1382         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1383         switch(IFM_TYPE(mii->mii_media_active)) {
1384         case IFM_ETHER:
1385                 kprintf("Ethernet )");
1386                 break;
1387         default:
1388                 kprintf("Unknown )");
1389                 break;
1390         }
1391
1392         kprintf(" Media Options: ( ");
1393         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1394         case IFM_AUTO:
1395                 kprintf("Autoselect )");
1396                 break;
1397         case IFM_MANUAL:
1398                 kprintf("Manual )");
1399                 break;
1400         case IFM_NONE:
1401                 kprintf("None )");
1402                 break;
1403         case IFM_10_T:
1404                 kprintf("10Base-T )");
1405                 break;
1406         case IFM_100_TX:
1407                 kprintf("100Base-TX )");
1408                 break;
1409         case IFM_1000_SX:
1410                 kprintf("1000Base-SX )");
1411                 break;
1412         case IFM_1000_T:
1413                 kprintf("1000Base-T )");
1414                 break;
1415         default:
1416                 kprintf("Other )");
1417                 break;
1418         }
1419
1420         kprintf(" Global Options: (");
1421         if (mii->mii_media_active & IFM_FDX)
1422                 kprintf(" FullDuplex");
1423         if (mii->mii_media_active & IFM_HDX)
1424                 kprintf(" HalfDuplex");
1425         if (mii->mii_media_active & IFM_LOOP)
1426                 kprintf(" Loopback");
1427         if (mii->mii_media_active & IFM_FLAG0)
1428                 kprintf(" Flag0");
1429         if (mii->mii_media_active & IFM_FLAG1)
1430                 kprintf(" Flag1");
1431         if (mii->mii_media_active & IFM_FLAG2)
1432                 kprintf(" Flag2");
1433         kprintf(" )\n");
1434 #endif
1435
1436         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1437
1438         /*
1439          * Set MII or GMII interface based on the speed negotiated
1440          * by the PHY.
1441          */
1442         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1443             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1444                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1445                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1446         } else {
1447                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1448                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1449         }
1450
1451         /*
1452          * Set half or full duplex based on the duplicity negotiated
1453          * by the PHY.
1454          */
1455         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1456                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1457                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1458         } else {
1459                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1460                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1461         }
1462 }
1463
1464
1465 /****************************************************************************/
1466 /* Acquire NVRAM lock.                                                      */
1467 /*                                                                          */
1468 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1469 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1470 /* for use by the driver.                                                   */
1471 /*                                                                          */
1472 /* Returns:                                                                 */
1473 /*   0 on success, positive value on failure.                               */
1474 /****************************************************************************/
1475 static int
1476 bce_acquire_nvram_lock(struct bce_softc *sc)
1477 {
1478         uint32_t val;
1479         int j;
1480
1481         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1482
1483         /* Request access to the flash interface. */
1484         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1485         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1486                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1487                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1488                         break;
1489
1490                 DELAY(5);
1491         }
1492
1493         if (j >= NVRAM_TIMEOUT_COUNT) {
1494                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1495                 return EBUSY;
1496         }
1497         return 0;
1498 }
1499
1500
1501 /****************************************************************************/
1502 /* Release NVRAM lock.                                                      */
1503 /*                                                                          */
1504 /* When the caller is finished accessing NVRAM the lock must be released.   */
1505 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1506 /* for use by the driver.                                                   */
1507 /*                                                                          */
1508 /* Returns:                                                                 */
1509 /*   0 on success, positive value on failure.                               */
1510 /****************************************************************************/
1511 static int
1512 bce_release_nvram_lock(struct bce_softc *sc)
1513 {
1514         int j;
1515         uint32_t val;
1516
1517         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1518
1519         /*
1520          * Relinquish nvram interface.
1521          */
1522         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1523
1524         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1525                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1526                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1527                         break;
1528
1529                 DELAY(5);
1530         }
1531
1532         if (j >= NVRAM_TIMEOUT_COUNT) {
1533                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1534                 return EBUSY;
1535         }
1536         return 0;
1537 }
1538
1539
1540 /****************************************************************************/
1541 /* Enable NVRAM access.                                                     */
1542 /*                                                                          */
1543 /* Before accessing NVRAM for read or write operations the caller must      */
1544 /* enabled NVRAM access.                                                    */
1545 /*                                                                          */
1546 /* Returns:                                                                 */
1547 /*   Nothing.                                                               */
1548 /****************************************************************************/
1549 static void
1550 bce_enable_nvram_access(struct bce_softc *sc)
1551 {
1552         uint32_t val;
1553
1554         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1555
1556         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1557         /* Enable both bits, even on read. */
1558         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1559                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1560 }
1561
1562
1563 /****************************************************************************/
1564 /* Disable NVRAM access.                                                    */
1565 /*                                                                          */
1566 /* When the caller is finished accessing NVRAM access must be disabled.     */
1567 /*                                                                          */
1568 /* Returns:                                                                 */
1569 /*   Nothing.                                                               */
1570 /****************************************************************************/
1571 static void
1572 bce_disable_nvram_access(struct bce_softc *sc)
1573 {
1574         uint32_t val;
1575
1576         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1577
1578         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1579
1580         /* Disable both bits, even after read. */
1581         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1582                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1583 }
1584
1585
1586 /****************************************************************************/
1587 /* Read a dword (32 bits) from NVRAM.                                       */
1588 /*                                                                          */
1589 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1590 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1591 /*                                                                          */
1592 /* Returns:                                                                 */
1593 /*   0 on success and the 32 bit value read, positive value on failure.     */
1594 /****************************************************************************/
1595 static int
1596 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1597                      uint32_t cmd_flags)
1598 {
1599         uint32_t cmd;
1600         int i, rc = 0;
1601
1602         /* Build the command word. */
1603         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1604
1605         /* Calculate the offset for buffered flash. */
1606         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1607                 offset = ((offset / sc->bce_flash_info->page_size) <<
1608                           sc->bce_flash_info->page_bits) +
1609                          (offset % sc->bce_flash_info->page_size);
1610         }
1611
1612         /*
1613          * Clear the DONE bit separately, set the address to read,
1614          * and issue the read.
1615          */
1616         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1617         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1618         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1619
1620         /* Wait for completion. */
1621         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1622                 uint32_t val;
1623
1624                 DELAY(5);
1625
1626                 val = REG_RD(sc, BCE_NVM_COMMAND);
1627                 if (val & BCE_NVM_COMMAND_DONE) {
1628                         val = REG_RD(sc, BCE_NVM_READ);
1629
1630                         val = be32toh(val);
1631                         memcpy(ret_val, &val, 4);
1632                         break;
1633                 }
1634         }
1635
1636         /* Check for errors. */
1637         if (i >= NVRAM_TIMEOUT_COUNT) {
1638                 if_printf(&sc->arpcom.ac_if,
1639                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1640                           offset);
1641                 rc = EBUSY;
1642         }
1643         return rc;
1644 }
1645
1646
1647 /****************************************************************************/
1648 /* Initialize NVRAM access.                                                 */
1649 /*                                                                          */
1650 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1651 /* access that device.                                                      */
1652 /*                                                                          */
1653 /* Returns:                                                                 */
1654 /*   0 on success, positive value on failure.                               */
1655 /****************************************************************************/
1656 static int
1657 bce_init_nvram(struct bce_softc *sc)
1658 {
1659         uint32_t val;
1660         int j, entry_count, rc = 0;
1661         const struct flash_spec *flash;
1662
1663         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1664
1665         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1666             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1667                 sc->bce_flash_info = &flash_5709;
1668                 goto bce_init_nvram_get_flash_size;
1669         }
1670
1671         /* Determine the selected interface. */
1672         val = REG_RD(sc, BCE_NVM_CFG1);
1673
1674         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1675
1676         /*
1677          * Flash reconfiguration is required to support additional
1678          * NVRAM devices not directly supported in hardware.
1679          * Check if the flash interface was reconfigured
1680          * by the bootcode.
1681          */
1682
1683         if (val & 0x40000000) {
1684                 /* Flash interface reconfigured by bootcode. */
1685
1686                 DBPRINT(sc, BCE_INFO_LOAD,
1687                         "%s(): Flash WAS reconfigured.\n", __func__);
1688
1689                 for (j = 0, flash = flash_table; j < entry_count;
1690                      j++, flash++) {
1691                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1692                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1693                                 sc->bce_flash_info = flash;
1694                                 break;
1695                         }
1696                 }
1697         } else {
1698                 /* Flash interface not yet reconfigured. */
1699                 uint32_t mask;
1700
1701                 DBPRINT(sc, BCE_INFO_LOAD,
1702                         "%s(): Flash was NOT reconfigured.\n", __func__);
1703
1704                 if (val & (1 << 23))
1705                         mask = FLASH_BACKUP_STRAP_MASK;
1706                 else
1707                         mask = FLASH_STRAP_MASK;
1708
1709                 /* Look for the matching NVRAM device configuration data. */
1710                 for (j = 0, flash = flash_table; j < entry_count;
1711                      j++, flash++) {
1712                         /* Check if the device matches any of the known devices. */
1713                         if ((val & mask) == (flash->strapping & mask)) {
1714                                 /* Found a device match. */
1715                                 sc->bce_flash_info = flash;
1716
1717                                 /* Request access to the flash interface. */
1718                                 rc = bce_acquire_nvram_lock(sc);
1719                                 if (rc != 0)
1720                                         return rc;
1721
1722                                 /* Reconfigure the flash interface. */
1723                                 bce_enable_nvram_access(sc);
1724                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1725                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1726                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1727                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1728                                 bce_disable_nvram_access(sc);
1729                                 bce_release_nvram_lock(sc);
1730                                 break;
1731                         }
1732                 }
1733         }
1734
1735         /* Check if a matching device was found. */
1736         if (j == entry_count) {
1737                 sc->bce_flash_info = NULL;
1738                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1739                 return ENODEV;
1740         }
1741
1742 bce_init_nvram_get_flash_size:
1743         /* Write the flash config data to the shared memory interface. */
1744         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1745             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1746         if (val)
1747                 sc->bce_flash_size = val;
1748         else
1749                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1750
1751         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1752                 __func__, sc->bce_flash_info->total_size);
1753
1754         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1755
1756         return rc;
1757 }
1758
1759
1760 /****************************************************************************/
1761 /* Read an arbitrary range of data from NVRAM.                              */
1762 /*                                                                          */
1763 /* Prepares the NVRAM interface for access and reads the requested data     */
1764 /* into the supplied buffer.                                                */
1765 /*                                                                          */
1766 /* Returns:                                                                 */
1767 /*   0 on success and the data read, positive value on failure.             */
1768 /****************************************************************************/
1769 static int
1770 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1771                int buf_size)
1772 {
1773         uint32_t cmd_flags, offset32, len32, extra;
1774         int rc = 0;
1775
1776         if (buf_size == 0)
1777                 return 0;
1778
1779         /* Request access to the flash interface. */
1780         rc = bce_acquire_nvram_lock(sc);
1781         if (rc != 0)
1782                 return rc;
1783
1784         /* Enable access to flash interface */
1785         bce_enable_nvram_access(sc);
1786
1787         len32 = buf_size;
1788         offset32 = offset;
1789         extra = 0;
1790
1791         cmd_flags = 0;
1792
1793         /* XXX should we release nvram lock if read_dword() fails? */
1794         if (offset32 & 3) {
1795                 uint8_t buf[4];
1796                 uint32_t pre_len;
1797
1798                 offset32 &= ~3;
1799                 pre_len = 4 - (offset & 3);
1800
1801                 if (pre_len >= len32) {
1802                         pre_len = len32;
1803                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1804                 } else {
1805                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1806                 }
1807
1808                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1809                 if (rc)
1810                         return rc;
1811
1812                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1813
1814                 offset32 += 4;
1815                 ret_buf += pre_len;
1816                 len32 -= pre_len;
1817         }
1818
1819         if (len32 & 3) {
1820                 extra = 4 - (len32 & 3);
1821                 len32 = (len32 + 4) & ~3;
1822         }
1823
1824         if (len32 == 4) {
1825                 uint8_t buf[4];
1826
1827                 if (cmd_flags)
1828                         cmd_flags = BCE_NVM_COMMAND_LAST;
1829                 else
1830                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1831                                     BCE_NVM_COMMAND_LAST;
1832
1833                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1834
1835                 memcpy(ret_buf, buf, 4 - extra);
1836         } else if (len32 > 0) {
1837                 uint8_t buf[4];
1838
1839                 /* Read the first word. */
1840                 if (cmd_flags)
1841                         cmd_flags = 0;
1842                 else
1843                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1844
1845                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1846
1847                 /* Advance to the next dword. */
1848                 offset32 += 4;
1849                 ret_buf += 4;
1850                 len32 -= 4;
1851
1852                 while (len32 > 4 && rc == 0) {
1853                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1854
1855                         /* Advance to the next dword. */
1856                         offset32 += 4;
1857                         ret_buf += 4;
1858                         len32 -= 4;
1859                 }
1860
1861                 if (rc)
1862                         goto bce_nvram_read_locked_exit;
1863
1864                 cmd_flags = BCE_NVM_COMMAND_LAST;
1865                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1866
1867                 memcpy(ret_buf, buf, 4 - extra);
1868         }
1869
1870 bce_nvram_read_locked_exit:
1871         /* Disable access to flash interface and release the lock. */
1872         bce_disable_nvram_access(sc);
1873         bce_release_nvram_lock(sc);
1874
1875         return rc;
1876 }
1877
1878
1879 /****************************************************************************/
1880 /* Verifies that NVRAM is accessible and contains valid data.               */
1881 /*                                                                          */
1882 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1883 /* correct.                                                                 */
1884 /*                                                                          */
1885 /* Returns:                                                                 */
1886 /*   0 on success, positive value on failure.                               */
1887 /****************************************************************************/
1888 static int
1889 bce_nvram_test(struct bce_softc *sc)
1890 {
1891         uint32_t buf[BCE_NVRAM_SIZE / 4];
1892         uint32_t magic, csum;
1893         uint8_t *data = (uint8_t *)buf;
1894         int rc = 0;
1895
1896         /*
1897          * Check that the device NVRAM is valid by reading
1898          * the magic value at offset 0.
1899          */
1900         rc = bce_nvram_read(sc, 0, data, 4);
1901         if (rc != 0)
1902                 return rc;
1903
1904         magic = be32toh(buf[0]);
1905         if (magic != BCE_NVRAM_MAGIC) {
1906                 if_printf(&sc->arpcom.ac_if,
1907                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1908                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1909                 return ENODEV;
1910         }
1911
1912         /*
1913          * Verify that the device NVRAM includes valid
1914          * configuration data.
1915          */
1916         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1917         if (rc != 0)
1918                 return rc;
1919
1920         csum = ether_crc32_le(data, 0x100);
1921         if (csum != BCE_CRC32_RESIDUAL) {
1922                 if_printf(&sc->arpcom.ac_if,
1923                           "Invalid Manufacturing Information NVRAM CRC! "
1924                           "Expected: 0x%08X, Found: 0x%08X\n",
1925                           BCE_CRC32_RESIDUAL, csum);
1926                 return ENODEV;
1927         }
1928
1929         csum = ether_crc32_le(data + 0x100, 0x100);
1930         if (csum != BCE_CRC32_RESIDUAL) {
1931                 if_printf(&sc->arpcom.ac_if,
1932                           "Invalid Feature Configuration Information "
1933                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1934                           BCE_CRC32_RESIDUAL, csum);
1935                 rc = ENODEV;
1936         }
1937         return rc;
1938 }
1939
1940
1941 /****************************************************************************/
1942 /* Identifies the current media type of the controller and sets the PHY     */
1943 /* address.                                                                 */
1944 /*                                                                          */
1945 /* Returns:                                                                 */
1946 /*   Nothing.                                                               */
1947 /****************************************************************************/
1948 static void
1949 bce_get_media(struct bce_softc *sc)
1950 {
1951         uint32_t val;
1952
1953         sc->bce_phy_addr = 1;
1954
1955         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1956             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1957                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1958                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1959                 uint32_t strap;
1960
1961                 /*
1962                  * The BCM5709S is software configurable
1963                  * for Copper or SerDes operation.
1964                  */
1965                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1966                         return;
1967                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1968                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1969                         return;
1970                 }
1971
1972                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1973                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1974                 } else {
1975                         strap =
1976                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1977                 }
1978
1979                 if (pci_get_function(sc->bce_dev) == 0) {
1980                         switch (strap) {
1981                         case 0x4:
1982                         case 0x5:
1983                         case 0x6:
1984                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1985                                 break;
1986                         }
1987                 } else {
1988                         switch (strap) {
1989                         case 0x1:
1990                         case 0x2:
1991                         case 0x4:
1992                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1993                                 break;
1994                         }
1995                 }
1996         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1997                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1998         }
1999
2000         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2001                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2002                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2003                         sc->bce_phy_addr = 2;
2004                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2005                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2006                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2007                 }
2008         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2009             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2010                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2011         }
2012 }
2013
2014
2015 /****************************************************************************/
2016 /* Free any DMA memory owned by the driver.                                 */
2017 /*                                                                          */
2018 /* Scans through each data structre that requires DMA memory and frees      */
2019 /* the memory if allocated.                                                 */
2020 /*                                                                          */
2021 /* Returns:                                                                 */
2022 /*   Nothing.                                                               */
2023 /****************************************************************************/
2024 static void
2025 bce_dma_free(struct bce_softc *sc)
2026 {
2027         int i;
2028
2029         /* Destroy the status block. */
2030         if (sc->status_tag != NULL) {
2031                 if (sc->status_block != NULL) {
2032                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2033                         bus_dmamem_free(sc->status_tag, sc->status_block,
2034                                         sc->status_map);
2035                 }
2036                 bus_dma_tag_destroy(sc->status_tag);
2037         }
2038
2039
2040         /* Destroy the statistics block. */
2041         if (sc->stats_tag != NULL) {
2042                 if (sc->stats_block != NULL) {
2043                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2044                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2045                                         sc->stats_map);
2046                 }
2047                 bus_dma_tag_destroy(sc->stats_tag);
2048         }
2049
2050         /* Destroy the CTX DMA stuffs. */
2051         if (sc->ctx_tag != NULL) {
2052                 for (i = 0; i < sc->ctx_pages; i++) {
2053                         if (sc->ctx_block[i] != NULL) {
2054                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2055                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2056                                                 sc->ctx_map[i]);
2057                         }
2058                 }
2059                 bus_dma_tag_destroy(sc->ctx_tag);
2060         }
2061
2062         /* Destroy the TX buffer descriptor DMA stuffs. */
2063         if (sc->tx_bd_chain_tag != NULL) {
2064                 for (i = 0; i < TX_PAGES; i++) {
2065                         if (sc->tx_bd_chain[i] != NULL) {
2066                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2067                                                   sc->tx_bd_chain_map[i]);
2068                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2069                                                 sc->tx_bd_chain[i],
2070                                                 sc->tx_bd_chain_map[i]);
2071                         }
2072                 }
2073                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2074         }
2075
2076         /* Destroy the RX buffer descriptor DMA stuffs. */
2077         if (sc->rx_bd_chain_tag != NULL) {
2078                 for (i = 0; i < RX_PAGES; i++) {
2079                         if (sc->rx_bd_chain[i] != NULL) {
2080                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2081                                                   sc->rx_bd_chain_map[i]);
2082                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2083                                                 sc->rx_bd_chain[i],
2084                                                 sc->rx_bd_chain_map[i]);
2085                         }
2086                 }
2087                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2088         }
2089
2090         /* Destroy the TX mbuf DMA stuffs. */
2091         if (sc->tx_mbuf_tag != NULL) {
2092                 for (i = 0; i < TOTAL_TX_BD; i++) {
2093                         /* Must have been unloaded in bce_stop() */
2094                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2095                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2096                                            sc->tx_mbuf_map[i]);
2097                 }
2098                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2099         }
2100
2101         /* Destroy the RX mbuf DMA stuffs. */
2102         if (sc->rx_mbuf_tag != NULL) {
2103                 for (i = 0; i < TOTAL_RX_BD; i++) {
2104                         /* Must have been unloaded in bce_stop() */
2105                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2106                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2107                                            sc->rx_mbuf_map[i]);
2108                 }
2109                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2110                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2111         }
2112
2113         /* Destroy the parent tag */
2114         if (sc->parent_tag != NULL)
2115                 bus_dma_tag_destroy(sc->parent_tag);
2116 }
2117
2118
2119 /****************************************************************************/
2120 /* Get DMA memory from the OS.                                              */
2121 /*                                                                          */
2122 /* Validates that the OS has provided DMA buffers in response to a          */
2123 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2124 /* When the callback is used the OS will return 0 for the mapping function  */
2125 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2126 /* failures back to the caller.                                             */
2127 /*                                                                          */
2128 /* Returns:                                                                 */
2129 /*   Nothing.                                                               */
2130 /****************************************************************************/
2131 static void
2132 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2133 {
2134         bus_addr_t *busaddr = arg;
2135
2136         /*
2137          * Simulate a mapping failure.
2138          * XXX not correct.
2139          */
2140         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2141                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2142                         __FILE__, __LINE__);
2143                 error = ENOMEM);
2144
2145         /* Check for an error and signal the caller that an error occurred. */
2146         if (error)
2147                 return;
2148
2149         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2150         *busaddr = segs->ds_addr;
2151 }
2152
2153
2154 /****************************************************************************/
2155 /* Allocate any DMA memory needed by the driver.                            */
2156 /*                                                                          */
2157 /* Allocates DMA memory needed for the various global structures needed by  */
2158 /* hardware.                                                                */
2159 /*                                                                          */
2160 /* Memory alignment requirements:                                           */
2161 /* -----------------+----------+----------+----------+----------+           */
2162 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2163 /* -----------------+----------+----------+----------+----------+           */
2164 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2165 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2166 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2167 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2168 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2169 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2170 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2171 /* -----------------+----------+----------+----------+----------+           */
2172 /*                                                                          */
2173 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2174 /*                                                                          */
2175 /* Returns:                                                                 */
2176 /*   0 for success, positive value for failure.                             */
2177 /****************************************************************************/
2178 static int
2179 bce_dma_alloc(struct bce_softc *sc)
2180 {
2181         struct ifnet *ifp = &sc->arpcom.ac_if;
2182         int i, j, rc = 0;
2183         bus_addr_t busaddr, max_busaddr;
2184         bus_size_t status_align, stats_align;
2185
2186         /*
2187          * The embedded PCIe to PCI-X bridge (EPB)
2188          * in the 5708 cannot address memory above
2189          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2190          */
2191         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2192                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2193         else
2194                 max_busaddr = BUS_SPACE_MAXADDR;
2195
2196         /*
2197          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2198          */
2199         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2200             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2201                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2202                 if (sc->ctx_pages == 0)
2203                         sc->ctx_pages = 1;
2204                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2205                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2206                             sc->ctx_pages);
2207                         return ENOMEM;
2208                 }
2209                 status_align = 16;
2210                 stats_align = 16;
2211         } else {
2212                 status_align = 8;
2213                 stats_align = 8;
2214         }
2215
2216         /*
2217          * Allocate the parent bus DMA tag appropriate for PCI.
2218          */
2219         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2220                                 max_busaddr, BUS_SPACE_MAXADDR,
2221                                 NULL, NULL,
2222                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2223                                 BUS_SPACE_MAXSIZE_32BIT,
2224                                 0, &sc->parent_tag);
2225         if (rc != 0) {
2226                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2227                 return rc;
2228         }
2229
2230         /*
2231          * Allocate status block.
2232          */
2233         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2234                                 status_align, BCE_STATUS_BLK_SZ,
2235                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2236                                 &sc->status_tag, &sc->status_map,
2237                                 &sc->status_block_paddr);
2238         if (sc->status_block == NULL) {
2239                 if_printf(ifp, "Could not allocate status block!\n");
2240                 return ENOMEM;
2241         }
2242
2243         /*
2244          * Allocate statistics block.
2245          */
2246         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2247                                 stats_align, BCE_STATS_BLK_SZ,
2248                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2249                                 &sc->stats_tag, &sc->stats_map,
2250                                 &sc->stats_block_paddr);
2251         if (sc->stats_block == NULL) {
2252                 if_printf(ifp, "Could not allocate statistics block!\n");
2253                 return ENOMEM;
2254         }
2255
2256         /*
2257          * Allocate context block, if needed
2258          */
2259         if (sc->ctx_pages != 0) {
2260                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2261                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2262                                         NULL, NULL,
2263                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2264                                         0, &sc->ctx_tag);
2265                 if (rc != 0) {
2266                         if_printf(ifp, "Could not allocate "
2267                                   "context block DMA tag!\n");
2268                         return rc;
2269                 }
2270
2271                 for (i = 0; i < sc->ctx_pages; i++) {
2272                         rc = bus_dmamem_alloc(sc->ctx_tag,
2273                                               (void **)&sc->ctx_block[i],
2274                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2275                                               BUS_DMA_COHERENT,
2276                                               &sc->ctx_map[i]);
2277                         if (rc != 0) {
2278                                 if_printf(ifp, "Could not allocate %dth context "
2279                                           "DMA memory!\n", i);
2280                                 return rc;
2281                         }
2282
2283                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2284                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2285                                              bce_dma_map_addr, &busaddr,
2286                                              BUS_DMA_WAITOK);
2287                         if (rc != 0) {
2288                                 if (rc == EINPROGRESS) {
2289                                         panic("%s coherent memory loading "
2290                                               "is still in progress!", ifp->if_xname);
2291                                 }
2292                                 if_printf(ifp, "Could not map %dth context "
2293                                           "DMA memory!\n", i);
2294                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2295                                                 sc->ctx_map[i]);
2296                                 sc->ctx_block[i] = NULL;
2297                                 return rc;
2298                         }
2299                         sc->ctx_paddr[i] = busaddr;
2300                 }
2301         }
2302
2303         /*
2304          * Create a DMA tag for the TX buffer descriptor chain,
2305          * allocate and clear the  memory, and fetch the
2306          * physical address of the block.
2307          */
2308         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2309                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2310                                 NULL, NULL,
2311                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2312                                 0, &sc->tx_bd_chain_tag);
2313         if (rc != 0) {
2314                 if_printf(ifp, "Could not allocate "
2315                           "TX descriptor chain DMA tag!\n");
2316                 return rc;
2317         }
2318
2319         for (i = 0; i < TX_PAGES; i++) {
2320                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2321                                       (void **)&sc->tx_bd_chain[i],
2322                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2323                                       BUS_DMA_COHERENT,
2324                                       &sc->tx_bd_chain_map[i]);
2325                 if (rc != 0) {
2326                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2327                                   "chain DMA memory!\n", i);
2328                         return rc;
2329                 }
2330
2331                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2332                                      sc->tx_bd_chain_map[i],
2333                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2334                                      bce_dma_map_addr, &busaddr,
2335                                      BUS_DMA_WAITOK);
2336                 if (rc != 0) {
2337                         if (rc == EINPROGRESS) {
2338                                 panic("%s coherent memory loading "
2339                                       "is still in progress!", ifp->if_xname);
2340                         }
2341                         if_printf(ifp, "Could not map %dth TX descriptor "
2342                                   "chain DMA memory!\n", i);
2343                         bus_dmamem_free(sc->tx_bd_chain_tag,
2344                                         sc->tx_bd_chain[i],
2345                                         sc->tx_bd_chain_map[i]);
2346                         sc->tx_bd_chain[i] = NULL;
2347                         return rc;
2348                 }
2349
2350                 sc->tx_bd_chain_paddr[i] = busaddr;
2351                 /* DRC - Fix for 64 bit systems. */
2352                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2353                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2354         }
2355
2356         /* Create a DMA tag for TX mbufs. */
2357         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2358                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2359                                 NULL, NULL,
2360                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2361                                 BCE_MAX_SEGMENTS, MCLBYTES,
2362                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2363                                 BUS_DMA_ONEBPAGE,
2364                                 &sc->tx_mbuf_tag);
2365         if (rc != 0) {
2366                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2367                 return rc;
2368         }
2369
2370         /* Create DMA maps for the TX mbufs clusters. */
2371         for (i = 0; i < TOTAL_TX_BD; i++) {
2372                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2373                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2374                                        &sc->tx_mbuf_map[i]);
2375                 if (rc != 0) {
2376                         for (j = 0; j < i; ++j) {
2377                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2378                                                    sc->tx_mbuf_map[i]);
2379                         }
2380                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2381                         sc->tx_mbuf_tag = NULL;
2382
2383                         if_printf(ifp, "Unable to create "
2384                                   "%dth TX mbuf DMA map!\n", i);
2385                         return rc;
2386                 }
2387         }
2388
2389         /*
2390          * Create a DMA tag for the RX buffer descriptor chain,
2391          * allocate and clear the  memory, and fetch the physical
2392          * address of the blocks.
2393          */
2394         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2395                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2396                                 NULL, NULL,
2397                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2398                                 0, &sc->rx_bd_chain_tag);
2399         if (rc != 0) {
2400                 if_printf(ifp, "Could not allocate "
2401                           "RX descriptor chain DMA tag!\n");
2402                 return rc;
2403         }
2404
2405         for (i = 0; i < RX_PAGES; i++) {
2406                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2407                                       (void **)&sc->rx_bd_chain[i],
2408                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2409                                       BUS_DMA_COHERENT,
2410                                       &sc->rx_bd_chain_map[i]);
2411                 if (rc != 0) {
2412                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2413                                   "chain DMA memory!\n", i);
2414                         return rc;
2415                 }
2416
2417                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2418                                      sc->rx_bd_chain_map[i],
2419                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2420                                      bce_dma_map_addr, &busaddr,
2421                                      BUS_DMA_WAITOK);
2422                 if (rc != 0) {
2423                         if (rc == EINPROGRESS) {
2424                                 panic("%s coherent memory loading "
2425                                       "is still in progress!", ifp->if_xname);
2426                         }
2427                         if_printf(ifp, "Could not map %dth RX descriptor "
2428                                   "chain DMA memory!\n", i);
2429                         bus_dmamem_free(sc->rx_bd_chain_tag,
2430                                         sc->rx_bd_chain[i],
2431                                         sc->rx_bd_chain_map[i]);
2432                         sc->rx_bd_chain[i] = NULL;
2433                         return rc;
2434                 }
2435
2436                 sc->rx_bd_chain_paddr[i] = busaddr;
2437                 /* DRC - Fix for 64 bit systems. */
2438                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2439                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2440         }
2441
2442         /* Create a DMA tag for RX mbufs. */
2443         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2444                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2445                                 NULL, NULL,
2446                                 MCLBYTES, 1, MCLBYTES,
2447                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2448                                 BUS_DMA_WAITOK,
2449                                 &sc->rx_mbuf_tag);
2450         if (rc != 0) {
2451                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2452                 return rc;
2453         }
2454
2455         /* Create tmp DMA map for RX mbuf clusters. */
2456         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2457                                &sc->rx_mbuf_tmpmap);
2458         if (rc != 0) {
2459                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2460                 sc->rx_mbuf_tag = NULL;
2461
2462                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2463                 return rc;
2464         }
2465
2466         /* Create DMA maps for the RX mbuf clusters. */
2467         for (i = 0; i < TOTAL_RX_BD; i++) {
2468                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2469                                        &sc->rx_mbuf_map[i]);
2470                 if (rc != 0) {
2471                         for (j = 0; j < i; ++j) {
2472                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2473                                                    sc->rx_mbuf_map[j]);
2474                         }
2475                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2476                         sc->rx_mbuf_tag = NULL;
2477
2478                         if_printf(ifp, "Unable to create "
2479                                   "%dth RX mbuf DMA map!\n", i);
2480                         return rc;
2481                 }
2482         }
2483         return 0;
2484 }
2485
2486
2487 /****************************************************************************/
2488 /* Firmware synchronization.                                                */
2489 /*                                                                          */
2490 /* Before performing certain events such as a chip reset, synchronize with  */
2491 /* the firmware first.                                                      */
2492 /*                                                                          */
2493 /* Returns:                                                                 */
2494 /*   0 for success, positive value for failure.                             */
2495 /****************************************************************************/
2496 static int
2497 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2498 {
2499         int i, rc = 0;
2500         uint32_t val;
2501
2502         /* Don't waste any time if we've timed out before. */
2503         if (sc->bce_fw_timed_out)
2504                 return EBUSY;
2505
2506         /* Increment the message sequence number. */
2507         sc->bce_fw_wr_seq++;
2508         msg_data |= sc->bce_fw_wr_seq;
2509
2510         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2511
2512         /* Send the message to the bootcode driver mailbox. */
2513         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2514
2515         /* Wait for the bootcode to acknowledge the message. */
2516         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2517                 /* Check for a response in the bootcode firmware mailbox. */
2518                 val = bce_shmem_rd(sc, BCE_FW_MB);
2519                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2520                         break;
2521                 DELAY(1000);
2522         }
2523
2524         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2525         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2526             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2527                 if_printf(&sc->arpcom.ac_if,
2528                           "Firmware synchronization timeout! "
2529                           "msg_data = 0x%08X\n", msg_data);
2530
2531                 msg_data &= ~BCE_DRV_MSG_CODE;
2532                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2533
2534                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2535
2536                 sc->bce_fw_timed_out = 1;
2537                 rc = EBUSY;
2538         }
2539         return rc;
2540 }
2541
2542
2543 /****************************************************************************/
2544 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2545 /*                                                                          */
2546 /* Returns:                                                                 */
2547 /*   Nothing.                                                               */
2548 /****************************************************************************/
2549 static void
2550 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2551                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2552 {
2553         int i;
2554         uint32_t val;
2555
2556         for (i = 0; i < rv2p_code_len; i += 8) {
2557                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2558                 rv2p_code++;
2559                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2560                 rv2p_code++;
2561
2562                 if (rv2p_proc == RV2P_PROC1) {
2563                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2564                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2565                 } else {
2566                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2567                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2568                 }
2569         }
2570
2571         /* Reset the processor, un-stall is done later. */
2572         if (rv2p_proc == RV2P_PROC1)
2573                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2574         else
2575                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2576 }
2577
2578
2579 /****************************************************************************/
2580 /* Load RISC processor firmware.                                            */
2581 /*                                                                          */
2582 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2583 /* associated with a particular processor.                                  */
2584 /*                                                                          */
2585 /* Returns:                                                                 */
2586 /*   Nothing.                                                               */
2587 /****************************************************************************/
2588 static void
2589 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2590                 struct fw_info *fw)
2591 {
2592         uint32_t offset;
2593         int j;
2594
2595         bce_halt_cpu(sc, cpu_reg);
2596
2597         /* Load the Text area. */
2598         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2599         if (fw->text) {
2600                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2601                         REG_WR_IND(sc, offset, fw->text[j]);
2602         }
2603
2604         /* Load the Data area. */
2605         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2606         if (fw->data) {
2607                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2608                         REG_WR_IND(sc, offset, fw->data[j]);
2609         }
2610
2611         /* Load the SBSS area. */
2612         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2613         if (fw->sbss) {
2614                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2615                         REG_WR_IND(sc, offset, fw->sbss[j]);
2616         }
2617
2618         /* Load the BSS area. */
2619         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2620         if (fw->bss) {
2621                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2622                         REG_WR_IND(sc, offset, fw->bss[j]);
2623         }
2624
2625         /* Load the Read-Only area. */
2626         offset = cpu_reg->spad_base +
2627                 (fw->rodata_addr - cpu_reg->mips_view_base);
2628         if (fw->rodata) {
2629                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2630                         REG_WR_IND(sc, offset, fw->rodata[j]);
2631         }
2632
2633         /* Clear the pre-fetch instruction and set the FW start address. */
2634         REG_WR_IND(sc, cpu_reg->inst, 0);
2635         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2636 }
2637
2638
2639 /****************************************************************************/
2640 /* Starts the RISC processor.                                               */
2641 /*                                                                          */
2642 /* Assumes the CPU starting address has already been set.                   */
2643 /*                                                                          */
2644 /* Returns:                                                                 */
2645 /*   Nothing.                                                               */
2646 /****************************************************************************/
2647 static void
2648 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2649 {
2650         uint32_t val;
2651
2652         /* Start the CPU. */
2653         val = REG_RD_IND(sc, cpu_reg->mode);
2654         val &= ~cpu_reg->mode_value_halt;
2655         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2656         REG_WR_IND(sc, cpu_reg->mode, val);
2657 }
2658
2659
2660 /****************************************************************************/
2661 /* Halts the RISC processor.                                                */
2662 /*                                                                          */
2663 /* Returns:                                                                 */
2664 /*   Nothing.                                                               */
2665 /****************************************************************************/
2666 static void
2667 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2668 {
2669         uint32_t val;
2670
2671         /* Halt the CPU. */
2672         val = REG_RD_IND(sc, cpu_reg->mode);
2673         val |= cpu_reg->mode_value_halt;
2674         REG_WR_IND(sc, cpu_reg->mode, val);
2675         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2676 }
2677
2678
2679 /****************************************************************************/
2680 /* Start the RX CPU.                                                        */
2681 /*                                                                          */
2682 /* Returns:                                                                 */
2683 /*   Nothing.                                                               */
2684 /****************************************************************************/
2685 static void
2686 bce_start_rxp_cpu(struct bce_softc *sc)
2687 {
2688         struct cpu_reg cpu_reg;
2689
2690         cpu_reg.mode = BCE_RXP_CPU_MODE;
2691         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2692         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2693         cpu_reg.state = BCE_RXP_CPU_STATE;
2694         cpu_reg.state_value_clear = 0xffffff;
2695         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2696         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2697         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2698         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2699         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2700         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2701         cpu_reg.mips_view_base = 0x8000000;
2702
2703         bce_start_cpu(sc, &cpu_reg);
2704 }
2705
2706
2707 /****************************************************************************/
2708 /* Initialize the RX CPU.                                                   */
2709 /*                                                                          */
2710 /* Returns:                                                                 */
2711 /*   Nothing.                                                               */
2712 /****************************************************************************/
2713 static void
2714 bce_init_rxp_cpu(struct bce_softc *sc)
2715 {
2716         struct cpu_reg cpu_reg;
2717         struct fw_info fw;
2718
2719         cpu_reg.mode = BCE_RXP_CPU_MODE;
2720         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2721         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2722         cpu_reg.state = BCE_RXP_CPU_STATE;
2723         cpu_reg.state_value_clear = 0xffffff;
2724         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2725         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2726         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2727         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2728         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2729         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2730         cpu_reg.mips_view_base = 0x8000000;
2731
2732         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2733             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2734                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2735                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2736                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2737                 fw.start_addr = bce_RXP_b09FwStartAddr;
2738
2739                 fw.text_addr = bce_RXP_b09FwTextAddr;
2740                 fw.text_len = bce_RXP_b09FwTextLen;
2741                 fw.text_index = 0;
2742                 fw.text = bce_RXP_b09FwText;
2743
2744                 fw.data_addr = bce_RXP_b09FwDataAddr;
2745                 fw.data_len = bce_RXP_b09FwDataLen;
2746                 fw.data_index = 0;
2747                 fw.data = bce_RXP_b09FwData;
2748
2749                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2750                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2751                 fw.sbss_index = 0;
2752                 fw.sbss = bce_RXP_b09FwSbss;
2753
2754                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2755                 fw.bss_len = bce_RXP_b09FwBssLen;
2756                 fw.bss_index = 0;
2757                 fw.bss = bce_RXP_b09FwBss;
2758
2759                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2760                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2761                 fw.rodata_index = 0;
2762                 fw.rodata = bce_RXP_b09FwRodata;
2763         } else {
2764                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2765                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2766                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2767                 fw.start_addr = bce_RXP_b06FwStartAddr;
2768
2769                 fw.text_addr = bce_RXP_b06FwTextAddr;
2770                 fw.text_len = bce_RXP_b06FwTextLen;
2771                 fw.text_index = 0;
2772                 fw.text = bce_RXP_b06FwText;
2773
2774                 fw.data_addr = bce_RXP_b06FwDataAddr;
2775                 fw.data_len = bce_RXP_b06FwDataLen;
2776                 fw.data_index = 0;
2777                 fw.data = bce_RXP_b06FwData;
2778
2779                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2780                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2781                 fw.sbss_index = 0;
2782                 fw.sbss = bce_RXP_b06FwSbss;
2783
2784                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2785                 fw.bss_len = bce_RXP_b06FwBssLen;
2786                 fw.bss_index = 0;
2787                 fw.bss = bce_RXP_b06FwBss;
2788
2789                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2790                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2791                 fw.rodata_index = 0;
2792                 fw.rodata = bce_RXP_b06FwRodata;
2793         }
2794
2795         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2796         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2797         /* Delay RXP start until initialization is complete. */
2798 }
2799
2800
2801 /****************************************************************************/
2802 /* Initialize the TX CPU.                                                   */
2803 /*                                                                          */
2804 /* Returns:                                                                 */
2805 /*   Nothing.                                                               */
2806 /****************************************************************************/
2807 static void
2808 bce_init_txp_cpu(struct bce_softc *sc)
2809 {
2810         struct cpu_reg cpu_reg;
2811         struct fw_info fw;
2812
2813         cpu_reg.mode = BCE_TXP_CPU_MODE;
2814         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2815         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2816         cpu_reg.state = BCE_TXP_CPU_STATE;
2817         cpu_reg.state_value_clear = 0xffffff;
2818         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2819         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2820         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2821         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2822         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2823         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2824         cpu_reg.mips_view_base = 0x8000000;
2825
2826         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2827             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2828                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2829                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2830                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2831                 fw.start_addr = bce_TXP_b09FwStartAddr;
2832
2833                 fw.text_addr = bce_TXP_b09FwTextAddr;
2834                 fw.text_len = bce_TXP_b09FwTextLen;
2835                 fw.text_index = 0;
2836                 fw.text = bce_TXP_b09FwText;
2837
2838                 fw.data_addr = bce_TXP_b09FwDataAddr;
2839                 fw.data_len = bce_TXP_b09FwDataLen;
2840                 fw.data_index = 0;
2841                 fw.data = bce_TXP_b09FwData;
2842
2843                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2844                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2845                 fw.sbss_index = 0;
2846                 fw.sbss = bce_TXP_b09FwSbss;
2847
2848                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2849                 fw.bss_len = bce_TXP_b09FwBssLen;
2850                 fw.bss_index = 0;
2851                 fw.bss = bce_TXP_b09FwBss;
2852
2853                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2854                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2855                 fw.rodata_index = 0;
2856                 fw.rodata = bce_TXP_b09FwRodata;
2857         } else {
2858                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2859                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2860                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2861                 fw.start_addr = bce_TXP_b06FwStartAddr;
2862
2863                 fw.text_addr = bce_TXP_b06FwTextAddr;
2864                 fw.text_len = bce_TXP_b06FwTextLen;
2865                 fw.text_index = 0;
2866                 fw.text = bce_TXP_b06FwText;
2867
2868                 fw.data_addr = bce_TXP_b06FwDataAddr;
2869                 fw.data_len = bce_TXP_b06FwDataLen;
2870                 fw.data_index = 0;
2871                 fw.data = bce_TXP_b06FwData;
2872
2873                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2874                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2875                 fw.sbss_index = 0;
2876                 fw.sbss = bce_TXP_b06FwSbss;
2877
2878                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2879                 fw.bss_len = bce_TXP_b06FwBssLen;
2880                 fw.bss_index = 0;
2881                 fw.bss = bce_TXP_b06FwBss;
2882
2883                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2884                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2885                 fw.rodata_index = 0;
2886                 fw.rodata = bce_TXP_b06FwRodata;
2887         }
2888
2889         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2890         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2891         bce_start_cpu(sc, &cpu_reg);
2892 }
2893
2894
2895 /****************************************************************************/
2896 /* Initialize the TPAT CPU.                                                 */
2897 /*                                                                          */
2898 /* Returns:                                                                 */
2899 /*   Nothing.                                                               */
2900 /****************************************************************************/
2901 static void
2902 bce_init_tpat_cpu(struct bce_softc *sc)
2903 {
2904         struct cpu_reg cpu_reg;
2905         struct fw_info fw;
2906
2907         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2908         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2909         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2910         cpu_reg.state = BCE_TPAT_CPU_STATE;
2911         cpu_reg.state_value_clear = 0xffffff;
2912         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2913         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2914         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2915         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2916         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2917         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2918         cpu_reg.mips_view_base = 0x8000000;
2919
2920         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2921             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2922                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2923                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2924                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2925                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2926
2927                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2928                 fw.text_len = bce_TPAT_b09FwTextLen;
2929                 fw.text_index = 0;
2930                 fw.text = bce_TPAT_b09FwText;
2931
2932                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2933                 fw.data_len = bce_TPAT_b09FwDataLen;
2934                 fw.data_index = 0;
2935                 fw.data = bce_TPAT_b09FwData;
2936
2937                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2938                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2939                 fw.sbss_index = 0;
2940                 fw.sbss = bce_TPAT_b09FwSbss;
2941
2942                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2943                 fw.bss_len = bce_TPAT_b09FwBssLen;
2944                 fw.bss_index = 0;
2945                 fw.bss = bce_TPAT_b09FwBss;
2946
2947                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2948                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2949                 fw.rodata_index = 0;
2950                 fw.rodata = bce_TPAT_b09FwRodata;
2951         } else {
2952                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2953                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2954                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2955                 fw.start_addr = bce_TPAT_b06FwStartAddr;
2956
2957                 fw.text_addr = bce_TPAT_b06FwTextAddr;
2958                 fw.text_len = bce_TPAT_b06FwTextLen;
2959                 fw.text_index = 0;
2960                 fw.text = bce_TPAT_b06FwText;
2961
2962                 fw.data_addr = bce_TPAT_b06FwDataAddr;
2963                 fw.data_len = bce_TPAT_b06FwDataLen;
2964                 fw.data_index = 0;
2965                 fw.data = bce_TPAT_b06FwData;
2966
2967                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2968                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2969                 fw.sbss_index = 0;
2970                 fw.sbss = bce_TPAT_b06FwSbss;
2971
2972                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2973                 fw.bss_len = bce_TPAT_b06FwBssLen;
2974                 fw.bss_index = 0;
2975                 fw.bss = bce_TPAT_b06FwBss;
2976
2977                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2978                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2979                 fw.rodata_index = 0;
2980                 fw.rodata = bce_TPAT_b06FwRodata;
2981         }
2982
2983         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2984         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2985         bce_start_cpu(sc, &cpu_reg);
2986 }
2987
2988
2989 /****************************************************************************/
2990 /* Initialize the CP CPU.                                                   */
2991 /*                                                                          */
2992 /* Returns:                                                                 */
2993 /*   Nothing.                                                               */
2994 /****************************************************************************/
2995 static void
2996 bce_init_cp_cpu(struct bce_softc *sc)
2997 {
2998         struct cpu_reg cpu_reg;
2999         struct fw_info fw;
3000
3001         cpu_reg.mode = BCE_CP_CPU_MODE;
3002         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3003         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3004         cpu_reg.state = BCE_CP_CPU_STATE;
3005         cpu_reg.state_value_clear = 0xffffff;
3006         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3007         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3008         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3009         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3010         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3011         cpu_reg.spad_base = BCE_CP_SCRATCH;
3012         cpu_reg.mips_view_base = 0x8000000;
3013
3014         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3015             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3016                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3017                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3018                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3019                 fw.start_addr = bce_CP_b09FwStartAddr;
3020
3021                 fw.text_addr = bce_CP_b09FwTextAddr;
3022                 fw.text_len = bce_CP_b09FwTextLen;
3023                 fw.text_index = 0;
3024                 fw.text = bce_CP_b09FwText;
3025
3026                 fw.data_addr = bce_CP_b09FwDataAddr;
3027                 fw.data_len = bce_CP_b09FwDataLen;
3028                 fw.data_index = 0;
3029                 fw.data = bce_CP_b09FwData;
3030
3031                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3032                 fw.sbss_len = bce_CP_b09FwSbssLen;
3033                 fw.sbss_index = 0;
3034                 fw.sbss = bce_CP_b09FwSbss;
3035
3036                 fw.bss_addr = bce_CP_b09FwBssAddr;
3037                 fw.bss_len = bce_CP_b09FwBssLen;
3038                 fw.bss_index = 0;
3039                 fw.bss = bce_CP_b09FwBss;
3040
3041                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3042                 fw.rodata_len = bce_CP_b09FwRodataLen;
3043                 fw.rodata_index = 0;
3044                 fw.rodata = bce_CP_b09FwRodata;
3045         } else {
3046                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3047                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3048                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3049                 fw.start_addr = bce_CP_b06FwStartAddr;
3050
3051                 fw.text_addr = bce_CP_b06FwTextAddr;
3052                 fw.text_len = bce_CP_b06FwTextLen;
3053                 fw.text_index = 0;
3054                 fw.text = bce_CP_b06FwText;
3055
3056                 fw.data_addr = bce_CP_b06FwDataAddr;
3057                 fw.data_len = bce_CP_b06FwDataLen;
3058                 fw.data_index = 0;
3059                 fw.data = bce_CP_b06FwData;
3060
3061                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3062                 fw.sbss_len = bce_CP_b06FwSbssLen;
3063                 fw.sbss_index = 0;
3064                 fw.sbss = bce_CP_b06FwSbss;
3065
3066                 fw.bss_addr = bce_CP_b06FwBssAddr;
3067                 fw.bss_len = bce_CP_b06FwBssLen;
3068                 fw.bss_index = 0;
3069                 fw.bss = bce_CP_b06FwBss;
3070
3071                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3072                 fw.rodata_len = bce_CP_b06FwRodataLen;
3073                 fw.rodata_index = 0;
3074                 fw.rodata = bce_CP_b06FwRodata;
3075         }
3076
3077         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3078         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3079         bce_start_cpu(sc, &cpu_reg);
3080 }
3081
3082
3083 /****************************************************************************/
3084 /* Initialize the COM CPU.                                                 */
3085 /*                                                                          */
3086 /* Returns:                                                                 */
3087 /*   Nothing.                                                               */
3088 /****************************************************************************/
3089 static void
3090 bce_init_com_cpu(struct bce_softc *sc)
3091 {
3092         struct cpu_reg cpu_reg;
3093         struct fw_info fw;
3094
3095         cpu_reg.mode = BCE_COM_CPU_MODE;
3096         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3097         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3098         cpu_reg.state = BCE_COM_CPU_STATE;
3099         cpu_reg.state_value_clear = 0xffffff;
3100         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3101         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3102         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3103         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3104         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3105         cpu_reg.spad_base = BCE_COM_SCRATCH;
3106         cpu_reg.mips_view_base = 0x8000000;
3107
3108         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3109             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3110                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3111                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3112                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3113                 fw.start_addr = bce_COM_b09FwStartAddr;
3114
3115                 fw.text_addr = bce_COM_b09FwTextAddr;
3116                 fw.text_len = bce_COM_b09FwTextLen;
3117                 fw.text_index = 0;
3118                 fw.text = bce_COM_b09FwText;
3119
3120                 fw.data_addr = bce_COM_b09FwDataAddr;
3121                 fw.data_len = bce_COM_b09FwDataLen;
3122                 fw.data_index = 0;
3123                 fw.data = bce_COM_b09FwData;
3124
3125                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3126                 fw.sbss_len = bce_COM_b09FwSbssLen;
3127                 fw.sbss_index = 0;
3128                 fw.sbss = bce_COM_b09FwSbss;
3129
3130                 fw.bss_addr = bce_COM_b09FwBssAddr;
3131                 fw.bss_len = bce_COM_b09FwBssLen;
3132                 fw.bss_index = 0;
3133                 fw.bss = bce_COM_b09FwBss;
3134
3135                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3136                 fw.rodata_len = bce_COM_b09FwRodataLen;
3137                 fw.rodata_index = 0;
3138                 fw.rodata = bce_COM_b09FwRodata;
3139         } else {
3140                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3141                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3142                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3143                 fw.start_addr = bce_COM_b06FwStartAddr;
3144
3145                 fw.text_addr = bce_COM_b06FwTextAddr;
3146                 fw.text_len = bce_COM_b06FwTextLen;
3147                 fw.text_index = 0;
3148                 fw.text = bce_COM_b06FwText;
3149
3150                 fw.data_addr = bce_COM_b06FwDataAddr;
3151                 fw.data_len = bce_COM_b06FwDataLen;
3152                 fw.data_index = 0;
3153                 fw.data = bce_COM_b06FwData;
3154
3155                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3156                 fw.sbss_len = bce_COM_b06FwSbssLen;
3157                 fw.sbss_index = 0;
3158                 fw.sbss = bce_COM_b06FwSbss;
3159
3160                 fw.bss_addr = bce_COM_b06FwBssAddr;
3161                 fw.bss_len = bce_COM_b06FwBssLen;
3162                 fw.bss_index = 0;
3163                 fw.bss = bce_COM_b06FwBss;
3164
3165                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3166                 fw.rodata_len = bce_COM_b06FwRodataLen;
3167                 fw.rodata_index = 0;
3168                 fw.rodata = bce_COM_b06FwRodata;
3169         }
3170
3171         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3172         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3173         bce_start_cpu(sc, &cpu_reg);
3174 }
3175
3176
3177 /****************************************************************************/
3178 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3179 /*                                                                          */
3180 /* Loads the firmware for each CPU and starts the CPU.                      */
3181 /*                                                                          */
3182 /* Returns:                                                                 */
3183 /*   Nothing.                                                               */
3184 /****************************************************************************/
3185 static void
3186 bce_init_cpus(struct bce_softc *sc)
3187 {
3188         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3189             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3190                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3191                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3192                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3193                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3194                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3195                 } else {
3196                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3197                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3198                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3199                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3200                 }
3201         } else {
3202                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3203                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3204                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3205                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3206         }
3207
3208         bce_init_rxp_cpu(sc);
3209         bce_init_txp_cpu(sc);
3210         bce_init_tpat_cpu(sc);
3211         bce_init_com_cpu(sc);
3212         bce_init_cp_cpu(sc);
3213 }
3214
3215
3216 /****************************************************************************/
3217 /* Initialize context memory.                                               */
3218 /*                                                                          */
3219 /* Clears the memory associated with each Context ID (CID).                 */
3220 /*                                                                          */
3221 /* Returns:                                                                 */
3222 /*   Nothing.                                                               */
3223 /****************************************************************************/
3224 static int
3225 bce_init_ctx(struct bce_softc *sc)
3226 {
3227         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3228             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3229                 /* DRC: Replace this constant value with a #define. */
3230                 int i, retry_cnt = 10;
3231                 uint32_t val;
3232
3233                 /*
3234                  * BCM5709 context memory may be cached
3235                  * in host memory so prepare the host memory
3236                  * for access.
3237                  */
3238                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3239                     (1 << 12);
3240                 val |= (BCM_PAGE_BITS - 8) << 16;
3241                 REG_WR(sc, BCE_CTX_COMMAND, val);
3242
3243                 /* Wait for mem init command to complete. */
3244                 for (i = 0; i < retry_cnt; i++) {
3245                         val = REG_RD(sc, BCE_CTX_COMMAND);
3246                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3247                                 break;
3248                         DELAY(2);
3249                 }
3250                 if (i == retry_cnt) {
3251                         device_printf(sc->bce_dev,
3252                             "Context memory initialization failed!\n");
3253                         return ETIMEDOUT;
3254                 }
3255
3256                 for (i = 0; i < sc->ctx_pages; i++) {
3257                         int j;
3258
3259                         /*
3260                          * Set the physical address of the context
3261                          * memory cache.
3262                          */
3263                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3264                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3265                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3266                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3267                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3268                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3269                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3270
3271                         /*
3272                          * Verify that the context memory write was successful.
3273                          */
3274                         for (j = 0; j < retry_cnt; j++) {
3275                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3276                                 if ((val &
3277                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3278                                         break;
3279                                 DELAY(5);
3280                         }
3281                         if (j == retry_cnt) {
3282                                 device_printf(sc->bce_dev,
3283                                     "Failed to initialize context page!\n");
3284                                 return ETIMEDOUT;
3285                         }
3286                 }
3287         } else {
3288                 uint32_t vcid_addr, offset;
3289
3290                 /*
3291                  * For the 5706/5708, context memory is local to
3292                  * the controller, so initialize the controller
3293                  * context memory.
3294                  */
3295
3296                 vcid_addr = GET_CID_ADDR(96);
3297                 while (vcid_addr) {
3298                         vcid_addr -= PHY_CTX_SIZE;
3299
3300                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3301                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3302
3303                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3304                                 CTX_WR(sc, 0x00, offset, 0);
3305
3306                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3307                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3308                 }
3309         }
3310         return 0;
3311 }
3312
3313
3314 /****************************************************************************/
3315 /* Fetch the permanent MAC address of the controller.                       */
3316 /*                                                                          */
3317 /* Returns:                                                                 */
3318 /*   Nothing.                                                               */
3319 /****************************************************************************/
3320 static void
3321 bce_get_mac_addr(struct bce_softc *sc)
3322 {
3323         uint32_t mac_lo = 0, mac_hi = 0;
3324
3325         /*
3326          * The NetXtreme II bootcode populates various NIC
3327          * power-on and runtime configuration items in a
3328          * shared memory area.  The factory configured MAC
3329          * address is available from both NVRAM and the
3330          * shared memory area so we'll read the value from
3331          * shared memory for speed.
3332          */
3333
3334         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3335         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3336
3337         if (mac_lo == 0 && mac_hi == 0) {
3338                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3339         } else {
3340                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3341                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3342                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3343                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3344                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3345                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3346         }
3347
3348         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3349 }
3350
3351
3352 /****************************************************************************/
3353 /* Program the MAC address.                                                 */
3354 /*                                                                          */
3355 /* Returns:                                                                 */
3356 /*   Nothing.                                                               */
3357 /****************************************************************************/
3358 static void
3359 bce_set_mac_addr(struct bce_softc *sc)
3360 {
3361         const uint8_t *mac_addr = sc->eaddr;
3362         uint32_t val;
3363
3364         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3365                 sc->eaddr, ":");
3366
3367         val = (mac_addr[0] << 8) | mac_addr[1];
3368         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3369
3370         val = (mac_addr[2] << 24) |
3371               (mac_addr[3] << 16) |
3372               (mac_addr[4] << 8) |
3373               mac_addr[5];
3374         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3375 }
3376
3377
3378 /****************************************************************************/
3379 /* Stop the controller.                                                     */
3380 /*                                                                          */
3381 /* Returns:                                                                 */
3382 /*   Nothing.                                                               */
3383 /****************************************************************************/
3384 static void
3385 bce_stop(struct bce_softc *sc)
3386 {
3387         struct ifnet *ifp = &sc->arpcom.ac_if;
3388
3389         ASSERT_SERIALIZED(ifp->if_serializer);
3390
3391         callout_stop(&sc->bce_tick_callout);
3392
3393         /* Disable the transmit/receive blocks. */
3394         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3395         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3396         DELAY(20);
3397
3398         bce_disable_intr(sc);
3399
3400         /* Free the RX lists. */
3401         bce_free_rx_chain(sc);
3402
3403         /* Free TX buffers. */
3404         bce_free_tx_chain(sc);
3405
3406         sc->bce_link = 0;
3407         sc->bce_coalchg_mask = 0;
3408
3409         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3410         ifp->if_timer = 0;
3411 }
3412
3413
3414 static int
3415 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3416 {
3417         uint32_t val;
3418         int i, rc = 0;
3419
3420         /* Wait for pending PCI transactions to complete. */
3421         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3422                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3423                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3424                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3425                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3426         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3427         DELAY(5);
3428
3429         /* Disable DMA */
3430         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3431             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3432                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3433                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3434                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3435         }
3436
3437         /* Assume bootcode is running. */
3438         sc->bce_fw_timed_out = 0;
3439         sc->bce_drv_cardiac_arrest = 0;
3440
3441         /* Give the firmware a chance to prepare for the reset. */
3442         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3443         if (rc) {
3444                 if_printf(&sc->arpcom.ac_if,
3445                           "Firmware is not ready for reset\n");
3446                 return rc;
3447         }
3448
3449         /* Set a firmware reminder that this is a soft reset. */
3450         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3451             BCE_DRV_RESET_SIGNATURE_MAGIC);
3452
3453         /* Dummy read to force the chip to complete all current transactions. */
3454         val = REG_RD(sc, BCE_MISC_ID);
3455
3456         /* Chip reset. */
3457         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3458             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3459                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3460                 REG_RD(sc, BCE_MISC_COMMAND);
3461                 DELAY(5);
3462
3463                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3464                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3465
3466                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3467         } else {
3468                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3469                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3470                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3471                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3472
3473                 /* Allow up to 30us for reset to complete. */
3474                 for (i = 0; i < 10; i++) {
3475                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3476                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3477                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3478                                 break;
3479                         DELAY(10);
3480                 }
3481
3482                 /* Check that reset completed successfully. */
3483                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3484                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3485                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3486                         return EBUSY;
3487                 }
3488         }
3489
3490         /* Make sure byte swapping is properly configured. */
3491         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3492         if (val != 0x01020304) {
3493                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3494                 return ENODEV;
3495         }
3496
3497         /* Just completed a reset, assume that firmware is running again. */
3498         sc->bce_fw_timed_out = 0;
3499         sc->bce_drv_cardiac_arrest = 0;
3500
3501         /* Wait for the firmware to finish its initialization. */
3502         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3503         if (rc) {
3504                 if_printf(&sc->arpcom.ac_if,
3505                           "Firmware did not complete initialization!\n");
3506         }
3507         return rc;
3508 }
3509
3510
3511 static int
3512 bce_chipinit(struct bce_softc *sc)
3513 {
3514         uint32_t val;
3515         int rc = 0;
3516
3517         /* Make sure the interrupt is not active. */
3518         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3519         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3520
3521         /*
3522          * Initialize DMA byte/word swapping, configure the number of DMA
3523          * channels and PCI clock compensation delay.
3524          */
3525         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3526               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3527 #if BYTE_ORDER == BIG_ENDIAN
3528               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3529 #endif
3530               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3531               DMA_READ_CHANS << 12 |
3532               DMA_WRITE_CHANS << 16;
3533
3534         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3535
3536         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3537                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3538
3539         /*
3540          * This setting resolves a problem observed on certain Intel PCI
3541          * chipsets that cannot handle multiple outstanding DMA operations.
3542          * See errata E9_5706A1_65.
3543          */
3544         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3545             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3546             !(sc->bce_flags & BCE_PCIX_FLAG))
3547                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3548
3549         REG_WR(sc, BCE_DMA_CONFIG, val);
3550
3551         /* Enable the RX_V2P and Context state machines before access. */
3552         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3553                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3554                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3555                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3556
3557         /* Initialize context mapping and zero out the quick contexts. */
3558         rc = bce_init_ctx(sc);
3559         if (rc != 0)
3560                 return rc;
3561
3562         /* Initialize the on-boards CPUs */
3563         bce_init_cpus(sc);
3564
3565         /* Enable management frames (NC-SI) to flow to the MCP. */
3566         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3567                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3568                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3569                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3570         }
3571
3572         /* Prepare NVRAM for access. */
3573         rc = bce_init_nvram(sc);
3574         if (rc != 0)
3575                 return rc;
3576
3577         /* Set the kernel bypass block size */
3578         val = REG_RD(sc, BCE_MQ_CONFIG);
3579         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3580         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3581
3582         /* Enable bins used on the 5709/5716. */
3583         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3584             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3585                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3586                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3587                         val |= BCE_MQ_CONFIG_HALT_DIS;
3588         }
3589
3590         REG_WR(sc, BCE_MQ_CONFIG, val);
3591
3592         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3593         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3594         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3595
3596         /* Set the page size and clear the RV2P processor stall bits. */
3597         val = (BCM_PAGE_BITS - 8) << 24;
3598         REG_WR(sc, BCE_RV2P_CONFIG, val);
3599
3600         /* Configure page size. */
3601         val = REG_RD(sc, BCE_TBDR_CONFIG);
3602         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3603         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3604         REG_WR(sc, BCE_TBDR_CONFIG, val);
3605
3606         /* Set the perfect match control register to default. */
3607         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3608
3609         return 0;
3610 }
3611
3612
3613 /****************************************************************************/
3614 /* Initialize the controller in preparation to send/receive traffic.        */
3615 /*                                                                          */
3616 /* Returns:                                                                 */
3617 /*   0 for success, positive value for failure.                             */
3618 /****************************************************************************/
3619 static int
3620 bce_blockinit(struct bce_softc *sc)
3621 {
3622         uint32_t reg, val;
3623         int rc = 0;
3624
3625         /* Load the hardware default MAC address. */
3626         bce_set_mac_addr(sc);
3627
3628         /* Set the Ethernet backoff seed value */
3629         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3630               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3631         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3632
3633         sc->last_status_idx = 0;
3634         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3635
3636         /* Set up link change interrupt generation. */
3637         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3638
3639         /* Program the physical address of the status block. */
3640         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3641         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3642
3643         /* Program the physical address of the statistics block. */
3644         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3645                BCE_ADDR_LO(sc->stats_block_paddr));
3646         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3647                BCE_ADDR_HI(sc->stats_block_paddr));
3648
3649         /* Program various host coalescing parameters. */
3650         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3651                (sc->bce_tx_quick_cons_trip_int << 16) |
3652                sc->bce_tx_quick_cons_trip);
3653         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3654                (sc->bce_rx_quick_cons_trip_int << 16) |
3655                sc->bce_rx_quick_cons_trip);
3656         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3657                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3658         REG_WR(sc, BCE_HC_TX_TICKS,
3659                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3660         REG_WR(sc, BCE_HC_RX_TICKS,
3661                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3662         REG_WR(sc, BCE_HC_COM_TICKS,
3663                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3664         REG_WR(sc, BCE_HC_CMD_TICKS,
3665                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3666         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3667         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3668         REG_WR(sc, BCE_HC_CONFIG,
3669                BCE_HC_CONFIG_TX_TMR_MODE |
3670                BCE_HC_CONFIG_COLLECT_STATS);
3671
3672         /* Clear the internal statistics counters. */
3673         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3674
3675         /* Verify that bootcode is running. */
3676         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3677
3678         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3679                 if_printf(&sc->arpcom.ac_if,
3680                           "%s(%d): Simulating bootcode failure.\n",
3681                           __FILE__, __LINE__);
3682                 reg = 0);
3683
3684         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3685             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3686                 if_printf(&sc->arpcom.ac_if,
3687                           "Bootcode not running! Found: 0x%08X, "
3688                           "Expected: 08%08X\n",
3689                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3690                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3691                 return ENODEV;
3692         }
3693
3694         /* Enable DMA */
3695         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3696             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3697                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3698                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3699                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3700         }
3701
3702         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3703         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3704
3705         /* Enable link state change interrupt generation. */
3706         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3707
3708         /* Enable the RXP. */
3709         bce_start_rxp_cpu(sc);
3710
3711         /* Disable management frames (NC-SI) from flowing to the MCP. */
3712         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3713                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3714                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3715                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3716         }
3717
3718         /* Enable all remaining blocks in the MAC. */
3719         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3720             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3721                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3722                     BCE_MISC_ENABLE_DEFAULT_XI);
3723         } else {
3724                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3725         }
3726         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3727         DELAY(20);
3728
3729         /* Save the current host coalescing block settings. */
3730         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3731
3732         return 0;
3733 }
3734
3735
3736 /****************************************************************************/
3737 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3738 /*                                                                          */
3739 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3740 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3741 /* necessary.                                                               */
3742 /*                                                                          */
3743 /* Returns:                                                                 */
3744 /*   0 for success, positive value for failure.                             */
3745 /****************************************************************************/
3746 static int
3747 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3748                uint32_t *prod_bseq, int init)
3749 {
3750         bus_dmamap_t map;
3751         bus_dma_segment_t seg;
3752         struct mbuf *m_new;
3753         int error, nseg;
3754 #ifdef BCE_DEBUG
3755         uint16_t debug_chain_prod = *chain_prod;
3756 #endif
3757
3758         /* Make sure the inputs are valid. */
3759         DBRUNIF((*chain_prod > MAX_RX_BD),
3760                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3761                           "RX producer out of range: 0x%04X > 0x%04X\n",
3762                           __FILE__, __LINE__,
3763                           *chain_prod, (uint16_t)MAX_RX_BD));
3764
3765         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3766                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3767
3768         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3769                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3770                           "Simulating mbuf allocation failure.\n",
3771                           __FILE__, __LINE__);
3772                 sc->mbuf_alloc_failed++;
3773                 return ENOBUFS);
3774
3775         /* This is a new mbuf allocation. */
3776         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3777         if (m_new == NULL)
3778                 return ENOBUFS;
3779         DBRUNIF(1, sc->rx_mbuf_alloc++);
3780
3781         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3782
3783         /* Map the mbuf cluster into device memory. */
3784         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3785                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3786                         BUS_DMA_NOWAIT);
3787         if (error) {
3788                 m_freem(m_new);
3789                 if (init) {
3790                         if_printf(&sc->arpcom.ac_if,
3791                                   "Error mapping mbuf into RX chain!\n");
3792                 }
3793                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3794                 return error;
3795         }
3796
3797         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3798                 bus_dmamap_unload(sc->rx_mbuf_tag,
3799                                   sc->rx_mbuf_map[*chain_prod]);
3800         }
3801
3802         map = sc->rx_mbuf_map[*chain_prod];
3803         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3804         sc->rx_mbuf_tmpmap = map;
3805
3806         /* Watch for overflow. */
3807         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3808                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3809                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3810                           __FILE__, __LINE__, sc->free_rx_bd,
3811                           (uint16_t)USABLE_RX_BD));
3812
3813         /* Update some debug statistic counters */
3814         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3815                 sc->rx_low_watermark = sc->free_rx_bd);
3816         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3817
3818         /* Save the mbuf and update our counter. */
3819         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3820         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3821         sc->free_rx_bd--;
3822
3823         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3824
3825         DBRUN(BCE_VERBOSE_RECV,
3826               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3827
3828         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3829                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3830
3831         return 0;
3832 }
3833
3834
3835 static void
3836 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3837 {
3838         struct rx_bd *rxbd;
3839         bus_addr_t paddr;
3840         int len;
3841
3842         paddr = sc->rx_mbuf_paddr[chain_prod];
3843         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3844
3845         /* Setup the rx_bd for the first segment. */
3846         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3847
3848         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3849         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3850         rxbd->rx_bd_len = htole32(len);
3851         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3852         *prod_bseq += len;
3853
3854         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3855 }
3856
3857
3858 /****************************************************************************/
3859 /* Initialize the TX context memory.                                        */
3860 /*                                                                          */
3861 /* Returns:                                                                 */
3862 /*   Nothing                                                                */
3863 /****************************************************************************/
3864 static void
3865 bce_init_tx_context(struct bce_softc *sc)
3866 {
3867         uint32_t val;
3868
3869         /* Initialize the context ID for an L2 TX chain. */
3870         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3871             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3872                 /* Set the CID type to support an L2 connection. */
3873                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3874                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3875                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3876                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3877
3878                 /* Point the hardware to the first page in the chain. */
3879                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3880                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3881                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3882                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3883                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3884                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3885         } else {
3886                 /* Set the CID type to support an L2 connection. */
3887                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3888                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3889                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3890                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3891
3892                 /* Point the hardware to the first page in the chain. */
3893                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3894                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3895                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3896                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3897                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3898                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3899         }
3900 }
3901
3902
3903 /****************************************************************************/
3904 /* Allocate memory and initialize the TX data structures.                   */
3905 /*                                                                          */
3906 /* Returns:                                                                 */
3907 /*   0 for success, positive value for failure.                             */
3908 /****************************************************************************/
3909 static int
3910 bce_init_tx_chain(struct bce_softc *sc)
3911 {
3912         struct tx_bd *txbd;
3913         int i, rc = 0;
3914
3915         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3916
3917         /* Set the initial TX producer/consumer indices. */
3918         sc->tx_prod = 0;
3919         sc->tx_cons = 0;
3920         sc->tx_prod_bseq   = 0;
3921         sc->used_tx_bd = 0;
3922         sc->max_tx_bd = USABLE_TX_BD;
3923         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3924         DBRUNIF(1, sc->tx_full_count = 0);
3925
3926         /*
3927          * The NetXtreme II supports a linked-list structre called
3928          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3929          * consists of a series of 1 or more chain pages, each of which
3930          * consists of a fixed number of BD entries.
3931          * The last BD entry on each page is a pointer to the next page
3932          * in the chain, and the last pointer in the BD chain
3933          * points back to the beginning of the chain.
3934          */
3935
3936         /* Set the TX next pointer chain entries. */
3937         for (i = 0; i < TX_PAGES; i++) {
3938                 int j;
3939
3940                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3941
3942                 /* Check if we've reached the last page. */
3943                 if (i == (TX_PAGES - 1))
3944                         j = 0;
3945                 else
3946                         j = i + 1;
3947
3948                 txbd->tx_bd_haddr_hi =
3949                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3950                 txbd->tx_bd_haddr_lo =
3951                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3952         }
3953         bce_init_tx_context(sc);
3954
3955         return(rc);
3956 }
3957
3958
3959 /****************************************************************************/
3960 /* Free memory and clear the TX data structures.                            */
3961 /*                                                                          */
3962 /* Returns:                                                                 */
3963 /*   Nothing.                                                               */
3964 /****************************************************************************/
3965 static void
3966 bce_free_tx_chain(struct bce_softc *sc)
3967 {
3968         int i;
3969
3970         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3971
3972         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3973         for (i = 0; i < TOTAL_TX_BD; i++) {
3974                 if (sc->tx_mbuf_ptr[i] != NULL) {
3975                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3976                         m_freem(sc->tx_mbuf_ptr[i]);
3977                         sc->tx_mbuf_ptr[i] = NULL;
3978                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3979                 }
3980         }
3981
3982         /* Clear each TX chain page. */
3983         for (i = 0; i < TX_PAGES; i++)
3984                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3985         sc->used_tx_bd = 0;
3986
3987         /* Check if we lost any mbufs in the process. */
3988         DBRUNIF((sc->tx_mbuf_alloc),
3989                 if_printf(&sc->arpcom.ac_if,
3990                           "%s(%d): Memory leak! "
3991                           "Lost %d mbufs from tx chain!\n",
3992                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3993
3994         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3995 }
3996
3997
3998 /****************************************************************************/
3999 /* Initialize the RX context memory.                                        */
4000 /*                                                                          */
4001 /* Returns:                                                                 */
4002 /*   Nothing                                                                */
4003 /****************************************************************************/
4004 static void
4005 bce_init_rx_context(struct bce_softc *sc)
4006 {
4007         uint32_t val;
4008
4009         /* Initialize the context ID for an L2 RX chain. */
4010         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4011             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4012
4013         /*
4014          * Set the level for generating pause frames
4015          * when the number of available rx_bd's gets
4016          * too low (the low watermark) and the level
4017          * when pause frames can be stopped (the high
4018          * watermark).
4019          */
4020         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4021             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4022                 uint32_t lo_water, hi_water;
4023
4024                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4025                 hi_water = USABLE_RX_BD / 4;
4026
4027                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4028                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4029
4030                 if (hi_water > 0xf)
4031                         hi_water = 0xf;
4032                 else if (hi_water == 0)
4033                         lo_water = 0;
4034                 val |= lo_water |
4035                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4036         }
4037
4038         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4039
4040         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4041         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4042             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4043                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4044                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4045         }
4046
4047         /* Point the hardware to the first page in the chain. */
4048         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4049         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4050         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4051         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4052 }
4053
4054
4055 /****************************************************************************/
4056 /* Allocate memory and initialize the RX data structures.                   */
4057 /*                                                                          */
4058 /* Returns:                                                                 */
4059 /*   0 for success, positive value for failure.                             */
4060 /****************************************************************************/
4061 static int
4062 bce_init_rx_chain(struct bce_softc *sc)
4063 {
4064         struct rx_bd *rxbd;
4065         int i, rc = 0;
4066         uint16_t prod, chain_prod;
4067         uint32_t prod_bseq;
4068
4069         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4070
4071         /* Initialize the RX producer and consumer indices. */
4072         sc->rx_prod = 0;
4073         sc->rx_cons = 0;
4074         sc->rx_prod_bseq = 0;
4075         sc->free_rx_bd = USABLE_RX_BD;
4076         sc->max_rx_bd = USABLE_RX_BD;
4077         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
4078         DBRUNIF(1, sc->rx_empty_count = 0);
4079
4080         /* Initialize the RX next pointer chain entries. */
4081         for (i = 0; i < RX_PAGES; i++) {
4082                 int j;
4083
4084                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4085
4086                 /* Check if we've reached the last page. */
4087                 if (i == (RX_PAGES - 1))
4088                         j = 0;
4089                 else
4090                         j = i + 1;
4091
4092                 /* Setup the chain page pointers. */
4093                 rxbd->rx_bd_haddr_hi =
4094                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4095                 rxbd->rx_bd_haddr_lo =
4096                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4097         }
4098
4099         /* Allocate mbuf clusters for the rx_bd chain. */
4100         prod = prod_bseq = 0;
4101         while (prod < TOTAL_RX_BD) {
4102                 chain_prod = RX_CHAIN_IDX(prod);
4103                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4104                         if_printf(&sc->arpcom.ac_if,
4105                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
4106                                   chain_prod);
4107                         rc = ENOBUFS;
4108                         break;
4109                 }
4110                 prod = NEXT_RX_BD(prod);
4111         }
4112
4113         /* Save the RX chain producer index. */
4114         sc->rx_prod = prod;
4115         sc->rx_prod_bseq = prod_bseq;
4116
4117         /* Tell the chip about the waiting rx_bd's. */
4118         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4119             sc->rx_prod);
4120         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4121             sc->rx_prod_bseq);
4122
4123         bce_init_rx_context(sc);
4124
4125         return(rc);
4126 }
4127
4128
4129 /****************************************************************************/
4130 /* Free memory and clear the RX data structures.                            */
4131 /*                                                                          */
4132 /* Returns:                                                                 */
4133 /*   Nothing.                                                               */
4134 /****************************************************************************/
4135 static void
4136 bce_free_rx_chain(struct bce_softc *sc)
4137 {
4138         int i;
4139
4140         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4141
4142         /* Free any mbufs still in the RX mbuf chain. */
4143         for (i = 0; i < TOTAL_RX_BD; i++) {
4144                 if (sc->rx_mbuf_ptr[i] != NULL) {
4145                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4146                         m_freem(sc->rx_mbuf_ptr[i]);
4147                         sc->rx_mbuf_ptr[i] = NULL;
4148                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4149                 }
4150         }
4151
4152         /* Clear each RX chain page. */
4153         for (i = 0; i < RX_PAGES; i++)
4154                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4155
4156         /* Check if we lost any mbufs in the process. */
4157         DBRUNIF((sc->rx_mbuf_alloc),
4158                 if_printf(&sc->arpcom.ac_if,
4159                           "%s(%d): Memory leak! "
4160                           "Lost %d mbufs from rx chain!\n",
4161                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
4162
4163         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4164 }
4165
4166
4167 /****************************************************************************/
4168 /* Set media options.                                                       */
4169 /*                                                                          */
4170 /* Returns:                                                                 */
4171 /*   0 for success, positive value for failure.                             */
4172 /****************************************************************************/
4173 static int
4174 bce_ifmedia_upd(struct ifnet *ifp)
4175 {
4176         struct bce_softc *sc = ifp->if_softc;
4177         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4178         int error = 0;
4179
4180         /*
4181          * 'mii' will be NULL, when this function is called on following
4182          * code path: bce_attach() -> bce_mgmt_init()
4183          */
4184         if (mii != NULL) {
4185                 /* Make sure the MII bus has been enumerated. */
4186                 sc->bce_link = 0;
4187                 if (mii->mii_instance) {
4188                         struct mii_softc *miisc;
4189
4190                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4191                                 mii_phy_reset(miisc);
4192                 }
4193                 error = mii_mediachg(mii);
4194         }
4195         return error;
4196 }
4197
4198
4199 /****************************************************************************/
4200 /* Reports current media status.                                            */
4201 /*                                                                          */
4202 /* Returns:                                                                 */
4203 /*   Nothing.                                                               */
4204 /****************************************************************************/
4205 static void
4206 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4207 {
4208         struct bce_softc *sc = ifp->if_softc;
4209         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4210
4211         mii_pollstat(mii);
4212         ifmr->ifm_active = mii->mii_media_active;
4213         ifmr->ifm_status = mii->mii_media_status;
4214 }
4215
4216
4217 /****************************************************************************/
4218 /* Handles PHY generated interrupt events.                                  */
4219 /*                                                                          */
4220 /* Returns:                                                                 */
4221 /*   Nothing.                                                               */
4222 /****************************************************************************/
4223 static void
4224 bce_phy_intr(struct bce_softc *sc)
4225 {
4226         uint32_t new_link_state, old_link_state;
4227         struct ifnet *ifp = &sc->arpcom.ac_if;
4228
4229         ASSERT_SERIALIZED(ifp->if_serializer);
4230
4231         new_link_state = sc->status_block->status_attn_bits &
4232                          STATUS_ATTN_BITS_LINK_STATE;
4233         old_link_state = sc->status_block->status_attn_bits_ack &
4234                          STATUS_ATTN_BITS_LINK_STATE;
4235
4236         /* Handle any changes if the link state has changed. */
4237         if (new_link_state != old_link_state) { /* XXX redundant? */
4238                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4239
4240                 /* Update the status_attn_bits_ack field in the status block. */
4241                 if (new_link_state) {
4242                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4243                                STATUS_ATTN_BITS_LINK_STATE);
4244                         if (bootverbose)
4245                                 if_printf(ifp, "Link is now UP.\n");
4246                 } else {
4247                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4248                                STATUS_ATTN_BITS_LINK_STATE);
4249                         if (bootverbose)
4250                                 if_printf(ifp, "Link is now DOWN.\n");
4251                 }
4252
4253                 /*
4254                  * Assume link is down and allow tick routine to
4255                  * update the state based on the actual media state.
4256                  */
4257                 sc->bce_link = 0;
4258                 callout_stop(&sc->bce_tick_callout);
4259                 bce_tick_serialized(sc);
4260         }
4261
4262         /* Acknowledge the link change interrupt. */
4263         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4264 }
4265
4266
4267 /****************************************************************************/
4268 /* Reads the receive consumer value from the status block (skipping over    */
4269 /* chain page pointer if necessary).                                        */
4270 /*                                                                          */
4271 /* Returns:                                                                 */
4272 /*   hw_cons                                                                */
4273 /****************************************************************************/
4274 static __inline uint16_t
4275 bce_get_hw_rx_cons(struct bce_softc *sc)
4276 {
4277         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4278
4279         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4280                 hw_cons++;
4281         return hw_cons;
4282 }
4283
4284
4285 /****************************************************************************/
4286 /* Handles received frame interrupt events.                                 */
4287 /*                                                                          */
4288 /* Returns:                                                                 */
4289 /*   Nothing.                                                               */
4290 /****************************************************************************/
4291 static void
4292 bce_rx_intr(struct bce_softc *sc, int count)
4293 {
4294         struct ifnet *ifp = &sc->arpcom.ac_if;
4295         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4296         uint32_t sw_prod_bseq;
4297         struct mbuf_chain chain[MAXCPU];
4298
4299         ASSERT_SERIALIZED(ifp->if_serializer);
4300
4301         ether_input_chain_init(chain);
4302
4303         DBRUNIF(1, sc->rx_interrupts++);
4304
4305         /* Get the hardware's view of the RX consumer index. */
4306         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4307
4308         /* Get working copies of the driver's view of the RX indices. */
4309         sw_cons = sc->rx_cons;
4310         sw_prod = sc->rx_prod;
4311         sw_prod_bseq = sc->rx_prod_bseq;
4312
4313         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4314                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4315                 __func__, sw_prod, sw_cons, sw_prod_bseq);
4316
4317         /* Prevent speculative reads from getting ahead of the status block. */
4318         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4319                           BUS_SPACE_BARRIER_READ);
4320
4321         /* Update some debug statistics counters */
4322         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4323                 sc->rx_low_watermark = sc->free_rx_bd);
4324         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4325
4326         /* Scan through the receive chain as long as there is work to do. */
4327         while (sw_cons != hw_cons) {
4328                 struct mbuf *m = NULL;
4329                 struct l2_fhdr *l2fhdr = NULL;
4330                 struct rx_bd *rxbd;
4331                 unsigned int len;
4332                 uint32_t status = 0;
4333
4334 #ifdef DEVICE_POLLING
4335                 if (count >= 0 && count-- == 0) {
4336                         sc->hw_rx_cons = sw_cons;
4337                         break;
4338                 }
4339 #endif
4340
4341                 /*
4342                  * Convert the producer/consumer indices
4343                  * to an actual rx_bd index.
4344                  */
4345                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4346                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4347
4348                 /* Get the used rx_bd. */
4349                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4350                                        [RX_IDX(sw_chain_cons)];
4351                 sc->free_rx_bd++;
4352
4353                 DBRUN(BCE_VERBOSE_RECV,
4354                       if_printf(ifp, "%s(): ", __func__);
4355                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4356
4357                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4358                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4359                         /* Validate that this is the last rx_bd. */
4360                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4361                                 if_printf(ifp, "%s(%d): "
4362                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4363                                 __FILE__, __LINE__, sw_chain_cons);
4364                                 bce_breakpoint(sc));
4365
4366                         if (sw_chain_cons != sw_chain_prod) {
4367                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4368                                           "drop!\n", sw_chain_cons,
4369                                           sw_chain_prod);
4370                                 ifp->if_ierrors++;
4371
4372                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4373                                                      &sw_prod_bseq);
4374                                 m = NULL;
4375                                 goto bce_rx_int_next_rx;
4376                         }
4377
4378                         /* Unmap the mbuf from DMA space. */
4379                         bus_dmamap_sync(sc->rx_mbuf_tag,
4380                                         sc->rx_mbuf_map[sw_chain_cons],
4381                                         BUS_DMASYNC_POSTREAD);
4382
4383                         /* Save the mbuf from the driver's chain. */
4384                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4385
4386                         /*
4387                          * Frames received on the NetXteme II are prepended
4388                          * with an l2_fhdr structure which provides status
4389                          * information about the received frame (including
4390                          * VLAN tags and checksum info).  The frames are also
4391                          * automatically adjusted to align the IP header
4392                          * (i.e. two null bytes are inserted before the
4393                          * Ethernet header).  As a result the data DMA'd by
4394                          * the controller into the mbuf is as follows:
4395                          *
4396                          * +---------+-----+---------------------+-----+
4397                          * | l2_fhdr | pad | packet data         | FCS |
4398                          * +---------+-----+---------------------+-----+
4399                          *
4400                          * The l2_fhdr needs to be checked and skipped and the
4401                          * FCS needs to be stripped before sending the packet
4402                          * up the stack.
4403                          */
4404                         l2fhdr = mtod(m, struct l2_fhdr *);
4405
4406                         len = l2fhdr->l2_fhdr_pkt_len;
4407                         status = l2fhdr->l2_fhdr_status;
4408
4409                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4410                                 if_printf(ifp,
4411                                 "Simulating l2_fhdr status error.\n");
4412                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4413
4414                         /* Watch for unusual sized frames. */
4415                         DBRUNIF((len < BCE_MIN_MTU ||
4416                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4417                                 if_printf(ifp,
4418                                 "%s(%d): Unusual frame size found. "
4419                                 "Min(%d), Actual(%d), Max(%d)\n",
4420                                 __FILE__, __LINE__,
4421                                 (int)BCE_MIN_MTU, len,
4422                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4423                                 bce_dump_mbuf(sc, m);
4424                                 bce_breakpoint(sc));
4425
4426                         len -= ETHER_CRC_LEN;
4427
4428                         /* Check the received frame for errors. */
4429                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4430                                       L2_FHDR_ERRORS_PHY_DECODE |
4431                                       L2_FHDR_ERRORS_ALIGNMENT |
4432                                       L2_FHDR_ERRORS_TOO_SHORT |
4433                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4434                                 ifp->if_ierrors++;
4435                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
4436
4437                                 /* Reuse the mbuf for a new frame. */
4438                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4439                                                      &sw_prod_bseq);
4440                                 m = NULL;
4441                                 goto bce_rx_int_next_rx;
4442                         }
4443
4444                         /*
4445                          * Get a new mbuf for the rx_bd.   If no new
4446                          * mbufs are available then reuse the current mbuf,
4447                          * log an ierror on the interface, and generate
4448                          * an error in the system log.
4449                          */
4450                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4451                                            &sw_prod_bseq, 0)) {
4452                                 DBRUN(BCE_WARN,
4453                                       if_printf(ifp,
4454                                       "%s(%d): Failed to allocate new mbuf, "
4455                                       "incoming frame dropped!\n",
4456                                       __FILE__, __LINE__));
4457
4458                                 ifp->if_ierrors++;
4459
4460                                 /* Try and reuse the exisitng mbuf. */
4461                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4462                                                      &sw_prod_bseq);
4463                                 m = NULL;
4464                                 goto bce_rx_int_next_rx;
4465                         }
4466
4467                         /*
4468                          * Skip over the l2_fhdr when passing
4469                          * the data up the stack.
4470                          */
4471                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4472
4473                         m->m_pkthdr.len = m->m_len = len;
4474                         m->m_pkthdr.rcvif = ifp;
4475
4476                         DBRUN(BCE_VERBOSE_RECV,
4477                               struct ether_header *eh;
4478                               eh = mtod(m, struct ether_header *);
4479                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
4480                                         "type: 0x%04X\n", __func__,
4481                                         eh->ether_dhost, ":",
4482                                         eh->ether_shost, ":",
4483                                         htons(eh->ether_type)));
4484
4485                         /* Validate the checksum if offload enabled. */
4486                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4487                                 /* Check for an IP datagram. */
4488                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4489                                         m->m_pkthdr.csum_flags |=
4490                                                 CSUM_IP_CHECKED;
4491
4492                                         /* Check if the IP checksum is valid. */
4493                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4494                                              0xffff) == 0) {
4495                                                 m->m_pkthdr.csum_flags |=
4496                                                         CSUM_IP_VALID;
4497                                         } else {
4498                                                 DBPRINT(sc, BCE_WARN_RECV,
4499                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
4500                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
4501                                         }
4502                                 }
4503
4504                                 /* Check for a valid TCP/UDP frame. */
4505                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4506                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4507
4508                                         /* Check for a good TCP/UDP checksum. */
4509                                         if ((status &
4510                                              (L2_FHDR_ERRORS_TCP_XSUM |
4511                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4512                                                 m->m_pkthdr.csum_data =
4513                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4514                                                 m->m_pkthdr.csum_flags |=
4515                                                         CSUM_DATA_VALID |
4516                                                         CSUM_PSEUDO_HDR;
4517                                         } else {
4518                                                 DBPRINT(sc, BCE_WARN_RECV,
4519                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4520                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4521                                         }
4522                                 }
4523                         }
4524
4525                         ifp->if_ipackets++;
4526 bce_rx_int_next_rx:
4527                         sw_prod = NEXT_RX_BD(sw_prod);
4528                 }
4529
4530                 sw_cons = NEXT_RX_BD(sw_cons);
4531
4532                 /* If we have a packet, pass it up the stack */
4533                 if (m) {
4534                         DBPRINT(sc, BCE_VERBOSE_RECV,
4535                                 "%s(): Passing received frame up.\n", __func__);
4536
4537                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4538                                 m->m_flags |= M_VLANTAG;
4539                                 m->m_pkthdr.ether_vlantag =
4540                                         l2fhdr->l2_fhdr_vlan_tag;
4541                         }
4542                         ether_input_chain(ifp, m, NULL, chain);
4543
4544                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4545                 }
4546
4547                 /*
4548                  * If polling(4) is not enabled, refresh hw_cons to see
4549                  * whether there's new work.
4550                  *
4551                  * If polling(4) is enabled, i.e count >= 0, refreshing
4552                  * should not be performed, so that we would not spend
4553                  * too much time in RX processing.
4554                  */
4555                 if (count < 0 && sw_cons == hw_cons)
4556                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4557
4558                 /*
4559                  * Prevent speculative reads from getting ahead
4560                  * of the status block.
4561                  */
4562                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4563                                   BUS_SPACE_BARRIER_READ);
4564         }
4565
4566         ether_input_dispatch(chain);
4567
4568         sc->rx_cons = sw_cons;
4569         sc->rx_prod = sw_prod;
4570         sc->rx_prod_bseq = sw_prod_bseq;
4571
4572         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4573             sc->rx_prod);
4574         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4575             sc->rx_prod_bseq);
4576
4577         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4578                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4579                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4580 }
4581
4582
4583 /****************************************************************************/
4584 /* Reads the transmit consumer value from the status block (skipping over   */
4585 /* chain page pointer if necessary).                                        */
4586 /*                                                                          */
4587 /* Returns:                                                                 */
4588 /*   hw_cons                                                                */
4589 /****************************************************************************/
4590 static __inline uint16_t
4591 bce_get_hw_tx_cons(struct bce_softc *sc)
4592 {
4593         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4594
4595         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4596                 hw_cons++;
4597         return hw_cons;
4598 }
4599
4600
4601 /****************************************************************************/
4602 /* Handles transmit completion interrupt events.                            */
4603 /*                                                                          */
4604 /* Returns:                                                                 */
4605 /*   Nothing.                                                               */
4606 /****************************************************************************/
4607 static void
4608 bce_tx_intr(struct bce_softc *sc)
4609 {
4610         struct ifnet *ifp = &sc->arpcom.ac_if;
4611         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4612
4613         ASSERT_SERIALIZED(ifp->if_serializer);
4614
4615         DBRUNIF(1, sc->tx_interrupts++);
4616
4617         /* Get the hardware's view of the TX consumer index. */
4618         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4619         sw_tx_cons = sc->tx_cons;
4620
4621         /* Prevent speculative reads from getting ahead of the status block. */
4622         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4623                           BUS_SPACE_BARRIER_READ);
4624
4625         /* Cycle through any completed TX chain page entries. */
4626         while (sw_tx_cons != hw_tx_cons) {
4627 #ifdef BCE_DEBUG
4628                 struct tx_bd *txbd = NULL;
4629 #endif
4630                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4631
4632                 DBPRINT(sc, BCE_INFO_SEND,
4633                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4634                         "sw_tx_chain_cons = 0x%04X\n",
4635                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4636
4637                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4638                         if_printf(ifp, "%s(%d): "
4639                                   "TX chain consumer out of range! "
4640                                   " 0x%04X > 0x%04X\n",
4641                                   __FILE__, __LINE__, sw_tx_chain_cons,
4642                                   (int)MAX_TX_BD);
4643                         bce_breakpoint(sc));
4644
4645                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4646                                 [TX_IDX(sw_tx_chain_cons)]);
4647
4648                 DBRUNIF((txbd == NULL),
4649                         if_printf(ifp, "%s(%d): "
4650                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4651                                   __FILE__, __LINE__, sw_tx_chain_cons);
4652                         bce_breakpoint(sc));
4653
4654                 DBRUN(BCE_INFO_SEND,
4655                       if_printf(ifp, "%s(): ", __func__);
4656                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4657
4658                 /*
4659                  * Free the associated mbuf. Remember
4660                  * that only the last tx_bd of a packet
4661                  * has an mbuf pointer and DMA map.
4662                  */
4663                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4664                         /* Validate that this is the last tx_bd. */
4665                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4666                                 if_printf(ifp, "%s(%d): "
4667                                 "tx_bd END flag not set but "
4668                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4669                                 bce_breakpoint(sc));
4670
4671                         DBRUN(BCE_INFO_SEND,
4672                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4673                                         "from tx_bd[0x%04X]\n", __func__,
4674                                         sw_tx_chain_cons));
4675
4676                         /* Unmap the mbuf. */
4677                         bus_dmamap_unload(sc->tx_mbuf_tag,
4678                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4679
4680                         /* Free the mbuf. */
4681                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4682                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4683                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4684
4685                         ifp->if_opackets++;
4686                 }
4687
4688                 sc->used_tx_bd--;
4689                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4690
4691                 if (sw_tx_cons == hw_tx_cons) {
4692                         /* Refresh hw_cons to see if there's new work. */
4693                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4694                 }
4695
4696                 /*
4697                  * Prevent speculative reads from getting
4698                  * ahead of the status block.
4699                  */
4700                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4701                                   BUS_SPACE_BARRIER_READ);
4702         }
4703
4704         if (sc->used_tx_bd == 0) {
4705                 /* Clear the TX timeout timer. */
4706                 ifp->if_timer = 0;
4707         }
4708
4709         /* Clear the tx hardware queue full flag. */
4710         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4711                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4712                         DBPRINT(sc, BCE_WARN_SEND,
4713                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4714                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4715                 ifp->if_flags &= ~IFF_OACTIVE;
4716         }
4717         sc->tx_cons = sw_tx_cons;
4718 }
4719
4720
4721 /****************************************************************************/
4722 /* Disables interrupt generation.                                           */
4723 /*                                                                          */
4724 /* Returns:                                                                 */
4725 /*   Nothing.                                                               */
4726 /****************************************************************************/
4727 static void
4728 bce_disable_intr(struct bce_softc *sc)
4729 {
4730         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4731         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4732         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4733 }
4734
4735
4736 /****************************************************************************/
4737 /* Enables interrupt generation.                                            */
4738 /*                                                                          */
4739 /* Returns:                                                                 */
4740 /*   Nothing.                                                               */
4741 /****************************************************************************/
4742 static void
4743 bce_enable_intr(struct bce_softc *sc, int coal_now)
4744 {
4745         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4746
4747         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4748                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4749                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4750
4751         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4752                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4753
4754         if (coal_now) {
4755                 REG_WR(sc, BCE_HC_COMMAND,
4756                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4757         }
4758 }
4759
4760
4761 /****************************************************************************/
4762 /* Handles controller initialization.                                       */
4763 /*                                                                          */
4764 /* Returns:                                                                 */
4765 /*   Nothing.                                                               */
4766 /****************************************************************************/
4767 static void
4768 bce_init(void *xsc)
4769 {
4770         struct bce_softc *sc = xsc;
4771         struct ifnet *ifp = &sc->arpcom.ac_if;
4772         uint32_t ether_mtu;
4773         int error;
4774
4775         ASSERT_SERIALIZED(ifp->if_serializer);
4776
4777         /* Check if the driver is still running and bail out if it is. */
4778         if (ifp->if_flags & IFF_RUNNING)
4779                 return;
4780
4781         bce_stop(sc);
4782
4783         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4784         if (error) {
4785                 if_printf(ifp, "Controller reset failed!\n");
4786                 goto back;
4787         }
4788
4789         error = bce_chipinit(sc);
4790         if (error) {
4791                 if_printf(ifp, "Controller initialization failed!\n");
4792                 goto back;
4793         }
4794
4795         error = bce_blockinit(sc);
4796         if (error) {
4797                 if_printf(ifp, "Block initialization failed!\n");
4798                 goto back;
4799         }
4800
4801         /* Load our MAC address. */
4802         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4803         bce_set_mac_addr(sc);
4804
4805         /* Calculate and program the Ethernet MTU size. */
4806         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4807
4808         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4809
4810         /*
4811          * Program the mtu, enabling jumbo frame
4812          * support if necessary.  Also set the mbuf
4813          * allocation count for RX frames.
4814          */
4815         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4816 #ifdef notyet
4817                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4818                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4819                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4820                 sc->mbuf_alloc_size = MJUM9BYTES;
4821 #else
4822                 panic("jumbo buffer is not supported yet\n");
4823 #endif
4824         } else {
4825                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4826                 sc->mbuf_alloc_size = MCLBYTES;
4827         }
4828
4829         /* Calculate the RX Ethernet frame size for rx_bd's. */
4830         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4831
4832         DBPRINT(sc, BCE_INFO,
4833                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4834                 "max_frame_size = %d\n",
4835                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4836                 sc->max_frame_size);
4837
4838         /* Program appropriate promiscuous/multicast filtering. */
4839         bce_set_rx_mode(sc);
4840
4841         /* Init RX buffer descriptor chain. */
4842         bce_init_rx_chain(sc);  /* XXX return value */
4843
4844         /* Init TX buffer descriptor chain. */
4845         bce_init_tx_chain(sc);  /* XXX return value */
4846
4847 #ifdef DEVICE_POLLING
4848         /* Disable interrupts if we are polling. */
4849         if (ifp->if_flags & IFF_POLLING) {
4850                 bce_disable_intr(sc);
4851
4852                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4853                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4854                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4855                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4856         } else
4857 #endif
4858         /* Enable host interrupts. */
4859         bce_enable_intr(sc, 1);
4860
4861         bce_ifmedia_upd(ifp);
4862
4863         ifp->if_flags |= IFF_RUNNING;
4864         ifp->if_flags &= ~IFF_OACTIVE;
4865
4866         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4867 back:
4868         if (error)
4869                 bce_stop(sc);
4870 }
4871
4872
4873 /****************************************************************************/
4874 /* Initialize the controller just enough so that any management firmware    */
4875 /* running on the device will continue to operate corectly.                 */
4876 /*                                                                          */
4877 /* Returns:                                                                 */
4878 /*   Nothing.                                                               */
4879 /****************************************************************************/
4880 static void
4881 bce_mgmt_init(struct bce_softc *sc)
4882 {
4883         struct ifnet *ifp = &sc->arpcom.ac_if;
4884
4885         /* Bail out if management firmware is not running. */
4886         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4887                 return;
4888
4889         /* Enable all critical blocks in the MAC. */
4890         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4891             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4892                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4893                     BCE_MISC_ENABLE_DEFAULT_XI);
4894         } else {
4895                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4896         }
4897         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4898         DELAY(20);
4899
4900         bce_ifmedia_upd(ifp);
4901 }
4902
4903
4904 /****************************************************************************/
4905 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4906 /* memory visible to the controller.                                        */
4907 /*                                                                          */
4908 /* Returns:                                                                 */
4909 /*   0 for success, positive value for failure.                             */
4910 /****************************************************************************/
4911 static int
4912 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4913 {
4914         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4915         bus_dmamap_t map, tmp_map;
4916         struct mbuf *m0 = *m_head;
4917         struct tx_bd *txbd = NULL;
4918         uint16_t vlan_tag = 0, flags = 0;
4919         uint16_t chain_prod, chain_prod_start, prod;
4920         uint32_t prod_bseq;
4921         int i, error, maxsegs, nsegs;
4922 #ifdef BCE_DEBUG
4923         uint16_t debug_prod;
4924 #endif
4925
4926         /* Transfer any checksum offload flags to the bd. */
4927         if (m0->m_pkthdr.csum_flags) {
4928                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4929                         flags |= TX_BD_FLAGS_IP_CKSUM;
4930                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4931                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4932         }
4933
4934         /* Transfer any VLAN tags to the bd. */
4935         if (m0->m_flags & M_VLANTAG) {
4936                 flags |= TX_BD_FLAGS_VLAN_TAG;
4937                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4938         }
4939
4940         prod = sc->tx_prod;
4941         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4942
4943         /* Map the mbuf into DMAable memory. */
4944         map = sc->tx_mbuf_map[chain_prod_start];
4945
4946         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4947         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4948                 ("not enough segements %d\n", maxsegs));
4949         if (maxsegs > BCE_MAX_SEGMENTS)
4950                 maxsegs = BCE_MAX_SEGMENTS;
4951
4952         /* Map the mbuf into our DMA address space. */
4953         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4954                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4955         if (error)
4956                 goto back;
4957         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4958
4959         /* Reset m0 */
4960         m0 = *m_head;
4961
4962         /* prod points to an empty tx_bd at this point. */
4963         prod_bseq  = sc->tx_prod_bseq;
4964
4965 #ifdef BCE_DEBUG
4966         debug_prod = chain_prod;
4967 #endif
4968
4969         DBPRINT(sc, BCE_INFO_SEND,
4970                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4971                 "prod_bseq = 0x%08X\n",
4972                 __func__, prod, chain_prod, prod_bseq);
4973
4974         /*
4975          * Cycle through each mbuf segment that makes up
4976          * the outgoing frame, gathering the mapping info
4977          * for that segment and creating a tx_bd to for
4978          * the mbuf.
4979          */
4980         for (i = 0; i < nsegs; i++) {
4981                 chain_prod = TX_CHAIN_IDX(prod);
4982                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4983
4984                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4985                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4986                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4987                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4988                 txbd->tx_bd_flags = htole16(flags);
4989                 prod_bseq += segs[i].ds_len;
4990                 if (i == 0)
4991                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4992                 prod = NEXT_TX_BD(prod);
4993         }
4994
4995         /* Set the END flag on the last TX buffer descriptor. */
4996         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4997
4998         DBRUN(BCE_EXCESSIVE_SEND,
4999               bce_dump_tx_chain(sc, debug_prod, nsegs));
5000
5001         DBPRINT(sc, BCE_INFO_SEND,
5002                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
5003                 "prod_bseq = 0x%08X\n",
5004                 __func__, prod, chain_prod, prod_bseq);
5005
5006         /*
5007          * Ensure that the mbuf pointer for this transmission
5008          * is placed at the array index of the last
5009          * descriptor in this chain.  This is done
5010          * because a single map is used for all
5011          * segments of the mbuf and we don't want to
5012          * unload the map before all of the segments
5013          * have been freed.
5014          */
5015         sc->tx_mbuf_ptr[chain_prod] = m0;
5016
5017         tmp_map = sc->tx_mbuf_map[chain_prod];
5018         sc->tx_mbuf_map[chain_prod] = map;
5019         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
5020
5021         sc->used_tx_bd += nsegs;
5022
5023         /* Update some debug statistic counters */
5024         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5025                 sc->tx_hi_watermark = sc->used_tx_bd);
5026         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5027         DBRUNIF(1, sc->tx_mbuf_alloc++);
5028
5029         DBRUN(BCE_VERBOSE_SEND,
5030               bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
5031
5032         /* prod points to the next free tx_bd at this point. */
5033         sc->tx_prod = prod;
5034         sc->tx_prod_bseq = prod_bseq;
5035 back:
5036         if (error) {
5037                 m_freem(*m_head);
5038                 *m_head = NULL;
5039         }
5040         return error;
5041 }
5042
5043
5044 /****************************************************************************/
5045 /* Main transmit routine when called from another routine with a lock.      */
5046 /*                                                                          */
5047 /* Returns:                                                                 */
5048 /*   Nothing.                                                               */
5049 /****************************************************************************/
5050 static void
5051 bce_start(struct ifnet *ifp)
5052 {
5053         struct bce_softc *sc = ifp->if_softc;
5054         int count = 0;
5055
5056         ASSERT_SERIALIZED(ifp->if_serializer);
5057
5058         /* If there's no link or the transmit queue is empty then just exit. */
5059         if (!sc->bce_link) {
5060                 ifq_purge(&ifp->if_snd);
5061                 return;
5062         }
5063
5064         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5065                 return;
5066
5067         DBPRINT(sc, BCE_INFO_SEND,
5068                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
5069                 "tx_prod_bseq = 0x%08X\n",
5070                 __func__,
5071                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5072
5073         for (;;) {
5074                 struct mbuf *m_head;
5075
5076                 /*
5077                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5078                  * unlikely to fail.
5079                  */
5080                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5081                         ifp->if_flags |= IFF_OACTIVE;
5082                         break;
5083                 }
5084
5085                 /* Check for any frames to send. */
5086                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5087                 if (m_head == NULL)
5088                         break;
5089
5090                 /*
5091                  * Pack the data into the transmit ring. If we
5092                  * don't have room, place the mbuf back at the
5093                  * head of the queue and set the OACTIVE flag
5094                  * to wait for the NIC to drain the chain.
5095                  */
5096                 if (bce_encap(sc, &m_head)) {
5097                         ifp->if_oerrors++;
5098                         if (sc->used_tx_bd == 0) {
5099                                 continue;
5100                         } else {
5101                                 ifp->if_flags |= IFF_OACTIVE;
5102                                 break;
5103                         }
5104                 }
5105
5106                 count++;
5107
5108                 /* Send a copy of the frame to any BPF listeners. */
5109                 ETHER_BPF_MTAP(ifp, m_head);
5110         }
5111
5112         if (count == 0) {
5113                 /* no packets were dequeued */
5114                 DBPRINT(sc, BCE_VERBOSE_SEND,
5115                         "%s(): No packets were dequeued\n", __func__);
5116                 return;
5117         }
5118
5119         DBPRINT(sc, BCE_INFO_SEND,
5120                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5121                 "tx_prod_bseq = 0x%08X\n",
5122                 __func__,
5123                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5124
5125         REG_WR(sc, BCE_MQ_COMMAND,
5126             REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5127
5128         /* Start the transmit. */
5129         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5130         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5131
5132         /* Set the tx timeout. */
5133         ifp->if_timer = BCE_TX_TIMEOUT;
5134 }
5135
5136
5137 /****************************************************************************/
5138 /* Handles any IOCTL calls from the operating system.                       */
5139 /*                                                                          */
5140 /* Returns:                                                                 */
5141 /*   0 for success, positive value for failure.                             */
5142 /****************************************************************************/
5143 static int
5144 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5145 {
5146         struct bce_softc *sc = ifp->if_softc;
5147         struct ifreq *ifr = (struct ifreq *)data;
5148         struct mii_data *mii;
5149         int mask, error = 0;
5150
5151         ASSERT_SERIALIZED(ifp->if_serializer);
5152
5153         switch(command) {
5154         case SIOCSIFMTU:
5155                 /* Check that the MTU setting is supported. */
5156                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5157 #ifdef notyet
5158                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5159 #else
5160                     ifr->ifr_mtu > ETHERMTU
5161 #endif
5162                    ) {
5163                         error = EINVAL;
5164                         break;
5165                 }
5166
5167                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5168
5169                 ifp->if_mtu = ifr->ifr_mtu;
5170                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5171                 bce_init(sc);
5172                 break;
5173
5174         case SIOCSIFFLAGS:
5175                 if (ifp->if_flags & IFF_UP) {
5176                         if (ifp->if_flags & IFF_RUNNING) {
5177                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5178
5179                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5180                                         bce_set_rx_mode(sc);
5181                         } else {
5182                                 bce_init(sc);
5183                         }
5184                 } else if (ifp->if_flags & IFF_RUNNING) {
5185                         bce_stop(sc);
5186
5187                         /* If MFW is running, restart the controller a bit. */
5188                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5189                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5190                                 bce_chipinit(sc);
5191                                 bce_mgmt_init(sc);
5192                         }
5193                 }
5194                 sc->bce_if_flags = ifp->if_flags;
5195                 break;
5196
5197         case SIOCADDMULTI:
5198         case SIOCDELMULTI:
5199                 if (ifp->if_flags & IFF_RUNNING)
5200                         bce_set_rx_mode(sc);
5201                 break;
5202
5203         case SIOCSIFMEDIA:
5204         case SIOCGIFMEDIA:
5205                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5206                         sc->bce_phy_flags);
5207                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5208
5209                 mii = device_get_softc(sc->bce_miibus);
5210                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5211                 break;
5212
5213         case SIOCSIFCAP:
5214                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5215                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5216                         (uint32_t) mask);
5217
5218                 if (mask & IFCAP_HWCSUM) {
5219                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5220                         if (IFCAP_HWCSUM & ifp->if_capenable)
5221                                 ifp->if_hwassist = BCE_IF_HWASSIST;
5222                         else
5223                                 ifp->if_hwassist = 0;
5224                 }
5225                 break;
5226
5227         default:
5228                 error = ether_ioctl(ifp, command, data);
5229                 break;
5230         }
5231         return error;
5232 }
5233
5234
5235 /****************************************************************************/
5236 /* Transmit timeout handler.                                                */
5237 /*                                                                          */
5238 /* Returns:                                                                 */
5239 /*   Nothing.                                                               */
5240 /****************************************************************************/
5241 static void
5242 bce_watchdog(struct ifnet *ifp)
5243 {
5244         struct bce_softc *sc = ifp->if_softc;
5245
5246         ASSERT_SERIALIZED(ifp->if_serializer);
5247
5248         DBRUN(BCE_VERBOSE_SEND,
5249               bce_dump_driver_state(sc);
5250               bce_dump_status_block(sc));
5251
5252         /*
5253          * If we are in this routine because of pause frames, then
5254          * don't reset the hardware.
5255          */
5256         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5257                 return;
5258
5259         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5260
5261         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5262
5263         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5264         bce_init(sc);
5265
5266         ifp->if_oerrors++;
5267
5268         if (!ifq_is_empty(&ifp->if_snd))
5269                 if_devstart(ifp);
5270 }
5271
5272
5273 #ifdef DEVICE_POLLING
5274
5275 static void
5276 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5277 {
5278         struct bce_softc *sc = ifp->if_softc;
5279         struct status_block *sblk = sc->status_block;
5280         uint16_t hw_tx_cons, hw_rx_cons;
5281
5282         ASSERT_SERIALIZED(ifp->if_serializer);
5283
5284         switch (cmd) {
5285         case POLL_REGISTER:
5286                 bce_disable_intr(sc);
5287
5288                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5289                        (1 << 16) | sc->bce_rx_quick_cons_trip);
5290                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5291                        (1 << 16) | sc->bce_tx_quick_cons_trip);
5292                 return;
5293         case POLL_DEREGISTER:
5294                 bce_enable_intr(sc, 1);
5295
5296                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5297                        (sc->bce_tx_quick_cons_trip_int << 16) |
5298                        sc->bce_tx_quick_cons_trip);
5299                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5300                        (sc->bce_rx_quick_cons_trip_int << 16) |
5301                        sc->bce_rx_quick_cons_trip);
5302                 return;
5303         default:
5304                 break;
5305         }
5306
5307         if (cmd == POLL_AND_CHECK_STATUS) {
5308                 uint32_t status_attn_bits;
5309
5310                 status_attn_bits = sblk->status_attn_bits;
5311
5312                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5313                         if_printf(ifp,
5314                         "Simulating unexpected status attention bit set.");
5315                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5316
5317                 /* Was it a link change interrupt? */
5318                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5319                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5320                         bce_phy_intr(sc);
5321
5322                 /* Clear any transient status updates during link state change. */
5323                 REG_WR(sc, BCE_HC_COMMAND,
5324                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5325                 REG_RD(sc, BCE_HC_COMMAND);
5326
5327                 /*
5328                  * If any other attention is asserted then
5329                  * the chip is toast.
5330                  */
5331                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5332                      (sblk->status_attn_bits_ack &
5333                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5334                         DBRUN(1, sc->unexpected_attentions++);
5335
5336                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5337                                   sblk->status_attn_bits);
5338
5339                         DBRUN(BCE_FATAL,
5340                         if (bce_debug_unexpected_attention == 0)
5341                                 bce_breakpoint(sc));
5342
5343                         bce_init(sc);
5344                         return;
5345                 }
5346         }
5347
5348         hw_rx_cons = bce_get_hw_rx_cons(sc);
5349         hw_tx_cons = bce_get_hw_tx_cons(sc);
5350
5351         /* Check for any completed RX frames. */
5352         if (hw_rx_cons != sc->hw_rx_cons)
5353                 bce_rx_intr(sc, count);
5354
5355         /* Check for any completed TX frames. */
5356         if (hw_tx_cons != sc->hw_tx_cons)
5357                 bce_tx_intr(sc);
5358
5359         /* Check for new frames to transmit. */
5360         if (!ifq_is_empty(&ifp->if_snd))
5361                 if_devstart(ifp);
5362 }
5363
5364 #endif  /* DEVICE_POLLING */
5365
5366
5367 /*
5368  * Interrupt handler.
5369  */
5370 /****************************************************************************/
5371 /* Main interrupt entry point.  Verifies that the controller generated the  */
5372 /* interrupt and then calls a separate routine for handle the various       */
5373 /* interrupt causes (PHY, TX, RX).                                          */
5374 /*                                                                          */
5375 /* Returns:                                                                 */
5376 /*   0 for success, positive value for failure.                             */
5377 /****************************************************************************/
5378 static void
5379 bce_intr(void *xsc)
5380 {
5381         struct bce_softc *sc = xsc;
5382         struct ifnet *ifp = &sc->arpcom.ac_if;
5383         struct status_block *sblk;
5384         uint16_t hw_rx_cons, hw_tx_cons;
5385
5386         ASSERT_SERIALIZED(ifp->if_serializer);
5387
5388         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5389         DBRUNIF(1, sc->interrupts_generated++);
5390
5391         sblk = sc->status_block;
5392
5393         /*
5394          * If the hardware status block index matches the last value
5395          * read by the driver and we haven't asserted our interrupt
5396          * then there's nothing to do.
5397          */
5398         if (sblk->status_idx == sc->last_status_idx &&
5399             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5400              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5401                 return;
5402
5403         /* Ack the interrupt and stop others from occuring. */
5404         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5405                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5406                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5407
5408         /*
5409          * Read back to deassert IRQ immediately to avoid too
5410          * many spurious interrupts.
5411          */
5412         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5413
5414         /* Check if the hardware has finished any work. */
5415         hw_rx_cons = bce_get_hw_rx_cons(sc);
5416         hw_tx_cons = bce_get_hw_tx_cons(sc);
5417
5418         /* Keep processing data as long as there is work to do. */
5419         for (;;) {
5420                 uint32_t status_attn_bits;
5421
5422                 status_attn_bits = sblk->status_attn_bits;
5423
5424                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5425                         if_printf(ifp,
5426                         "Simulating unexpected status attention bit set.");
5427                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5428
5429                 /* Was it a link change interrupt? */
5430                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5431                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5432                         bce_phy_intr(sc);
5433
5434                         /*
5435                          * Clear any transient status updates during link state
5436                          * change.
5437                          */
5438                         REG_WR(sc, BCE_HC_COMMAND,
5439                             sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5440                         REG_RD(sc, BCE_HC_COMMAND);
5441                 }
5442
5443                 /*
5444                  * If any other attention is asserted then
5445                  * the chip is toast.
5446                  */
5447                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5448                      (sblk->status_attn_bits_ack &
5449                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5450                         DBRUN(1, sc->unexpected_attentions++);
5451
5452                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5453                                   sblk->status_attn_bits);
5454
5455                         DBRUN(BCE_FATAL,
5456                         if (bce_debug_unexpected_attention == 0)
5457                                 bce_breakpoint(sc));
5458
5459                         bce_init(sc);
5460                         return;
5461                 }
5462
5463                 /* Check for any completed RX frames. */
5464                 if (hw_rx_cons != sc->hw_rx_cons)
5465                         bce_rx_intr(sc, -1);
5466
5467                 /* Check for any completed TX frames. */
5468                 if (hw_tx_cons != sc->hw_tx_cons)
5469                         bce_tx_intr(sc);
5470
5471                 /*
5472                  * Save the status block index value
5473                  * for use during the next interrupt.
5474                  */
5475                 sc->last_status_idx = sblk->status_idx;
5476
5477                 /*
5478                  * Prevent speculative reads from getting
5479                  * ahead of the status block.
5480                  */
5481                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5482                                   BUS_SPACE_BARRIER_READ);
5483
5484                 /*
5485                  * If there's no work left then exit the
5486                  * interrupt service routine.
5487                  */
5488                 hw_rx_cons = bce_get_hw_rx_cons(sc);
5489                 hw_tx_cons = bce_get_hw_tx_cons(sc);
5490                 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5491                         break;
5492         }
5493
5494         /* Re-enable interrupts. */
5495         bce_enable_intr(sc, 0);
5496
5497         if (sc->bce_coalchg_mask)
5498                 bce_coal_change(sc);
5499
5500         /* Handle any frames that arrived while handling the interrupt. */
5501         if (!ifq_is_empty(&ifp->if_snd))
5502                 if_devstart(ifp);
5503 }
5504
5505
5506 /****************************************************************************/
5507 /* Programs the various packet receive modes (broadcast and multicast).     */
5508 /*                                                                          */
5509 /* Returns:                                                                 */
5510 /*   Nothing.                                                               */
5511 /****************************************************************************/
5512 static void
5513 bce_set_rx_mode(struct bce_softc *sc)
5514 {
5515         struct ifnet *ifp = &sc->arpcom.ac_if;
5516         struct ifmultiaddr *ifma;
5517         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5518         uint32_t rx_mode, sort_mode;
5519         int h, i;
5520
5521         ASSERT_SERIALIZED(ifp->if_serializer);
5522
5523         /* Initialize receive mode default settings. */
5524         rx_mode = sc->rx_mode &
5525                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5526                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5527         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5528
5529         /*
5530          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5531          * be enbled.
5532          */
5533         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5534             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5535                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5536
5537         /*
5538          * Check for promiscuous, all multicast, or selected
5539          * multicast address filtering.
5540          */
5541         if (ifp->if_flags & IFF_PROMISC) {
5542                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5543
5544                 /* Enable promiscuous mode. */
5545                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5546                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5547         } else if (ifp->if_flags & IFF_ALLMULTI) {
5548                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5549
5550                 /* Enable all multicast addresses. */
5551                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5552                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5553                                0xffffffff);
5554                 }
5555                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5556         } else {
5557                 /* Accept one or more multicast(s). */
5558                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5559
5560                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5561                         if (ifma->ifma_addr->sa_family != AF_LINK)
5562                                 continue;
5563                         h = ether_crc32_le(
5564                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5565                             ETHER_ADDR_LEN) & 0xFF;
5566                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5567                 }
5568
5569                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5570                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5571                                hashes[i]);
5572                 }
5573                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5574         }
5575
5576         /* Only make changes if the recive mode has actually changed. */
5577         if (rx_mode != sc->rx_mode) {
5578                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5579                         rx_mode);
5580
5581                 sc->rx_mode = rx_mode;
5582                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5583         }
5584
5585         /* Disable and clear the exisitng sort before enabling a new sort. */
5586         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5587         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5588         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5589 }
5590
5591
5592 /****************************************************************************/
5593 /* Called periodically to updates statistics from the controllers           */
5594 /* statistics block.                                                        */
5595 /*                                                                          */
5596 /* Returns:                                                                 */
5597 /*   Nothing.                                                               */
5598 /****************************************************************************/
5599 static void
5600 bce_stats_update(struct bce_softc *sc)
5601 {
5602         struct ifnet *ifp = &sc->arpcom.ac_if;
5603         struct statistics_block *stats = sc->stats_block;
5604
5605         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5606
5607         ASSERT_SERIALIZED(ifp->if_serializer);
5608
5609         /*
5610          * Certain controllers don't report carrier sense errors correctly.
5611          * See errata E11_5708CA0_1165.
5612          */
5613         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5614             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5615                 ifp->if_oerrors +=
5616                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5617         }
5618
5619         /*
5620          * Update the sysctl statistics from the hardware statistics.
5621          */
5622         sc->stat_IfHCInOctets =
5623                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5624                  (uint64_t)stats->stat_IfHCInOctets_lo;
5625
5626         sc->stat_IfHCInBadOctets =
5627                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5628                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5629
5630         sc->stat_IfHCOutOctets =
5631                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5632                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5633
5634         sc->stat_IfHCOutBadOctets =
5635                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5636                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5637
5638         sc->stat_IfHCInUcastPkts =
5639                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5640                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5641
5642         sc->stat_IfHCInMulticastPkts =
5643                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5644                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5645
5646         sc->stat_IfHCInBroadcastPkts =
5647                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5648                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5649
5650         sc->stat_IfHCOutUcastPkts =
5651                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5652                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5653
5654         sc->stat_IfHCOutMulticastPkts =
5655                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5656                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5657
5658         sc->stat_IfHCOutBroadcastPkts =
5659                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5660                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5661
5662         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5663                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5664
5665         sc->stat_Dot3StatsCarrierSenseErrors =
5666                 stats->stat_Dot3StatsCarrierSenseErrors;
5667
5668         sc->stat_Dot3StatsFCSErrors =
5669                 stats->stat_Dot3StatsFCSErrors;
5670
5671         sc->stat_Dot3StatsAlignmentErrors =
5672                 stats->stat_Dot3StatsAlignmentErrors;
5673
5674         sc->stat_Dot3StatsSingleCollisionFrames =
5675                 stats->stat_Dot3StatsSingleCollisionFrames;
5676
5677         sc->stat_Dot3StatsMultipleCollisionFrames =
5678                 stats->stat_Dot3StatsMultipleCollisionFrames;
5679
5680         sc->stat_Dot3StatsDeferredTransmissions =
5681                 stats->stat_Dot3StatsDeferredTransmissions;
5682
5683         sc->stat_Dot3StatsExcessiveCollisions =
5684                 stats->stat_Dot3StatsExcessiveCollisions;
5685
5686         sc->stat_Dot3StatsLateCollisions =
5687                 stats->stat_Dot3StatsLateCollisions;
5688
5689         sc->stat_EtherStatsCollisions =
5690                 stats->stat_EtherStatsCollisions;
5691
5692         sc->stat_EtherStatsFragments =
5693                 stats->stat_EtherStatsFragments;
5694
5695         sc->stat_EtherStatsJabbers =
5696                 stats->stat_EtherStatsJabbers;
5697
5698         sc->stat_EtherStatsUndersizePkts =
5699                 stats->stat_EtherStatsUndersizePkts;
5700
5701         sc->stat_EtherStatsOverrsizePkts =
5702                 stats->stat_EtherStatsOverrsizePkts;
5703
5704         sc->stat_EtherStatsPktsRx64Octets =
5705                 stats->stat_EtherStatsPktsRx64Octets;
5706
5707         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5708                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5709
5710         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5711                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5712
5713         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5714                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5715
5716         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5717                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5718
5719         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5720                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5721
5722         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5723                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5724
5725         sc->stat_EtherStatsPktsTx64Octets =
5726                 stats->stat_EtherStatsPktsTx64Octets;
5727
5728         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5729                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5730
5731         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5732                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5733
5734         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5735                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5736
5737         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5738                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5739
5740         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5741                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5742
5743         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5744                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5745
5746         sc->stat_XonPauseFramesReceived =
5747                 stats->stat_XonPauseFramesReceived;
5748
5749         sc->stat_XoffPauseFramesReceived =
5750                 stats->stat_XoffPauseFramesReceived;
5751
5752         sc->stat_OutXonSent =
5753                 stats->stat_OutXonSent;
5754
5755         sc->stat_OutXoffSent =
5756                 stats->stat_OutXoffSent;
5757
5758         sc->stat_FlowControlDone =
5759                 stats->stat_FlowControlDone;
5760
5761         sc->stat_MacControlFramesReceived =
5762                 stats->stat_MacControlFramesReceived;
5763
5764         sc->stat_XoffStateEntered =
5765                 stats->stat_XoffStateEntered;
5766
5767         sc->stat_IfInFramesL2FilterDiscards =
5768                 stats->stat_IfInFramesL2FilterDiscards;
5769
5770         sc->stat_IfInRuleCheckerDiscards =
5771                 stats->stat_IfInRuleCheckerDiscards;
5772
5773         sc->stat_IfInFTQDiscards =
5774                 stats->stat_IfInFTQDiscards;
5775
5776         sc->stat_IfInMBUFDiscards =
5777                 stats->stat_IfInMBUFDiscards;
5778
5779         sc->stat_IfInRuleCheckerP4Hit =
5780                 stats->stat_IfInRuleCheckerP4Hit;
5781
5782         sc->stat_CatchupInRuleCheckerDiscards =
5783                 stats->stat_CatchupInRuleCheckerDiscards;
5784
5785         sc->stat_CatchupInFTQDiscards =
5786                 stats->stat_CatchupInFTQDiscards;
5787
5788         sc->stat_CatchupInMBUFDiscards =
5789                 stats->stat_CatchupInMBUFDiscards;
5790
5791         sc->stat_CatchupInRuleCheckerP4Hit =
5792                 stats->stat_CatchupInRuleCheckerP4Hit;
5793
5794         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5795
5796         /*
5797          * Update the interface statistics from the
5798          * hardware statistics.
5799          */
5800         ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5801
5802         ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5803             (u_long)sc->stat_EtherStatsOverrsizePkts +
5804             (u_long)sc->stat_IfInMBUFDiscards +
5805             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5806             (u_long)sc->stat_Dot3StatsFCSErrors +
5807             (u_long)sc->stat_IfInRuleCheckerDiscards +
5808             (u_long)sc->stat_IfInFTQDiscards +
5809             (u_long)sc->com_no_buffers;
5810
5811         ifp->if_oerrors =
5812             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5813             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5814             (u_long)sc->stat_Dot3StatsLateCollisions;
5815
5816         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5817 }
5818
5819
5820 /****************************************************************************/
5821 /* Periodic function to notify the bootcode that the driver is still        */
5822 /* present.                                                                 */
5823 /*                                                                          */
5824 /* Returns:                                                                 */
5825 /*   Nothing.                                                               */
5826 /****************************************************************************/
5827 static void
5828 bce_pulse(void *xsc)
5829 {
5830         struct bce_softc *sc = xsc;
5831         struct ifnet *ifp = &sc->arpcom.ac_if;
5832         uint32_t msg;
5833
5834         lwkt_serialize_enter(ifp->if_serializer);
5835
5836         /* Tell the firmware that the driver is still running. */
5837         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5838         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5839
5840         /* Update the bootcode condition. */
5841         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5842
5843         /* Report whether the bootcode still knows the driver is running. */
5844         if (!sc->bce_drv_cardiac_arrest) {
5845                 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5846                         sc->bce_drv_cardiac_arrest = 1;
5847                         if_printf(ifp, "Bootcode lost the driver pulse! "
5848                             "(bc_state = 0x%08X)\n", sc->bc_state);
5849                 }
5850         } else {
5851                 /*
5852                  * Not supported by all bootcode versions.
5853                  * (v5.0.11+ and v5.2.1+)  Older bootcode
5854                  * will require the driver to reset the
5855                  * controller to clear this condition.
5856                  */
5857                 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5858                         sc->bce_drv_cardiac_arrest = 0;
5859                         if_printf(ifp, "Bootcode found the driver pulse! "
5860                             "(bc_state = 0x%08X)\n", sc->bc_state);
5861                 }
5862         }
5863
5864         /* Schedule the next pulse. */
5865         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5866
5867         lwkt_serialize_exit(ifp->if_serializer);
5868 }
5869
5870
5871 /****************************************************************************/
5872 /* Periodic function to perform maintenance tasks.                          */
5873 /*                                                                          */
5874 /* Returns:                                                                 */
5875 /*   Nothing.                                                               */
5876 /****************************************************************************/
5877 static void
5878 bce_tick_serialized(struct bce_softc *sc)
5879 {
5880         struct ifnet *ifp = &sc->arpcom.ac_if;
5881         struct mii_data *mii;
5882
5883         ASSERT_SERIALIZED(ifp->if_serializer);
5884
5885         /* Update the statistics from the hardware statistics block. */
5886         bce_stats_update(sc);
5887
5888         /* Schedule the next tick. */
5889         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5890
5891         /* If link is up already up then we're done. */
5892         if (sc->bce_link)
5893                 return;
5894
5895         mii = device_get_softc(sc->bce_miibus);
5896         mii_tick(mii);
5897
5898         /* Check if the link has come up. */
5899         if ((mii->mii_media_status & IFM_ACTIVE) &&
5900             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5901                 sc->bce_link++;
5902                 /* Now that link is up, handle any outstanding TX traffic. */
5903                 if (!ifq_is_empty(&ifp->if_snd))
5904                         if_devstart(ifp);
5905         }
5906 }
5907
5908
5909 static void
5910 bce_tick(void *xsc)
5911 {
5912         struct bce_softc *sc = xsc;
5913         struct ifnet *ifp = &sc->arpcom.ac_if;
5914
5915         lwkt_serialize_enter(ifp->if_serializer);
5916         bce_tick_serialized(sc);
5917         lwkt_serialize_exit(ifp->if_serializer);
5918 }
5919
5920
5921 #ifdef BCE_DEBUG
5922 /****************************************************************************/
5923 /* Allows the driver state to be dumped through the sysctl interface.       */
5924 /*                                                                          */
5925 /* Returns:                                                                 */
5926 /*   0 for success, positive value for failure.                             */
5927 /****************************************************************************/
5928 static int
5929 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5930 {
5931         int error;
5932         int result;
5933         struct bce_softc *sc;
5934
5935         result = -1;
5936         error = sysctl_handle_int(oidp, &result, 0, req);
5937
5938         if (error || !req->newptr)
5939                 return (error);
5940
5941         if (result == 1) {
5942                 sc = (struct bce_softc *)arg1;
5943                 bce_dump_driver_state(sc);
5944         }
5945
5946         return error;
5947 }
5948
5949
5950 /****************************************************************************/
5951 /* Allows the hardware state to be dumped through the sysctl interface.     */
5952 /*                                                                          */
5953 /* Returns:                                                                 */
5954 /*   0 for success, positive value for failure.                             */
5955 /****************************************************************************/
5956 static int
5957 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5958 {
5959         int error;
5960         int result;
5961         struct bce_softc *sc;
5962
5963         result = -1;
5964         error = sysctl_handle_int(oidp, &result, 0, req);
5965
5966         if (error || !req->newptr)
5967                 return (error);
5968
5969         if (result == 1) {
5970                 sc = (struct bce_softc *)arg1;
5971                 bce_dump_hw_state(sc);
5972         }
5973
5974         return error;
5975 }
5976
5977
5978 /****************************************************************************/
5979 /* Provides a sysctl interface to allows dumping the RX chain.              */
5980 /*                                                                          */
5981 /* Returns:                                                                 */
5982 /*   0 for success, positive value for failure.                             */
5983 /****************************************************************************/
5984 static int
5985 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5986 {
5987         int error;
5988         int result;
5989         struct bce_softc *sc;
5990
5991         result = -1;
5992         error = sysctl_handle_int(oidp, &result, 0, req);
5993
5994         if (error || !req->newptr)
5995                 return (error);
5996
5997         if (result == 1) {
5998                 sc = (struct bce_softc *)arg1;
5999                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
6000         }
6001
6002         return error;
6003 }
6004
6005
6006 /****************************************************************************/
6007 /* Provides a sysctl interface to allows dumping the TX chain.              */
6008 /*                                                                          */
6009 /* Returns:                                                                 */
6010 /*   0 for success, positive value for failure.                             */
6011 /****************************************************************************/
6012 static int
6013 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
6014 {
6015         int error;
6016         int result;
6017         struct bce_softc *sc;
6018
6019         result = -1;
6020         error = sysctl_handle_int(oidp, &result, 0, req);
6021
6022         if (error || !req->newptr)
6023                 return (error);
6024
6025         if (result == 1) {
6026                 sc = (struct bce_softc *)arg1;
6027                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
6028         }
6029
6030         return error;
6031 }
6032
6033
6034 /****************************************************************************/
6035 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
6036 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
6037 /*                                                                          */
6038 /* Returns:                                                                 */
6039 /*   0 for success, positive value for failure.                             */
6040 /****************************************************************************/
6041 static int
6042 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6043 {
6044         struct bce_softc *sc;
6045         int error;
6046         uint32_t val, result;
6047
6048         result = -1;
6049         error = sysctl_handle_int(oidp, &result, 0, req);
6050         if (error || (req->newptr == NULL))
6051                 return (error);
6052
6053         /* Make sure the register is accessible. */
6054         if (result < 0x8000) {
6055                 sc = (struct bce_softc *)arg1;
6056                 val = REG_RD(sc, result);
6057                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6058                           result, val);
6059         } else if (result < 0x0280000) {
6060                 sc = (struct bce_softc *)arg1;
6061                 val = REG_RD_IND(sc, result);
6062                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6063                           result, val);
6064         }
6065         return (error);
6066 }
6067
6068
6069 /****************************************************************************/
6070 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
6071 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
6072 /*                                                                          */
6073 /* Returns:                                                                 */
6074 /*   0 for success, positive value for failure.                             */
6075 /****************************************************************************/
6076 static int
6077 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6078 {
6079         struct bce_softc *sc;
6080         device_t dev;
6081         int error, result;
6082         uint16_t val;
6083
6084         result = -1;
6085         error = sysctl_handle_int(oidp, &result, 0, req);
6086         if (error || (req->newptr == NULL))
6087                 return (error);
6088
6089         /* Make sure the register is accessible. */
6090         if (result < 0x20) {
6091                 sc = (struct bce_softc *)arg1;
6092                 dev = sc->bce_dev;
6093                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6094                 if_printf(&sc->arpcom.ac_if,
6095                           "phy 0x%02X = 0x%04X\n", result, val);
6096         }
6097         return (error);
6098 }
6099
6100
6101 /****************************************************************************/
6102 /* Provides a sysctl interface to forcing the driver to dump state and      */
6103 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
6104 /*                                                                          */
6105 /* Returns:                                                                 */
6106 /*   0 for success, positive value for failure.                             */
6107 /****************************************************************************/
6108 static int
6109 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6110 {
6111         int error;
6112         int result;
6113         struct bce_softc *sc;
6114
6115         result = -1;
6116         error = sysctl_handle_int(oidp, &result, 0, req);
6117
6118         if (error || !req->newptr)
6119                 return (error);
6120
6121         if (result == 1) {
6122                 sc = (struct bce_softc *)arg1;
6123                 bce_breakpoint(sc);
6124         }
6125
6126         return error;
6127 }
6128 #endif
6129
6130
6131 /****************************************************************************/
6132 /* Adds any sysctl parameters for tuning or debugging purposes.             */
6133 /*                                                                          */
6134 /* Returns:                                                                 */
6135 /*   0 for success, positive value for failure.                             */
6136 /****************************************************************************/
6137 static void
6138 bce_add_sysctls(struct bce_softc *sc)
6139 {
6140         struct sysctl_ctx_list *ctx;
6141         struct sysctl_oid_list *children;
6142
6143         sysctl_ctx_init(&sc->bce_sysctl_ctx);
6144         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6145                                               SYSCTL_STATIC_CHILDREN(_hw),
6146                                               OID_AUTO,
6147                                               device_get_nameunit(sc->bce_dev),
6148                                               CTLFLAG_RD, 0, "");
6149         if (sc->bce_sysctl_tree == NULL) {
6150                 device_printf(sc->bce_dev, "can't add sysctl node\n");
6151                 return;
6152         }
6153
6154         ctx = &sc->bce_sysctl_ctx;
6155         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6156
6157         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6158                         CTLTYPE_INT | CTLFLAG_RW,
6159                         sc, 0, bce_sysctl_tx_bds_int, "I",
6160                         "Send max coalesced BD count during interrupt");
6161         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6162                         CTLTYPE_INT | CTLFLAG_RW,
6163                         sc, 0, bce_sysctl_tx_bds, "I",
6164                         "Send max coalesced BD count");
6165         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6166                         CTLTYPE_INT | CTLFLAG_RW,
6167                         sc, 0, bce_sysctl_tx_ticks_int, "I",
6168                         "Send coalescing ticks during interrupt");
6169         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6170                         CTLTYPE_INT | CTLFLAG_RW,
6171                         sc, 0, bce_sysctl_tx_ticks, "I",
6172                         "Send coalescing ticks");
6173
6174         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6175                         CTLTYPE_INT | CTLFLAG_RW,
6176                         sc, 0, bce_sysctl_rx_bds_int, "I",
6177                         "Receive max coalesced BD count during interrupt");
6178         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6179                         CTLTYPE_INT | CTLFLAG_RW,
6180                         sc, 0, bce_sysctl_rx_bds, "I",
6181                         "Receive max coalesced BD count");
6182         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6183                         CTLTYPE_INT | CTLFLAG_RW,
6184                         sc, 0, bce_sysctl_rx_ticks_int, "I",
6185                         "Receive coalescing ticks during interrupt");
6186         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6187                         CTLTYPE_INT | CTLFLAG_RW,
6188                         sc, 0, bce_sysctl_rx_ticks, "I",
6189                         "Receive coalescing ticks");
6190
6191 #ifdef BCE_DEBUG
6192         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6193                 "rx_low_watermark",
6194                 CTLFLAG_RD, &sc->rx_low_watermark,
6195                 0, "Lowest level of free rx_bd's");
6196
6197         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6198                 "rx_empty_count",
6199                 CTLFLAG_RD, &sc->rx_empty_count,
6200                 0, "Number of times the RX chain was empty");
6201
6202         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6203                 "tx_hi_watermark",
6204                 CTLFLAG_RD, &sc->tx_hi_watermark,
6205                 0, "Highest level of used tx_bd's");
6206
6207         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6208                 "tx_full_count",
6209                 CTLFLAG_RD, &sc->tx_full_count,
6210                 0, "Number of times the TX chain was full");
6211
6212         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6213                 "l2fhdr_status_errors",
6214                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6215                 0, "l2_fhdr status errors");
6216
6217         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6218                 "unexpected_attentions",
6219                 CTLFLAG_RD, &sc->unexpected_attentions,
6220                 0, "unexpected attentions");
6221
6222         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6223                 "lost_status_block_updates",
6224                 CTLFLAG_RD, &sc->lost_status_block_updates,
6225                 0, "lost status block updates");
6226
6227         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6228                 "mbuf_alloc_failed",
6229                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6230                 0, "mbuf cluster allocation failures");
6231 #endif
6232
6233         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6234                 "stat_IfHCInOctets",
6235                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6236                 "Bytes received");
6237
6238         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6239                 "stat_IfHCInBadOctets",
6240                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6241                 "Bad bytes received");
6242
6243         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6244                 "stat_IfHCOutOctets",
6245                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6246                 "Bytes sent");
6247
6248         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6249                 "stat_IfHCOutBadOctets",
6250                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6251                 "Bad bytes sent");
6252
6253         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6254                 "stat_IfHCInUcastPkts",
6255                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6256                 "Unicast packets received");
6257
6258         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6259                 "stat_IfHCInMulticastPkts",
6260                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6261                 "Multicast packets received");
6262
6263         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6264                 "stat_IfHCInBroadcastPkts",
6265                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6266                 "Broadcast packets received");
6267
6268         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6269                 "stat_IfHCOutUcastPkts",
6270                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6271                 "Unicast packets sent");
6272
6273         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6274                 "stat_IfHCOutMulticastPkts",
6275                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6276                 "Multicast packets sent");
6277
6278         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6279                 "stat_IfHCOutBroadcastPkts",
6280                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6281                 "Broadcast packets sent");
6282
6283         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6284                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6285                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6286                 0, "Internal MAC transmit errors");
6287
6288         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6289                 "stat_Dot3StatsCarrierSenseErrors",
6290                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6291                 0, "Carrier sense errors");
6292
6293         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6294                 "stat_Dot3StatsFCSErrors",
6295                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6296                 0, "Frame check sequence errors");
6297
6298         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6299                 "stat_Dot3StatsAlignmentErrors",
6300                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6301                 0, "Alignment errors");
6302
6303         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6304                 "stat_Dot3StatsSingleCollisionFrames",
6305                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6306                 0, "Single Collision Frames");
6307
6308         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6309                 "stat_Dot3StatsMultipleCollisionFrames",
6310                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6311                 0, "Multiple Collision Frames");
6312
6313         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6314                 "stat_Dot3StatsDeferredTransmissions",
6315                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6316                 0, "Deferred Transmissions");
6317
6318         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6319                 "stat_Dot3StatsExcessiveCollisions",
6320                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6321                 0, "Excessive Collisions");
6322
6323         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6324                 "stat_Dot3StatsLateCollisions",
6325                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6326                 0, "Late Collisions");
6327
6328         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6329                 "stat_EtherStatsCollisions",
6330                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6331                 0, "Collisions");
6332
6333         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6334                 "stat_EtherStatsFragments",
6335                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6336                 0, "Fragments");
6337
6338         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6339                 "stat_EtherStatsJabbers",
6340                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6341                 0, "Jabbers");
6342
6343         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6344                 "stat_EtherStatsUndersizePkts",
6345                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6346                 0, "Undersize packets");
6347
6348         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6349                 "stat_EtherStatsOverrsizePkts",
6350                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6351                 0, "stat_EtherStatsOverrsizePkts");
6352
6353         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6354                 "stat_EtherStatsPktsRx64Octets",
6355                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6356                 0, "Bytes received in 64 byte packets");
6357
6358         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6359                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6360                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6361                 0, "Bytes received in 65 to 127 byte packets");
6362
6363         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6364                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6365                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6366                 0, "Bytes received in 128 to 255 byte packets");
6367
6368         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6369                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6370                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6371                 0, "Bytes received in 256 to 511 byte packets");
6372
6373         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6374                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6375                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6376                 0, "Bytes received in 512 to 1023 byte packets");
6377
6378         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6379                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6380                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6381                 0, "Bytes received in 1024 t0 1522 byte packets");
6382
6383         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6384                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6385                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6386                 0, "Bytes received in 1523 to 9022 byte packets");
6387
6388         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6389                 "stat_EtherStatsPktsTx64Octets",
6390                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6391                 0, "Bytes sent in 64 byte packets");
6392
6393         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6394                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6395                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6396                 0, "Bytes sent in 65 to 127 byte packets");
6397
6398         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6399                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6400                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6401                 0, "Bytes sent in 128 to 255 byte packets");
6402
6403         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6404                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6405                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6406                 0, "Bytes sent in 256 to 511 byte packets");
6407
6408         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6409                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6410                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6411                 0, "Bytes sent in 512 to 1023 byte packets");
6412
6413         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6414                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6415                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6416                 0, "Bytes sent in 1024 to 1522 byte packets");
6417
6418         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6419                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6420                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6421                 0, "Bytes sent in 1523 to 9022 byte packets");
6422
6423         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6424                 "stat_XonPauseFramesReceived",
6425                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6426                 0, "XON pause frames receved");
6427
6428         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6429                 "stat_XoffPauseFramesReceived",
6430                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6431                 0, "XOFF pause frames received");
6432
6433         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6434                 "stat_OutXonSent",
6435                 CTLFLAG_RD, &sc->stat_OutXonSent,
6436                 0, "XON pause frames sent");
6437
6438         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6439                 "stat_OutXoffSent",
6440                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6441                 0, "XOFF pause frames sent");
6442
6443         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6444                 "stat_FlowControlDone",
6445                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6446                 0, "Flow control done");
6447
6448         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6449                 "stat_MacControlFramesReceived",
6450                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6451                 0, "MAC control frames received");
6452
6453         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6454                 "stat_XoffStateEntered",
6455                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6456                 0, "XOFF state entered");
6457
6458         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6459                 "stat_IfInFramesL2FilterDiscards",
6460                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6461                 0, "Received L2 packets discarded");
6462
6463         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6464                 "stat_IfInRuleCheckerDiscards",
6465                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6466                 0, "Received packets discarded by rule");
6467
6468         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6469                 "stat_IfInFTQDiscards",
6470                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6471                 0, "Received packet FTQ discards");
6472
6473         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6474                 "stat_IfInMBUFDiscards",
6475                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6476                 0, "Received packets discarded due to lack of controller buffer memory");
6477
6478         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6479                 "stat_IfInRuleCheckerP4Hit",
6480                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6481                 0, "Received packets rule checker hits");
6482
6483         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6484                 "stat_CatchupInRuleCheckerDiscards",
6485                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6486                 0, "Received packets discarded in Catchup path");
6487
6488         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6489                 "stat_CatchupInFTQDiscards",
6490                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6491                 0, "Received packets discarded in FTQ in Catchup path");
6492
6493         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6494                 "stat_CatchupInMBUFDiscards",
6495                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6496                 0, "Received packets discarded in controller buffer memory in Catchup path");
6497
6498         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6499                 "stat_CatchupInRuleCheckerP4Hit",
6500                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6501                 0, "Received packets rule checker hits in Catchup path");
6502
6503         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6504                 "com_no_buffers",
6505                 CTLFLAG_RD, &sc->com_no_buffers,
6506                 0, "Valid packets received but no RX buffers available");
6507
6508 #ifdef BCE_DEBUG
6509         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6510                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6511                 (void *)sc, 0,
6512                 bce_sysctl_driver_state, "I", "Drive state information");
6513
6514         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6515                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6516                 (void *)sc, 0,
6517                 bce_sysctl_hw_state, "I", "Hardware state information");
6518
6519         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6520                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6521                 (void *)sc, 0,
6522                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6523
6524         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6525                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6526                 (void *)sc, 0,
6527                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6528
6529         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6530                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6531                 (void *)sc, 0,
6532                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6533
6534         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6535                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6536                 (void *)sc, 0,
6537                 bce_sysctl_reg_read, "I", "Register read");
6538
6539         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6540                 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6541                 (void *)sc, 0,
6542                 bce_sysctl_phy_read, "I", "PHY register read");
6543
6544 #endif
6545
6546 }
6547
6548
6549 /****************************************************************************/
6550 /* BCE Debug Routines                                                       */
6551 /****************************************************************************/
6552 #ifdef BCE_DEBUG
6553
6554 /****************************************************************************/
6555 /* Freezes the controller to allow for a cohesive state dump.               */
6556 /*                                                                          */
6557 /* Returns:                                                                 */
6558 /*   Nothing.                                                               */
6559 /****************************************************************************/
6560 static void
6561 bce_freeze_controller(struct bce_softc *sc)
6562 {
6563         uint32_t val;
6564
6565         val = REG_RD(sc, BCE_MISC_COMMAND);
6566         val |= BCE_MISC_COMMAND_DISABLE_ALL;
6567         REG_WR(sc, BCE_MISC_COMMAND, val);
6568 }
6569
6570
6571 /****************************************************************************/
6572 /* Unfreezes the controller after a freeze operation.  This may not always  */
6573 /* work and the controller will require a reset!                            */
6574 /*                                                                          */
6575 /* Returns:                                                                 */
6576 /*   Nothing.                                                               */
6577 /****************************************************************************/
6578 static void
6579 bce_unfreeze_controller(struct bce_softc *sc)
6580 {
6581         uint32_t val;
6582
6583         val = REG_RD(sc, BCE_MISC_COMMAND);
6584         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6585         REG_WR(sc, BCE_MISC_COMMAND, val);
6586 }
6587
6588
6589 /****************************************************************************/
6590 /* Prints out information about an mbuf.                                    */
6591 /*                                                                          */
6592 /* Returns:                                                                 */
6593 /*   Nothing.                                                               */
6594 /****************************************************************************/
6595 static void
6596 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6597 {
6598         struct ifnet *ifp = &sc->arpcom.ac_if;
6599         uint32_t val_hi, val_lo;
6600         struct mbuf *mp = m;
6601
6602         if (m == NULL) {
6603                 /* Index out of range. */
6604                 if_printf(ifp, "mbuf: null pointer\n");
6605                 return;
6606         }
6607
6608         while (mp) {
6609                 val_hi = BCE_ADDR_HI(mp);
6610                 val_lo = BCE_ADDR_LO(mp);
6611                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6612                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6613
6614                 if (mp->m_flags & M_EXT)
6615                         kprintf("M_EXT ");
6616                 if (mp->m_flags & M_PKTHDR)
6617                         kprintf("M_PKTHDR ");
6618                 if (mp->m_flags & M_EOR)
6619                         kprintf("M_EOR ");
6620 #ifdef M_RDONLY
6621                 if (mp->m_flags & M_RDONLY)
6622                         kprintf("M_RDONLY ");
6623 #endif
6624
6625                 val_hi = BCE_ADDR_HI(mp->m_data);
6626                 val_lo = BCE_ADDR_LO(mp->m_data);
6627                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6628
6629                 if (mp->m_flags & M_PKTHDR) {
6630                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6631                         if (mp->m_flags & M_BCAST)
6632                                 kprintf("M_BCAST ");
6633                         if (mp->m_flags & M_MCAST)
6634                                 kprintf("M_MCAST ");
6635                         if (mp->m_flags & M_FRAG)
6636                                 kprintf("M_FRAG ");
6637                         if (mp->m_flags & M_FIRSTFRAG)
6638                                 kprintf("M_FIRSTFRAG ");
6639                         if (mp->m_flags & M_LASTFRAG)
6640                                 kprintf("M_LASTFRAG ");
6641 #ifdef M_VLANTAG
6642                         if (mp->m_flags & M_VLANTAG)
6643                                 kprintf("M_VLANTAG ");
6644 #endif
6645 #ifdef M_PROMISC
6646                         if (mp->m_flags & M_PROMISC)
6647                                 kprintf("M_PROMISC ");
6648 #endif
6649                         kprintf(") csum_flags = ( ");
6650                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6651                                 kprintf("CSUM_IP ");
6652                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6653                                 kprintf("CSUM_TCP ");
6654                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6655                                 kprintf("CSUM_UDP ");
6656                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6657                                 kprintf("CSUM_IP_FRAGS ");
6658                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6659                                 kprintf("CSUM_FRAGMENT ");
6660 #ifdef CSUM_TSO
6661                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6662                                 kprintf("CSUM_TSO ");
6663 #endif
6664                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6665                                 kprintf("CSUM_IP_CHECKED ");
6666                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6667                                 kprintf("CSUM_IP_VALID ");
6668                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6669                                 kprintf("CSUM_DATA_VALID ");
6670                         kprintf(")\n");
6671                 }
6672
6673                 if (mp->m_flags & M_EXT) {
6674                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6675                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6676                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6677                                   "ext_size = %d\n",
6678                                   val_hi, val_lo, mp->m_ext.ext_size);
6679                 }
6680                 mp = mp->m_next;
6681         }
6682 }
6683
6684
6685 /****************************************************************************/
6686 /* Prints out the mbufs in the TX mbuf chain.                               */
6687 /*                                                                          */
6688 /* Returns:                                                                 */
6689 /*   Nothing.                                                               */
6690 /****************************************************************************/
6691 static void
6692 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6693 {
6694         struct ifnet *ifp = &sc->arpcom.ac_if;
6695         int i;
6696
6697         if_printf(ifp,
6698         "----------------------------"
6699         "  tx mbuf data  "
6700         "----------------------------\n");
6701
6702         for (i = 0; i < count; i++) {
6703                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6704                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6705                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6706         }
6707
6708         if_printf(ifp,
6709         "----------------------------"
6710         "----------------"
6711         "----------------------------\n");
6712 }
6713
6714
6715 /****************************************************************************/
6716 /* Prints out the mbufs in the RX mbuf chain.                               */
6717 /*                                                                          */
6718 /* Returns:                                                                 */
6719 /*   Nothing.                                                               */
6720 /****************************************************************************/
6721 static void
6722 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6723 {
6724         struct ifnet *ifp = &sc->arpcom.ac_if;
6725         int i;
6726
6727         if_printf(ifp,
6728         "----------------------------"
6729         "  rx mbuf data  "
6730         "----------------------------\n");
6731
6732         for (i = 0; i < count; i++) {
6733                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6734                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6735                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6736         }
6737
6738         if_printf(ifp,
6739         "----------------------------"
6740         "----------------"
6741         "----------------------------\n");
6742 }
6743
6744
6745 /****************************************************************************/
6746 /* Prints out a tx_bd structure.                                            */
6747 /*                                                                          */
6748 /* Returns:                                                                 */
6749 /*   Nothing.                                                               */
6750 /****************************************************************************/
6751 static void
6752 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6753 {
6754         struct ifnet *ifp = &sc->arpcom.ac_if;
6755
6756         if (idx > MAX_TX_BD) {
6757                 /* Index out of range. */
6758                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6759         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6760                 /* TX Chain page pointer. */
6761                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6762                           "chain page pointer\n",
6763                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6764         } else {
6765                 /* Normal tx_bd entry. */
6766                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6767                           "nbytes = 0x%08X, "
6768                           "vlan tag= 0x%04X, flags = 0x%04X (",
6769                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6770                           txbd->tx_bd_mss_nbytes,
6771                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6772
6773                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6774                         kprintf(" CONN_FAULT");
6775
6776                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6777                         kprintf(" TCP_UDP_CKSUM");
6778
6779                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6780                         kprintf(" IP_CKSUM");
6781
6782                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6783                         kprintf("  VLAN");
6784
6785                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6786                         kprintf(" COAL_NOW");
6787
6788                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6789                         kprintf(" DONT_GEN_CRC");
6790
6791                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6792                         kprintf(" START");
6793
6794                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6795                         kprintf(" END");
6796
6797                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6798                         kprintf(" LSO");
6799
6800                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6801                         kprintf(" OPTION_WORD");
6802
6803                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6804                         kprintf(" FLAGS");
6805
6806                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6807                         kprintf(" SNAP");
6808
6809                 kprintf(" )\n");
6810         }
6811 }
6812
6813
6814 /****************************************************************************/
6815 /* Prints out a rx_bd structure.                                            */
6816 /*                                                                          */
6817 /* Returns:                                                                 */
6818 /*   Nothing.                                                               */
6819 /****************************************************************************/
6820 static void
6821 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6822 {
6823         struct ifnet *ifp = &sc->arpcom.ac_if;
6824
6825         if (idx > MAX_RX_BD) {
6826                 /* Index out of range. */
6827                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6828         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6829                 /* TX Chain page pointer. */
6830                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6831                           "chain page pointer\n",
6832                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6833         } else {
6834                 /* Normal tx_bd entry. */
6835                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6836                           "nbytes = 0x%08X, flags = 0x%08X\n",
6837                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6838                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6839         }
6840 }
6841
6842
6843 /****************************************************************************/
6844 /* Prints out a l2_fhdr structure.                                          */
6845 /*                                                                          */
6846 /* Returns:                                                                 */
6847 /*   Nothing.                                                               */
6848 /****************************************************************************/
6849 static void
6850 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6851 {
6852         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6853                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6854                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6855                   idx, l2fhdr->l2_fhdr_status,
6856                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6857                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6858 }
6859
6860
6861 /****************************************************************************/
6862 /* Prints out the tx chain.                                                 */
6863 /*                                                                          */
6864 /* Returns:                                                                 */
6865 /*   Nothing.                                                               */
6866 /****************************************************************************/
6867 static void
6868 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6869 {
6870         struct ifnet *ifp = &sc->arpcom.ac_if;
6871         int i;
6872
6873         /* First some info about the tx_bd chain structure. */
6874         if_printf(ifp,
6875         "----------------------------"
6876         "  tx_bd  chain  "
6877         "----------------------------\n");
6878
6879         if_printf(ifp, "page size      = 0x%08X, "
6880                   "tx chain pages        = 0x%08X\n",
6881                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6882
6883         if_printf(ifp, "tx_bd per page = 0x%08X, "
6884                   "usable tx_bd per page = 0x%08X\n",
6885                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6886                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6887
6888         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6889
6890         if_printf(ifp,
6891         "----------------------------"
6892         "  tx_bd data    "
6893         "----------------------------\n");
6894
6895         /* Now print out the tx_bd's themselves. */
6896         for (i = 0; i < count; i++) {
6897                 struct tx_bd *txbd;
6898
6899                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6900                 bce_dump_txbd(sc, tx_prod, txbd);
6901                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6902         }
6903
6904         if_printf(ifp,
6905         "----------------------------"
6906         "----------------"
6907         "----------------------------\n");
6908 }
6909
6910
6911 /****************************************************************************/
6912 /* Prints out the rx chain.                                                 */
6913 /*                                                                          */
6914 /* Returns:                                                                 */
6915 /*   Nothing.                                                               */
6916 /****************************************************************************/
6917 static void
6918 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6919 {
6920         struct ifnet *ifp = &sc->arpcom.ac_if;
6921         int i;
6922
6923         /* First some info about the tx_bd chain structure. */
6924         if_printf(ifp,
6925         "----------------------------"
6926         "  rx_bd  chain  "
6927         "----------------------------\n");
6928
6929         if_printf(ifp, "page size      = 0x%08X, "
6930                   "rx chain pages        = 0x%08X\n",
6931                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6932
6933         if_printf(ifp, "rx_bd per page = 0x%08X, "
6934                   "usable rx_bd per page = 0x%08X\n",
6935                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6936                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6937
6938         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6939
6940         if_printf(ifp,
6941         "----------------------------"
6942         "   rx_bd data   "
6943         "----------------------------\n");
6944
6945         /* Now print out the rx_bd's themselves. */
6946         for (i = 0; i < count; i++) {
6947                 struct rx_bd *rxbd;
6948
6949                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6950                 bce_dump_rxbd(sc, rx_prod, rxbd);
6951                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6952         }
6953
6954         if_printf(ifp,
6955         "----------------------------"
6956         "----------------"
6957         "----------------------------\n");
6958 }
6959
6960
6961 /****************************************************************************/
6962 /* Prints out the status block from host memory.                            */
6963 /*                                                                          */
6964 /* Returns:                                                                 */
6965 /*   Nothing.                                                               */
6966 /****************************************************************************/
6967 static void
6968 bce_dump_status_block(struct bce_softc *sc)
6969 {
6970         struct status_block *sblk = sc->status_block;
6971         struct ifnet *ifp = &sc->arpcom.ac_if;
6972
6973         if_printf(ifp,
6974         "----------------------------"
6975         "  Status Block  "
6976         "----------------------------\n");
6977
6978         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6979
6980         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6981                   sblk->status_attn_bits_ack);
6982
6983         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6984             sblk->status_rx_quick_consumer_index0,
6985             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6986
6987         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6988             sblk->status_tx_quick_consumer_index0,
6989             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6990
6991         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6992
6993         /* Theses indices are not used for normal L2 drivers. */
6994         if (sblk->status_rx_quick_consumer_index1) {
6995                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6996                 sblk->status_rx_quick_consumer_index1,
6997                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6998         }
6999
7000         if (sblk->status_tx_quick_consumer_index1) {
7001                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
7002                 sblk->status_tx_quick_consumer_index1,
7003                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
7004         }
7005
7006         if (sblk->status_rx_quick_consumer_index2) {
7007                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
7008                 sblk->status_rx_quick_consumer_index2,
7009                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
7010         }
7011
7012         if (sblk->status_tx_quick_consumer_index2) {
7013                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
7014                 sblk->status_tx_quick_consumer_index2,
7015                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
7016         }
7017
7018         if (sblk->status_rx_quick_consumer_index3) {
7019                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
7020                 sblk->status_rx_quick_consumer_index3,
7021                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
7022         }
7023
7024         if (sblk->status_tx_quick_consumer_index3) {
7025                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7026                 sblk->status_tx_quick_consumer_index3,
7027                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
7028         }
7029
7030         if (sblk->status_rx_quick_consumer_index4 ||
7031             sblk->status_rx_quick_consumer_index5) {
7032                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
7033                           sblk->status_rx_quick_consumer_index4,
7034                           sblk->status_rx_quick_consumer_index5);
7035         }
7036
7037         if (sblk->status_rx_quick_consumer_index6 ||
7038             sblk->status_rx_quick_consumer_index7) {
7039                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
7040                           sblk->status_rx_quick_consumer_index6,
7041                           sblk->status_rx_quick_consumer_index7);
7042         }
7043
7044         if (sblk->status_rx_quick_consumer_index8 ||
7045             sblk->status_rx_quick_consumer_index9) {
7046                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
7047                           sblk->status_rx_quick_consumer_index8,
7048                           sblk->status_rx_quick_consumer_index9);
7049         }
7050
7051         if (sblk->status_rx_quick_consumer_index10 ||
7052             sblk->status_rx_quick_consumer_index11) {
7053                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
7054                           sblk->status_rx_quick_consumer_index10,
7055                           sblk->status_rx_quick_consumer_index11);
7056         }
7057
7058         if (sblk->status_rx_quick_consumer_index12 ||
7059             sblk->status_rx_quick_consumer_index13) {
7060                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
7061                           sblk->status_rx_quick_consumer_index12,
7062                           sblk->status_rx_quick_consumer_index13);
7063         }
7064
7065         if (sblk->status_rx_quick_consumer_index14 ||
7066             sblk->status_rx_quick_consumer_index15) {
7067                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
7068                           sblk->status_rx_quick_consumer_index14,
7069                           sblk->status_rx_quick_consumer_index15);
7070         }
7071
7072         if (sblk->status_completion_producer_index ||
7073             sblk->status_cmd_consumer_index) {
7074                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
7075                           sblk->status_completion_producer_index,
7076                           sblk->status_cmd_consumer_index);
7077         }
7078
7079         if_printf(ifp,
7080         "----------------------------"
7081         "----------------"
7082         "----------------------------\n");
7083 }
7084
7085
7086 /****************************************************************************/
7087 /* Prints out the statistics block.                                         */
7088 /*                                                                          */
7089 /* Returns:                                                                 */
7090 /*   Nothing.                                                               */
7091 /****************************************************************************/
7092 static void
7093 bce_dump_stats_block(struct bce_softc *sc)
7094 {
7095         struct statistics_block *sblk = sc->stats_block;
7096         struct ifnet *ifp = &sc->arpcom.ac_if;
7097
7098         if_printf(ifp,
7099         "---------------"
7100         " Stats Block  (All Stats Not Shown Are 0) "
7101         "---------------\n");
7102
7103         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7104                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7105                           sblk->stat_IfHCInOctets_hi,
7106                           sblk->stat_IfHCInOctets_lo);
7107         }
7108
7109         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7110                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7111                           sblk->stat_IfHCInBadOctets_hi,
7112                           sblk->stat_IfHCInBadOctets_lo);
7113         }
7114
7115         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7116                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7117                           sblk->stat_IfHCOutOctets_hi,
7118                           sblk->stat_IfHCOutOctets_lo);
7119         }
7120
7121         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7122                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7123                           sblk->stat_IfHCOutBadOctets_hi,
7124                           sblk->stat_IfHCOutBadOctets_lo);
7125         }
7126
7127         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7128                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7129                           sblk->stat_IfHCInUcastPkts_hi,
7130                           sblk->stat_IfHCInUcastPkts_lo);
7131         }
7132
7133         if (sblk->stat_IfHCInBroadcastPkts_hi ||
7134             sblk->stat_IfHCInBroadcastPkts_lo) {
7135                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7136                           sblk->stat_IfHCInBroadcastPkts_hi,
7137                           sblk->stat_IfHCInBroadcastPkts_lo);
7138         }
7139
7140         if (sblk->stat_IfHCInMulticastPkts_hi ||
7141             sblk->stat_IfHCInMulticastPkts_lo) {
7142                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7143                           sblk->stat_IfHCInMulticastPkts_hi,
7144                           sblk->stat_IfHCInMulticastPkts_lo);
7145         }
7146
7147         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7148                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7149                           sblk->stat_IfHCOutUcastPkts_hi,
7150                           sblk->stat_IfHCOutUcastPkts_lo);
7151         }
7152
7153         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7154             sblk->stat_IfHCOutBroadcastPkts_lo) {
7155                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7156                           sblk->stat_IfHCOutBroadcastPkts_hi,
7157                           sblk->stat_IfHCOutBroadcastPkts_lo);
7158         }
7159
7160         if (sblk->stat_IfHCOutMulticastPkts_hi ||
7161             sblk->stat_IfHCOutMulticastPkts_lo) {
7162                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7163                           sblk->stat_IfHCOutMulticastPkts_hi,
7164                           sblk->stat_IfHCOutMulticastPkts_lo);
7165         }
7166
7167         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7168                 if_printf(ifp, "         0x%08X : "
7169                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7170                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7171         }
7172
7173         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7174                 if_printf(ifp, "         0x%08X : "
7175                           "Dot3StatsCarrierSenseErrors\n",
7176                           sblk->stat_Dot3StatsCarrierSenseErrors);
7177         }
7178
7179         if (sblk->stat_Dot3StatsFCSErrors) {
7180                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
7181                           sblk->stat_Dot3StatsFCSErrors);
7182         }
7183
7184         if (sblk->stat_Dot3StatsAlignmentErrors) {
7185                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
7186                           sblk->stat_Dot3StatsAlignmentErrors);
7187         }
7188
7189         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7190                 if_printf(ifp, "         0x%08X : "
7191                           "Dot3StatsSingleCollisionFrames\n",
7192                           sblk->stat_Dot3StatsSingleCollisionFrames);
7193         }
7194
7195         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7196                 if_printf(ifp, "         0x%08X : "
7197                           "Dot3StatsMultipleCollisionFrames\n",
7198                           sblk->stat_Dot3StatsMultipleCollisionFrames);
7199         }
7200
7201         if (sblk->stat_Dot3StatsDeferredTransmissions) {
7202                 if_printf(ifp, "         0x%08X : "
7203                           "Dot3StatsDeferredTransmissions\n",
7204                           sblk->stat_Dot3StatsDeferredTransmissions);
7205         }
7206
7207         if (sblk->stat_Dot3StatsExcessiveCollisions) {
7208                 if_printf(ifp, "         0x%08X : "
7209                           "Dot3StatsExcessiveCollisions\n",
7210                           sblk->stat_Dot3StatsExcessiveCollisions);
7211         }
7212
7213         if (sblk->stat_Dot3StatsLateCollisions) {
7214                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
7215                           sblk->stat_Dot3StatsLateCollisions);
7216         }
7217
7218         if (sblk->stat_EtherStatsCollisions) {
7219                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
7220                           sblk->stat_EtherStatsCollisions);
7221         }
7222
7223         if (sblk->stat_EtherStatsFragments)  {
7224                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
7225                           sblk->stat_EtherStatsFragments);
7226         }
7227
7228         if (sblk->stat_EtherStatsJabbers) {
7229                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
7230                           sblk->stat_EtherStatsJabbers);
7231         }
7232
7233         if (sblk->stat_EtherStatsUndersizePkts) {
7234                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
7235                           sblk->stat_EtherStatsUndersizePkts);
7236         }
7237
7238         if (sblk->stat_EtherStatsOverrsizePkts) {
7239                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
7240                           sblk->stat_EtherStatsOverrsizePkts);
7241         }
7242
7243         if (sblk->stat_EtherStatsPktsRx64Octets) {
7244                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
7245                           sblk->stat_EtherStatsPktsRx64Octets);
7246         }
7247
7248         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7249                 if_printf(ifp, "         0x%08X : "
7250                           "EtherStatsPktsRx65Octetsto127Octets\n",
7251                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7252         }
7253
7254         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7255                 if_printf(ifp, "         0x%08X : "
7256                           "EtherStatsPktsRx128Octetsto255Octets\n",
7257                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7258         }
7259
7260         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7261                 if_printf(ifp, "         0x%08X : "
7262                           "EtherStatsPktsRx256Octetsto511Octets\n",
7263                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7264         }
7265
7266         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7267                 if_printf(ifp, "         0x%08X : "
7268                           "EtherStatsPktsRx512Octetsto1023Octets\n",
7269                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7270         }
7271
7272         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7273                 if_printf(ifp, "         0x%08X : "
7274                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
7275                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7276         }
7277
7278         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7279                 if_printf(ifp, "         0x%08X : "
7280                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
7281                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7282         }
7283
7284         if (sblk->stat_EtherStatsPktsTx64Octets) {
7285                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
7286                           sblk->stat_EtherStatsPktsTx64Octets);
7287         }
7288
7289         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7290                 if_printf(ifp, "         0x%08X : "
7291                           "EtherStatsPktsTx65Octetsto127Octets\n",
7292                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7293         }
7294
7295         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7296                 if_printf(ifp, "         0x%08X : "
7297                           "EtherStatsPktsTx128Octetsto255Octets\n",
7298                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7299         }
7300
7301         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7302                 if_printf(ifp, "         0x%08X : "
7303                           "EtherStatsPktsTx256Octetsto511Octets\n",
7304                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7305         }
7306
7307         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7308                 if_printf(ifp, "         0x%08X : "
7309                           "EtherStatsPktsTx512Octetsto1023Octets\n",
7310                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7311         }
7312
7313         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7314                 if_printf(ifp, "         0x%08X : "
7315                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
7316                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7317         }
7318
7319         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7320                 if_printf(ifp, "         0x%08X : "
7321                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
7322                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7323         }
7324
7325         if (sblk->stat_XonPauseFramesReceived) {
7326                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
7327                           sblk->stat_XonPauseFramesReceived);
7328         }
7329
7330         if (sblk->stat_XoffPauseFramesReceived) {
7331                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
7332                           sblk->stat_XoffPauseFramesReceived);
7333         }
7334
7335         if (sblk->stat_OutXonSent) {
7336                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7337                           sblk->stat_OutXonSent);
7338         }
7339
7340         if (sblk->stat_OutXoffSent) {
7341                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7342                           sblk->stat_OutXoffSent);
7343         }
7344
7345         if (sblk->stat_FlowControlDone) {
7346                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
7347                           sblk->stat_FlowControlDone);
7348         }
7349
7350         if (sblk->stat_MacControlFramesReceived) {
7351                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
7352                           sblk->stat_MacControlFramesReceived);
7353         }
7354
7355         if (sblk->stat_XoffStateEntered) {
7356                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
7357                           sblk->stat_XoffStateEntered);
7358         }
7359
7360         if (sblk->stat_IfInFramesL2FilterDiscards) {
7361                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
7362         }
7363
7364         if (sblk->stat_IfInRuleCheckerDiscards) {
7365                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
7366                           sblk->stat_IfInRuleCheckerDiscards);
7367         }
7368
7369         if (sblk->stat_IfInFTQDiscards) {
7370                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
7371                           sblk->stat_IfInFTQDiscards);
7372         }
7373
7374         if (sblk->stat_IfInMBUFDiscards) {
7375                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
7376                           sblk->stat_IfInMBUFDiscards);
7377         }
7378
7379         if (sblk->stat_IfInRuleCheckerP4Hit) {
7380                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
7381                           sblk->stat_IfInRuleCheckerP4Hit);
7382         }
7383
7384         if (sblk->stat_CatchupInRuleCheckerDiscards) {
7385                 if_printf(ifp, "         0x%08X : "
7386                           "CatchupInRuleCheckerDiscards\n",
7387                           sblk->stat_CatchupInRuleCheckerDiscards);
7388         }
7389
7390         if (sblk->stat_CatchupInFTQDiscards) {
7391                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
7392                           sblk->stat_CatchupInFTQDiscards);
7393         }
7394
7395         if (sblk->stat_CatchupInMBUFDiscards) {
7396                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
7397                           sblk->stat_CatchupInMBUFDiscards);
7398         }
7399
7400         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7401                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
7402                           sblk->stat_CatchupInRuleCheckerP4Hit);
7403         }
7404
7405         if_printf(ifp,
7406         "----------------------------"
7407         "----------------"
7408         "----------------------------\n");
7409 }
7410
7411
7412 /****************************************************************************/
7413 /* Prints out a summary of the driver state.                                */
7414 /*                                                                          */
7415 /* Returns:                                                                 */
7416 /*   Nothing.                                                               */
7417 /****************************************************************************/
7418 static void
7419 bce_dump_driver_state(struct bce_softc *sc)
7420 {
7421         struct ifnet *ifp = &sc->arpcom.ac_if;
7422         uint32_t val_hi, val_lo;
7423
7424         if_printf(ifp,
7425         "-----------------------------"
7426         " Driver State "
7427         "-----------------------------\n");
7428
7429         val_hi = BCE_ADDR_HI(sc);
7430         val_lo = BCE_ADDR_LO(sc);
7431         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7432                   "virtual address\n", val_hi, val_lo);
7433
7434         val_hi = BCE_ADDR_HI(sc->status_block);
7435         val_lo = BCE_ADDR_LO(sc->status_block);
7436         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7437                   "virtual address\n", val_hi, val_lo);
7438
7439         val_hi = BCE_ADDR_HI(sc->stats_block);
7440         val_lo = BCE_ADDR_LO(sc->stats_block);
7441         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7442                   "virtual address\n", val_hi, val_lo);
7443
7444         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7445         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7446         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7447                   "virtual adddress\n", val_hi, val_lo);
7448
7449         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7450         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7451         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7452                   "virtual address\n", val_hi, val_lo);
7453
7454         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7455         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7456         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7457                   "virtual address\n", val_hi, val_lo);
7458
7459         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7460         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7461         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7462                   "virtual address\n", val_hi, val_lo);
7463
7464         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
7465                   "h/w intrs\n", sc->interrupts_generated);
7466
7467         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
7468                   "rx interrupts handled\n", sc->rx_interrupts);
7469
7470         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
7471                   "tx interrupts handled\n", sc->tx_interrupts);
7472
7473         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
7474                   "status block index\n", sc->last_status_idx);
7475
7476         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
7477                   "tx producer index\n",
7478                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7479
7480         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
7481                   "tx consumer index\n",
7482                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7483
7484         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
7485                   "tx producer bseq index\n", sc->tx_prod_bseq);
7486
7487         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
7488                   "rx producer index\n",
7489                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7490
7491         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
7492                   "rx consumer index\n",
7493                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7494
7495         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
7496                   "rx producer bseq index\n", sc->rx_prod_bseq);
7497
7498         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7499                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7500
7501         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
7502                   "free rx_bd's\n", sc->free_rx_bd);
7503
7504         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7505                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7506
7507         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
7508                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7509
7510         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7511                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7512
7513         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7514                   sc->used_tx_bd);
7515
7516         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7517                   sc->tx_hi_watermark, sc->max_tx_bd);
7518
7519         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
7520                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7521
7522         if_printf(ifp,
7523         "----------------------------"
7524         "----------------"
7525         "----------------------------\n");
7526 }
7527
7528
7529 /****************************************************************************/
7530 /* Prints out the hardware state through a summary of important registers,  */
7531 /* followed by a complete register dump.                                    */
7532 /*                                                                          */
7533 /* Returns:                                                                 */
7534 /*   Nothing.                                                               */
7535 /****************************************************************************/
7536 static void
7537 bce_dump_hw_state(struct bce_softc *sc)
7538 {
7539         struct ifnet *ifp = &sc->arpcom.ac_if;
7540         uint32_t val1;
7541         int i;
7542
7543         if_printf(ifp,
7544         "----------------------------"
7545         " Hardware State "
7546         "----------------------------\n");
7547
7548         if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7549
7550         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7551         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7552                   val1, BCE_MISC_ENABLE_STATUS_BITS);
7553
7554         val1 = REG_RD(sc, BCE_DMA_STATUS);
7555         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7556
7557         val1 = REG_RD(sc, BCE_CTX_STATUS);
7558         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7559
7560         val1 = REG_RD(sc, BCE_EMAC_STATUS);
7561         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7562                   val1, BCE_EMAC_STATUS);
7563
7564         val1 = REG_RD(sc, BCE_RPM_STATUS);
7565         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7566
7567         val1 = REG_RD(sc, BCE_TBDR_STATUS);
7568         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7569                   val1, BCE_TBDR_STATUS);
7570
7571         val1 = REG_RD(sc, BCE_TDMA_STATUS);
7572         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7573                   val1, BCE_TDMA_STATUS);
7574
7575         val1 = REG_RD(sc, BCE_HC_STATUS);
7576         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7577
7578         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7579         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7580                   val1, BCE_TXP_CPU_STATE);
7581
7582         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7583         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7584                   val1, BCE_TPAT_CPU_STATE);
7585
7586         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7587         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7588                   val1, BCE_RXP_CPU_STATE);
7589
7590         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7591         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7592                   val1, BCE_COM_CPU_STATE);
7593
7594         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7595         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7596                   val1, BCE_MCP_CPU_STATE);
7597
7598         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7599         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7600                   val1, BCE_CP_CPU_STATE);
7601
7602         if_printf(ifp,
7603         "----------------------------"
7604         "----------------"
7605         "----------------------------\n");
7606
7607         if_printf(ifp,
7608         "----------------------------"
7609         " Register  Dump "
7610         "----------------------------\n");
7611
7612         for (i = 0x400; i < 0x8000; i += 0x10) {
7613                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7614                           REG_RD(sc, i),
7615                           REG_RD(sc, i + 0x4),
7616                           REG_RD(sc, i + 0x8),
7617                           REG_RD(sc, i + 0xc));
7618         }
7619
7620         if_printf(ifp,
7621         "----------------------------"
7622         "----------------"
7623         "----------------------------\n");
7624 }
7625
7626
7627 /****************************************************************************/
7628 /* Prints out the TXP state.                                                */
7629 /*                                                                          */
7630 /* Returns:                                                                 */
7631 /*   Nothing.                                                               */
7632 /****************************************************************************/
7633 static void
7634 bce_dump_txp_state(struct bce_softc *sc)
7635 {
7636         struct ifnet *ifp = &sc->arpcom.ac_if;
7637         uint32_t val1;
7638         int i;
7639
7640         if_printf(ifp,
7641         "----------------------------"
7642         "   TXP  State   "
7643         "----------------------------\n");
7644
7645         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7646         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7647                   val1, BCE_TXP_CPU_MODE);
7648
7649         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7650         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7651                   val1, BCE_TXP_CPU_STATE);
7652
7653         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7654         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7655                   val1, BCE_TXP_CPU_EVENT_MASK);
7656
7657         if_printf(ifp,
7658         "----------------------------"
7659         " Register  Dump "
7660         "----------------------------\n");
7661
7662         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7663                 /* Skip the big blank spaces */
7664                 if (i < 0x454000 && i > 0x5ffff) {
7665                         if_printf(ifp, "0x%04X: "
7666                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7667                                   REG_RD_IND(sc, i),
7668                                   REG_RD_IND(sc, i + 0x4),
7669                                   REG_RD_IND(sc, i + 0x8),
7670                                   REG_RD_IND(sc, i + 0xc));
7671                 }
7672         }
7673
7674         if_printf(ifp,
7675         "----------------------------"
7676         "----------------"
7677         "----------------------------\n");
7678 }
7679
7680
7681 /****************************************************************************/
7682 /* Prints out the RXP state.                                                */
7683 /*                                                                          */
7684 /* Returns:                                                                 */
7685 /*   Nothing.                                                               */
7686 /****************************************************************************/
7687 static void
7688 bce_dump_rxp_state(struct bce_softc *sc)
7689 {
7690         struct ifnet *ifp = &sc->arpcom.ac_if;
7691         uint32_t val1;
7692         int i;
7693
7694         if_printf(ifp,
7695         "----------------------------"
7696         "   RXP  State   "
7697         "----------------------------\n");
7698
7699         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7700         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7701                   val1, BCE_RXP_CPU_MODE);
7702
7703         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7704         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7705                   val1, BCE_RXP_CPU_STATE);
7706
7707         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7708         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7709                   val1, BCE_RXP_CPU_EVENT_MASK);
7710
7711         if_printf(ifp,
7712         "----------------------------"
7713         " Register  Dump "
7714         "----------------------------\n");
7715
7716         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7717                 /* Skip the big blank sapces */
7718                 if (i < 0xc5400 && i > 0xdffff) {
7719                         if_printf(ifp, "0x%04X: "
7720                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7721                                   REG_RD_IND(sc, i),
7722                                   REG_RD_IND(sc, i + 0x4),
7723                                   REG_RD_IND(sc, i + 0x8),
7724                                   REG_RD_IND(sc, i + 0xc));
7725                 }
7726         }
7727
7728         if_printf(ifp,
7729         "----------------------------"
7730         "----------------"
7731         "----------------------------\n");
7732 }
7733
7734
7735 /****************************************************************************/
7736 /* Prints out the TPAT state.                                               */
7737 /*                                                                          */
7738 /* Returns:                                                                 */
7739 /*   Nothing.                                                               */
7740 /****************************************************************************/
7741 static void
7742 bce_dump_tpat_state(struct bce_softc *sc)
7743 {
7744         struct ifnet *ifp = &sc->arpcom.ac_if;
7745         uint32_t val1;
7746         int i;
7747
7748         if_printf(ifp,
7749         "----------------------------"
7750         "   TPAT State   "
7751         "----------------------------\n");
7752
7753         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7754         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7755                   val1, BCE_TPAT_CPU_MODE);
7756
7757         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7758         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7759                   val1, BCE_TPAT_CPU_STATE);
7760
7761         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7762         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7763                   val1, BCE_TPAT_CPU_EVENT_MASK);
7764
7765         if_printf(ifp,
7766         "----------------------------"
7767         " Register  Dump "
7768         "----------------------------\n");
7769
7770         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7771                 /* Skip the big blank spaces */
7772                 if (i < 0x854000 && i > 0x9ffff) {
7773                         if_printf(ifp, "0x%04X: "
7774                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7775                                   REG_RD_IND(sc, i),
7776                                   REG_RD_IND(sc, i + 0x4),
7777                                   REG_RD_IND(sc, i + 0x8),
7778                                   REG_RD_IND(sc, i + 0xc));
7779                 }
7780         }
7781
7782         if_printf(ifp,
7783         "----------------------------"
7784         "----------------"
7785         "----------------------------\n");
7786 }
7787
7788
7789 /****************************************************************************/
7790 /* Prints out the driver state and then enters the debugger.                */
7791 /*                                                                          */
7792 /* Returns:                                                                 */
7793 /*   Nothing.                                                               */
7794 /****************************************************************************/
7795 static void
7796 bce_breakpoint(struct bce_softc *sc)
7797 {
7798 #if 0
7799         bce_freeze_controller(sc);
7800 #endif
7801
7802         bce_dump_driver_state(sc);
7803         bce_dump_status_block(sc);
7804         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7805         bce_dump_hw_state(sc);
7806         bce_dump_txp_state(sc);
7807
7808 #if 0
7809         bce_unfreeze_controller(sc);
7810 #endif
7811
7812         /* Call the debugger. */
7813         breakpoint();
7814 }
7815
7816 #endif  /* BCE_DEBUG */
7817
7818 static int
7819 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7820 {
7821         struct bce_softc *sc = arg1;
7822
7823         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7824                         &sc->bce_tx_quick_cons_trip_int,
7825                         BCE_COALMASK_TX_BDS_INT);
7826 }
7827
7828 static int
7829 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7830 {
7831         struct bce_softc *sc = arg1;
7832
7833         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7834                         &sc->bce_tx_quick_cons_trip,
7835                         BCE_COALMASK_TX_BDS);
7836 }
7837
7838 static int
7839 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7840 {
7841         struct bce_softc *sc = arg1;
7842
7843         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7844                         &sc->bce_tx_ticks_int,
7845                         BCE_COALMASK_TX_TICKS_INT);
7846 }
7847
7848 static int
7849 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7850 {
7851         struct bce_softc *sc = arg1;
7852
7853         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7854                         &sc->bce_tx_ticks,
7855                         BCE_COALMASK_TX_TICKS);
7856 }
7857
7858 static int
7859 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7860 {
7861         struct bce_softc *sc = arg1;
7862
7863         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7864                         &sc->bce_rx_quick_cons_trip_int,
7865                         BCE_COALMASK_RX_BDS_INT);
7866 }
7867
7868 static int
7869 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7870 {
7871         struct bce_softc *sc = arg1;
7872
7873         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7874                         &sc->bce_rx_quick_cons_trip,
7875                         BCE_COALMASK_RX_BDS);
7876 }
7877
7878 static int
7879 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7880 {
7881         struct bce_softc *sc = arg1;
7882
7883         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7884                         &sc->bce_rx_ticks_int,
7885                         BCE_COALMASK_RX_TICKS_INT);
7886 }
7887
7888 static int
7889 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7890 {
7891         struct bce_softc *sc = arg1;
7892
7893         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7894                         &sc->bce_rx_ticks,
7895                         BCE_COALMASK_RX_TICKS);
7896 }
7897
7898 static int
7899 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7900                        uint32_t coalchg_mask)
7901 {
7902         struct bce_softc *sc = arg1;
7903         struct ifnet *ifp = &sc->arpcom.ac_if;
7904         int error = 0, v;
7905
7906         lwkt_serialize_enter(ifp->if_serializer);
7907
7908         v = *coal;
7909         error = sysctl_handle_int(oidp, &v, 0, req);
7910         if (!error && req->newptr != NULL) {
7911                 if (v < 0) {
7912                         error = EINVAL;
7913                 } else {
7914                         *coal = v;
7915                         sc->bce_coalchg_mask |= coalchg_mask;
7916                 }
7917         }
7918
7919         lwkt_serialize_exit(ifp->if_serializer);
7920         return error;
7921 }
7922
7923 static void
7924 bce_coal_change(struct bce_softc *sc)
7925 {
7926         struct ifnet *ifp = &sc->arpcom.ac_if;
7927
7928         ASSERT_SERIALIZED(ifp->if_serializer);
7929
7930         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7931                 sc->bce_coalchg_mask = 0;
7932                 return;
7933         }
7934
7935         if (sc->bce_coalchg_mask &
7936             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7937                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7938                        (sc->bce_tx_quick_cons_trip_int << 16) |
7939                        sc->bce_tx_quick_cons_trip);
7940                 if (bootverbose) {
7941                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7942                                   sc->bce_tx_quick_cons_trip,
7943                                   sc->bce_tx_quick_cons_trip_int);
7944                 }
7945         }
7946
7947         if (sc->bce_coalchg_mask &
7948             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7949                 REG_WR(sc, BCE_HC_TX_TICKS,
7950                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7951                 if (bootverbose) {
7952                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7953                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7954                 }
7955         }
7956
7957         if (sc->bce_coalchg_mask &
7958             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7959                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7960                        (sc->bce_rx_quick_cons_trip_int << 16) |
7961                        sc->bce_rx_quick_cons_trip);
7962                 if (bootverbose) {
7963                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7964                                   sc->bce_rx_quick_cons_trip,
7965                                   sc->bce_rx_quick_cons_trip_int);
7966                 }
7967         }
7968
7969         if (sc->bce_coalchg_mask &
7970             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7971                 REG_WR(sc, BCE_HC_RX_TICKS,
7972                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7973                 if (bootverbose) {
7974                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7975                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7976                 }
7977         }
7978
7979         sc->bce_coalchg_mask = 0;
7980 }