1 /* $FreeBSD: src/sys/dev/mii/e1000phy.c,v 1.18 2006/12/11 11:09:48 yongari Exp $ */
2 /* $OpenBSD: eephy.c,v 1.26 2006/06/08 00:27:12 brad Exp $ */
4 * Principal Author: Parag Patel
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Additonal Copyright (c) 2001 by Traakan Software under same licence.
31 * Secondary Author: Matthew Jacob
35 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
39 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseT and
41 * Nathan Binkert <nate@openbsd.org>
42 * Jung-uk Kim <jkim@niksun.com>
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
52 #include <net/if_var.h>
53 #include <net/if_media.h>
59 #include "e1000phyreg.h"
61 #include "miibus_if.h"
63 static int e1000phy_probe(device_t);
64 static int e1000phy_attach(device_t);
65 static int e1000phy_service(struct mii_softc *, struct mii_data *, int);
66 static void e1000phy_status(struct mii_softc *);
67 static void e1000phy_mii_phy_auto(struct mii_softc *);
68 static void e1000phy_reset(struct mii_softc *);
70 static device_method_t e1000phy_methods[] = {
71 /* device interface */
72 DEVMETHOD(device_probe, e1000phy_probe),
73 DEVMETHOD(device_attach, e1000phy_attach),
74 DEVMETHOD(device_detach, ukphy_detach),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
79 static const struct mii_phydesc e1000phys[] = {
80 MII_PHYDESC(xxMARVELL, E1011),
81 MII_PHYDESC(xxMARVELL, E1000_3),
82 MII_PHYDESC(xxMARVELL, E1000_5),
83 MII_PHYDESC(xxMARVELL, E1111),
84 MII_PHYDESC(MARVELL, E1000),
85 MII_PHYDESC(MARVELL, E1011),
86 MII_PHYDESC(MARVELL, E1000_3),
87 MII_PHYDESC(MARVELL, E1000S),
88 MII_PHYDESC(MARVELL, E1000_5),
89 MII_PHYDESC(MARVELL, E1101),
90 MII_PHYDESC(MARVELL, E3082),
91 MII_PHYDESC(MARVELL, E1112),
92 MII_PHYDESC(MARVELL, E1149),
93 MII_PHYDESC(MARVELL, E1111),
94 MII_PHYDESC(MARVELL, E1116),
95 MII_PHYDESC(MARVELL, E1116R),
96 MII_PHYDESC(MARVELL, E1118),
97 MII_PHYDESC(MARVELL, E3016),
98 MII_PHYDESC(MARVELL, PHYG65G),
99 MII_PHYDESC(MARVELL, E1149R),
103 static devclass_t e1000phy_devclass;
105 static driver_t e1000phy_driver = {
108 sizeof(struct mii_softc)
110 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, NULL, NULL);
113 e1000phy_probe(device_t dev)
115 struct mii_attach_args *ma = device_get_ivars(dev);
116 const struct mii_phydesc *mpd;
118 mpd = mii_phy_match(ma, e1000phys);
120 device_set_desc(dev, mpd->mpd_name);
127 e1000phy_attach(device_t dev)
129 struct mii_softc *sc;
130 struct mii_attach_args *ma;
131 struct mii_data *mii;
133 sc = device_get_softc(dev);
134 ma = device_get_ivars(dev);
135 mii_softc_init(sc, ma);
136 sc->mii_dev = device_get_parent(dev);
137 mii = device_get_softc(sc->mii_dev);
138 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
140 sc->mii_inst = mii->mii_instance;
141 sc->mii_service = e1000phy_service;
142 sc->mii_reset = e1000phy_reset;
143 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
146 sc->mii_flags |= MIIF_NOISOLATE;
148 switch (sc->mii_model) {
149 case MII_MODEL_MARVELL_E1011:
150 case MII_MODEL_MARVELL_E1112:
151 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
152 sc->mii_flags |= MIIF_HAVEFIBER;
154 case MII_MODEL_MARVELL_E1149:
155 case MII_MODEL_MARVELL_E1149R:
157 * Some 88E1149 PHY's page select is initialized to
158 * point to other bank instead of copper/fiber bank
159 * which in turn resulted in wrong registers were
160 * accessed during PHY operation. It is believed that
161 * page 0 should be used for copper PHY so reinitialize
162 * E1000_EADR to select default copper PHY. If parent
163 * device know the type of PHY(either copper or fiber),
164 * that information should be used to select default
167 PHY_WRITE(sc, E1000_EADR, 0);
175 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
176 if (sc->mii_capabilities & BMSR_EXTSTAT)
177 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
179 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)
180 sc->mii_anegticks = MII_ANEGTICKS;
182 device_printf(dev, " ");
183 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
184 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
185 kprintf("no media present");
187 mii_phy_add_media(sc);
190 MIIBUS_MEDIAINIT(sc->mii_dev);
195 e1000phy_reset(struct mii_softc *sc)
199 reg = PHY_READ(sc, E1000_SCR);
200 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
201 reg &= ~E1000_SCR_AUTO_X_MODE;
202 PHY_WRITE(sc, E1000_SCR, reg);
203 if (sc->mii_model == MII_MODEL_MARVELL_E1112) {
204 /* Select 1000BASE-X only mode. */
205 page = PHY_READ(sc, E1000_EADR);
206 PHY_WRITE(sc, E1000_EADR, 2);
207 reg = PHY_READ(sc, E1000_SCR);
208 reg &= ~E1000_SCR_MODE_MASK;
209 reg |= E1000_SCR_MODE_1000BX;
210 PHY_WRITE(sc, E1000_SCR, reg);
212 PHY_WRITE(sc, E1000_EADR, page);
215 switch (sc->mii_model) {
216 case MII_MODEL_MARVELL_E1111:
217 case MII_MODEL_MARVELL_E1112:
218 case MII_MODEL_MARVELL_E1116:
219 case MII_MODEL_MARVELL_E1118:
220 case MII_MODEL_MARVELL_E1149:
221 case MII_MODEL_MARVELL_E1149R:
222 case MII_MODEL_MARVELL_PHYG65G:
223 /* Disable energy detect mode. */
224 reg &= ~E1000_SCR_EN_DETECT_MASK;
225 reg |= E1000_SCR_AUTO_X_MODE;
226 if (sc->mii_model == MII_MODEL_MARVELL_E1116)
227 reg &= ~E1000_SCR_POWER_DOWN;
228 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
230 case MII_MODEL_MARVELL_E3082:
231 reg |= (E1000_SCR_AUTO_X_MODE >> 1);
232 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
234 case MII_MODEL_MARVELL_E3016:
235 reg |= E1000_SCR_AUTO_MDIX;
236 reg &= ~(E1000_SCR_EN_DETECT |
237 E1000_SCR_SCRAMBLER_DISABLE);
238 reg |= E1000_SCR_LPNP;
239 /* XXX Enable class A driver for Yukon FE+ A0. */
240 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
243 reg &= ~E1000_SCR_AUTO_X_MODE;
244 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
247 if (sc->mii_model != MII_MODEL_MARVELL_E3016) {
248 /* Auto correction for reversed cable polarity. */
249 reg &= ~E1000_SCR_POLARITY_REVERSAL;
251 PHY_WRITE(sc, E1000_SCR, reg);
253 if (sc->mii_model == MII_MODEL_MARVELL_E1116 ||
254 sc->mii_model == MII_MODEL_MARVELL_E1149 ||
255 sc->mii_model == MII_MODEL_MARVELL_E1149R) {
256 PHY_WRITE(sc, E1000_EADR, 2);
257 reg = PHY_READ(sc, E1000_SCR);
258 reg |= E1000_SCR_RGMII_POWER_UP;
259 PHY_WRITE(sc, E1000_SCR, reg);
260 PHY_WRITE(sc, E1000_EADR, 0);
264 switch (MII_MODEL(sc->mii_model)) {
265 case MII_MODEL_MARVELL_E3082:
266 case MII_MODEL_MARVELL_E1112:
267 case MII_MODEL_MARVELL_E1118:
269 case MII_MODEL_MARVELL_E1116:
270 page = PHY_READ(sc, E1000_EADR);
271 /* Select page 3, LED control register. */
272 PHY_WRITE(sc, E1000_EADR, 3);
273 PHY_WRITE(sc, E1000_SCR,
274 E1000_SCR_LED_LOS(1) | /* Link/Act */
275 E1000_SCR_LED_INIT(8) | /* 10Mbps */
276 E1000_SCR_LED_STAT1(7) | /* 100Mbps */
277 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */
278 /* Set blink rate. */
279 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
280 E1000_BLINK_RATE(E1000_BLINK_84MS));
281 PHY_WRITE(sc, E1000_EADR, page);
283 case MII_MODEL_MARVELL_E3016:
284 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
285 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
286 /* Integrated register calibration workaround. */
287 PHY_WRITE(sc, 0x1D, 17);
288 PHY_WRITE(sc, 0x1E, 0x3F60);
291 /* Force TX_CLK to 25MHz clock. */
292 reg = PHY_READ(sc, E1000_ESCR);
293 reg |= E1000_ESCR_TX_CLK_25;
294 PHY_WRITE(sc, E1000_ESCR, reg);
298 /* Reset the PHY so all changes take effect. */
299 reg = PHY_READ(sc, E1000_CR);
300 reg |= E1000_CR_RESET;
301 PHY_WRITE(sc, E1000_CR, reg);
305 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
307 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
314 * If we're not polling our PHY instance, just return.
316 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
322 * If the media indicates a different PHY instance,
325 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
326 reg = PHY_READ(sc, E1000_CR);
327 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE);
332 * If the interface is not up, don't do anything.
334 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
337 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
338 e1000phy_mii_phy_auto(sc);
343 switch (IFM_SUBTYPE(ife->ifm_media)) {
345 if ((sc->mii_extcapabilities &
346 (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)
348 speed = E1000_CR_SPEED_1000;
351 if ((sc->mii_extcapabilities &
352 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
354 speed = E1000_CR_SPEED_1000;
357 speed = E1000_CR_SPEED_100;
360 speed = E1000_CR_SPEED_10;
363 reg = PHY_READ(sc, E1000_CR);
364 PHY_WRITE(sc, E1000_CR,
365 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
371 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
372 speed |= E1000_CR_FULL_DUPLEX;
373 gig = E1000_1GCR_1000T_FD;
375 gig = E1000_1GCR_1000T;
378 reg = PHY_READ(sc, E1000_CR);
379 reg &= ~E1000_CR_AUTO_NEG_ENABLE;
380 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
383 * When setting the link manually, one side must
384 * be the master and the other the slave. However
385 * ifmedia doesn't give us a good way to specify
386 * this, so we fake it by using one of the LINK
387 * flags. If LINK0 is set, we program the PHY to
388 * be a master, otherwise it's a slave.
390 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T ||
391 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX) {
392 if (mii->mii_ifp->if_flags & IFF_LINK0) {
393 PHY_WRITE(sc, E1000_1GCR, gig |
394 E1000_1GCR_MS_ENABLE | E1000_1GCR_MS_VALUE);
396 PHY_WRITE(sc, E1000_1GCR, gig |
397 E1000_1GCR_MS_ENABLE);
400 if ((sc->mii_extcapabilities &
401 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
402 PHY_WRITE(sc, E1000_1GCR, 0);
404 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
405 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
411 * If we're not currently selected, just return.
413 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
417 * Is the interface even up?
419 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
423 * Only used for autonegotiation.
425 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
429 * Check to see if we have link. If we do, we don't
430 * need to restart the autonegotiation process. Read
431 * the BMSR twice in case it's latched.
433 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
434 if (reg & BMSR_LINK) {
440 * Only retry autonegotiation every mii_anegticks seconds.
442 if (++sc->mii_ticks <= sc->mii_anegticks)
447 e1000phy_mii_phy_auto(sc);
451 /* Update the media status. */
454 /* Callback if something changed. */
455 mii_phy_update(sc, cmd);
460 e1000phy_status(struct mii_softc *sc)
462 struct mii_data *mii = sc->mii_pdata;
463 int bmsr, bmcr, gsr, ssr, ar, lpar;
465 mii->mii_media_status = IFM_AVALID;
466 mii->mii_media_active = IFM_ETHER;
468 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
469 bmcr = PHY_READ(sc, E1000_CR);
470 ssr = PHY_READ(sc, E1000_SSR);
472 if (bmsr & E1000_SR_LINK_STATUS)
473 mii->mii_media_status |= IFM_ACTIVE;
475 if (bmcr & E1000_CR_LOOPBACK)
476 mii->mii_media_active |= IFM_LOOP;
478 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
479 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
480 /* Erg, still trying, I guess... */
481 mii->mii_media_active |= IFM_NONE;
485 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
486 switch (ssr & E1000_SSR_SPEED) {
487 case E1000_SSR_1000MBS:
488 mii->mii_media_active |= IFM_1000_T;
490 case E1000_SSR_100MBS:
491 mii->mii_media_active |= IFM_100_TX;
493 case E1000_SSR_10MBS:
494 mii->mii_media_active |= IFM_10_T;
497 mii->mii_media_active |= IFM_NONE;
502 * Some fiber PHY(88E1112) does not seem to set resolved
503 * speed so always assume we've got IFM_1000_SX.
505 mii->mii_media_active |= IFM_1000_SX;
508 if (ssr & E1000_SSR_DUPLEX)
509 mii->mii_media_active |= IFM_FDX;
511 mii->mii_media_active |= IFM_HDX;
513 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
514 ar = PHY_READ(sc, E1000_AR);
515 lpar = PHY_READ(sc, E1000_LPAR);
516 /* FLAG0==rx-flow-control FLAG1==tx-flow-control */
517 if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
518 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
519 } else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
520 (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
521 mii->mii_media_active |= IFM_FLAG1;
522 } else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
523 !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
524 mii->mii_media_active |= IFM_FLAG0;
528 /* FLAG2 : local PHY resolved to MASTER */
529 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
530 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
531 PHY_READ(sc, E1000_1GSR);
532 gsr = PHY_READ(sc, E1000_1GSR);
533 if ((gsr & E1000_1GSR_MS_CONFIG_RES) != 0)
534 mii->mii_media_active |= IFM_FLAG2;
539 e1000phy_mii_phy_auto(struct mii_softc *sc)
541 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
544 reg = PHY_READ(sc, E1000_AR);
545 reg |= E1000_AR_10T | E1000_AR_10T_FD |
546 E1000_AR_100TX | E1000_AR_100TX_FD |
547 E1000_AR_PAUSE | E1000_AR_ASM_DIR;
548 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
550 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X |
551 E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE);
553 if ((sc->mii_extcapabilities &
554 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) {
555 PHY_WRITE(sc, E1000_1GCR,
556 E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
558 PHY_WRITE(sc, E1000_CR,
559 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);