sys/dev/disk/aic7xxx/aic79xx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      aic7901 and aic7902 SCSI controllers
   4  *
   5  * Copyright (c) 1994-2001 Justin T. Gibbs.
   6  * Copyright (c) 2000-2002 Adaptec Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16  *    substantially similar to the "NO WARRANTY" disclaimer below
  17  *    ("Disclaimer") and any redistribution must be conditioned upon
  18  *    including a substantially similar Disclaimer requirement for further
  19  *    binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39  * POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $
  42  *
  43  * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/09/25 23:36:41 scottl Exp $
  44  * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx_pci.c,v 1.8 2007/07/05 05:17:39 pavalos Exp $
  45  */
  46
  47 #ifdef __linux__
  48 #include "aic79xx_osm.h"
  49 #include "aic79xx_inline.h"
  50 #else
  51 #include "aic79xx_osm.h"
  52 #include "aic79xx_inline.h"
  53 #endif
  54
  55 static __inline uint64_t
  56 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  57 {
  58         uint64_t id;
  59
  60         id = subvendor
  61            | (subdevice << 16)
  62            | ((uint64_t)vendor << 32)
  63            | ((uint64_t)device << 48);
  64
  65         return (id);
  66 }
  67
  68 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  69 #define ID_ALL_IROC_MASK                0xFFFFFF7FFFFFFFFFull
  70 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  71 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  72 #define ID_9005_GENERIC_IROC_MASK       0xFFF0FF7F00000000ull
  73
  74 #define ID_AIC7901                      0x800F9005FFFF9005ull
  75 #define ID_AHA_29320A                   0x8000900500609005ull
  76 #define ID_AHA_29320ALP                 0x8017900500449005ull
  77
  78 #define ID_AIC7901A                     0x801E9005FFFF9005ull
  79 #define ID_AHA_29320                    0x8012900500429005ull
  80 #define ID_AHA_29320B                   0x8013900500439005ull
  81 #define ID_AHA_29320LP                  0x8014900500449005ull
  82
  83 #define ID_AIC7902                      0x801F9005FFFF9005ull
  84 #define ID_AIC7902_B                    0x801D9005FFFF9005ull
  85 #define ID_AHA_39320                    0x8010900500409005ull
  86 #define ID_AHA_39320_B                  0x8015900500409005ull
  87 #define ID_AHA_39320A                   0x8016900500409005ull
  88 #define ID_AHA_39320D                   0x8011900500419005ull
  89 #define ID_AHA_39320D_B                 0x801C900500419005ull
  90 #define ID_AHA_39320D_HP                0x8011900500AC0E11ull
  91 #define ID_AHA_39320D_B_HP              0x801C900500AC0E11ull
  92 #define ID_AIC7902_PCI_REV_A4           0x3
  93 #define ID_AIC7902_PCI_REV_B0           0x10
  94 #define SUBID_HP                        0x0E11
  95
  96 #define DEVID_9005_TYPE(id) ((id) & 0xF)
  97 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
  98 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
  99 #define         DEVID_9005_TYPE_IROC            0x8     /* Raid(0,1,10) Card */
 100 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 101
 102 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
 103
 104 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
 105
 106 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 107 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
 108 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 109
 110 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
 111
 112 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
 113
 114 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
 115 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 116 #define         SUBID_9005_SEEPTYPE_4K          0x1
 117
 118 static ahd_device_setup_t ahd_aic7901_setup;
 119 static ahd_device_setup_t ahd_aic7901A_setup;
 120 static ahd_device_setup_t ahd_aic7902_setup;
 121 static ahd_device_setup_t ahd_aic790X_setup;
 122
 123 struct ahd_pci_identity ahd_pci_ident_table [] =
 124 {
 125         /* aic7901 based controllers */
 126         {
 127                 ID_AHA_29320A,
 128                 ID_ALL_MASK,
 129                 "Adaptec 29320A Ultra320 SCSI adapter",
 130                 ahd_aic7901_setup
 131         },
 132         {
 133                 ID_AHA_29320ALP,
 134                 ID_ALL_MASK,
 135                 "Adaptec 29320ALP Ultra320 SCSI adapter",
 136                 ahd_aic7901_setup
 137         },
 138         /* aic7901A based controllers */
 139         {
 140                 ID_AHA_29320,
 141                 ID_ALL_MASK,
 142                 "Adaptec 29320 Ultra320 SCSI adapter",
 143                 ahd_aic7901A_setup
 144         },
 145         {
 146                 ID_AHA_29320B,
 147                 ID_ALL_MASK,
 148                 "Adaptec 29320B Ultra320 SCSI adapter",
 149                 ahd_aic7901A_setup
 150         },
 151         {
 152                 ID_AHA_29320LP,
 153                 ID_ALL_MASK,
 154                 "Adaptec 29320LP Ultra320 SCSI adapter",
 155                 ahd_aic7901A_setup
 156         },
 157         /* aic7902 based controllers */
 158         {
 159                 ID_AHA_39320,
 160                 ID_ALL_MASK,
 161                 "Adaptec 39320 Ultra320 SCSI adapter",
 162                 ahd_aic7902_setup
 163         },
 164         {
 165                 ID_AHA_39320_B,
 166                 ID_ALL_MASK,
 167                 "Adaptec 39320 Ultra320 SCSI adapter",
 168                 ahd_aic7902_setup
 169         },
 170         {
 171                 ID_AHA_39320A,
 172                 ID_ALL_MASK,
 173                 "Adaptec 39320A Ultra320 SCSI adapter",
 174                 ahd_aic7902_setup
 175         },
 176         {
 177                 ID_AHA_39320D,
 178                 ID_ALL_MASK,
 179                 "Adaptec 39320D Ultra320 SCSI adapter",
 180                 ahd_aic7902_setup
 181         },
 182         {
 183                 ID_AHA_39320D_HP,
 184                 ID_ALL_MASK,
 185                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 186                 ahd_aic7902_setup
 187         },
 188         {
 189                 ID_AHA_39320D_B,
 190                 ID_ALL_MASK,
 191                 "Adaptec 39320D Ultra320 SCSI adapter",
 192                 ahd_aic7902_setup
 193         },
 194         {
 195                 ID_AHA_39320D_B_HP,
 196                 ID_ALL_MASK,
 197                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 198                 ahd_aic7902_setup
 199         },
 200         {
 201                 ID_AHA_29320,
 202                 ID_ALL_MASK,
 203                 "Adaptec 29320 Ultra320 SCSI adapter",
 204                 ahd_aic7902_setup
 205         },
 206         {
 207                 ID_AHA_29320B,
 208                 ID_ALL_MASK,
 209                 "Adaptec 29320B Ultra320 SCSI adapter",
 210                 ahd_aic7902_setup
 211         },
 212         /* Generic chip probes for devices we don't know 'exactly' */
 213         {
 214                 ID_AIC7901 & ID_DEV_VENDOR_MASK,
 215                 ID_DEV_VENDOR_MASK,
 216                 "Adaptec AIC7901 Ultra320 SCSI adapter",
 217                 ahd_aic7901_setup
 218         },
 219         {
 220                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
 221                 ID_DEV_VENDOR_MASK,
 222                 "Adaptec AIC7901A Ultra320 SCSI adapter",
 223                 ahd_aic7901A_setup
 224         },
 225         {
 226                 ID_AIC7902 & ID_9005_GENERIC_MASK,
 227                 ID_9005_GENERIC_MASK,
 228                 "Adaptec AIC7902 Ultra320 SCSI adapter",
 229                 ahd_aic7902_setup
 230         }
 231 };
 232
 233 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
 234
 235 #define DEVCONFIG               0x40
 236 #define         PCIXINITPAT     0x0000E000ul
 237 #define                 PCIXINIT_PCI33_66       0x0000E000ul
 238 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
 239 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
 240 #define                 PCIXINIT_PCIX100_133    0x00008000ul
 241 #define PCI_BUS_MODES_INDEX(devconfig)  \
 242         (((devconfig) & PCIXINITPAT) >> 13)
 243 static const char *pci_bus_modes[] =
 244 {
 245         "PCI bus mode unknown",
 246         "PCI bus mode unknown",
 247         "PCI bus mode unknown",
 248         "PCI bus mode unknown",
 249         "PCI-X 101-133Mhz",
 250         "PCI-X 67-100Mhz",
 251         "PCI-X 50-66Mhz",
 252         "PCI 33 or 66Mhz"
 253 };
 254
 255 #define         TESTMODE        0x00000800ul
 256 #define         IRDY_RST        0x00000200ul
 257 #define         FRAME_RST       0x00000100ul
 258 #define         PCI64BIT        0x00000080ul
 259 #define         MRDCEN          0x00000040ul
 260 #define         ENDIANSEL       0x00000020ul
 261 #define         MIXQWENDIANEN   0x00000008ul
 262 #define         DACEN           0x00000004ul
 263 #define         STPWLEVEL       0x00000002ul
 264 #define         QWENDIANSEL     0x00000001ul
 265
 266 #define DEVCONFIG1              0x44
 267 #define         PREQDIS         0x01
 268
 269 #define CSIZE_LATTIME           0x0c
 270 #define         CACHESIZE       0x000000fful
 271 #define         LATTIME         0x0000ff00ul
 272
 273 static int      ahd_check_extport(struct ahd_softc *ahd);
 274 static void     ahd_configure_termination(struct ahd_softc *ahd,
 275                                           u_int adapter_control);
 276 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
 277
 278 struct ahd_pci_identity *
 279 ahd_find_pci_device(ahd_dev_softc_t pci)
 280 {
 281         uint64_t  full_id;
 282         uint16_t  device;
 283         uint16_t  vendor;
 284         uint16_t  subdevice;
 285         uint16_t  subvendor;
 286         struct    ahd_pci_identity *entry;
 287         u_int     i;
 288
 289         vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 290         device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 291         subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 292         subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 293         full_id = ahd_compose_id(device,
 294                                  vendor,
 295                                  subdevice,
 296                                  subvendor);
 297
 298         for (i = 0; i < ahd_num_pci_devs; i++) {
 299                 entry = &ahd_pci_ident_table[i];
 300                 if (entry->full_id == (full_id & entry->id_mask)) {
 301                         /* Honor exclusion entries. */
 302                         if (entry->name == NULL)
 303                                 return (NULL);
 304                         return (entry);
 305                 }
 306         }
 307         return (NULL);
 308 }
 309
 310 int
 311 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
 312 {
 313         struct scb_data *shared_scb_data;
 314         u_int            command;
 315         uint32_t         devconfig;
 316         uint16_t         subvendor;
 317         int              error;
 318
 319         shared_scb_data = NULL;
 320         ahd->description = entry->name;
 321         /*
 322          * Record if this is an HP board.
 323          */
 324         subvendor = ahd_pci_read_config(ahd->dev_softc,
 325                                         PCIR_SUBVEND_0, /*bytes*/2);
 326         if (subvendor == SUBID_HP)
 327                 ahd->flags |= AHD_HP_BOARD;
 328
 329         error = entry->setup(ahd);
 330         if (error != 0)
 331                 return (error);
 332
 333         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 334         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 335                 ahd->chip |= AHD_PCI;
 336                 /* Disable PCIX workarounds when running in PCI mode. */
 337                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 338         } else {
 339                 ahd->chip |= AHD_PCIX;
 340         }
 341         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 342
 343         ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
 344
 345         error = ahd_pci_map_registers(ahd);
 346         if (error != 0)
 347                 return (error);
 348
 349         /*
 350          * If we need to support high memory, enable dual
 351          * address cycles.  This bit must be set to enable
 352          * high address bit generation even if we are on a
 353          * 64bit bus (PCI64BIT set in devconfig).
 354          */
 355         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
 356                 uint32_t devconfig;
 357
 358                 if (bootverbose)
 359                         kprintf("%s: Enabling 39Bit Addressing\n",
 360                                ahd_name(ahd));
 361                 devconfig = ahd_pci_read_config(ahd->dev_softc,
 362                                                 DEVCONFIG, /*bytes*/4);
 363                 devconfig |= DACEN;
 364                 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
 365                                      devconfig, /*bytes*/4);
 366         }
 367
 368         /* Ensure busmastering is enabled */
 369         command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 370         command |= PCIM_CMD_BUSMASTEREN;
 371         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 372
 373         error = ahd_softc_init(ahd);
 374         if (error != 0)
 375                 return (error);
 376
 377         ahd->bus_intr = ahd_pci_intr;
 378
 379         error = ahd_reset(ahd, /*reinit*/FALSE);
 380         if (error != 0)
 381                 return (ENXIO);
 382
 383         ahd->pci_cachesize =
 384             ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
 385                                 /*bytes*/1) & CACHESIZE;
 386         ahd->pci_cachesize *= 4;
 387
 388         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 389         /* See if we have a SEEPROM and perform auto-term */
 390         error = ahd_check_extport(ahd);
 391         if (error != 0)
 392                 return (error);
 393
 394         /* Core initialization */
 395         error = ahd_init(ahd);
 396         if (error != 0)
 397                 return (error);
 398
 399         /*
 400          * Allow interrupts now that we are completely setup.
 401          */
 402         error = ahd_pci_map_int(ahd);
 403         if (error != 0)
 404                 return (error);
 405
 406         /*
 407          * Link this softc in with all other ahd instances.
 408          */
 409         ahd_softc_insert(ahd);
 410         return (0);
 411 }
 412
 413 /*
 414  * Perform some simple tests that should catch situations where
 415  * our registers are invalidly mapped.
 416  */
 417 int
 418 ahd_pci_test_register_access(struct ahd_softc *ahd)
 419 {
 420         uint32_t cmd;
 421         u_int    targpcistat;
 422         u_int    pci_status1;
 423         int      error;
 424         uint8_t  hcntrl;
 425
 426         error = EIO;
 427
 428         /*
 429          * Enable PCI error interrupt status, but suppress NMIs
 430          * generated by SERR raised due to target aborts.
 431          */
 432         cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 433         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 434                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
 435
 436         /*
 437          * First a simple test to see if any
 438          * registers can be read.  Reading
 439          * HCNTRL has no side effects and has
 440          * at least one bit that is guaranteed to
 441          * be zero so it is a good register to
 442          * use for this test.
 443          */
 444         hcntrl = ahd_inb(ahd, HCNTRL);
 445         if (hcntrl == 0xFF)
 446                 goto fail;
 447
 448         /*
 449          * Next create a situation where write combining
 450          * or read prefetching could be initiated by the
 451          * CPU or host bridge.  Our device does not support
 452          * either, so look for data corruption and/or flaged
 453          * PCI errors.  First pause without causing another
 454          * chip reset.
 455          */
 456         hcntrl &= ~CHIPRST;
 457         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
 458         while (ahd_is_paused(ahd) == 0)
 459                 ;
 460
 461         /* Clear any PCI errors that occurred before our driver attached. */
 462         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 463         targpcistat = ahd_inb(ahd, TARGPCISTAT);
 464         ahd_outb(ahd, TARGPCISTAT, targpcistat);
 465         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 466                                           PCIR_STATUS + 1, /*bytes*/1);
 467         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 468                              pci_status1, /*bytes*/1);
 469         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 470         ahd_outb(ahd, CLRINT, CLRPCIINT);
 471
 472         ahd_outb(ahd, SEQCTL0, PERRORDIS);
 473         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
 474         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
 475                 goto fail;
 476
 477         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 478                 u_int targpcistat;
 479
 480                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 481                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 482                 if ((targpcistat & STA) != 0)
 483                         goto fail;
 484         }
 485
 486         error = 0;
 487
 488 fail:
 489         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 490
 491                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 492                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 493
 494                 /* Silently clear any latched errors. */
 495                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
 496                 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 497                                                   PCIR_STATUS + 1, /*bytes*/1);
 498                 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 499                                      pci_status1, /*bytes*/1);
 500                 ahd_outb(ahd, CLRINT, CLRPCIINT);
 501         }
 502         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
 503         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 504         return (error);
 505 }
 506
 507 /*
 508  * Check the external port logic for a serial eeprom
 509  * and termination/cable detection contrls.
 510  */
 511 static int
 512 ahd_check_extport(struct ahd_softc *ahd)
 513 {
 514         struct  vpd_config vpd;
 515         struct  seeprom_config *sc;
 516         u_int   adapter_control;
 517         int     have_seeprom;
 518         int     error;
 519
 520         sc = ahd->seep_config;
 521         have_seeprom = ahd_acquire_seeprom(ahd);
 522         if (have_seeprom) {
 523                 u_int start_addr;
 524
 525                 /*
 526                  * Fetch VPD for this function and parse it.
 527                  */
 528                 if (bootverbose)
 529                         kprintf("%s: Reading VPD from SEEPROM...",
 530                                ahd_name(ahd));
 531
 532                 /* Address is always in units of 16bit words */
 533                 start_addr = ((2 * sizeof(*sc))
 534                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
 535
 536                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
 537                                          start_addr, sizeof(vpd)/2,
 538                                          /*bytestream*/TRUE);
 539                 if (error == 0)
 540                         error = ahd_parse_vpddata(ahd, &vpd);
 541                 if (bootverbose)
 542                         kprintf("%s: VPD parsing %s\n",
 543                                ahd_name(ahd),
 544                                error == 0 ? "successful" : "failed");
 545
 546                 if (bootverbose)
 547                         kprintf("%s: Reading SEEPROM...", ahd_name(ahd));
 548
 549                 /* Address is always in units of 16bit words */
 550                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
 551
 552                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
 553                                          start_addr, sizeof(*sc)/2,
 554                                          /*bytestream*/FALSE);
 555
 556                 if (error != 0) {
 557                         kprintf("Unable to read SEEPROM\n");
 558                         have_seeprom = 0;
 559                 } else {
 560                         have_seeprom = ahd_verify_cksum(sc);
 561
 562                         if (bootverbose) {
 563                                 if (have_seeprom == 0)
 564                                         kprintf ("checksum error\n");
 565                                 else
 566                                         kprintf ("done.\n");
 567                         }
 568                 }
 569                 ahd_release_seeprom(ahd);
 570         }
 571
 572         if (!have_seeprom) {
 573                 u_int     nvram_scb;
 574
 575                 /*
 576                  * Pull scratch ram settings and treat them as
 577                  * if they are the contents of an seeprom if
 578                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
 579                  * in SCB 0xFF.  We manually compose the data as 16bit
 580                  * values to avoid endian issues.
 581                  */
 582                 ahd_set_scbptr(ahd, 0xFF);
 583                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
 584                 if (nvram_scb != 0xFF
 585                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 586                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
 587                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 588                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
 589                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
 590                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
 591                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
 592                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
 593                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 594                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
 595                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 596                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
 597                         uint16_t *sc_data;
 598                         int       i;
 599
 600                         ahd_set_scbptr(ahd, nvram_scb);
 601                         sc_data = (uint16_t *)sc;
 602                         for (i = 0; i < 64; i += 2)
 603                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
 604                         have_seeprom = ahd_verify_cksum(sc);
 605                         if (have_seeprom)
 606                                 ahd->flags |= AHD_SCB_CONFIG_USED;
 607                 }
 608         }
 609
 610 #if AHD_DEBUG
 611         if (have_seeprom != 0
 612          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 613                 uint16_t *sc_data;
 614                 int       i;
 615
 616                 kprintf("%s: Seeprom Contents:", ahd_name(ahd));
 617                 sc_data = (uint16_t *)sc;
 618                 for (i = 0; i < (sizeof(*sc)); i += 2)
 619                         kprintf("\n\t0x%.4x", sc_data[i]);
 620                 kprintf("\n");
 621         }
 622 #endif
 623
 624         if (!have_seeprom) {
 625                 if (bootverbose)
 626                         kprintf("%s: No SEEPROM available.\n", ahd_name(ahd));
 627                 ahd->flags |= AHD_USEDEFAULTS;
 628                 error = ahd_default_config(ahd);
 629                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
 630                 kfree(ahd->seep_config, M_DEVBUF);
 631                 ahd->seep_config = NULL;
 632         } else {
 633                 error = ahd_parse_cfgdata(ahd, sc);
 634                 adapter_control = sc->adapter_control;
 635         }
 636         if (error != 0)
 637                 return (error);
 638
 639         ahd_configure_termination(ahd, adapter_control);
 640
 641         return (0);
 642 }
 643
 644 static void
 645 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
 646 {
 647         int      error;
 648         u_int    sxfrctl1;
 649         uint8_t  termctl;
 650         uint32_t devconfig;
 651
 652         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 653         devconfig &= ~STPWLEVEL;
 654         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
 655                 devconfig |= STPWLEVEL;
 656         if (bootverbose)
 657                 kprintf("%s: STPWLEVEL is %s\n",
 658                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
 659         ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 660
 661         /* Make sure current sensing is off. */
 662         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
 663                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
 664         }
 665
 666         /*
 667          * Read to sense.  Write to set.
 668          */
 669         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
 670         if ((adapter_control & CFAUTOTERM) == 0) {
 671                 if (bootverbose)
 672                         kprintf("%s: Manual Primary Termination\n",
 673                                ahd_name(ahd));
 674                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
 675                 if ((adapter_control & CFSTERM) != 0)
 676                         termctl |= FLX_TERMCTL_ENPRILOW;
 677                 if ((adapter_control & CFWSTERM) != 0)
 678                         termctl |= FLX_TERMCTL_ENPRIHIGH;
 679         } else if (error != 0) {
 680                 kprintf("%s: Primary Auto-Term Sensing failed! "
 681                        "Using Defaults.\n", ahd_name(ahd));
 682                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
 683         }
 684
 685         if ((adapter_control & CFSEAUTOTERM) == 0) {
 686                 if (bootverbose)
 687                         kprintf("%s: Manual Secondary Termination\n",
 688                                ahd_name(ahd));
 689                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
 690                 if ((adapter_control & CFSELOWTERM) != 0)
 691                         termctl |= FLX_TERMCTL_ENSECLOW;
 692                 if ((adapter_control & CFSEHIGHTERM) != 0)
 693                         termctl |= FLX_TERMCTL_ENSECHIGH;
 694         } else if (error != 0) {
 695                 kprintf("%s: Secondary Auto-Term Sensing failed! "
 696                        "Using Defaults.\n", ahd_name(ahd));
 697                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
 698         }
 699
 700         /*
 701          * Now set the termination based on what we found.
 702          */
 703         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
 704         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
 705                 ahd->flags |= AHD_TERM_ENB_A;
 706                 sxfrctl1 |= STPWEN;
 707         }
 708         /* Must set the latch once in order to be effective. */
 709         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
 710         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
 711
 712         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
 713         if (error != 0) {
 714                 kprintf("%s: Unable to set termination settings!\n",
 715                        ahd_name(ahd));
 716         } else if (bootverbose) {
 717                 kprintf("%s: Primary High byte termination %sabled\n",
 718                        ahd_name(ahd),
 719                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
 720
 721                 kprintf("%s: Primary Low byte termination %sabled\n",
 722                        ahd_name(ahd),
 723                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
 724
 725                 kprintf("%s: Secondary High byte termination %sabled\n",
 726                        ahd_name(ahd),
 727                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
 728
 729                 kprintf("%s: Secondary Low byte termination %sabled\n",
 730                        ahd_name(ahd),
 731                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
 732         }
 733         return;
 734 }
 735
 736 #define DPE     0x80
 737 #define SSE     0x40
 738 #define RMA     0x20
 739 #define RTA     0x10
 740 #define STA     0x08
 741 #define DPR     0x01
 742
 743 static const char *split_status_source[] =
 744 {
 745         "DFF0",
 746         "DFF1",
 747         "OVLY",
 748         "CMC",
 749 };
 750
 751 static const char *pci_status_source[] =
 752 {
 753         "DFF0",
 754         "DFF1",
 755         "SG",
 756         "CMC",
 757         "OVLY",
 758         "NONE",
 759         "MSI",
 760         "TARG"
 761 };
 762
 763 static const char *split_status_strings[] =
 764 {
 765         "%s: Received split response in %s.\n",
 766         "%s: Received split completion error message in %s\n",
 767         "%s: Receive overrun in %s\n",
 768         "%s: Count not complete in %s\n",
 769         "%s: Split completion data bucket in %s\n",
 770         "%s: Split completion address error in %s\n",
 771         "%s: Split completion byte count error in %s\n",
 772         "%s: Signaled Target-abort to early terminate a split in %s\n"
 773 };
 774
 775 static const char *pci_status_strings[] =
 776 {
 777         "%s: Data Parity Error has been reported via PERR# in %s\n",
 778         "%s: Target initial wait state error in %s\n",
 779         "%s: Split completion read data parity error in %s\n",
 780         "%s: Split completion address attribute parity error in %s\n",
 781         "%s: Received a Target Abort in %s\n",
 782         "%s: Received a Master Abort in %s\n",
 783         "%s: Signal System Error Detected in %s\n",
 784         "%s: Address or Write Phase Parity Error Detected in %s.\n"
 785 };
 786
 787 void
 788 ahd_pci_intr(struct ahd_softc *ahd)
 789 {
 790         uint8_t         pci_status[8];
 791         ahd_mode_state  saved_modes;
 792         u_int           pci_status1;
 793         u_int           intstat;
 794         u_int           i;
 795         u_int           reg;
 796
 797         intstat = ahd_inb(ahd, INTSTAT);
 798
 799         if ((intstat & SPLTINT) != 0)
 800                 ahd_pci_split_intr(ahd, intstat);
 801
 802         if ((intstat & PCIINT) == 0)
 803                 return;
 804
 805         kprintf("%s: PCI error Interrupt\n", ahd_name(ahd));
 806         saved_modes = ahd_save_modes(ahd);
 807         ahd_dump_card_state(ahd);
 808         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 809         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
 810
 811                 if (i == 5)
 812                         continue;
 813                 pci_status[i] = ahd_inb(ahd, reg);
 814                 /* Clear latched errors.  So our interrupt deasserts. */
 815                 ahd_outb(ahd, reg, pci_status[i]);
 816         }
 817
 818         for (i = 0; i < 8; i++) {
 819                 u_int bit;
 820
 821                 if (i == 5)
 822                         continue;
 823
 824                 for (bit = 0; bit < 8; bit++) {
 825
 826                         if ((pci_status[i] & (0x1 << bit)) != 0) {
 827                                 static const char *s;
 828
 829                                 s = pci_status_strings[bit];
 830                                 if (i == 7/*TARG*/ && bit == 3)
 831                                         s = "%s: Signaled Target Abort\n";
 832                                 kprintf(s, ahd_name(ahd), pci_status_source[i]);
 833                         }
 834                 }
 835         }
 836         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 837                                           PCIR_STATUS + 1, /*bytes*/1);
 838         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 839                              pci_status1, /*bytes*/1);
 840         ahd_restore_modes(ahd, saved_modes);
 841         ahd_outb(ahd, CLRINT, CLRPCIINT);
 842         ahd_unpause(ahd);
 843 }
 844
 845 static void
 846 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
 847 {
 848         uint8_t         split_status[4];
 849         uint8_t         split_status1[4];
 850         uint8_t         sg_split_status[2];
 851         uint8_t         sg_split_status1[2];
 852         ahd_mode_state  saved_modes;
 853         u_int           i;
 854         uint16_t        pcix_status;
 855
 856         /*
 857          * Check for splits in all modes.  Modes 0 and 1
 858          * additionally have SG engine splits to look at.
 859          */
 860         pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
 861                                           /*bytes*/2);
 862         kprintf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
 863                ahd_name(ahd), pcix_status);
 864         saved_modes = ahd_save_modes(ahd);
 865         for (i = 0; i < 4; i++) {
 866                 ahd_set_modes(ahd, i, i);
 867
 868                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
 869                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
 870                 /* Clear latched errors.  So our interrupt deasserts. */
 871                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
 872                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
 873                 if (i > 1)
 874                         continue;
 875                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
 876                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
 877                 /* Clear latched errors.  So our interrupt deasserts. */
 878                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
 879                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
 880         }
 881
 882         for (i = 0; i < 4; i++) {
 883                 u_int bit;
 884
 885                 for (bit = 0; bit < 8; bit++) {
 886
 887                         if ((split_status[i] & (0x1 << bit)) != 0) {
 888                                 static const char *s;
 889
 890                                 s = split_status_strings[bit];
 891                                 kprintf(s, ahd_name(ahd),
 892                                        split_status_source[i]);
 893                         }
 894
 895                         if (i > 1)
 896                                 continue;
 897
 898                         if ((sg_split_status[i] & (0x1 << bit)) != 0) {
 899                                 static const char *s;
 900
 901                                 s = split_status_strings[bit];
 902                                 kprintf(s, ahd_name(ahd), "SG");
 903                         }
 904                 }
 905         }
 906         /*
 907          * Clear PCI-X status bits.
 908          */
 909         ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
 910                              pcix_status, /*bytes*/2);
 911         ahd_outb(ahd, CLRINT, CLRSPLTINT);
 912         ahd_restore_modes(ahd, saved_modes);
 913 }
 914
 915 static int
 916 ahd_aic7901_setup(struct ahd_softc *ahd)
 917 {
 918
 919         ahd->chip = AHD_AIC7901;
 920         ahd->features = AHD_AIC7901_FE;
 921         return (ahd_aic790X_setup(ahd));
 922 }
 923
 924 static int
 925 ahd_aic7901A_setup(struct ahd_softc *ahd)
 926 {
 927
 928         ahd->chip = AHD_AIC7901A;
 929         ahd->features = AHD_AIC7901A_FE;
 930         return (ahd_aic790X_setup(ahd));
 931 }
 932
 933 static int
 934 ahd_aic7902_setup(struct ahd_softc *ahd)
 935 {
 936         ahd->chip = AHD_AIC7902;
 937         ahd->features = AHD_AIC7902_FE;
 938         return (ahd_aic790X_setup(ahd));
 939 }
 940
 941 static int
 942 ahd_aic790X_setup(struct ahd_softc *ahd)
 943 {
 944         ahd_dev_softc_t pci;
 945         u_int rev;
 946
 947         pci = ahd->dev_softc;
 948         rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
 949         if (rev < ID_AIC7902_PCI_REV_A4) {
 950                 kprintf("%s: Unable to attach to unsupported chip revision %d\n",
 951                        ahd_name(ahd), rev);
 952                 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
 953                 return (ENXIO);
 954         }
 955         ahd->channel = ahd_get_pci_function(pci) + 'A';
 956         if (rev < ID_AIC7902_PCI_REV_B0) {
 957                 /*
 958                  * Enable A series workarounds.
 959                  */
 960                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
 961                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
 962                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
 963                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
 964                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
 965                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
 966                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
 967                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
 968                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
 969                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
 970                           |  AHD_FAINT_LED_BUG;
 971
 972                 /*
 973                  * IO Cell paramter setup.
 974                  */
 975                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 976
 977                 if ((ahd->flags & AHD_HP_BOARD) == 0)
 978                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
 979         } else {
 980                 u_int devconfig1;
 981
 982                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
 983                               |  AHD_NEW_DFCNTRL_OPTS;
 984                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
 985
 986                 /*
 987                  * Some issues have been resolved in the 7901B.
 988                  */
 989                 if ((ahd->features & AHD_MULTI_FUNC) != 0)
 990                         ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
 991
 992                 /*
 993                  * IO Cell paramter setup.
 994                  */
 995                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 996                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
 997                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
 998
 999                 /*
1000                  * Set the PREQDIS bit for H2B which disables some workaround
1001                  * that doesn't work on regular PCI busses.
1002                  * XXX - Find out exactly what this does from the hardware
1003                  *       folks!
1004                  */
1005                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1006                 ahd_pci_write_config(pci, DEVCONFIG1,
1007                                      devconfig1|PREQDIS, /*bytes*/1);
1008                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1009         }
1010
1011         return (0);
1012 }