1 /* $DragonFly: src/sys/dev/netif/mii_layer/miidevs.h,v 1.13 2007/10/12 14:03:41 sephe Exp $ */
4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
7 * DragonFly: src/sys/dev/netif/mii_layer/miidevs,v 1.12 2007/09/17 11:13:55 hasso Exp
9 /* $FreeBSD: src/sys/dev/mii/miidevs,v 1.4.2.13 2003/07/22 02:12:55 ps Exp $ */
10 /*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/
13 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
14 * All rights reserved.
16 * This code is derived from software contributed to The NetBSD Foundation
17 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
18 * NASA Ames Research Center.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
23 * 1. Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * 3. All advertising materials mentioning features or use of this software
29 * must display the following acknowledgement:
30 * This product includes software developed by the NetBSD
31 * Foundation, Inc. and its contributors.
32 * 4. Neither the name of The NetBSD Foundation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
36 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
38 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
39 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
40 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
46 * POSSIBILITY OF SUCH DAMAGE.
50 * List of known MII OUIs.
51 * For a complete list see http://standards.ieee.org/regauth/oui/
53 * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped
54 * to the 16 bits available in the id registers. The MII_OUI() macro
55 * in "mii.h" reflects the most obvious way. If a vendor uses a
56 * different mapping, an "xx" prefixed OUI is defined here which is
57 * mangled accordingly to compensate.
60 #define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
61 #define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
62 #define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
63 #define MII_OUI_CICADA 0x0003f1 /* Cicada Semiconductor */
64 #define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
65 #define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
66 #define MII_OUI_INTEL 0x00aa00 /* Intel */
67 #define MII_OUI_JATO 0x00e083 /* Jato Technologies */
68 #define MII_OUI_LEVEL1 0x00207b /* Level 1 */
69 #define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
70 #define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
71 #define MII_OUI_REALTEK 0x000020 /* RealTek Semicondctor */
72 #define MII_OUI_REALTEK2 0x00e04c /* RealTek Semicondctor */
73 #define MII_OUI_SEEQ 0x00a07d /* Seeq */
74 #define MII_OUI_AGERE 0x00a0bc /* Agere Systems */
75 #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
76 #define MII_OUI_TDK 0x00c039 /* TDK */
77 #define MII_OUI_TI 0x080028 /* Texas Instruments */
78 #define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
79 #define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
80 #define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */
81 #define MII_OUI_VITESSE 0x0001c1 /* Vitesse Semiconductor */
83 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */
84 #define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
86 /* Intel 82553 A/B steppings */
87 #define MII_OUI_xxINTEL 0x00f800 /* Intel */
89 /* some vendors have the bits swapped within bytes
90 (ie, ordered as on the wire) */
91 #define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */
92 #define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
93 #define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */
94 #define MII_OUI_xxSEEQ 0x0005be /* Seeq */
95 #define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */
96 #define MII_OUI_xxTI 0x100014 /* Texas Instruments */
97 #define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */
99 /* Level 1 is completely different - from right to left.
100 (Two bits get lost in the third OUI byte.) */
101 #define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */
102 #define MII_OUI_xxLEVEL1a 0x0004de /* Level 1 */
104 /* Don't know what's going on here. */
105 #define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */
106 #define MII_OUI_xxBROADCOM2 0x0050ef /* Broadcom Corporation */
108 /* This is the OUI of the gigE PHY in the RealTek 8211B/8169S/8110S chips */
109 #define MII_OUI_xxREALTEK 0x000732 /* */
111 #define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */
112 #define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */
115 * List of known models. Grouped by oui.
118 /* Agere Systems PHYs */
119 #define MII_MODEL_AGERE_ET1011C 0x0004
120 #define MII_STR_AGERE_ET1011C "ET1011C 10/100/1000baseT PHY"
122 /* Altima Communications PHYs */
123 #define MII_MODEL_xxALTIMA_AC_UNKNOWN 0x0001
124 #define MII_STR_xxALTIMA_AC_UNKNOWN "AC_UNKNOWN 10/100 media interface"
125 #define MII_MODEL_xxALTIMA_AC101L 0x0012
126 #define MII_STR_xxALTIMA_AC101L "AC101L 10/100 media interface"
127 #define MII_MODEL_xxALTIMA_AC101 0x0021
128 #define MII_STR_xxALTIMA_AC101 "AC101 10/100 media interface"
129 /* AMD Am79C875 have ALTIMA OUI */
130 #define MII_MODEL_xxALTIMA_Am79C875 0x0014
131 #define MII_STR_xxALTIMA_Am79C875 "Am79C875 10/100 media interface"
133 /* Advanced Micro Devices PHYs */
134 #define MII_MODEL_xxAMD_79C873 0x0000
135 #define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface"
136 #define MII_MODEL_AMD_79c973phy 0x0036
137 #define MII_STR_AMD_79c973phy "Am79c973 internal PHY"
138 #define MII_MODEL_AMD_79c978 0x0039
139 #define MII_STR_AMD_79c978 "Am79c978 HomePNA PHY"
141 /* Broadcom Corp. PHYs. */
142 #define MII_MODEL_BROADCOM_BCM5400 0x0004
143 #define MII_STR_BROADCOM_BCM5400 "BCM5400 1000baseT PHY"
144 #define MII_MODEL_BROADCOM_BCM5401 0x0005
145 #define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseT PHY"
146 #define MII_MODEL_BROADCOM_BCM5411 0x0007
147 #define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseT PHY"
148 #define MII_MODEL_BROADCOM_3C905B 0x0012
149 #define MII_STR_BROADCOM_3C905B "Broadcom 3C905B internal PHY"
150 #define MII_MODEL_BROADCOM_3C905C 0x0017
151 #define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY"
152 #define MII_MODEL_BROADCOM_BCM5221 0x001e
153 #define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY"
154 #define MII_MODEL_BROADCOM_BCM5201 0x0021
155 #define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 PHY"
156 #define MII_MODEL_BROADCOM_BCM5214 0x0028
157 #define MII_STR_BROADCOM_BCM5214 "BCM5214 Quad 10/100 PHY"
158 #define MII_MODEL_BROADCOM_BCM5222 0x0032
159 #define MII_STR_BROADCOM_BCM5222 "BCM5222 Dual 10/100 PHY"
160 #define MII_MODEL_BROADCOM_BCM5220 0x0033
161 #define MII_STR_BROADCOM_BCM5220 "BCM5220 10/100 PHY"
162 #define MII_MODEL_BROADCOM_BCM4401 0x0036
163 #define MII_STR_BROADCOM_BCM4401 "BCM4401 10/100baseTX PHY"
164 #define MII_MODEL_xxBROADCOM_BCM5400 0x0004
165 #define MII_STR_xxBROADCOM_BCM5400 "Broadcom 1000baseTX PHY"
166 #define MII_MODEL_xxBROADCOM_BCM5401 0x0005
167 #define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseTX PHY"
168 #define MII_MODEL_xxBROADCOM_BCM5411 0x0007
169 #define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseTX PHY"
170 #define MII_MODEL_xxBROADCOM_BCM5462 0x000d
171 #define MII_STR_xxBROADCOM_BCM5462 "BCM5462 10/100/1000baseT PHY"
172 #define MII_MODEL_xxBROADCOM_BCM5421 0x000e
173 #define MII_STR_xxBROADCOM_BCM5421 "BCM5421 10/100/1000baseT PHY"
174 #define MII_MODEL_xxBROADCOM_BCM5752 0x0010
175 #define MII_STR_xxBROADCOM_BCM5752 "BCM5752 10/100/1000baseT PHY"
176 #define MII_MODEL_xxBROADCOM_BCM5701 0x0011
177 #define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseTX PHY"
178 #define MII_MODEL_xxBROADCOM_BCM5706C 0x0015
179 #define MII_STR_xxBROADCOM_BCM5706C "BCM5706C 10/100/1000baseT PHY"
180 #define MII_MODEL_xxBROADCOM_BCM5703 0x0016
181 #define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseTX PHY"
182 #define MII_MODEL_xxBROADCOM_BCM5704 0x0019
183 #define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseTX PHY"
184 #define MII_MODEL_xxBROADCOM_BCM5705 0x001a
185 #define MII_STR_xxBROADCOM_BCM5705 "BCM5705 10/100/1000baseTX PHY"
186 #define MII_MODEL_xxBROADCOM_BCM5750 0x0018
187 #define MII_STR_xxBROADCOM_BCM5750 "BCM5750 10/100/1000baseT PHY"
188 #define MII_MODEL_xxBROADCOM_BCM54K2 0x002e
189 #define MII_STR_xxBROADCOM_BCM54K2 "BCM54K2 10/100/1000baseT PHY"
190 #define MII_MODEL_xxBROADCOM_BCM5714 0x0034
191 #define MII_STR_xxBROADCOM_BCM5714 "BCM5714 10/100/1000baseT PHY"
192 #define MII_MODEL_xxBROADCOM_BCM5780 0x0035
193 #define MII_STR_xxBROADCOM_BCM5780 "BCM5780 10/100/1000baseT PHY"
194 #define MII_MODEL_xxBROADCOM_BCM5708C 0x0036
195 #define MII_STR_xxBROADCOM_BCM5708C "BCM5708C 10/100/1000baseT PHY"
196 #define MII_MODEL_xxBROADCOM2_BCM5755 0x000c
197 #define MII_STR_xxBROADCOM2_BCM5755 "BCM5755 10/100/1000baseT PHY"
198 #define MII_MODEL_xxBROADCOM2_BCM5787 0x000e
199 #define MII_STR_xxBROADCOM2_BCM5787 "BCM5787 10/100/1000baseT PHY"
201 /* Cicada Semiconductor PHYs (now owned by Vitesse?) */
202 #define MII_MODEL_CICADA_CS8201 0x0001
203 #define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY"
204 #define MII_MODEL_CICADA_CS8201A 0x0020
205 #define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY"
206 #define MII_MODEL_CICADA_CS8201B 0x0021
207 #define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY"
208 #define MII_MODEL_xxCICADA_CS8201 0x0001
209 #define MII_STR_xxCICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY"
210 #define MII_MODEL_xxCICADA_CS8201A 0x0020
211 #define MII_STR_xxCICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY"
212 #define MII_MODEL_xxCICADA_CS8201B 0x0021
213 #define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY"
215 /* Davicom Semiconductor PHYs */
216 #define MII_MODEL_xxDAVICOM_DM9101 0x0000
217 #define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 media interface"
218 #define MII_MODEL_DAVICOM_DM9102 0x0004
219 #define MII_STR_DAVICOM_DM9102 "DM9102 10/100 media interface"
220 #define MII_MODEL_DAVICOM_DM9601 0x000c
221 #define MII_STR_DAVICOM_DM9601 "DM9601 10/100 media interface"
223 /* Integrated Circuit Systems PHYs */
224 #define MII_MODEL_xxICS_1890 0x0002
225 #define MII_STR_xxICS_1890 "ICS1890 10/100 media interface"
228 #define MII_MODEL_xxINTEL_I82553AB 0x0000
229 #define MII_STR_xxINTEL_I82553AB "i83553 10/100 media interface"
230 #define MII_MODEL_INTEL_I82555 0x0015
231 #define MII_STR_INTEL_I82555 "i82555 10/100 media interface"
232 #define MII_MODEL_INTEL_I82562EM 0x0032
233 #define MII_STR_INTEL_I82562EM "i82562EM 10/100 media interface"
234 #define MII_MODEL_INTEL_I82562ET 0x0033
235 #define MII_STR_INTEL_I82562ET "i82562ET 10/100 media interface"
236 #define MII_MODEL_INTEL_I82553C 0x0035
237 #define MII_STR_INTEL_I82553C "i82553 10/100 media interface"
239 /* Jato Technologies PHYs */
240 #define MII_MODEL_JATO_BASEX 0x0000
241 #define MII_STR_JATO_BASEX "Jato 1000baseX media interface"
244 #define MII_MODEL_xxLEVEL1_LXT970 0x0000
245 #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
246 #define MII_MODEL_xxLEVEL1a_LXT971 0x000e
247 #define MII_STR_xxLEVEL1a_LXT971 "LXT971 10/100 media interface"
249 /* National Semiconductor PHYs */
250 #define MII_MODEL_NATSEMI_DP83840 0x0000
251 #define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface"
252 #define MII_MODEL_NATSEMI_DP83843 0x0001
253 #define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface"
254 #define MII_MODEL_NATSEMI_DP83891 0x0005
255 #define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 media interface"
256 #define MII_MODEL_NATSEMI_DP83861 0x0006
257 #define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 media interface"
259 /* Quality Semiconductor PHYs */
260 #define MII_MODEL_QUALSEMI_QS6612 0x0000
261 #define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface"
263 /* RealTek Semiconductor PHYs */
264 #define MII_MODEL_REALTEK_RTL8201L 0x0020
265 #define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 media interface"
266 #define MII_MODEL_xxREALTEK_RTL8169S 0x0011
267 #define MII_STR_xxREALTEK_RTL8169S "8211B/RTL8169S/8110S media interface"
268 #define MII_MODEL_REALTEK2_RTL8169S 0x0011
269 #define MII_STR_REALTEK2_RTL8169S "RTL8169S/8110S media interface"
272 #define MII_MODEL_xxSEEQ_80220 0x0003
273 #define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface"
274 #define MII_MODEL_xxSEEQ_84220 0x0004
275 #define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface"
277 /* Silicon Integrated Systems PHYs */
278 #define MII_MODEL_xxSIS_900 0x0000
279 #define MII_STR_xxSIS_900 "SiS 900 10/100 media interface"
282 #define MII_MODEL_TDK_78Q2120 0x0014
283 #define MII_STR_TDK_78Q2120 "TDK 78Q2120 media interface"
285 /* Texas Instruments PHYs */
286 #define MII_MODEL_xxTI_TLAN10T 0x0001
287 #define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface"
288 #define MII_MODEL_xxTI_100VGPMI 0x0002
289 #define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
291 /* XaQti Corp. PHYs. */
292 #define MII_MODEL_xxXAQTI_XMACII 0x0000
293 #define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
295 /* Marvell Semiconductor PHYs */
296 #define MII_MODEL_MARVELL_E1000 0x0000
297 #define MII_STR_MARVELL_E1000 "Marvell Semiconductor 88E1000* gigabit PHY"
298 #define MII_MODEL_MARVELL_E1011 0x0002
299 #define MII_STR_MARVELL_E1011 "Marvell Semiconductor 88E1011 Gigabit PHY"
300 #define MII_MODEL_MARVELL_E1000_3 0x0003
301 #define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
302 #define MII_MODEL_MARVELL_E1000_4 0x0004
303 #define MII_STR_MARVELL_E1000_4 "Marvell 88E1000S Gigabit PHY"
304 #define MII_MODEL_MARVELL_E1000_5 0x0005
305 #define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
306 #define MII_MODEL_MARVELL_E1000_6 0x0006
307 #define MII_STR_MARVELL_E1000_6 "Marvell 88E1000 Gigabit PHY"
308 #define MII_MODEL_MARVELL_E3082 0x0008
309 #define MII_STR_MARVELL_E3082 "Marvell 88E3082 10/100 PHY"
310 #define MII_MODEL_MARVELL_E1112 0x0009
311 #define MII_STR_MARVELL_E1112 "Marvell 88E1112 Gigabit PHY"
312 #define MII_MODEL_MARVELL_E1149 0x000b
313 #define MII_STR_MARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
314 #define MII_MODEL_MARVELL_E1111 0x000c
315 #define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
316 #define MII_MODEL_MARVELL_E1116 0x0021
317 #define MII_STR_MARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
318 #define MII_MODEL_MARVELL_E1118 0x0022
319 #define MII_STR_MARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
320 #define MII_MODEL_xxMARVELL_E1000_2 0x0002
321 #define MII_STR_xxMARVELL_E1000_2 "Marvell 88E1000 Gigabit PHY"
322 #define MII_MODEL_xxMARVELL_E1000_3 0x0003
323 #define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
324 #define MII_MODEL_xxMARVELL_E1000_5 0x0005
325 #define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
326 #define MII_MODEL_xxMARVELL_E1111 0x000c
327 #define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
329 /* IC Plus Corp. PHYs */
330 #define MII_MODEL_ICPLUS_IP101 0x0005
331 #define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY"
332 #define MII_MODEL_ICPLUS_IP1000A 0x0008
333 #define MII_STR_ICPLUS_IP1000A "IC Plus 10/100/1000 media interface"
335 /* Vitesse Semiconductor PHYs */
336 #define MII_MODEL_VITESSE_VSC8601 0x0002
337 #define MII_STR_VITESSE_VSC8601 "VSC8601 10/100/1000TX PHY"