2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $
27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.8 2007/06/17 16:34:43 dillon Exp $
32 #include <sys/param.h>
34 #include <sys/bus_dma.h>
35 #include <sys/bus_resource.h>
36 #include <sys/callout.h>
37 #include <sys/endian.h>
38 #include <sys/libkern.h>
39 #include <sys/lock.h> /* for {get,rel}_mplock() */
40 #include <sys/malloc.h>
42 #include <sys/queue.h>
44 #include <sys/spinlock.h>
45 #include <sys/spinlock2.h>
46 #include <sys/systm.h>
47 #include <sys/taskqueue.h>
49 #include <machine/bus_dma.h>
51 #include <bus/pci/pcireg.h>
52 #include <bus/pci/pcivar.h>
58 /* local prototypes */
60 static int ata_generic_chipinit(device_t dev);
61 static void ata_generic_intr(void *data);
62 static void ata_generic_setmode(device_t dev, int mode);
63 static void ata_sata_phy_check_events(device_t dev);
64 static void ata_sata_phy_event(void *context, int dummy);
65 static int ata_sata_phy_reset(device_t dev);
66 static int ata_sata_connect(struct ata_channel *ch);
67 static void ata_sata_setmode(device_t dev, int mode);
68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
69 static int ata_ahci_chipinit(device_t dev);
70 static int ata_ahci_allocate(device_t dev);
71 static int ata_ahci_status(device_t dev);
72 static int ata_ahci_begin_transaction(struct ata_request *request);
73 static int ata_ahci_end_transaction(struct ata_request *request);
74 static void ata_ahci_reset(device_t dev);
75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
76 static void ata_ahci_dmainit(device_t dev);
77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
78 static int ata_acard_chipinit(device_t dev);
79 static int ata_acard_allocate(device_t dev);
80 static int ata_acard_status(device_t dev);
81 static void ata_acard_850_setmode(device_t dev, int mode);
82 static void ata_acard_86X_setmode(device_t dev, int mode);
83 static int ata_ali_chipinit(device_t dev);
84 static int ata_ali_allocate(device_t dev);
85 static int ata_ali_sata_allocate(device_t dev);
86 static void ata_ali_reset(device_t dev);
87 static void ata_ali_setmode(device_t dev, int mode);
88 static int ata_amd_chipinit(device_t dev);
89 static int ata_ati_chipinit(device_t dev);
90 static void ata_ati_setmode(device_t dev, int mode);
91 static int ata_cyrix_chipinit(device_t dev);
92 static void ata_cyrix_setmode(device_t dev, int mode);
93 static int ata_cypress_chipinit(device_t dev);
94 static void ata_cypress_setmode(device_t dev, int mode);
95 static int ata_highpoint_chipinit(device_t dev);
96 static int ata_highpoint_allocate(device_t dev);
97 static void ata_highpoint_setmode(device_t dev, int mode);
98 static int ata_highpoint_check_80pin(device_t dev, int mode);
99 static int ata_intel_chipinit(device_t dev);
100 static int ata_intel_allocate(device_t dev);
101 static void ata_intel_reset(device_t dev);
102 static void ata_intel_old_setmode(device_t dev, int mode);
103 static void ata_intel_new_setmode(device_t dev, int mode);
104 static int ata_intel_31244_allocate(device_t dev);
105 static int ata_intel_31244_status(device_t dev);
106 static int ata_intel_31244_command(struct ata_request *request);
107 static void ata_intel_31244_reset(device_t dev);
108 static int ata_ite_chipinit(device_t dev);
109 static void ata_ite_setmode(device_t dev, int mode);
110 static int ata_jmicron_chipinit(device_t dev);
111 static int ata_jmicron_allocate(device_t dev);
112 static void ata_jmicron_reset(device_t dev);
113 static void ata_jmicron_dmainit(device_t dev);
114 static void ata_jmicron_setmode(device_t dev, int mode);
115 static int ata_marvell_pata_chipinit(device_t dev);
116 static int ata_marvell_pata_allocate(device_t dev);
117 static void ata_marvell_pata_setmode(device_t dev, int mode);
118 static int ata_marvell_edma_chipinit(device_t dev);
119 static int ata_marvell_edma_allocate(device_t dev);
120 static int ata_marvell_edma_status(device_t dev);
121 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
122 static int ata_marvell_edma_end_transaction(struct ata_request *request);
123 static void ata_marvell_edma_reset(device_t dev);
124 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
125 static void ata_marvell_edma_dmainit(device_t dev);
126 static int ata_national_chipinit(device_t dev);
127 static void ata_national_setmode(device_t dev, int mode);
128 static int ata_netcell_chipinit(device_t dev);
129 static int ata_netcell_allocate(device_t dev);
130 static int ata_nvidia_chipinit(device_t dev);
131 static int ata_nvidia_allocate(device_t dev);
132 static int ata_nvidia_status(device_t dev);
133 static void ata_nvidia_reset(device_t dev);
134 static int ata_promise_chipinit(device_t dev);
135 static int ata_promise_allocate(device_t dev);
136 static int ata_promise_status(device_t dev);
137 static int ata_promise_dmastart(device_t dev);
138 static int ata_promise_dmastop(device_t dev);
139 static void ata_promise_dmareset(device_t dev);
140 static void ata_promise_dmainit(device_t dev);
141 static void ata_promise_setmode(device_t dev, int mode);
142 static int ata_promise_tx2_allocate(device_t dev);
143 static int ata_promise_tx2_status(device_t dev);
144 static int ata_promise_mio_allocate(device_t dev);
145 static void ata_promise_mio_intr(void *data);
146 static int ata_promise_mio_status(device_t dev);
147 static int ata_promise_mio_command(struct ata_request *request);
148 static void ata_promise_mio_reset(device_t dev);
149 static void ata_promise_mio_dmainit(device_t dev);
150 static void ata_promise_mio_setmode(device_t dev, int mode);
151 static void ata_promise_sx4_intr(void *data);
152 static int ata_promise_sx4_command(struct ata_request *request);
153 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
154 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
155 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
156 static int ata_serverworks_chipinit(device_t dev);
157 static int ata_serverworks_allocate(device_t dev);
158 static void ata_serverworks_setmode(device_t dev, int mode);
159 static int ata_sii_chipinit(device_t dev);
160 static int ata_cmd_allocate(device_t dev);
161 static int ata_cmd_status(device_t dev);
162 static void ata_cmd_setmode(device_t dev, int mode);
163 static int ata_sii_allocate(device_t dev);
164 static int ata_sii_status(device_t dev);
165 static void ata_sii_reset(device_t dev);
166 static void ata_sii_setmode(device_t dev, int mode);
167 static int ata_siiprb_allocate(device_t dev);
168 static int ata_siiprb_status(device_t dev);
169 static int ata_siiprb_begin_transaction(struct ata_request *request);
170 static int ata_siiprb_end_transaction(struct ata_request *request);
171 static void ata_siiprb_reset(device_t dev);
172 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
173 static void ata_siiprb_dmainit(device_t dev);
174 static int ata_sis_chipinit(device_t dev);
175 static int ata_sis_allocate(device_t dev);
176 static void ata_sis_reset(device_t dev);
177 static void ata_sis_setmode(device_t dev, int mode);
178 static int ata_via_chipinit(device_t dev);
179 static int ata_via_allocate(device_t dev);
180 static void ata_via_reset(device_t dev);
181 static void ata_via_setmode(device_t dev, int mode);
182 static void ata_via_southbridge_fixup(device_t dev);
183 static void ata_via_family_setmode(device_t dev, int mode);
184 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
185 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
186 static int ata_setup_interrupt(device_t dev);
187 static int ata_serialize(device_t dev, int flags);
188 static void ata_print_cable(device_t dev, u_int8_t *who);
189 static int ata_atapi(device_t dev);
190 static int ata_check_80pin(device_t dev, int mode);
191 static int ata_mode2idx(int mode);
195 * generic ATA support functions
198 ata_generic_ident(device_t dev)
200 struct ata_pci_controller *ctlr = device_get_softc(dev);
202 device_set_desc(dev, "GENERIC ATA controller");
203 ctlr->chipinit = ata_generic_chipinit;
208 ata_generic_chipinit(device_t dev)
210 struct ata_pci_controller *ctlr = device_get_softc(dev);
212 if (ata_setup_interrupt(dev))
214 ctlr->setmode = ata_generic_setmode;
219 ata_generic_intr(void *data)
221 struct ata_pci_controller *ctlr = data;
222 struct ata_channel *ch;
225 for (unit = 0; unit < ctlr->channels; unit++) {
226 if ((ch = ctlr->interrupt[unit].argument))
227 ctlr->interrupt[unit].function(ch);
232 ata_generic_setmode(device_t dev, int mode)
234 struct ata_device *atadev = device_get_softc(dev);
236 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
237 mode = ata_check_80pin(dev, mode);
238 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
244 * SATA support functions
247 ata_sata_phy_check_events(device_t dev)
249 struct ata_channel *ch = device_get_softc(dev);
250 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
252 /* clear error bits/interrupt */
253 ATA_IDX_OUTL(ch, ATA_SERROR, error);
255 /* do we have any events flagged ? */
257 struct ata_connect_task *tp;
258 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
260 /* if we have a connection event deal with it */
261 if ((error & ATA_SE_PHY_CHANGED) &&
262 (tp = (struct ata_connect_task *)
263 kmalloc(sizeof(struct ata_connect_task),
264 M_ATA, M_INTWAIT | M_ZERO))) {
266 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
267 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
269 device_printf(ch->dev, "CONNECT requested\n");
270 tp->action = ATA_C_ATTACH;
274 device_printf(ch->dev, "DISCONNECT requested\n");
275 tp->action = ATA_C_DETACH;
278 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
279 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
285 ata_sata_phy_event(void *context, int dummy)
287 struct ata_connect_task *tp = (struct ata_connect_task *)context;
288 struct ata_channel *ch = device_get_softc(tp->dev);
293 if (tp->action == ATA_C_ATTACH) {
295 device_printf(tp->dev, "CONNECTED\n");
297 ata_identify(tp->dev);
299 if (tp->action == ATA_C_DETACH) {
300 if (!device_get_children(tp->dev, &children, &nchildren)) {
301 for (i = 0; i < nchildren; i++)
303 device_delete_child(tp->dev, children[i]);
304 kfree(children, M_TEMP);
306 spin_lock_wr(&ch->state_mtx);
307 ch->state = ATA_IDLE;
308 spin_unlock_wr(&ch->state_mtx);
310 device_printf(tp->dev, "DISCONNECTED\n");
317 ata_sata_phy_reset(device_t dev)
319 struct ata_channel *ch = device_get_softc(dev);
322 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
323 return ata_sata_connect(ch);
325 for (retry = 0; retry < 10; retry++) {
326 for (loop = 0; loop < 10; loop++) {
327 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
329 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
330 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
334 for (loop = 0; loop < 10; loop++) {
335 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
336 ATA_SC_IPM_DIS_PARTIAL |
337 ATA_SC_IPM_DIS_SLUMBER);
339 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
340 return ata_sata_connect(ch);
347 ata_sata_connect(struct ata_channel *ch)
352 /* wait up to 1 second for "connect well" */
353 for (timeout = 0; timeout < 100 ; timeout++) {
354 status = ATA_IDX_INL(ch, ATA_SSTATUS);
355 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
356 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
360 if (timeout >= 100) {
362 device_printf(ch->dev, "SATA connect status=%08x\n", status);
367 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
369 /* clear SATA error register */
370 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
376 ata_sata_setmode(device_t dev, int mode)
378 struct ata_device *atadev = device_get_softc(dev);
381 * if we detect that the device isn't a real SATA device we limit
382 * the transfer mode to UDMA5/ATA100.
383 * this works around the problems some devices has with the
384 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
386 if (atadev->param.satacapabilities != 0x0000 &&
387 atadev->param.satacapabilities != 0xffff) {
388 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
390 /* on some drives we need to set the transfer mode */
391 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
392 ata_limit_mode(dev, mode, ATA_UDMA6));
394 /* query SATA STATUS for the speed */
395 if (ch->r_io[ATA_SSTATUS].res &&
396 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
397 ATA_SS_CONWELL_GEN2))
398 atadev->mode = ATA_SA300;
400 atadev->mode = ATA_SA150;
403 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
404 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
410 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
412 struct ata_device *atadev = device_get_softc(request->dev);
414 if (request->flags & ATA_R_ATAPI) {
415 fis[0] = 0x27; /* host to device */
416 fis[1] = 0x80; /* command FIS (note PM goes here) */
417 fis[2] = ATA_PACKET_CMD;
418 if (request->flags & ATA_R_DMA)
421 fis[5] = request->transfersize;
422 fis[6] = request->transfersize >> 8;
424 fis[7] = ATA_D_LBA | atadev->unit;
425 fis[15] = ATA_A_4BIT;
429 ata_modify_if_48bit(request);
430 fis[0] = 0x27; /* host to device */
431 fis[1] = 0x80; /* command FIS (note PM goes here) */
432 fis[2] = request->u.ata.command;
433 fis[3] = request->u.ata.feature;
434 fis[4] = request->u.ata.lba;
435 fis[5] = request->u.ata.lba >> 8;
436 fis[6] = request->u.ata.lba >> 16;
437 fis[7] = ATA_D_LBA | atadev->unit;
438 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
439 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
440 fis[8] = request->u.ata.lba >> 24;
441 fis[9] = request->u.ata.lba >> 32;
442 fis[10] = request->u.ata.lba >> 40;
443 fis[11] = request->u.ata.feature >> 8;
444 fis[12] = request->u.ata.count;
445 fis[13] = request->u.ata.count >> 8;
446 fis[15] = ATA_A_4BIT;
453 * AHCI v1.x compliant SATA chipset support functions
456 ata_ahci_chipinit(device_t dev)
458 struct ata_pci_controller *ctlr = device_get_softc(dev);
462 /* reset AHCI controller */
463 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
464 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR);
466 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
467 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
468 device_printf(dev, "AHCI controller reset failure\n");
472 /* enable AHCI mode */
473 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
474 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE);
476 /* get the number of HW channels */
478 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
479 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
481 /* disable interrupt sources and clear interrupts */
482 for (unit = 0; unit < ctlr->channels; unit++) {
483 int offset = unit << 7;
484 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
485 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1);
487 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
489 /* enable AHCI interrupts */
490 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
491 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
493 ctlr->reset = ata_ahci_reset;
494 ctlr->dmainit = ata_ahci_dmainit;
495 ctlr->allocate = ata_ahci_allocate;
496 ctlr->setmode = ata_sata_setmode;
498 /* enable PCI interrupt */
499 pci_write_config(dev, PCIR_COMMAND,
500 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
502 /* announce we support the HW */
503 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
505 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
506 (version >> 24) & 0xff, (version >> 16) & 0xff,
507 (version >> 8) & 0xff, version & 0xff,
508 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
513 ata_ahci_allocate(device_t dev)
515 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
516 struct ata_channel *ch = device_get_softc(dev);
518 int offset = ch->unit << 7;
520 /* set the SATA resources */
521 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
522 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
523 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
524 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
525 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
526 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
527 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
528 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
530 ch->hw.status = ata_ahci_status;
531 ch->hw.begin_transaction = ata_ahci_begin_transaction;
532 ch->hw.end_transaction = ata_ahci_end_transaction;
533 ch->hw.command = NULL; /* not used here */
535 /* setup work areas */
536 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
537 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
538 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
540 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
541 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
542 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
544 /* enable wanted port interrupts */
545 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
546 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
547 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
548 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
549 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
550 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
552 /* start operations on this channel */
553 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
554 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
555 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
560 ata_ahci_status(device_t dev)
562 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
563 struct ata_channel *ch = device_get_softc(dev);
564 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
565 int offset = ch->unit << 7;
568 if (action & (1 << ch->unit)) {
569 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
571 /* clear interrupt(s) */
572 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
573 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
575 /* do we have any PHY events ? */
576 ata_sata_phy_check_events(dev);
578 /* do we have any device action ? */
579 return (!(ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset) & (1 << tag)));
584 /* must be called with ATA channel locked and state_mtx held */
586 ata_ahci_begin_transaction(struct ata_request *request)
588 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
589 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
590 struct ata_ahci_cmd_tab *ctp;
591 struct ata_ahci_cmd_list *clp;
592 int offset = ch->unit << 7;
593 int tag = 0, entries = 0;
596 /* get a piece of the workspace for this request */
597 ctp = (struct ata_ahci_cmd_tab *)
598 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
600 /* setup the FIS for this request */
601 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
602 device_printf(request->dev, "setting up SATA FIS failed\n");
603 request->result = EIO;
604 return ATA_OP_FINISHED;
607 /* if request moves data setup and load SG list */
608 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
609 if (ch->dma->load(ch->dev, request->data, request->bytecount,
610 request->flags & ATA_R_READ,
611 ctp->prd_tab, &entries)) {
612 device_printf(request->dev, "setting up DMA failed\n");
613 request->result = EIO;
614 return ATA_OP_FINISHED;
618 /* setup the command list entry */
619 clp = (struct ata_ahci_cmd_list *)
620 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
622 clp->prd_length = entries;
623 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
624 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
625 (fis_size / sizeof(u_int32_t));
627 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
628 (ATA_AHCI_CT_SIZE * tag));
630 /* clear eventual ACTIVE bit */
631 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
633 /* set command type bit */
634 if (request->flags & ATA_R_ATAPI)
635 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
636 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
637 ATA_AHCI_P_CMD_ATAPI);
639 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
640 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
641 ~ATA_AHCI_P_CMD_ATAPI);
643 /* issue the command */
644 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
646 /* start the timeout */
647 callout_reset(&request->callout, request->timeout * hz,
648 (timeout_t*)ata_timeout, request);
649 return ATA_OP_CONTINUES;
652 /* must be called with ATA channel locked and state_mtx held */
654 ata_ahci_end_transaction(struct ata_request *request)
656 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
657 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
658 struct ata_ahci_cmd_list *clp;
660 int offset = ch->unit << 7;
663 /* kill the timeout */
664 callout_stop(&request->callout);
667 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
668 request->status = tf_data;
670 /* if error status get details */
671 if (request->status & ATA_S_ERROR)
672 request->error = tf_data >> 8;
674 /* record how much data we actually moved */
675 clp = (struct ata_ahci_cmd_list *)
676 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
677 request->donecount = clp->bytecount;
679 /* release SG list etc */
680 ch->dma->unload(ch->dev);
682 return ATA_OP_FINISHED;
686 ata_ahci_reset(device_t dev)
688 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
689 struct ata_channel *ch = device_get_softc(dev);
691 int offset = ch->unit << 7;
694 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
695 device_printf(dev, "port not implemented\n");
700 /* kill off all activity on this channel */
701 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
702 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
703 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
705 /* XXX SOS this is not entirely wrong */
710 device_printf(dev, "stopping AHCI engine failed\n");
713 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
715 /* issue Command List Override if supported */
716 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
717 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
718 cmd |= ATA_AHCI_P_CMD_CLO;
719 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
724 device_printf(dev, "executing CLO failed\n");
727 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
731 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SUD);
733 /* enable interface */
734 if (ata_sata_phy_reset(dev)) {
735 switch (ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset)) {
737 ch->devices = ATA_ATAPI_MASTER;
738 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n");
742 ch->devices = ATA_PORTMULTIPLIER;
743 device_printf(ch->dev, "Portmultipliers not supported yet\n");
747 ch->devices = ATA_ATA_MASTER;
752 /* clear any interrupts pending on this channel */
753 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
754 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
756 /* start operations on this channel */
757 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
758 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
759 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
763 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
765 struct ata_dmasetprd_args *args = xsc;
766 struct ata_ahci_dma_prd *prd = args->dmatab;
769 if (!(args->error = error)) {
770 for (i = 0; i < nsegs; i++) {
771 prd[i].dba = htole64(segs[i].ds_addr);
772 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
779 ata_ahci_dmainit(device_t dev)
781 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
782 struct ata_channel *ch = device_get_softc(dev);
786 /* note start and stop are not used here */
787 ch->dma->setprd = ata_ahci_dmasetprd;
788 ch->dma->max_iosize = 8192 * DEV_BSIZE;
789 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
790 ch->dma->max_address = BUS_SPACE_MAXADDR;
795 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
797 bzero(ctp->cfis, 64);
798 if (request->flags & ATA_R_ATAPI) {
799 bzero(ctp->acmd, 32);
800 bcopy(request->u.atapi.ccb, ctp->acmd, 12);
802 return ata_request2fis_h2d(request, &ctp->cfis[0]);
807 * Acard chipset support functions
810 ata_acard_ident(device_t dev)
812 struct ata_pci_controller *ctlr = device_get_softc(dev);
813 struct ata_chip_id *idx;
814 static struct ata_chip_id ids[] =
815 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
816 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
817 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
818 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
819 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
820 { 0, 0, 0, 0, 0, 0}};
823 if (!(idx = ata_match_chip(dev, ids)))
826 ksprintf(buffer, "Acard %s %s controller",
827 idx->text, ata_mode2str(idx->max_dma));
828 device_set_desc_copy(dev, buffer);
830 ctlr->chipinit = ata_acard_chipinit;
835 ata_acard_chipinit(device_t dev)
837 struct ata_pci_controller *ctlr = device_get_softc(dev);
839 if (ata_setup_interrupt(dev))
842 ctlr->allocate = ata_acard_allocate;
843 if (ctlr->chip->cfg1 == ATPOLD) {
844 ctlr->setmode = ata_acard_850_setmode;
845 ctlr->locking = ata_serialize;
848 ctlr->setmode = ata_acard_86X_setmode;
853 ata_acard_allocate(device_t dev)
855 struct ata_channel *ch = device_get_softc(dev);
857 /* setup the usual register normal pci style */
858 if (ata_pci_allocate(dev))
861 ch->hw.status = ata_acard_status;
866 ata_acard_status(device_t dev)
868 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
869 struct ata_channel *ch = device_get_softc(dev);
871 if (ctlr->chip->cfg1 == ATPOLD &&
872 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
874 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
875 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
877 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
878 ATA_BMSTAT_INTERRUPT)
880 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
882 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
883 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
886 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
888 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
895 ata_acard_850_setmode(device_t dev, int mode)
897 device_t gparent = GRANDPARENT(dev);
898 struct ata_pci_controller *ctlr = device_get_softc(gparent);
899 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
900 struct ata_device *atadev = device_get_softc(dev);
901 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
904 mode = ata_limit_mode(dev, mode,
905 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
907 /* XXX SOS missing WDMA0+1 + PIO modes */
908 if (mode >= ATA_WDMA2) {
909 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
911 device_printf(dev, "%ssetting %s on %s chip\n",
912 (error) ? "FAILURE " : "",
913 ata_mode2str(mode), ctlr->chip->text);
915 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
917 reg54 &= ~(0x03 << (devno << 1));
918 if (mode >= ATA_UDMA0)
919 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
920 pci_write_config(gparent, 0x54, reg54, 1);
921 pci_write_config(gparent, 0x4a, 0xa6, 1);
922 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
927 /* we could set PIO mode timings, but we assume the BIOS did that */
931 ata_acard_86X_setmode(device_t dev, int mode)
933 device_t gparent = GRANDPARENT(dev);
934 struct ata_pci_controller *ctlr = device_get_softc(gparent);
935 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
936 struct ata_device *atadev = device_get_softc(dev);
937 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
941 mode = ata_limit_mode(dev, mode,
942 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
944 mode = ata_check_80pin(dev, mode);
946 /* XXX SOS missing WDMA0+1 + PIO modes */
947 if (mode >= ATA_WDMA2) {
948 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
950 device_printf(dev, "%ssetting %s on %s chip\n",
951 (error) ? "FAILURE " : "",
952 ata_mode2str(mode), ctlr->chip->text);
954 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
956 reg44 &= ~(0x000f << (devno << 2));
957 if (mode >= ATA_UDMA0)
958 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
959 pci_write_config(gparent, 0x44, reg44, 2);
960 pci_write_config(gparent, 0x4a, 0xa6, 1);
961 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
966 /* we could set PIO mode timings, but we assume the BIOS did that */
971 * Acer Labs Inc (ALI) chipset support functions
974 ata_ali_ident(device_t dev)
976 struct ata_pci_controller *ctlr = device_get_softc(dev);
977 struct ata_chip_id *idx;
978 static struct ata_chip_id ids[] =
979 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
980 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
981 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
982 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
983 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
984 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
985 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
986 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
987 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
988 { 0, 0, 0, 0, 0, 0}};
991 if (!(idx = ata_match_chip(dev, ids)))
994 ksprintf(buffer, "AcerLabs %s %s controller",
995 idx->text, ata_mode2str(idx->max_dma));
996 device_set_desc_copy(dev, buffer);
998 ctlr->chipinit = ata_ali_chipinit;
1003 ata_ali_chipinit(device_t dev)
1005 struct ata_pci_controller *ctlr = device_get_softc(dev);
1007 if (ata_setup_interrupt(dev))
1010 switch (ctlr->chip->cfg2) {
1012 ctlr->channels = ctlr->chip->cfg1;
1013 ctlr->allocate = ata_ali_sata_allocate;
1014 ctlr->setmode = ata_sata_setmode;
1016 /* if we have a memory resource we can likely do AHCI */
1017 ctlr->r_type2 = SYS_RES_MEMORY;
1018 ctlr->r_rid2 = PCIR_BAR(5);
1019 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1020 &ctlr->r_rid2, RF_ACTIVE)))
1021 return ata_ahci_chipinit(dev);
1023 /* enable PCI interrupt */
1024 pci_write_config(dev, PCIR_COMMAND,
1025 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1029 /* use device interrupt as byte count end */
1030 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1032 /* enable cable detection and UDMA support on newer chips */
1033 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1035 /* enable ATAPI UDMA mode */
1036 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1038 /* only chips with revision > 0xc4 can do 48bit DMA */
1039 if (ctlr->chip->chiprev <= 0xc4)
1041 "using PIO transfers above 137GB as workaround for "
1042 "48bit DMA access bug, expect reduced performance\n");
1043 ctlr->allocate = ata_ali_allocate;
1044 ctlr->reset = ata_ali_reset;
1045 ctlr->setmode = ata_ali_setmode;
1049 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1050 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1051 ctlr->setmode = ata_ali_setmode;
1058 ata_ali_allocate(device_t dev)
1060 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1061 struct ata_channel *ch = device_get_softc(dev);
1063 /* setup the usual register normal pci style */
1064 if (ata_pci_allocate(dev))
1067 /* older chips can't do 48bit DMA transfers */
1068 if (ctlr->chip->chiprev <= 0xc4)
1069 ch->flags |= ATA_NO_48BIT_DMA;
1075 ata_ali_sata_allocate(device_t dev)
1077 device_t parent = device_get_parent(dev);
1078 struct ata_pci_controller *ctlr = device_get_softc(parent);
1079 struct ata_channel *ch = device_get_softc(dev);
1080 struct resource *io = NULL, *ctlio = NULL;
1081 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1084 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1085 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1089 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1090 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1092 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1096 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1097 ch->r_io[i].res = io;
1098 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1100 ch->r_io[ATA_CONTROL].res = ctlio;
1101 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1102 ch->r_io[ATA_IDX_ADDR].res = io;
1103 ata_default_registers(dev);
1105 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1106 ch->r_io[i].res = ctlr->r_res1;
1107 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1110 ch->flags |= ATA_NO_SLAVE;
1112 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1118 ata_ali_reset(device_t dev)
1120 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1121 struct ata_channel *ch = device_get_softc(dev);
1125 ata_generic_reset(dev);
1128 * workaround for datacorruption bug found on at least SUN Blade-100
1129 * find the ISA function on the southbridge and disable then enable
1130 * the ATA channel tristate buffer
1132 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1133 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1134 for (i = 0; i < nchildren; i++) {
1135 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1136 pci_write_config(children[i], 0x58,
1137 pci_read_config(children[i], 0x58, 1) &
1138 ~(0x04 << ch->unit), 1);
1139 pci_write_config(children[i], 0x58,
1140 pci_read_config(children[i], 0x58, 1) |
1141 (0x04 << ch->unit), 1);
1145 kfree(children, M_TEMP);
1151 ata_ali_setmode(device_t dev, int mode)
1153 device_t gparent = GRANDPARENT(dev);
1154 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1155 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1156 struct ata_device *atadev = device_get_softc(dev);
1157 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1160 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1162 if (ctlr->chip->cfg2 & ALINEW) {
1163 if (mode > ATA_UDMA2 &&
1164 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1165 ata_print_cable(dev, "controller");
1170 mode = ata_check_80pin(dev, mode);
1172 if (ctlr->chip->cfg2 & ALIOLD) {
1173 /* doesn't support ATAPI DMA on write */
1174 ch->flags |= ATA_ATAPI_DMA_RO;
1175 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1176 /* doesn't support ATAPI DMA on two ATAPI devices */
1177 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1178 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1182 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1185 device_printf(dev, "%ssetting %s on %s chip\n",
1186 (error) ? "FAILURE " : "",
1187 ata_mode2str(mode), ctlr->chip->text);
1189 if (mode >= ATA_UDMA0) {
1190 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1191 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1193 word54 &= ~(0x000f000f << (devno << 2));
1194 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1195 pci_write_config(gparent, 0x54, word54, 4);
1196 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1200 u_int32_t piotimings[] =
1201 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1202 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1204 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1205 ~(0x0008000f << (devno << 2)), 4);
1206 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1207 piotimings[ata_mode2idx(mode)], 4);
1209 atadev->mode = mode;
1215 * American Micro Devices (AMD) chipset support functions
1218 ata_amd_ident(device_t dev)
1220 struct ata_pci_controller *ctlr = device_get_softc(dev);
1221 struct ata_chip_id *idx;
1222 static struct ata_chip_id ids[] =
1223 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1224 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1225 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1226 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1227 { 0, 0, 0, 0, 0, 0}};
1230 if (!(idx = ata_match_chip(dev, ids)))
1233 ksprintf(buffer, "AMD %s %s controller",
1234 idx->text, ata_mode2str(idx->max_dma));
1235 device_set_desc_copy(dev, buffer);
1237 ctlr->chipinit = ata_amd_chipinit;
1242 ata_amd_chipinit(device_t dev)
1244 struct ata_pci_controller *ctlr = device_get_softc(dev);
1246 if (ata_setup_interrupt(dev))
1249 /* disable/set prefetch, postwrite */
1250 if (ctlr->chip->cfg2 & AMDBUG)
1251 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1253 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1255 ctlr->setmode = ata_via_family_setmode;
1261 * ATI chipset support functions
1264 ata_ati_ident(device_t dev)
1266 struct ata_pci_controller *ctlr = device_get_softc(dev);
1267 struct ata_chip_id *idx;
1268 static struct ata_chip_id ids[] =
1269 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1270 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1271 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1272 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" },
1273 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1274 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1275 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1276 { ATA_ATI_SB600_S1, 0x00, SIIMEMIO, 0, ATA_SA300, "SB600" },
1277 { ATA_ATI_SB600_S2, 0x00, SIIMEMIO, 0, ATA_SA300, "SB600" },
1278 { 0, 0, 0, 0, 0, 0}};
1281 if (!(idx = ata_match_chip(dev, ids)))
1284 ksprintf(buffer, "ATI %s %s controller",
1285 idx->text, ata_mode2str(idx->max_dma));
1286 device_set_desc_copy(dev, buffer);
1289 /* the ATI SATA controller is actually a SiI 3112 controller*/
1290 if (ctlr->chip->cfg1 & SIIMEMIO)
1291 ctlr->chipinit = ata_sii_chipinit;
1293 ctlr->chipinit = ata_ati_chipinit;
1298 ata_ati_chipinit(device_t dev)
1300 struct ata_pci_controller *ctlr = device_get_softc(dev);
1302 if (ata_setup_interrupt(dev))
1305 ctlr->setmode = ata_ati_setmode;
1310 ata_ati_setmode(device_t dev, int mode)
1312 device_t gparent = GRANDPARENT(dev);
1313 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1314 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1315 struct ata_device *atadev = device_get_softc(dev);
1316 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1317 int offset = (devno ^ 0x01) << 3;
1319 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1320 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1321 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1323 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1325 mode = ata_check_80pin(dev, mode);
1327 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1330 device_printf(dev, "%ssetting %s on %s chip\n",
1331 (error) ? "FAILURE " : "",
1332 ata_mode2str(mode), ctlr->chip->text);
1334 if (mode >= ATA_UDMA0) {
1335 pci_write_config(gparent, 0x56,
1336 (pci_read_config(gparent, 0x56, 2) &
1337 ~(0xf << (devno << 2))) |
1338 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1339 pci_write_config(gparent, 0x54,
1340 pci_read_config(gparent, 0x54, 1) |
1341 (0x01 << devno), 1);
1342 pci_write_config(gparent, 0x44,
1343 (pci_read_config(gparent, 0x44, 4) &
1344 ~(0xff << offset)) |
1345 (dmatimings[2] << offset), 4);
1347 else if (mode >= ATA_WDMA0) {
1348 pci_write_config(gparent, 0x54,
1349 pci_read_config(gparent, 0x54, 1) &
1350 ~(0x01 << devno), 1);
1351 pci_write_config(gparent, 0x44,
1352 (pci_read_config(gparent, 0x44, 4) &
1353 ~(0xff << offset)) |
1354 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1357 pci_write_config(gparent, 0x54,
1358 pci_read_config(gparent, 0x54, 1) &
1359 ~(0x01 << devno), 1);
1361 pci_write_config(gparent, 0x4a,
1362 (pci_read_config(gparent, 0x4a, 2) &
1363 ~(0xf << (devno << 2))) |
1364 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1365 pci_write_config(gparent, 0x40,
1366 (pci_read_config(gparent, 0x40, 4) &
1367 ~(0xff << offset)) |
1368 (piotimings[ata_mode2idx(mode)] << offset), 4);
1369 atadev->mode = mode;
1374 * Cyrix chipset support functions
1377 ata_cyrix_ident(device_t dev)
1379 struct ata_pci_controller *ctlr = device_get_softc(dev);
1381 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1382 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1383 ctlr->chipinit = ata_cyrix_chipinit;
1390 ata_cyrix_chipinit(device_t dev)
1392 struct ata_pci_controller *ctlr = device_get_softc(dev);
1394 if (ata_setup_interrupt(dev))
1398 ctlr->setmode = ata_cyrix_setmode;
1400 ctlr->setmode = ata_generic_setmode;
1405 ata_cyrix_setmode(device_t dev, int mode)
1407 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1408 struct ata_device *atadev = device_get_softc(dev);
1409 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1410 u_int32_t piotiming[] =
1411 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1412 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1413 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1416 ch->dma->alignment = 16;
1417 ch->dma->max_iosize = 126 * DEV_BSIZE;
1419 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1421 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1424 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1425 (error) ? "FAILURE " : "", ata_mode2str(mode));
1427 if (mode >= ATA_UDMA0) {
1428 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1429 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1431 else if (mode >= ATA_WDMA0) {
1432 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1433 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1436 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1437 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1439 atadev->mode = mode;
1445 * Cypress chipset support functions
1448 ata_cypress_ident(device_t dev)
1450 struct ata_pci_controller *ctlr = device_get_softc(dev);
1453 * the Cypress chip is a mess, it contains two ATA functions, but
1454 * both channels are visible on the first one.
1455 * simply ignore the second function for now, as the right
1456 * solution (ignoring the second channel on the first function)
1457 * doesn't work with the crappy ATA interrupt setup on the alpha.
1459 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1460 pci_get_function(dev) == 1 &&
1461 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1462 device_set_desc(dev, "Cypress 82C693 ATA controller");
1463 ctlr->chipinit = ata_cypress_chipinit;
1470 ata_cypress_chipinit(device_t dev)
1472 struct ata_pci_controller *ctlr = device_get_softc(dev);
1474 if (ata_setup_interrupt(dev))
1477 ctlr->setmode = ata_cypress_setmode;
1482 ata_cypress_setmode(device_t dev, int mode)
1484 device_t gparent = GRANDPARENT(dev);
1485 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1486 struct ata_device *atadev = device_get_softc(dev);
1489 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1491 /* XXX SOS missing WDMA0+1 + PIO modes */
1492 if (mode == ATA_WDMA2) {
1493 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1495 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1496 error ? "FAILURE " : "");
1498 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1499 atadev->mode = mode;
1503 /* we could set PIO mode timings, but we assume the BIOS did that */
1508 * HighPoint chipset support functions
1511 ata_highpoint_ident(device_t dev)
1513 struct ata_pci_controller *ctlr = device_get_softc(dev);
1514 struct ata_chip_id *idx;
1515 static struct ata_chip_id ids[] =
1516 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1517 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1518 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1519 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1520 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1521 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1522 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1523 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1524 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1525 { 0, 0, 0, 0, 0, 0}};
1528 if (!(idx = ata_match_chip(dev, ids)))
1531 strcpy(buffer, "HighPoint ");
1532 strcat(buffer, idx->text);
1533 if (idx->cfg1 == HPT374) {
1534 if (pci_get_function(dev) == 0)
1535 strcat(buffer, " (channel 0+1)");
1536 if (pci_get_function(dev) == 1)
1537 strcat(buffer, " (channel 2+3)");
1539 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1540 device_set_desc_copy(dev, buffer);
1542 ctlr->chipinit = ata_highpoint_chipinit;
1547 ata_highpoint_chipinit(device_t dev)
1549 struct ata_pci_controller *ctlr = device_get_softc(dev);
1551 if (ata_setup_interrupt(dev))
1554 if (ctlr->chip->cfg2 == HPTOLD) {
1555 /* disable interrupt prediction */
1556 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1559 /* disable interrupt prediction */
1560 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1561 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1563 /* enable interrupts */
1564 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1566 /* set clocks etc */
1567 if (ctlr->chip->cfg1 < HPT372)
1568 pci_write_config(dev, 0x5b, 0x22, 1);
1570 pci_write_config(dev, 0x5b,
1571 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1573 ctlr->allocate = ata_highpoint_allocate;
1574 ctlr->setmode = ata_highpoint_setmode;
1579 ata_highpoint_allocate(device_t dev)
1581 struct ata_channel *ch = device_get_softc(dev);
1583 /* setup the usual register normal pci style */
1584 if (ata_pci_allocate(dev))
1587 ch->flags |= ATA_ALWAYS_DMASTAT;
1592 ata_highpoint_setmode(device_t dev, int mode)
1594 device_t gparent = GRANDPARENT(dev);
1595 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1596 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1597 struct ata_device *atadev = device_get_softc(dev);
1598 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1600 u_int32_t timings33[][4] = {
1601 /* HPT366 HPT370 HPT372 HPT374 mode */
1602 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1603 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1604 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1605 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1606 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1607 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1608 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1609 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1610 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1611 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1612 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1613 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1614 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1615 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1616 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1619 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1621 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1622 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1624 mode = ata_highpoint_check_80pin(dev, mode);
1627 * most if not all HPT chips cant really handle that the device is
1628 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1629 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1631 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1632 ata_limit_mode(dev, mode, ATA_UDMA5));
1634 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1635 (error) ? "FAILURE " : "", ata_mode2str(mode));
1637 pci_write_config(gparent, 0x40 + (devno << 2),
1638 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1639 atadev->mode = mode;
1643 ata_highpoint_check_80pin(device_t dev, int mode)
1645 device_t gparent = GRANDPARENT(dev);
1646 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1647 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1648 u_int8_t reg, val, res;
1650 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1651 reg = ch->unit ? 0x57 : 0x53;
1652 val = pci_read_config(gparent, reg, 1);
1653 pci_write_config(gparent, reg, val | 0x80, 1);
1657 val = pci_read_config(gparent, reg, 1);
1658 pci_write_config(gparent, reg, val & 0xfe, 1);
1660 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1661 pci_write_config(gparent, reg, val, 1);
1663 if (mode > ATA_UDMA2 && res) {
1664 ata_print_cable(dev, "controller");
1672 * Intel chipset support functions
1675 ata_intel_ident(device_t dev)
1677 struct ata_pci_controller *ctlr = device_get_softc(dev);
1678 struct ata_chip_id *idx;
1679 static struct ata_chip_id ids[] =
1680 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1681 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1682 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1683 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1684 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1685 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1686 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1687 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1688 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1689 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1690 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1691 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1692 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1693 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1694 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1695 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1696 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1697 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1698 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1699 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1700 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1701 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1702 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1703 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1704 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1705 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1706 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1707 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1708 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1709 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1710 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1711 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1712 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1713 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1714 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1715 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1716 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1717 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1718 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1719 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1720 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1721 { ATA_I82801HBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1722 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1723 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1724 { 0, 0, 0, 0, 0, 0}};
1727 if (!(idx = ata_match_chip(dev, ids)))
1730 ksprintf(buffer, "Intel %s %s controller",
1731 idx->text, ata_mode2str(idx->max_dma));
1732 device_set_desc_copy(dev, buffer);
1734 ctlr->chipinit = ata_intel_chipinit;
1739 ata_intel_chipinit(device_t dev)
1741 struct ata_pci_controller *ctlr = device_get_softc(dev);
1743 if (ata_setup_interrupt(dev))
1746 /* good old PIIX needs special treatment (not implemented) */
1747 if (ctlr->chip->chipid == ATA_I82371FB) {
1748 ctlr->setmode = ata_intel_old_setmode;
1751 /* the intel 31244 needs special care if in DPA mode */
1752 else if (ctlr->chip->chipid == ATA_I31244) {
1753 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1754 ctlr->r_type2 = SYS_RES_MEMORY;
1755 ctlr->r_rid2 = PCIR_BAR(0);
1756 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1761 ctlr->allocate = ata_intel_31244_allocate;
1762 ctlr->reset = ata_intel_31244_reset;
1764 ctlr->setmode = ata_sata_setmode;
1767 /* non SATA intel chips goes here */
1768 else if (ctlr->chip->max_dma < ATA_SA150) {
1769 ctlr->allocate = ata_intel_allocate;
1770 ctlr->setmode = ata_intel_new_setmode;
1773 /* SATA parts can be either compat or AHCI */
1775 /* force all ports active "the legacy way" */
1776 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1778 ctlr->allocate = ata_intel_allocate;
1779 ctlr->reset = ata_intel_reset;
1782 * if we have AHCI capability and BAR(5) as a memory resource
1783 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode
1785 if ((ctlr->chip->cfg1 == AHCI) &&
1786 (pci_read_config(dev, 0x90, 1) & 0xc0)) {
1787 ctlr->r_type2 = SYS_RES_MEMORY;
1788 ctlr->r_rid2 = PCIR_BAR(5);
1789 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1792 return ata_ahci_chipinit(dev);
1794 ctlr->setmode = ata_sata_setmode;
1796 /* enable PCI interrupt */
1797 pci_write_config(dev, PCIR_COMMAND,
1798 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1804 ata_intel_allocate(device_t dev)
1806 struct ata_channel *ch = device_get_softc(dev);
1808 /* setup the usual register normal pci style */
1809 if (ata_pci_allocate(dev))
1812 ch->flags |= ATA_ALWAYS_DMASTAT;
1817 ata_intel_reset(device_t dev)
1819 device_t parent = device_get_parent(dev);
1820 struct ata_pci_controller *ctlr = device_get_softc(parent);
1821 struct ata_channel *ch = device_get_softc(dev);
1824 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1825 if (ctlr->chip->cfg1) {
1826 mask = (0x0005 << ch->unit);
1829 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1830 if (pci_read_config(parent, 0x90, 1) & 0x04)
1833 mask = (0x0001 << ch->unit);
1834 /* XXX SOS should be in intel_allocate if we grow it */
1835 ch->flags |= ATA_NO_SLAVE;
1838 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1840 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1842 /* wait up to 1 sec for "connect well" */
1843 for (timeout = 0; timeout < 100 ; timeout++) {
1844 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1845 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1849 ata_generic_reset(dev);
1853 ata_intel_old_setmode(device_t dev, int mode)
1859 ata_intel_new_setmode(device_t dev, int mode)
1861 device_t gparent = GRANDPARENT(dev);
1862 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1863 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1864 struct ata_device *atadev = device_get_softc(dev);
1865 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1866 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1867 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1868 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1869 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1870 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1871 u_int32_t mask40 = 0, new40 = 0;
1872 u_int8_t mask44 = 0, new44 = 0;
1874 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1875 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1876 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */
1877 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */
1879 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1881 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1882 ata_print_cable(dev, "controller");
1886 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1889 device_printf(dev, "%ssetting %s on %s chip\n",
1890 (error) ? "FAILURE " : "",
1891 ata_mode2str(mode), ctlr->chip->text);
1896 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary
1897 * drive 0, secondary drive 1)
1899 * 0 Disable Ultra DMA mode
1900 * 1 Enable Ultra DMA mode
1902 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary
1903 * drive 0, secondary drive 1).
1905 * 0001 UDMA mode 1, 3, 5
1906 * 0010 UDMA mode 2, 4, reserved
1908 * (top two bits for each drive reserved)
1912 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
1913 reg40, reg44, reg48 ,reg4a, reg54);
1915 reg48 &= ~(0x0001 << devno);
1916 reg4a &= ~(0x3 << (devno << 2));
1917 if (mode >= ATA_UDMA0) {
1918 reg48 |= 0x0001 << devno;
1919 if (mode > ATA_UDMA0)
1920 reg4a |= (1 + !(mode & 0x01)) << (devno << 2);
1922 pci_write_config(gparent, 0x48, reg48, 2);
1923 pci_write_config(gparent, 0x4a, reg4a, 2);
1929 * 19:18 Secondary ATA signal mode
1930 * 17:16 Primary ATA signal mode
1931 * 00 = Normal (enabled)
1932 * 01 = Tri-state (disabled)
1933 * 10 = Drive Low (disabled)
1936 * 15 Secondary drive 1 - Base Clock
1937 * 14 Secondary drive 0 - Base Clock
1938 * 13 Primary drive 1 - Base Clock
1939 * 12 Primary drive 0 - Base Clock
1940 * 0 = Select 33 MHz clock
1941 * 1 = Select 100 Mhz clock
1944 * 10 Vendor specific (set by BIOS?)
1947 * 07 Secondary drive 1 - Cable Type
1948 * 06 Secondary drive 0 - Cable Type
1949 * 05 Primary drive 1 - Cable Type
1950 * 04 Primary drive 0 - Cable Type
1952 * 1 = 80 Conductor (or high speed cable)
1954 * 03 Secondary drive 1 - Select 33/66 clock
1955 * 02 Secondary drive 0 - Select 33/66 clock
1956 * 01 Primary drive 1 - Select 33/66 clock
1957 * 00 Primary drive 0 - Select 33/66 clock
1961 * It is unclear what this should be set to when operating
1964 * NOTE: UDMA2 = 33 MHz
1965 * UDMA3 = 40 MHz (?) - unsupported
1970 reg54 |= 0x0400; /* set vendor specific bit */
1971 reg54 &= ~((0x1 << devno) | (0x1000 << devno));
1973 if (mode >= ATA_UDMA5)
1974 reg54 |= (0x1000 << devno);
1975 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */
1976 reg54 |= (0x1 << devno);
1978 pci_write_config(gparent, 0x54, reg54, 2);
1981 * Reg40 (32 bits... well, actually two 16 bit registers)
1983 * Primary channel bits 15:00, Secondary channel bits 31:00. Note
1984 * that slave timings are handled in register 44.
1986 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges
1988 * 14 Slave ATA Timing Register Enable (R/W)
1990 * 13:12 IORDY Sample Mode
1993 * 10 PIO-3, PIO-4, MW-1, MW-2
1998 * 09:08 Recovery Mode
1999 * 00 PIO-0, PIO-2, SW-2
2004 * 07:04 Secondary Device Control Bits
2005 * 03:00 Primary Device Control Bits
2007 * bit 3 DMA Timing Enable
2009 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device
2011 * bit 1 Enable IORDY sample point capability for PIO
2012 * xfers. Always enabled for PIO4 and PIO3, enabled
2013 * for PIO2 if indicated by the device, and otherwise
2014 * probably should be 0.
2016 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0
2021 * Modify reg40 according to the table
2023 if (atadev->unit == ATA_MASTER) {
2025 new40 = timings[ata_mode2idx(mode)] << 8;
2029 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2030 (timings[ata_mode2idx(mode)] & 0x03);
2034 * Slave ATA timing register enable
2040 * Device control bits 3:0 for master, 7:4 for slave.
2042 * bit3 DMA Timing enable.
2043 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly
2044 * bit1 Enable IORDY sample point capability for PIO xfers. Always
2045 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by
2046 * the device, and otherwise should be 0.
2047 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes.
2052 if (atadev->unit == ATA_MASTER) {
2055 if (!ata_atapi(dev))
2060 if (!ata_atapi(dev))
2064 reg40 &= ~0x00ff00ff;
2065 reg40 |= 0x40774077;
2069 * Primary or Secondary controller
2077 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2078 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2081 reg40 = pci_read_config(gparent, 0x40, 4);
2082 reg44 = pci_read_config(gparent, 0x44, 1);
2083 reg48 = pci_read_config(gparent, 0x48, 1);
2084 reg4a = pci_read_config(gparent, 0x4a, 2);
2085 reg54 = pci_read_config(gparent, 0x54, 2);
2087 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2088 reg40, reg44, reg48 ,reg4a, reg54);
2091 atadev->mode = mode;
2095 ata_intel_31244_allocate(device_t dev)
2097 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2098 struct ata_channel *ch = device_get_softc(dev);
2102 ch_offset = 0x200 + ch->unit * 0x200;
2104 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2105 ch->r_io[i].res = ctlr->r_res2;
2107 /* setup ATA registers */
2108 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2109 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2110 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2111 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2112 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2113 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2114 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2115 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2116 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2117 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2118 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2119 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2121 /* setup DMA registers */
2122 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2123 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2124 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2126 /* setup SATA registers */
2127 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2128 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2129 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2131 ch->flags |= ATA_NO_SLAVE;
2133 ch->hw.status = ata_intel_31244_status;
2134 ch->hw.command = ata_intel_31244_command;
2136 /* enable PHY state change interrupt */
2137 ATA_OUTL(ctlr->r_res2, 0x4,
2138 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2143 ata_intel_31244_status(device_t dev)
2145 /* do we have any PHY events ? */
2146 ata_sata_phy_check_events(dev);
2148 /* any drive action to take care of ? */
2149 return ata_pci_status(dev);
2153 ata_intel_31244_command(struct ata_request *request)
2155 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2156 struct ata_device *atadev = device_get_softc(request->dev);
2159 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
2160 return (ata_generic_command(request));
2162 lba = request->u.ata.lba;
2163 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
2164 /* enable interrupt */
2165 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
2166 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2167 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2168 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
2169 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
2170 ((lba >> 8) & 0x00ff));
2171 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
2172 ((lba >> 16) & 0x00ff));
2174 /* issue command to controller */
2175 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
2181 ata_intel_31244_reset(device_t dev)
2183 if (ata_sata_phy_reset(dev))
2184 ata_generic_reset(dev);
2189 * Integrated Technology Express Inc. (ITE) chipset support functions
2192 ata_ite_ident(device_t dev)
2194 struct ata_pci_controller *ctlr = device_get_softc(dev);
2195 struct ata_chip_id *idx;
2196 static struct ata_chip_id ids[] =
2197 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2198 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2199 { 0, 0, 0, 0, 0, 0}};
2202 if (!(idx = ata_match_chip(dev, ids)))
2205 ksprintf(buffer, "ITE %s %s controller",
2206 idx->text, ata_mode2str(idx->max_dma));
2207 device_set_desc_copy(dev, buffer);
2209 ctlr->chipinit = ata_ite_chipinit;
2214 ata_ite_chipinit(device_t dev)
2216 struct ata_pci_controller *ctlr = device_get_softc(dev);
2218 if (ata_setup_interrupt(dev))
2221 ctlr->setmode = ata_ite_setmode;
2223 /* set PCI mode and 66Mhz reference clock */
2224 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2226 /* set default active & recover timings */
2227 pci_write_config(dev, 0x54, 0x31, 1);
2228 pci_write_config(dev, 0x56, 0x31, 1);
2233 ata_ite_setmode(device_t dev, int mode)
2235 device_t gparent = GRANDPARENT(dev);
2236 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2237 struct ata_device *atadev = device_get_softc(dev);
2238 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2241 /* correct the mode for what the HW supports */
2242 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2244 /* check the CBLID bits for 80 conductor cable detection */
2245 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2246 (ch->unit ? (1<<3) : (1<<2)))) {
2247 ata_print_cable(dev, "controller");
2251 /* set the wanted mode on the device */
2252 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2255 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2256 (error) ? "failed" : "success", ata_mode2str(mode));
2258 /* if the device accepted the mode change, setup the HW accordingly */
2260 if (mode >= ATA_UDMA0) {
2261 u_int8_t udmatiming[] =
2262 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2264 /* enable UDMA mode */
2265 pci_write_config(gparent, 0x50,
2266 pci_read_config(gparent, 0x50, 1) &
2267 ~(1 << (devno + 3)), 1);
2269 /* set UDMA timing */
2270 pci_write_config(gparent,
2271 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2272 udmatiming[mode & ATA_MODE_MASK], 1);
2275 u_int8_t chtiming[] =
2276 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2278 /* disable UDMA mode */
2279 pci_write_config(gparent, 0x50,
2280 pci_read_config(gparent, 0x50, 1) |
2281 (1 << (devno + 3)), 1);
2283 /* set active and recover timing (shared between master & slave) */
2284 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2285 chtiming[ata_mode2idx(mode)])
2286 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2287 chtiming[ata_mode2idx(mode)], 1);
2289 atadev->mode = mode;
2295 * JMicron chipset support functions
2298 ata_jmicron_ident(device_t dev)
2300 struct ata_pci_controller *ctlr = device_get_softc(dev);
2301 struct ata_chip_id *idx;
2302 static struct ata_chip_id ids[] =
2303 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2304 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2305 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2306 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2307 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2308 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2309 { 0, 0, 0, 0, 0, 0}};
2312 if (!(idx = ata_match_chip(dev, ids)))
2315 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2316 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2317 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2318 idx->text, ata_mode2str(ATA_UDMA6));
2320 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2321 idx->text, ata_mode2str(idx->max_dma));
2322 device_set_desc_copy(dev, buffer);
2324 ctlr->chipinit = ata_jmicron_chipinit;
2329 ata_jmicron_chipinit(device_t dev)
2331 struct ata_pci_controller *ctlr = device_get_softc(dev);
2334 if (ata_setup_interrupt(dev))
2337 /* do we have multiple PCI functions ? */
2338 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2339 /* if we have a memory BAR(5) we are on the AHCI part */
2340 ctlr->r_type2 = SYS_RES_MEMORY;
2341 ctlr->r_rid2 = PCIR_BAR(5);
2342 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2343 &ctlr->r_rid2, RF_ACTIVE)))
2344 return ata_ahci_chipinit(dev);
2346 /* otherwise we are on the PATA part */
2347 ctlr->allocate = ata_pci_allocate;
2348 ctlr->reset = ata_generic_reset;
2349 ctlr->dmainit = ata_pci_dmainit;
2350 ctlr->setmode = ata_jmicron_setmode;
2351 ctlr->channels = ctlr->chip->cfg2;
2354 /* set controller configuration to a combined setup we support */
2355 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2356 pci_write_config(dev, 0x80, 0x01200000, 4);
2358 ctlr->r_type2 = SYS_RES_MEMORY;
2359 ctlr->r_rid2 = PCIR_BAR(5);
2360 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2361 &ctlr->r_rid2, RF_ACTIVE))) {
2362 if ((error = ata_ahci_chipinit(dev)))
2366 ctlr->allocate = ata_jmicron_allocate;
2367 ctlr->reset = ata_jmicron_reset;
2368 ctlr->dmainit = ata_jmicron_dmainit;
2369 ctlr->setmode = ata_jmicron_setmode;
2371 /* set the number of HW channels */
2372 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2378 ata_jmicron_allocate(device_t dev)
2380 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2381 struct ata_channel *ch = device_get_softc(dev);
2384 if (ch->unit >= ctlr->chip->cfg1) {
2385 ch->unit -= ctlr->chip->cfg1;
2386 error = ata_pci_allocate(dev);
2387 ch->unit += ctlr->chip->cfg1;
2390 error = ata_ahci_allocate(dev);
2395 ata_jmicron_reset(device_t dev)
2397 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2398 struct ata_channel *ch = device_get_softc(dev);
2400 if (ch->unit >= ctlr->chip->cfg1)
2401 ata_generic_reset(dev);
2403 ata_ahci_reset(dev);
2407 ata_jmicron_dmainit(device_t dev)
2409 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2410 struct ata_channel *ch = device_get_softc(dev);
2412 if (ch->unit >= ctlr->chip->cfg1)
2413 ata_pci_dmainit(dev);
2415 ata_ahci_dmainit(dev);
2419 ata_jmicron_setmode(device_t dev, int mode)
2421 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2422 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2424 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2425 struct ata_device *atadev = device_get_softc(dev);
2427 /* check for 80pin cable present */
2428 if (pci_read_config(dev, 0x40, 1) & 0x08)
2429 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2431 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2433 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2434 atadev->mode = mode;
2437 ata_sata_setmode(dev, mode);
2442 * Marvell chipset support functions
2444 #define ATA_MV_HOST_BASE(ch) \
2445 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2446 #define ATA_MV_EDMA_BASE(ch) \
2447 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2449 struct ata_marvell_response {
2451 u_int8_t edma_status;
2452 u_int8_t dev_status;
2453 u_int32_t timestamp;
2456 struct ata_marvell_dma_prdentry {
2464 ata_marvell_ident(device_t dev)
2466 struct ata_pci_controller *ctlr = device_get_softc(dev);
2467 struct ata_chip_id *idx;
2468 static struct ata_chip_id ids[] =
2469 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2470 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2471 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2472 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2473 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2474 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2475 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2476 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2477 { 0, 0, 0, 0, 0, 0}};
2480 if (!(idx = ata_match_chip(dev, ids)))
2483 ksprintf(buffer, "Marvell %s %s controller",
2484 idx->text, ata_mode2str(idx->max_dma));
2485 device_set_desc_copy(dev, buffer);
2487 switch (ctlr->chip->cfg2) {
2490 ctlr->chipinit = ata_marvell_edma_chipinit;
2493 ctlr->chipinit = ata_marvell_pata_chipinit;
2500 ata_marvell_pata_chipinit(device_t dev)
2502 struct ata_pci_controller *ctlr = device_get_softc(dev);
2504 if (ata_setup_interrupt(dev))
2507 ctlr->allocate = ata_marvell_pata_allocate;
2508 ctlr->setmode = ata_marvell_pata_setmode;
2509 ctlr->channels = ctlr->chip->cfg1;
2514 ata_marvell_pata_allocate(device_t dev)
2516 struct ata_channel *ch = device_get_softc(dev);
2518 /* setup the usual register normal pci style */
2519 if (ata_pci_allocate(dev))
2522 /* dont use 32 bit PIO transfers */
2523 ch->flags |= ATA_USE_16BIT;
2529 ata_marvell_pata_setmode(device_t dev, int mode)
2531 device_t gparent = GRANDPARENT(dev);
2532 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2533 struct ata_device *atadev = device_get_softc(dev);
2535 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2536 mode = ata_check_80pin(dev, mode);
2537 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2538 atadev->mode = mode;
2542 ata_marvell_edma_chipinit(device_t dev)
2544 struct ata_pci_controller *ctlr = device_get_softc(dev);
2546 if (ata_setup_interrupt(dev))
2549 ctlr->r_type1 = SYS_RES_MEMORY;
2550 ctlr->r_rid1 = PCIR_BAR(0);
2551 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2552 &ctlr->r_rid1, RF_ACTIVE)))
2555 /* mask all host controller interrupts */
2556 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2558 /* mask all PCI interrupts */
2559 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2561 ctlr->allocate = ata_marvell_edma_allocate;
2562 ctlr->reset = ata_marvell_edma_reset;
2563 ctlr->dmainit = ata_marvell_edma_dmainit;
2564 ctlr->setmode = ata_sata_setmode;
2565 ctlr->channels = ctlr->chip->cfg1;
2567 /* clear host controller interrupts */
2568 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2569 if (ctlr->chip->cfg1 > 4)
2570 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2572 /* clear PCI interrupts */
2573 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2575 /* unmask PCI interrupts we want */
2576 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2578 /* unmask host controller interrupts we want */
2579 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2580 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2582 /* enable PCI interrupt */
2583 pci_write_config(dev, PCIR_COMMAND,
2584 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2589 ata_marvell_edma_allocate(device_t dev)
2591 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2592 struct ata_channel *ch = device_get_softc(dev);
2593 u_int64_t work = ch->dma->work_bus;
2596 /* clear work area */
2597 bzero(ch->dma->work, 1024+256);
2599 /* set legacy ATA resources */
2600 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2601 ch->r_io[i].res = ctlr->r_res1;
2602 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2604 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2605 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2606 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2607 ata_default_registers(dev);
2609 /* set SATA resources */
2610 switch (ctlr->chip->cfg2) {
2612 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2613 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2614 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2615 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2616 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2617 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2620 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2621 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2622 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2623 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2624 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2625 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2626 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2627 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2631 ch->flags |= ATA_NO_SLAVE;
2632 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2633 ata_generic_hw(dev);
2634 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2635 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2636 ch->hw.status = ata_marvell_edma_status;
2638 /* disable the EDMA machinery */
2639 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2640 DELAY(100000); /* SOS should poll for disabled */
2642 /* set configuration to non-queued 128b read transfers stop on error */
2643 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2645 /* request queue base high */
2646 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2648 /* request queue in ptr */
2649 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2651 /* request queue out ptr */
2652 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2654 /* response queue base high */
2656 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2658 /* response queue in ptr */
2659 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2661 /* response queue out ptr */
2662 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2664 /* clear SATA error register */
2665 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2667 /* clear any outstanding error interrupts */
2668 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2670 /* unmask all error interrupts */
2671 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2673 /* enable EDMA machinery */
2674 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2679 ata_marvell_edma_status(device_t dev)
2681 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2682 struct ata_channel *ch = device_get_softc(dev);
2683 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2684 int shift = (ch->unit << 1) + (ch->unit > 3);
2686 if (cause & (1 << shift)) {
2688 /* clear interrupt(s) */
2689 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2691 /* do we have any PHY events ? */
2692 ata_sata_phy_check_events(dev);
2695 /* do we have any device action ? */
2696 return (cause & (2 << shift));
2699 /* must be called with ATA channel locked and state_mtx held */
2701 ata_marvell_edma_begin_transaction(struct ata_request *request)
2703 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2704 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2710 int dummy, error, slot;
2712 /* only DMA R/W goes through the EMDA machine */
2713 if (request->u.ata.command != ATA_READ_DMA &&
2714 request->u.ata.command != ATA_WRITE_DMA) {
2716 /* disable the EDMA machinery */
2717 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2718 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2719 return ata_begin_transaction(request);
2722 /* check for 48 bit access and convert if needed */
2723 ata_modify_if_48bit(request);
2725 /* check sanity, setup SG list and DMA engine */
2726 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2727 request->flags & ATA_R_READ, ch->dma->sg,
2729 device_printf(request->dev, "setting up DMA failed\n");
2730 request->result = error;
2731 return ATA_OP_FINISHED;
2734 /* get next free request queue slot */
2735 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2736 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2737 bytep = (u_int8_t *)(ch->dma->work);
2738 bytep += (slot << 5);
2739 wordp = (u_int16_t *)bytep;
2740 quadp = (u_int32_t *)bytep;
2742 /* fill in this request */
2743 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2744 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2745 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2748 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2749 bytep[i++] = 0x10 | ATA_COUNT;
2750 bytep[i++] = request->u.ata.count & 0xff;
2751 bytep[i++] = 0x10 | ATA_COUNT;
2753 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2754 bytep[i++] = 0x10 | ATA_SECTOR;
2755 bytep[i++] = request->u.ata.lba & 0xff;
2756 bytep[i++] = 0x10 | ATA_SECTOR;
2758 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2759 bytep[i++] = 0x10 | ATA_CYL_LSB;
2760 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2761 bytep[i++] = 0x10 | ATA_CYL_LSB;
2763 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2764 bytep[i++] = 0x10 | ATA_CYL_MSB;
2765 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2766 bytep[i++] = 0x10 | ATA_CYL_MSB;
2768 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2769 bytep[i++] = 0x10 | ATA_DRIVE;
2771 bytep[i++] = request->u.ata.command;
2772 bytep[i++] = 0x90 | ATA_COMMAND;
2774 /* enable EDMA machinery if needed */
2775 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2776 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2777 while (!(ATA_INL(ctlr->r_res1,
2778 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2782 /* tell EDMA it has a new request */
2783 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2784 req_in &= 0xfffffc00;
2785 req_in += (slot << 5);
2786 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2788 return ATA_OP_CONTINUES;
2791 /* must be called with ATA channel locked and state_mtx held */
2793 ata_marvell_edma_end_transaction(struct ata_request *request)
2795 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2796 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2797 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2798 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2801 /* EDMA interrupt */
2802 if ((icr & (0x0001 << (ch->unit & 3)))) {
2803 struct ata_marvell_response *response;
2804 u_int32_t rsp_in, rsp_out;
2808 callout_stop(&request->callout);
2810 /* get response ptr's */
2811 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2812 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2813 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2814 rsp_out &= 0xffffff00;
2815 rsp_out += (slot << 3);
2816 response = (struct ata_marvell_response *)
2817 (ch->dma->work + 1024 + (slot << 3));
2819 /* record status for this request */
2820 request->status = response->dev_status;
2824 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2826 /* update progress */
2827 if (!(request->status & ATA_S_ERROR) &&
2828 !(request->flags & ATA_R_TIMEOUT))
2829 request->donecount = request->bytecount;
2831 /* unload SG list */
2832 ch->dma->unload(ch->dev);
2834 res = ATA_OP_FINISHED;
2837 /* legacy ATA interrupt */
2839 res = ata_end_transaction(request);
2843 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2848 ata_marvell_edma_reset(device_t dev)
2850 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2851 struct ata_channel *ch = device_get_softc(dev);
2853 /* disable the EDMA machinery */
2854 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2855 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2858 /* clear SATA error register */
2859 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2861 /* clear any outstanding error interrupts */
2862 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2864 /* unmask all error interrupts */
2865 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2867 /* enable channel and test for devices */
2868 if (ata_sata_phy_reset(dev))
2869 ata_generic_reset(dev);
2871 /* enable EDMA machinery */
2872 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2876 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
2879 struct ata_dmasetprd_args *args = xsc;
2880 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2883 if ((args->error = error))
2886 for (i = 0; i < nsegs; i++) {
2887 prd[i].addrlo = htole32(segs[i].ds_addr);
2888 prd[i].count = htole32(segs[i].ds_len);
2889 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
2891 prd[i - 1].count |= htole32(ATA_DMA_EOT);
2895 ata_marvell_edma_dmainit(device_t dev)
2897 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2898 struct ata_channel *ch = device_get_softc(dev);
2902 /* note start and stop are not used here */
2903 ch->dma->setprd = ata_marvell_edma_dmasetprd;
2905 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
2906 ch->dma->max_address = BUS_SPACE_MAXADDR;
2912 * National chipset support functions
2915 ata_national_ident(device_t dev)
2917 struct ata_pci_controller *ctlr = device_get_softc(dev);
2919 /* this chip is a clone of the Cyrix chip, bugs and all */
2920 if (pci_get_devid(dev) == ATA_SC1100) {
2921 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
2922 ctlr->chipinit = ata_national_chipinit;
2929 ata_national_chipinit(device_t dev)
2931 struct ata_pci_controller *ctlr = device_get_softc(dev);
2933 if (ata_setup_interrupt(dev))
2936 ctlr->setmode = ata_national_setmode;
2941 ata_national_setmode(device_t dev, int mode)
2943 device_t gparent = GRANDPARENT(dev);
2944 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2945 struct ata_device *atadev = device_get_softc(dev);
2946 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2947 u_int32_t piotiming[] =
2948 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
2949 0x00803020, 0x20102010, 0x00100010,
2950 0x00100010, 0x00100010, 0x00100010 };
2951 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
2952 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
2955 ch->dma->alignment = 16;
2956 ch->dma->max_iosize = 126 * DEV_BSIZE;
2958 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2960 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2963 device_printf(dev, "%s setting %s on National chip\n",
2964 (error) ? "failed" : "success", ata_mode2str(mode));
2966 if (mode >= ATA_UDMA0) {
2967 pci_write_config(gparent, 0x44 + (devno << 3),
2968 udmatiming[mode & ATA_MODE_MASK], 4);
2970 else if (mode >= ATA_WDMA0) {
2971 pci_write_config(gparent, 0x44 + (devno << 3),
2972 dmatiming[mode & ATA_MODE_MASK], 4);
2975 pci_write_config(gparent, 0x44 + (devno << 3),
2976 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
2979 pci_write_config(gparent, 0x40 + (devno << 3),
2980 piotiming[ata_mode2idx(mode)], 4);
2981 atadev->mode = mode;
2986 * NetCell chipset support functions
2989 ata_netcell_ident(device_t dev)
2991 struct ata_pci_controller *ctlr = device_get_softc(dev);
2993 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
2994 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
2995 ctlr->chipinit = ata_netcell_chipinit;
3002 ata_netcell_chipinit(device_t dev)
3004 struct ata_pci_controller *ctlr = device_get_softc(dev);
3006 if (ata_generic_chipinit(dev))
3009 ctlr->allocate = ata_netcell_allocate;
3014 ata_netcell_allocate(device_t dev)
3016 struct ata_channel *ch = device_get_softc(dev);
3018 /* setup the usual register normal pci style */
3019 if (ata_pci_allocate(dev))
3022 /* the NetCell only supports 16 bit PIO transfers */
3023 ch->flags |= ATA_USE_16BIT;
3030 * nVidia chipset support functions
3033 ata_nvidia_ident(device_t dev)
3035 struct ata_pci_controller *ctlr = device_get_softc(dev);
3036 struct ata_chip_id *idx;
3037 static struct ata_chip_id ids[] =
3038 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3039 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3040 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3041 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3042 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3043 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3044 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3045 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3046 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3047 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3048 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3049 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3050 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3051 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3052 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3053 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3054 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3055 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3056 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3057 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3058 { 0, 0, 0, 0, 0, 0}} ;
3061 if (!(idx = ata_match_chip(dev, ids)))
3064 ksprintf(buffer, "nVidia %s %s controller",
3065 idx->text, ata_mode2str(idx->max_dma));
3066 device_set_desc_copy(dev, buffer);
3068 ctlr->chipinit = ata_nvidia_chipinit;
3073 ata_nvidia_chipinit(device_t dev)
3075 struct ata_pci_controller *ctlr = device_get_softc(dev);
3077 if (ata_setup_interrupt(dev))
3080 if (ctlr->chip->max_dma >= ATA_SA150) {
3081 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3082 ctlr->r_type2 = SYS_RES_IOPORT;
3084 ctlr->r_type2 = SYS_RES_MEMORY;
3085 ctlr->r_rid2 = PCIR_BAR(5);
3086 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3087 &ctlr->r_rid2, RF_ACTIVE))) {
3088 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3090 ctlr->allocate = ata_nvidia_allocate;
3091 ctlr->reset = ata_nvidia_reset;
3093 /* enable control access */
3094 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3096 if (ctlr->chip->cfg2 & NVQ) {
3097 /* clear interrupt status */
3098 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3100 /* enable device and PHY state change interrupts */
3101 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3103 /* disable NCQ support */
3104 ATA_OUTL(ctlr->r_res2, 0x0400,
3105 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3108 /* clear interrupt status */
3109 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3111 /* enable device and PHY state change interrupts */
3112 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3115 /* enable PCI interrupt */
3116 pci_write_config(dev, PCIR_COMMAND,
3117 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3120 ctlr->setmode = ata_sata_setmode;
3123 /* disable prefetch, postwrite */
3124 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3125 ctlr->setmode = ata_via_family_setmode;
3131 ata_nvidia_allocate(device_t dev)
3133 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3134 struct ata_channel *ch = device_get_softc(dev);
3136 /* setup the usual register normal pci style */
3137 if (ata_pci_allocate(dev))
3140 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3141 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3142 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3143 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3144 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3145 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3147 ch->hw.status = ata_nvidia_status;
3148 ch->flags |= ATA_NO_SLAVE;
3154 ata_nvidia_status(device_t dev)
3156 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3157 struct ata_channel *ch = device_get_softc(dev);
3158 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3159 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3160 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
3162 /* do we have any PHY events ? */
3163 if (istatus & (0x0c << shift))
3164 ata_sata_phy_check_events(dev);
3166 /* clear interrupt(s) */
3167 ATA_OUTB(ctlr->r_res2, offset,
3168 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
3170 /* do we have any device action ? */
3171 return (istatus & (0x01 << shift));
3175 ata_nvidia_reset(device_t dev)
3177 if (ata_sata_phy_reset(dev))
3178 ata_generic_reset(dev);
3183 * Promise chipset support functions
3185 #define ATA_PDC_APKT_OFFSET 0x00000010
3186 #define ATA_PDC_HPKT_OFFSET 0x00000040
3187 #define ATA_PDC_ASG_OFFSET 0x00000080
3188 #define ATA_PDC_LSG_OFFSET 0x000000c0
3189 #define ATA_PDC_HSG_OFFSET 0x00000100
3190 #define ATA_PDC_CHN_OFFSET 0x00000400
3191 #define ATA_PDC_BUF_BASE 0x00400000
3192 #define ATA_PDC_BUF_OFFSET 0x00100000
3193 #define ATA_PDC_MAX_HPKT 8
3194 #define ATA_PDC_WRITE_REG 0x00
3195 #define ATA_PDC_WRITE_CTL 0x0e
3196 #define ATA_PDC_WRITE_END 0x08
3197 #define ATA_PDC_WAIT_NBUSY 0x10
3198 #define ATA_PDC_WAIT_READY 0x18
3199 #define ATA_PDC_1B 0x20
3200 #define ATA_PDC_2B 0x40
3202 struct host_packet {
3204 TAILQ_ENTRY(host_packet) chain;
3207 struct ata_promise_sx4 {
3208 struct spinlock mtx;
3209 TAILQ_HEAD(, host_packet) queue;
3214 ata_promise_ident(device_t dev)
3216 struct ata_pci_controller *ctlr = device_get_softc(dev);
3217 struct ata_chip_id *idx;
3218 static struct ata_chip_id ids[] =
3219 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3220 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3221 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3222 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3223 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3224 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3225 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3226 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3227 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3228 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3229 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3230 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3231 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3232 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3233 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3234 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3235 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3236 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3237 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3238 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3239 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3240 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3241 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3242 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3243 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3244 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3245 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3246 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3247 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3248 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3249 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3250 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3251 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3252 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3253 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3254 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3255 { 0, 0, 0, 0, 0, 0}};
3257 uintptr_t devid = 0;
3259 if (!(idx = ata_match_chip(dev, ids)))
3262 /* if we are on a SuperTrak SX6000 dont attach */
3263 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3264 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3265 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3266 devid == ATA_I960RM)
3269 strcpy(buffer, "Promise ");
3270 strcat(buffer, idx->text);
3272 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3273 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3274 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3275 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3276 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3277 static long start = 0, end = 0;
3279 if (pci_get_slot(dev) == 1) {
3280 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3281 strcat(buffer, " (channel 0+1)");
3283 else if (pci_get_slot(dev) == 2 && start && end) {
3284 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3285 strcat(buffer, " (channel 2+3)");
3291 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3292 device_set_desc_copy(dev, buffer);
3294 ctlr->chipinit = ata_promise_chipinit;
3299 ata_promise_chipinit(device_t dev)
3301 struct ata_pci_controller *ctlr = device_get_softc(dev);
3302 int fake_reg, stat_reg;
3304 if (ata_setup_interrupt(dev))
3307 switch (ctlr->chip->cfg1) {
3310 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3312 ctlr->dmainit = ata_promise_dmainit;
3316 /* enable burst mode */
3317 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3318 ctlr->allocate = ata_promise_allocate;
3319 ctlr->setmode = ata_promise_setmode;
3323 ctlr->allocate = ata_promise_tx2_allocate;
3324 ctlr->setmode = ata_promise_setmode;
3328 ctlr->r_type1 = SYS_RES_MEMORY;
3329 ctlr->r_rid1 = PCIR_BAR(4);
3330 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3331 &ctlr->r_rid1, RF_ACTIVE)))
3334 ctlr->r_type2 = SYS_RES_MEMORY;
3335 ctlr->r_rid2 = PCIR_BAR(3);
3336 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3337 &ctlr->r_rid2, RF_ACTIVE)))
3340 if (ctlr->chip->cfg2 == PRSX4X) {
3341 struct ata_promise_sx4 *hpkt;
3342 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3344 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3345 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3346 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) {
3347 device_printf(dev, "unable to setup interrupt\n");
3351 /* print info about cache memory */
3352 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3353 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3354 ((dimm >> 24) & 0xff),
3355 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3356 " ECC enabled" : "" );
3358 /* adjust cache memory parameters */
3359 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3360 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3362 /* setup host packet controls */
3363 hpkt = kmalloc(sizeof(struct ata_promise_sx4),
3364 M_TEMP, M_INTWAIT | M_ZERO);
3365 spin_init(&hpkt->mtx);
3366 TAILQ_INIT(&hpkt->queue);
3368 device_set_ivars(dev, hpkt);
3369 ctlr->allocate = ata_promise_mio_allocate;
3370 ctlr->reset = ata_promise_mio_reset;
3371 ctlr->dmainit = ata_promise_mio_dmainit;
3372 ctlr->setmode = ata_promise_setmode;
3377 /* mio type controllers need an interrupt intercept */
3378 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3379 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3380 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) {
3381 device_printf(dev, "unable to setup interrupt\n");
3385 switch (ctlr->chip->cfg2) {
3387 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3388 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3412 /* prime fake interrupt register */
3413 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3415 /* clear SATA status */
3416 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3418 ctlr->allocate = ata_promise_mio_allocate;
3419 ctlr->reset = ata_promise_mio_reset;
3420 ctlr->dmainit = ata_promise_mio_dmainit;
3421 ctlr->setmode = ata_promise_mio_setmode;
3428 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3430 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3435 ata_promise_allocate(device_t dev)
3437 struct ata_channel *ch = device_get_softc(dev);
3439 if (ata_pci_allocate(dev))
3442 ch->hw.status = ata_promise_status;
3447 ata_promise_status(device_t dev)
3449 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3450 struct ata_channel *ch = device_get_softc(dev);
3452 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3453 return ata_pci_status(dev);
3459 ata_promise_dmastart(device_t dev)
3461 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3462 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3463 struct ata_device *atadev = device_get_softc(dev);
3465 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3466 ATA_OUTB(ctlr->r_res1, 0x11,
3467 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3468 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3469 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3470 (ch->dma->cur_iosize >> 1));
3472 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3473 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3474 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3475 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3476 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3477 ATA_BMCMD_START_STOP);
3478 ch->flags |= ATA_DMA_ACTIVE;
3483 ata_promise_dmastop(device_t dev)
3485 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3486 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3487 struct ata_device *atadev = device_get_softc(dev);
3490 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3491 ATA_OUTB(ctlr->r_res1, 0x11,
3492 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3493 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3495 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3496 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3497 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3498 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3499 ch->flags &= ~ATA_DMA_ACTIVE;
3504 ata_promise_dmareset(device_t dev)
3506 struct ata_channel *ch = device_get_softc(dev);
3508 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3509 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3510 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3511 ch->flags &= ~ATA_DMA_ACTIVE;
3515 ata_promise_dmainit(device_t dev)
3517 struct ata_channel *ch = device_get_softc(dev);
3521 ch->dma->start = ata_promise_dmastart;
3522 ch->dma->stop = ata_promise_dmastop;
3523 ch->dma->reset = ata_promise_dmareset;
3528 ata_promise_setmode(device_t dev, int mode)
3530 device_t gparent = GRANDPARENT(dev);
3531 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3532 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3533 struct ata_device *atadev = device_get_softc(dev);
3534 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3536 u_int32_t timings[][2] = {
3537 /* PROLD PRNEW mode */
3538 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3539 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3540 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3541 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3542 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3543 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3544 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3545 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3546 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3547 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3548 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3549 { 0, 0x00424ef6 }, /* UDMA 3 */
3550 { 0, 0x004127f3 }, /* UDMA 4 */
3551 { 0, 0x004127f3 } /* UDMA 5 */
3554 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3556 switch (ctlr->chip->cfg1) {
3559 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3560 (ch->unit ? 1 << 11 : 1 << 10))) {
3561 ata_print_cable(dev, "controller");
3564 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3565 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3569 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3570 if (mode > ATA_UDMA2 &&
3571 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3572 ata_print_cable(dev, "controller");
3578 if (mode > ATA_UDMA2 &&
3579 (ATA_INL(ctlr->r_res2,
3580 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3581 (ch->unit << 7)) & 0x01000000)) {
3582 ata_print_cable(dev, "controller");
3588 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3591 device_printf(dev, "%ssetting %s on %s chip\n",
3592 (error) ? "FAILURE " : "",
3593 ata_mode2str(mode), ctlr->chip->text);
3595 if (ctlr->chip->cfg1 < PRTX)
3596 pci_write_config(gparent, 0x60 + (devno << 2),
3597 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3598 atadev->mode = mode;
3604 ata_promise_tx2_allocate(device_t dev)
3606 struct ata_channel *ch = device_get_softc(dev);
3608 if (ata_pci_allocate(dev))
3611 ch->hw.status = ata_promise_tx2_status;
3616 ata_promise_tx2_status(device_t dev)
3618 struct ata_channel *ch = device_get_softc(dev);
3620 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3621 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3622 return ata_pci_status(dev);
3628 ata_promise_mio_allocate(device_t dev)
3630 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3631 struct ata_channel *ch = device_get_softc(dev);
3632 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3635 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3636 ch->r_io[i].res = ctlr->r_res2;
3637 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3639 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3640 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3641 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3642 ata_default_registers(dev);
3643 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3644 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3645 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3646 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3647 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3648 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3649 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3650 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3651 ch->flags |= ATA_NO_SLAVE;
3653 ch->flags |= ATA_USE_16BIT;
3655 ata_generic_hw(dev);
3656 if (ctlr->chip->cfg2 & PRSX4X) {
3657 ch->hw.command = ata_promise_sx4_command;
3660 ch->hw.command = ata_promise_mio_command;
3661 ch->hw.status = ata_promise_mio_status;
3667 ata_promise_mio_intr(void *data)
3669 struct ata_pci_controller *ctlr = data;
3670 struct ata_channel *ch;
3674 switch (ctlr->chip->cfg2) {
3688 * since reading interrupt status register on early "mio" chips
3689 * clears the status bits we cannot read it for each channel later on
3690 * in the generic interrupt routine.
3691 * store the bits in an unused register in the chip so we can read
3692 * it from there safely to get around this "feature".
3694 vector = ATA_INL(ctlr->r_res2, 0x040);
3695 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3696 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3698 for (unit = 0; unit < ctlr->channels; unit++) {
3699 if ((ch = ctlr->interrupt[unit].argument))
3700 ctlr->interrupt[unit].function(ch);
3703 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3707 ata_promise_mio_status(device_t dev)
3709 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3710 struct ata_channel *ch = device_get_softc(dev);
3711 struct ata_connect_task *tp;
3712 u_int32_t fake_reg, stat_reg, vector, status;
3714 switch (ctlr->chip->cfg2) {
3729 /* read and acknowledge interrupt */
3730 vector = ATA_INL(ctlr->r_res2, fake_reg);
3732 /* read and clear interface status */
3733 status = ATA_INL(ctlr->r_res2, stat_reg);
3734 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3736 /* check for and handle disconnect events */
3737 if ((status & (0x00000001 << ch->unit)) &&
3738 (tp = (struct ata_connect_task *)
3739 kmalloc(sizeof(struct ata_connect_task),
3740 M_ATA, M_INTWAIT | M_ZERO))) {
3743 device_printf(ch->dev, "DISCONNECT requested\n");
3744 tp->action = ATA_C_DETACH;
3746 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3747 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3750 /* check for and handle connect events */
3751 if ((status & (0x00000010 << ch->unit)) &&
3752 (tp = (struct ata_connect_task *)
3753 kmalloc(sizeof(struct ata_connect_task),
3754 M_ATA, M_INTWAIT | M_ZERO))) {
3757 device_printf(ch->dev, "CONNECT requested\n");
3758 tp->action = ATA_C_ATTACH;
3760 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3761 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3764 /* do we have any device action ? */
3765 return (vector & (1 << (ch->unit + 1)));
3769 ata_promise_mio_command(struct ata_request *request)
3771 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3772 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3773 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3775 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3777 /* XXX SOS add ATAPI commands support later */
3778 switch (request->u.ata.command) {
3780 return ata_generic_command(request);
3783 case ATA_READ_DMA48:
3784 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3788 case ATA_WRITE_DMA48:
3789 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3792 wordp[1] = htole32(ch->dma->sg_bus);
3794 ata_promise_apkt((u_int8_t*)wordp, request);
3796 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3801 ata_promise_mio_reset(device_t dev)
3803 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3804 struct ata_channel *ch = device_get_softc(dev);
3805 struct ata_promise_sx4 *hpktp;
3807 switch (ctlr->chip->cfg2) {
3810 /* softreset channel ATA module */
3811 hpktp = device_get_ivars(ctlr->dev);
3812 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3814 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3815 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3816 ~0x00003f9f) | (ch->unit + 1));
3818 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3819 spin_lock_wr(&hpktp->mtx);
3820 ATA_OUTL(ctlr->r_res2, 0xc012c,
3821 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3823 ATA_OUTL(ctlr->r_res2, 0xc012c,
3824 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3826 spin_unlock_wr(&hpktp->mtx);
3827 ata_generic_reset(dev);
3833 if ((ctlr->chip->cfg2 == PRSATA) ||
3834 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3836 /* mask plug/unplug intr */
3837 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3840 /* softreset channels ATA module */
3841 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3843 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3844 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3845 ~0x00003f9f) | (ch->unit + 1));
3847 if ((ctlr->chip->cfg2 == PRSATA) ||
3848 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3850 if (ata_sata_phy_reset(dev))
3851 ata_generic_reset(dev);
3853 /* reset and enable plug/unplug intr */
3854 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3857 ata_generic_reset(dev);
3862 if ((ctlr->chip->cfg2 == PRSATA2) ||
3863 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3864 /* set portmultiplier port */
3865 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3867 /* mask plug/unplug intr */
3868 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3871 /* softreset channels ATA module */
3872 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3874 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3875 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3876 ~0x00003f9f) | (ch->unit + 1));
3878 if ((ctlr->chip->cfg2 == PRSATA2) ||
3879 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3881 /* set PHY mode to "improved" */
3882 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
3883 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
3884 ~0x00000003) | 0x00000001);
3886 if (ata_sata_phy_reset(dev))
3887 ata_generic_reset(dev);
3889 /* reset and enable plug/unplug intr */
3890 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
3892 /* set portmultiplier port */
3893 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
3896 ata_generic_reset(dev);
3903 ata_promise_mio_dmainit(device_t dev)
3905 /* note start and stop are not used here */
3910 ata_promise_mio_setmode(device_t dev, int mode)
3912 device_t gparent = GRANDPARENT(dev);
3913 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3914 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3916 if ( (ctlr->chip->cfg2 == PRSATA) ||
3917 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
3918 (ctlr->chip->cfg2 == PRSATA2) ||
3919 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
3920 ata_sata_setmode(dev, mode);
3922 ata_promise_setmode(dev, mode);
3926 ata_promise_sx4_intr(void *data)
3928 struct ata_pci_controller *ctlr = data;
3929 struct ata_channel *ch;
3930 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
3933 for (unit = 0; unit < ctlr->channels; unit++) {
3934 if (vector & (1 << (unit + 1)))
3935 if ((ch = ctlr->interrupt[unit].argument))
3936 ctlr->interrupt[unit].function(ch);
3937 if (vector & (1 << (unit + 5)))
3938 if ((ch = ctlr->interrupt[unit].argument))
3939 ata_promise_queue_hpkt(ctlr,
3940 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3941 ATA_PDC_HPKT_OFFSET));
3942 if (vector & (1 << (unit + 9))) {
3943 ata_promise_next_hpkt(ctlr);
3944 if ((ch = ctlr->interrupt[unit].argument))
3945 ctlr->interrupt[unit].function(ch);
3947 if (vector & (1 << (unit + 13))) {
3948 ata_promise_next_hpkt(ctlr);
3949 if ((ch = ctlr->interrupt[unit].argument))
3950 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3951 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3952 ATA_PDC_APKT_OFFSET));
3958 ata_promise_sx4_command(struct ata_request *request)
3960 device_t gparent = GRANDPARENT(request->dev);
3961 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3962 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3963 struct ata_dma_prdentry *prd = ch->dma->sg;
3964 caddr_t window = rman_get_virtual(ctlr->r_res1);
3966 int i, idx, length = 0;
3968 /* XXX SOS add ATAPI commands support later */
3969 switch (request->u.ata.command) {
3974 case ATA_ATA_IDENTIFY:
3978 case ATA_READ_MUL48:
3982 case ATA_WRITE_MUL48:
3983 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
3984 return ata_generic_command(request);
3986 case ATA_SETFEATURES:
3987 case ATA_FLUSHCACHE:
3988 case ATA_FLUSHCACHE48:
3991 wordp = (u_int32_t *)
3992 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
3993 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
3996 ata_promise_apkt((u_int8_t *)wordp, request);
3997 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
3998 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
3999 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4000 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4004 case ATA_READ_DMA48:
4006 case ATA_WRITE_DMA48:
4007 wordp = (u_int32_t *)
4008 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4011 wordp[idx++] = prd[i].addr;
4012 wordp[idx++] = prd[i].count;
4013 length += (prd[i].count & ~ATA_DMA_EOT);
4014 } while (!(prd[i++].count & ATA_DMA_EOT));
4016 wordp = (u_int32_t *)
4017 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4018 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4019 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4021 wordp = (u_int32_t *)
4022 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4023 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4024 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4026 wordp = (u_int32_t *)
4027 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4028 if (request->flags & ATA_R_READ)
4029 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4030 if (request->flags & ATA_R_WRITE)
4031 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4032 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4033 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4036 wordp = (u_int32_t *)
4037 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4038 if (request->flags & ATA_R_READ)
4039 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4040 if (request->flags & ATA_R_WRITE)
4041 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4042 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4044 ata_promise_apkt((u_int8_t *)wordp, request);
4045 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4047 if (request->flags & ATA_R_READ) {
4048 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4049 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4050 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4051 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4053 if (request->flags & ATA_R_WRITE) {
4054 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4055 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4056 ata_promise_queue_hpkt(ctlr,
4057 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4064 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4066 struct ata_device *atadev = device_get_softc(request->dev);
4069 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4070 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4071 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4072 bytep[i++] = ATA_A_4BIT;
4074 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4075 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4076 bytep[i++] = request->u.ata.feature >> 8;
4077 bytep[i++] = request->u.ata.feature;
4078 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4079 bytep[i++] = request->u.ata.count >> 8;
4080 bytep[i++] = request->u.ata.count;
4081 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4082 bytep[i++] = request->u.ata.lba >> 24;
4083 bytep[i++] = request->u.ata.lba;
4084 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4085 bytep[i++] = request->u.ata.lba >> 32;
4086 bytep[i++] = request->u.ata.lba >> 8;
4087 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4088 bytep[i++] = request->u.ata.lba >> 40;
4089 bytep[i++] = request->u.ata.lba >> 16;
4090 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4091 bytep[i++] = ATA_D_LBA | atadev->unit;
4094 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4095 bytep[i++] = request->u.ata.feature;
4096 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4097 bytep[i++] = request->u.ata.count;
4098 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4099 bytep[i++] = request->u.ata.lba;
4100 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4101 bytep[i++] = request->u.ata.lba >> 8;
4102 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4103 bytep[i++] = request->u.ata.lba >> 16;
4104 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4105 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4106 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4108 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4109 bytep[i++] = request->u.ata.command;
4114 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4116 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4118 spin_lock_wr(&hpktp->mtx);
4120 struct host_packet *hp =
4121 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO);
4123 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4127 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4129 spin_unlock_wr(&hpktp->mtx);
4133 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4135 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4136 struct host_packet *hp;
4138 spin_lock_wr(&hpktp->mtx);
4139 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4140 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4141 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4146 spin_unlock_wr(&hpktp->mtx);
4151 * ServerWorks chipset support functions
4154 ata_serverworks_ident(device_t dev)
4156 struct ata_pci_controller *ctlr = device_get_softc(dev);
4157 struct ata_chip_id *idx;
4158 static struct ata_chip_id ids[] =
4159 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4160 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4161 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4162 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4163 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4164 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4165 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
4166 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4167 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4168 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4169 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4170 { 0, 0, 0, 0, 0, 0}};
4173 if (!(idx = ata_match_chip(dev, ids)))
4176 ksprintf(buffer, "ServerWorks %s %s controller",
4177 idx->text, ata_mode2str(idx->max_dma));
4178 device_set_desc_copy(dev, buffer);
4180 ctlr->chipinit = ata_serverworks_chipinit;
4185 ata_serverworks_chipinit(device_t dev)
4187 struct ata_pci_controller *ctlr = device_get_softc(dev);
4189 if (ata_setup_interrupt(dev))
4192 if (ctlr->chip->cfg1 == SWKSMIO) {
4193 ctlr->r_type2 = SYS_RES_MEMORY;
4194 ctlr->r_rid2 = PCIR_BAR(5);
4195 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4196 &ctlr->r_rid2, RF_ACTIVE)))
4199 ctlr->channels = ctlr->chip->cfg2;
4200 ctlr->allocate = ata_serverworks_allocate;
4201 ctlr->setmode = ata_sata_setmode;
4204 else if (ctlr->chip->cfg1 == SWKS33) {
4208 /* locate the ISA part in the southbridge and enable UDMA33 */
4209 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4210 for (i = 0; i < nchildren; i++) {
4211 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4212 pci_write_config(children[i], 0x64,
4213 (pci_read_config(children[i], 0x64, 4) &
4214 ~0x00002000) | 0x00004000, 4);
4218 kfree(children, M_TEMP);
4222 pci_write_config(dev, 0x5a,
4223 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4224 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4226 ctlr->setmode = ata_serverworks_setmode;
4231 ata_serverworks_allocate(device_t dev)
4233 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4234 struct ata_channel *ch = device_get_softc(dev);
4238 ch_offset = ch->unit * 0x100;
4240 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4241 ch->r_io[i].res = ctlr->r_res2;
4243 /* setup ATA registers */
4244 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4245 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4246 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4247 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4248 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4249 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4250 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4251 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4252 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4253 ata_default_registers(dev);
4255 /* setup DMA registers */
4256 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4257 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4258 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4260 /* setup SATA registers */
4261 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4262 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4263 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4265 ch->flags |= ATA_NO_SLAVE;
4271 ata_serverworks_setmode(device_t dev, int mode)
4273 device_t gparent = GRANDPARENT(dev);
4274 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4275 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4276 struct ata_device *atadev = device_get_softc(dev);
4277 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4278 int offset = (devno ^ 0x01) << 3;
4280 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4281 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4282 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4284 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4286 mode = ata_check_80pin(dev, mode);
4288 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4291 device_printf(dev, "%ssetting %s on %s chip\n",
4292 (error) ? "FAILURE " : "",
4293 ata_mode2str(mode), ctlr->chip->text);
4295 if (mode >= ATA_UDMA0) {
4296 pci_write_config(gparent, 0x56,
4297 (pci_read_config(gparent, 0x56, 2) &
4298 ~(0xf << (devno << 2))) |
4299 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4300 pci_write_config(gparent, 0x54,
4301 pci_read_config(gparent, 0x54, 1) |
4302 (0x01 << devno), 1);
4303 pci_write_config(gparent, 0x44,
4304 (pci_read_config(gparent, 0x44, 4) &
4305 ~(0xff << offset)) |
4306 (dmatimings[2] << offset), 4);
4308 else if (mode >= ATA_WDMA0) {
4309 pci_write_config(gparent, 0x54,
4310 pci_read_config(gparent, 0x54, 1) &
4311 ~(0x01 << devno), 1);
4312 pci_write_config(gparent, 0x44,
4313 (pci_read_config(gparent, 0x44, 4) &
4314 ~(0xff << offset)) |
4315 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4318 pci_write_config(gparent, 0x54,
4319 pci_read_config(gparent, 0x54, 1) &
4320 ~(0x01 << devno), 1);
4322 pci_write_config(gparent, 0x40,
4323 (pci_read_config(gparent, 0x40, 4) &
4324 ~(0xff << offset)) |
4325 (piotimings[ata_mode2idx(mode)] << offset), 4);
4326 atadev->mode = mode;
4332 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4335 ata_sii_ident(device_t dev)
4337 struct ata_pci_controller *ctlr = device_get_softc(dev);
4338 struct ata_chip_id *idx;
4339 static struct ata_chip_id ids[] =
4340 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4341 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4342 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4343 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4344 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4345 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4346 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4347 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4348 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4349 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4350 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4351 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4352 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4353 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4354 { 0, 0, 0, 0, 0, 0}};
4357 if (!(idx = ata_match_chip(dev, ids)))
4360 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4361 device_set_desc_copy(dev, buffer);
4363 ctlr->chipinit = ata_sii_chipinit;
4368 ata_sii_chipinit(device_t dev)
4370 struct ata_pci_controller *ctlr = device_get_softc(dev);
4372 if (ata_setup_interrupt(dev))
4375 switch (ctlr->chip->cfg1) {
4377 ctlr->r_type1 = SYS_RES_MEMORY;
4378 ctlr->r_rid1 = PCIR_BAR(0);
4379 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4380 &ctlr->r_rid1, RF_ACTIVE)))
4383 ctlr->r_rid2 = PCIR_BAR(2);
4384 ctlr->r_type2 = SYS_RES_MEMORY;
4385 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4386 &ctlr->r_rid2, RF_ACTIVE))){
4387 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4390 ctlr->allocate = ata_siiprb_allocate;
4391 ctlr->reset = ata_siiprb_reset;
4392 ctlr->dmainit = ata_siiprb_dmainit;
4393 ctlr->setmode = ata_sata_setmode;
4394 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4396 /* reset controller */
4397 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4399 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4401 /* enable PCI interrupt */
4402 pci_write_config(dev, PCIR_COMMAND,
4403 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4407 ctlr->r_type2 = SYS_RES_MEMORY;
4408 ctlr->r_rid2 = PCIR_BAR(5);
4409 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4410 &ctlr->r_rid2, RF_ACTIVE)))
4413 if (ctlr->chip->cfg2 & SIISETCLK) {
4414 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4415 pci_write_config(dev, 0x8a,
4416 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4417 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4418 device_printf(dev, "%s could not set ATA133 clock\n",
4422 /* if we have 4 channels enable the second set */
4423 if (ctlr->chip->cfg2 & SII4CH) {
4424 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4428 /* dont block interrupts from any channel */
4429 pci_write_config(dev, 0x48,
4430 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4432 /* enable PCI interrupt as BIOS might not */
4433 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4435 ctlr->allocate = ata_sii_allocate;
4436 if (ctlr->chip->max_dma >= ATA_SA150) {
4437 ctlr->reset = ata_sii_reset;
4438 ctlr->setmode = ata_sata_setmode;
4441 ctlr->setmode = ata_sii_setmode;
4445 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4446 device_printf(dev, "HW has secondary channel disabled\n");
4450 /* enable interrupt as BIOS might not */
4451 pci_write_config(dev, 0x71, 0x01, 1);
4453 ctlr->allocate = ata_cmd_allocate;
4454 ctlr->setmode = ata_cmd_setmode;
4461 ata_cmd_allocate(device_t dev)
4463 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4464 struct ata_channel *ch = device_get_softc(dev);
4466 /* setup the usual register normal pci style */
4467 if (ata_pci_allocate(dev))
4470 if (ctlr->chip->cfg2 & SIIINTR)
4471 ch->hw.status = ata_cmd_status;
4477 ata_cmd_status(device_t dev)
4479 struct ata_channel *ch = device_get_softc(dev);
4482 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4483 (ch->unit ? 0x08 : 0x04))) {
4484 pci_write_config(device_get_parent(ch->dev), 0x71,
4485 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4486 return ata_pci_status(dev);
4492 ata_cmd_setmode(device_t dev, int mode)
4494 device_t gparent = GRANDPARENT(dev);
4495 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4496 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4497 struct ata_device *atadev = device_get_softc(dev);
4498 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4501 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4503 mode = ata_check_80pin(dev, mode);
4505 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4508 device_printf(dev, "%ssetting %s on %s chip\n",
4509 (error) ? "FAILURE " : "",
4510 ata_mode2str(mode), ctlr->chip->text);
4512 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4513 int ureg = ch->unit ? 0x7b : 0x73;
4515 if (mode >= ATA_UDMA0) {
4516 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4517 { 0x11, 0x42 }, { 0x25, 0x8a },
4518 { 0x15, 0x4a }, { 0x05, 0x0a } };
4520 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4522 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4523 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4524 pci_write_config(gparent, ureg, umode, 1);
4526 else if (mode >= ATA_WDMA0) {
4527 int dmatimings[] = { 0x87, 0x32, 0x3f };
4529 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4530 pci_write_config(gparent, ureg,
4531 pci_read_config(gparent, ureg, 1) &
4532 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4535 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4536 pci_write_config(gparent, treg,
4537 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4538 pci_write_config(gparent, ureg,
4539 pci_read_config(gparent, ureg, 1) &
4540 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4542 atadev->mode = mode;
4547 ata_sii_allocate(device_t dev)
4549 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4550 struct ata_channel *ch = device_get_softc(dev);
4551 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4554 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4555 ch->r_io[i].res = ctlr->r_res2;
4556 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4558 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4559 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4560 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4561 ata_default_registers(dev);
4563 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4564 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4565 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4566 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4567 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4568 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4570 if (ctlr->chip->max_dma >= ATA_SA150) {
4571 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4572 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4573 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4574 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4575 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4576 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4577 ch->flags |= ATA_NO_SLAVE;
4579 /* enable PHY state change interrupt */
4580 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4583 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4584 /* work around errata in early chips */
4585 ch->dma->boundary = 16 * DEV_BSIZE;
4586 ch->dma->segsize = 15 * DEV_BSIZE;
4590 ch->hw.status = ata_sii_status;
4595 ata_sii_status(device_t dev)
4597 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4598 struct ata_channel *ch = device_get_softc(dev);
4599 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4600 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4602 /* do we have any PHY events ? */
4603 if (ctlr->chip->max_dma >= ATA_SA150 &&
4604 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4605 ata_sata_phy_check_events(dev);
4607 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4608 return ata_pci_status(dev);
4614 ata_sii_reset(device_t dev)
4616 if (ata_sata_phy_reset(dev))
4617 ata_generic_reset(dev);
4621 ata_sii_setmode(device_t dev, int mode)
4623 device_t gparent = GRANDPARENT(dev);
4624 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4625 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4626 struct ata_device *atadev = device_get_softc(dev);
4627 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4628 int mreg = ch->unit ? 0x84 : 0x80;
4629 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4630 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4633 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4635 if (ctlr->chip->cfg2 & SIISETCLK) {
4636 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4637 (ch->unit ? 0x02 : 0x01))) {
4638 ata_print_cable(dev, "controller");
4643 mode = ata_check_80pin(dev, mode);
4645 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4648 device_printf(dev, "%ssetting %s on %s chip\n",
4649 (error) ? "FAILURE " : "",
4650 ata_mode2str(mode), ctlr->chip->text);
4654 if (mode >= ATA_UDMA0) {
4655 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4656 u_int8_t ureg = 0xac + rego;
4658 pci_write_config(gparent, mreg,
4659 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4660 pci_write_config(gparent, ureg,
4661 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4662 udmatimings[mode & ATA_MODE_MASK], 1);
4665 else if (mode >= ATA_WDMA0) {
4666 u_int8_t dreg = 0xa8 + rego;
4667 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4669 pci_write_config(gparent, mreg,
4670 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4671 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4675 u_int8_t preg = 0xa4 + rego;
4676 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4678 pci_write_config(gparent, mreg,
4679 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4680 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4682 atadev->mode = mode;
4685 struct ata_siiprb_dma_prdentry {
4691 struct ata_siiprb_ata_command {
4692 u_int32_t reserved0;
4693 struct ata_siiprb_dma_prdentry prd[126];
4696 struct ata_siiprb_atapi_command {
4698 struct ata_siiprb_dma_prdentry prd[125];
4701 struct ata_siiprb_command {
4703 u_int16_t protocol_override;
4704 u_int32_t transfer_count;
4707 struct ata_siiprb_ata_command ata;
4708 struct ata_siiprb_atapi_command atapi;
4713 ata_siiprb_allocate(device_t dev)
4715 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4716 struct ata_channel *ch = device_get_softc(dev);
4717 int offset = ch->unit * 0x2000;
4719 /* set the SATA resources */
4720 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4721 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4722 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4723 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4724 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4725 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4726 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4727 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4729 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4730 ch->hw.end_transaction = ata_siiprb_end_transaction;
4731 ch->hw.status = ata_siiprb_status;
4732 ch->hw.command = NULL; /* not used here */
4737 ata_siiprb_status(device_t dev)
4739 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4740 struct ata_channel *ch = device_get_softc(dev);
4741 int offset = ch->unit * 0x2000;
4743 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) {
4744 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4746 /* do we have any PHY events ? */
4747 ata_sata_phy_check_events(dev);
4749 /* clear interrupt(s) */
4750 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4752 /* do we have any device action ? */
4753 return (istatus & 0x00000001);
4759 ata_siiprb_begin_transaction(struct ata_request *request)
4761 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4762 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4763 struct ata_siiprb_command *prb;
4764 int offset = ch->unit * 0x2000;
4768 /* check for 48 bit access and convert if needed */
4769 ata_modify_if_48bit(request);
4771 /* get a piece of the workspace for this request */
4772 prb = (struct ata_siiprb_command *)
4773 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4775 /* set basic prd options ata/atapi etc etc */
4776 bzero(prb, sizeof(struct ata_siiprb_command));
4778 /* setup the FIS for this request */
4779 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4780 device_printf(request->dev, "setting up SATA FIS failed\n");
4781 request->result = EIO;
4782 return ATA_OP_FINISHED;
4785 /* if request moves data setup and load SG list */
4786 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4787 struct ata_siiprb_dma_prdentry *prd;
4789 if (request->flags & ATA_R_ATAPI)
4790 prd = &prb->u.atapi.prd[0];
4792 prd = &prb->u.ata.prd[0];
4793 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4794 request->flags & ATA_R_READ, prd, &dummy)) {
4795 device_printf(request->dev, "setting up DMA failed\n");
4796 request->result = EIO;
4797 return ATA_OP_FINISHED;
4801 /* activate the prb */
4802 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4803 ATA_OUTL(ctlr->r_res2,
4804 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4805 ATA_OUTL(ctlr->r_res2,
4806 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4808 /* start the timeout */
4809 callout_reset(&request->callout, request->timeout * hz,
4810 (timeout_t*)ata_timeout, request);
4811 return ATA_OP_CONTINUES;
4815 ata_siiprb_end_transaction(struct ata_request *request)
4817 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4818 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4819 struct ata_siiprb_command *prb;
4820 int offset = ch->unit * 0x2000;
4823 /* kill the timeout */
4824 callout_stop(&request->callout);
4826 prb = (struct ata_siiprb_command *)
4827 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4829 /* if error status get details */
4830 request->status = prb->fis[2];
4831 if (request->status & ATA_S_ERROR)
4832 request->error = prb->fis[3];
4834 /* update progress */
4835 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
4836 if (request->flags & ATA_R_READ)
4837 request->donecount = prb->transfer_count;
4839 request->donecount = request->bytecount;
4842 /* any controller errors flagged ? */
4843 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
4844 kprintf("ata_siiprb_end_transaction %s error=%08x\n",
4845 ata_cmd2str(request), error);
4848 /* release SG list etc */
4849 ch->dma->unload(ch->dev);
4851 return ATA_OP_FINISHED;
4855 ata_siiprb_reset(device_t dev)
4857 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4858 struct ata_channel *ch = device_get_softc(dev);
4859 int offset = ch->unit * 0x2000;
4860 struct ata_siiprb_command *prb;
4862 u_int32_t status, signature;
4863 int timeout, tag = 0;
4865 /* reset channel HW */
4866 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
4868 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
4871 /* poll for channel ready */
4872 for (timeout = 0; timeout < 1000; timeout++) {
4873 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000)
4877 if (timeout >= 1000) {
4878 device_printf(ch->dev, "channel HW reset timeout reset failure\n");
4883 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1);
4886 if (!ata_sata_phy_reset(dev)) {
4888 device_printf(ch->dev, "phy reset found no device\n");
4893 /* get a piece of the workspace for a soft reset request */
4894 prb = (struct ata_siiprb_command *)
4895 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4896 bzero(prb, sizeof(struct ata_siiprb_command));
4897 prb->control = htole16(0x0080);
4899 /* activate the soft reset prb */
4900 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4901 ATA_OUTL(ctlr->r_res2,
4902 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4903 ATA_OUTL(ctlr->r_res2,
4904 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4906 /* poll for channel ready */
4907 for (timeout = 0; timeout < 1000; timeout++) {
4909 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
4912 if (timeout >= 1000) {
4913 device_printf(ch->dev, "reset timeout - no device found\n");
4918 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
4921 /* find out whats there */
4922 prb = (struct ata_siiprb_command *)
4923 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4925 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
4927 device_printf(ch->dev, "signature=%08x\n", signature);
4928 switch (signature) {
4930 ch->devices = ATA_ATAPI_MASTER;
4931 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n");
4935 ch->devices = ATA_PORTMULTIPLIER;
4936 device_printf(ch->dev, "Portmultipliers not supported yet\n");
4940 ch->devices = ATA_ATA_MASTER;
4947 /* clear interrupt(s) */
4948 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
4950 /* require explicit interrupt ack */
4951 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
4954 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
4956 /* enable interrupts wanted */
4957 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
4961 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
4963 struct ata_dmasetprd_args *args = xsc;
4964 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
4967 if ((args->error = error))
4970 for (i = 0; i < nsegs; i++) {
4971 prd[i].addr = htole64(segs[i].ds_addr);
4972 prd[i].count = htole32(segs[i].ds_len);
4974 prd[i - 1].control = htole32(ATA_DMA_EOT);
4978 ata_siiprb_dmainit(device_t dev)
4980 struct ata_channel *ch = device_get_softc(dev);
4984 /* note start and stop are not used here */
4985 ch->dma->setprd = ata_siiprb_dmasetprd;
4986 ch->dma->max_address = BUS_SPACE_MAXADDR;
4992 * Silicon Integrated Systems Corp. (SiS) chipset support functions
4995 ata_sis_ident(device_t dev)
4997 struct ata_pci_controller *ctlr = device_get_softc(dev);
4998 struct ata_chip_id *idx;
4999 static struct ata_chip_id ids[] =
5000 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5001 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5002 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5003 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5004 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5005 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5006 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5008 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5009 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5010 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5011 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5013 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5014 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5015 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5016 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5017 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5019 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5020 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5021 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5023 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5024 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5025 { 0, 0, 0, 0, 0, 0 }};
5029 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5032 if (idx->cfg2 && !found) {
5033 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5035 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5036 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5038 idx->cfg1 = SIS133NEW;
5039 idx->max_dma = ATA_UDMA6;
5040 ksprintf(buffer, "SiS 962/963 %s controller",
5041 ata_mode2str(idx->max_dma));
5043 pci_write_config(dev, 0x57, reg57, 1);
5045 if (idx->cfg2 && !found) {
5046 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5048 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5049 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5050 struct ata_chip_id id[] =
5051 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5054 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5055 idx->cfg1 = SIS133OLD;
5056 idx->max_dma = ATA_UDMA6;
5059 idx->cfg1 = SIS100NEW;
5060 idx->max_dma = ATA_UDMA5;
5062 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5064 pci_write_config(dev, 0x4a, reg4a, 1);
5067 ksprintf(buffer,"SiS %s %s controller",
5068 idx->text, ata_mode2str(idx->max_dma));
5070 device_set_desc_copy(dev, buffer);
5072 ctlr->chipinit = ata_sis_chipinit;
5077 ata_sis_chipinit(device_t dev)
5079 struct ata_pci_controller *ctlr = device_get_softc(dev);
5081 if (ata_setup_interrupt(dev))
5084 switch (ctlr->chip->cfg1) {
5089 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
5093 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
5096 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
5097 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
5100 ctlr->r_type2 = SYS_RES_IOPORT;
5101 ctlr->r_rid2 = PCIR_BAR(5);
5102 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5103 &ctlr->r_rid2, RF_ACTIVE))) {
5104 ctlr->allocate = ata_sis_allocate;
5105 ctlr->reset = ata_sis_reset;
5107 /* enable PCI interrupt */
5108 pci_write_config(dev, PCIR_COMMAND,
5109 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5111 ctlr->setmode = ata_sata_setmode;
5116 ctlr->setmode = ata_sis_setmode;
5121 ata_sis_allocate(device_t dev)
5123 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5124 struct ata_channel *ch = device_get_softc(dev);
5125 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
5127 /* setup the usual register normal pci style */
5128 if (ata_pci_allocate(dev))
5131 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5132 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
5133 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5134 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
5135 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5136 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
5137 ch->flags |= ATA_NO_SLAVE;
5139 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
5140 /* XXX SOS unknown how to enable PHY state change interrupt */
5145 ata_sis_reset(device_t dev)
5147 if (ata_sata_phy_reset(dev))
5148 ata_generic_reset(dev);
5152 ata_sis_setmode(device_t dev, int mode)
5154 device_t gparent = GRANDPARENT(dev);
5155 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5156 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5157 struct ata_device *atadev = device_get_softc(dev);
5158 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5161 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5163 if (ctlr->chip->cfg1 == SIS133NEW) {
5164 if (mode > ATA_UDMA2 &&
5165 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
5166 ata_print_cable(dev, "controller");
5171 if (mode > ATA_UDMA2 &&
5172 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
5173 ata_print_cable(dev, "controller");
5178 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5181 device_printf(dev, "%ssetting %s on %s chip\n",
5182 (error) ? "FAILURE " : "",
5183 ata_mode2str(mode), ctlr->chip->text);
5185 switch (ctlr->chip->cfg1) {
5187 u_int32_t timings[] =
5188 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
5189 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
5190 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
5193 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
5194 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
5198 u_int16_t timings[] =
5199 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
5200 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
5202 u_int16_t reg = 0x40 + (devno << 1);
5204 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5208 u_int16_t timings[] =
5209 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
5210 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
5211 u_int16_t reg = 0x40 + (devno << 1);
5213 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5219 u_int16_t timings[] =
5220 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
5221 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
5222 u_int16_t reg = 0x40 + (devno << 1);
5224 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5228 atadev->mode = mode;
5233 /* VIA Technologies Inc. chipset support functions */
5235 ata_via_ident(device_t dev)
5237 struct ata_pci_controller *ctlr = device_get_softc(dev);
5238 struct ata_chip_id *idx;
5239 static struct ata_chip_id ids[] =
5240 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
5241 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
5242 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
5243 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
5244 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
5245 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
5246 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
5247 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
5248 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
5249 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
5250 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
5251 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
5252 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
5253 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
5254 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
5255 { 0, 0, 0, 0, 0, 0 }};
5256 static struct ata_chip_id new_ids[] =
5257 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
5258 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
5259 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
5260 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
5261 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
5262 { 0, 0, 0, 0, 0, 0 }};
5265 if (pci_get_devid(dev) == ATA_VIA82C571) {
5266 if (!(idx = ata_find_chip(dev, ids, -99)))
5270 if (!(idx = ata_match_chip(dev, new_ids)))
5274 ksprintf(buffer, "VIA %s %s controller",
5275 idx->text, ata_mode2str(idx->max_dma));
5276 device_set_desc_copy(dev, buffer);
5278 ctlr->chipinit = ata_via_chipinit;
5283 ata_via_chipinit(device_t dev)
5285 struct ata_pci_controller *ctlr = device_get_softc(dev);
5287 if (ata_setup_interrupt(dev))
5290 if (ctlr->chip->max_dma >= ATA_SA150) {
5291 if (ctlr->chip->cfg2 == VIAAHCI) {
5292 ctlr->r_type2 = SYS_RES_MEMORY;
5293 ctlr->r_rid2 = PCIR_BAR(5);
5294 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5297 return ata_ahci_chipinit(dev);
5300 ctlr->r_type2 = SYS_RES_IOPORT;
5301 ctlr->r_rid2 = PCIR_BAR(5);
5302 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5303 &ctlr->r_rid2, RF_ACTIVE))) {
5304 ctlr->allocate = ata_via_allocate;
5305 ctlr->reset = ata_via_reset;
5307 /* enable PCI interrupt */
5308 pci_write_config(dev, PCIR_COMMAND,
5309 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5312 if (ctlr->chip->cfg2 & VIABAR) {
5314 ctlr->setmode = ata_via_setmode;
5317 ctlr->setmode = ata_sata_setmode;
5321 /* prepare for ATA-66 on the 82C686a and 82C596b */
5322 if (ctlr->chip->cfg2 & VIACLK)
5323 pci_write_config(dev, 0x50, 0x030b030b, 4);
5325 /* the southbridge might need the data corruption fix */
5326 if (ctlr->chip->cfg2 & VIABUG)
5327 ata_via_southbridge_fixup(dev);
5329 /* set fifo configuration half'n'half */
5330 pci_write_config(dev, 0x43,
5331 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
5333 /* set status register read retry */
5334 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
5336 /* set DMA read & end-of-sector fifo flush */
5337 pci_write_config(dev, 0x46,
5338 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
5340 /* set sector size */
5341 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
5342 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
5344 ctlr->setmode = ata_via_family_setmode;
5349 ata_via_allocate(device_t dev)
5351 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5352 struct ata_channel *ch = device_get_softc(dev);
5354 /* newer SATA chips has resources in one BAR for each channel */
5355 if (ctlr->chip->cfg2 & VIABAR) {
5356 struct resource *r_io;
5359 rid = PCIR_BAR(ch->unit);
5360 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
5365 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
5366 ch->r_io[i].res = r_io;
5367 ch->r_io[i].offset = i;
5369 ch->r_io[ATA_CONTROL].res = r_io;
5370 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
5371 ch->r_io[ATA_IDX_ADDR].res = r_io;
5372 ata_default_registers(dev);
5373 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
5374 ch->r_io[i].res = ctlr->r_res1;
5375 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
5382 /* setup the usual register normal pci style */
5383 if (ata_pci_allocate(dev))
5387 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5388 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
5389 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5390 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
5391 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5392 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
5393 ch->flags |= ATA_NO_SLAVE;
5395 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
5396 /* XXX SOS unknown how to enable PHY state change interrupt */
5401 ata_via_reset(device_t dev)
5403 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5404 struct ata_channel *ch = device_get_softc(dev);
5406 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
5407 ata_generic_reset(dev);
5409 if (ata_sata_phy_reset(dev))
5410 ata_generic_reset(dev);
5414 ata_via_setmode(device_t dev, int mode)
5416 device_t gparent = GRANDPARENT(dev);
5417 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5418 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5419 struct ata_device *atadev = device_get_softc(dev);
5422 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
5423 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
5425 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5426 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
5428 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
5429 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5431 device_printf(dev, "%ssetting %s on %s chip\n",
5432 (error) ? "FAILURE " : "", ata_mode2str(mode),
5435 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
5436 if (mode >= ATA_UDMA0)
5437 pci_write_config(gparent, 0xb3,
5438 dma_timings[mode & ATA_MODE_MASK], 1);
5439 atadev->mode = mode;
5443 ata_sata_setmode(dev, mode);
5447 ata_via_southbridge_fixup(device_t dev)
5452 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5455 for (i = 0; i < nchildren; i++) {
5456 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
5457 pci_get_devid(children[i]) == ATA_VIA8371 ||
5458 pci_get_devid(children[i]) == ATA_VIA8662 ||
5459 pci_get_devid(children[i]) == ATA_VIA8361) {
5460 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
5462 if ((reg76 & 0xf0) != 0xd0) {
5464 "Correcting VIA config for southbridge data corruption bug\n");
5465 pci_write_config(children[i], 0x75, 0x80, 1);
5466 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
5471 kfree(children, M_TEMP);
5475 /* common code for VIA, AMD & nVidia */
5477 ata_via_family_setmode(device_t dev, int mode)
5479 device_t gparent = GRANDPARENT(dev);
5480 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5481 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5482 struct ata_device *atadev = device_get_softc(dev);
5483 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
5484 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5486 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
5487 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
5488 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
5489 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
5490 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
5491 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5492 int reg = 0x53 - devno;
5495 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5497 if (ctlr->chip->cfg2 & AMDCABLE) {
5498 if (mode > ATA_UDMA2 &&
5499 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
5500 ata_print_cable(dev, "controller");
5505 mode = ata_check_80pin(dev, mode);
5507 if (ctlr->chip->cfg2 & NVIDIA)
5510 if (ctlr->chip->cfg1 != VIA133)
5511 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
5513 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5516 device_printf(dev, "%ssetting %s on %s chip\n",
5517 (error) ? "FAILURE " : "", ata_mode2str(mode),
5520 if (mode >= ATA_UDMA0)
5521 pci_write_config(gparent, reg,
5522 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
5524 pci_write_config(gparent, reg, 0x8b, 1);
5525 atadev->mode = mode;
5530 /* misc functions */
5531 static struct ata_chip_id *
5532 ata_match_chip(device_t dev, struct ata_chip_id *index)
5534 while (index->chipid != 0) {
5535 if (pci_get_devid(dev) == index->chipid &&
5536 pci_get_revid(dev) >= index->chiprev)
5543 static struct ata_chip_id *
5544 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
5549 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5552 while (index->chipid != 0) {
5553 for (i = 0; i < nchildren; i++) {
5554 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
5555 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
5556 pci_get_devid(children[i]) == index->chipid &&
5557 pci_get_revid(children[i]) >= index->chiprev) {
5558 kfree(children, M_TEMP);
5564 kfree(children, M_TEMP);
5569 ata_setup_interrupt(device_t dev)
5571 struct ata_pci_controller *ctlr = device_get_softc(dev);
5572 int rid = ATA_IRQ_RID;
5574 if (!ata_legacy(dev)) {
5575 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
5576 RF_SHAREABLE | RF_ACTIVE))) {
5577 device_printf(dev, "unable to map interrupt\n");
5580 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
5581 ata_generic_intr, ctlr, &ctlr->handle, NULL))) {
5582 device_printf(dev, "unable to setup interrupt\n");
5589 struct ata_serialize {
5590 struct spinlock locked_mtx;
5596 ata_serialize(device_t dev, int flags)
5598 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5599 struct ata_channel *ch = device_get_softc(dev);
5600 struct ata_serialize *serial;
5601 static int inited = 0;
5605 serial = kmalloc(sizeof(struct ata_serialize),
5606 M_TEMP, M_INTWAIT | M_ZERO);
5607 spin_init(&serial->locked_mtx);
5608 serial->locked_ch = -1;
5609 serial->restart_ch = -1;
5610 device_set_ivars(ctlr->dev, serial);
5614 serial = device_get_ivars(ctlr->dev);
5616 spin_lock_wr(&serial->locked_mtx);
5619 if (serial->locked_ch == -1)
5620 serial->locked_ch = ch->unit;
5621 if (serial->locked_ch != ch->unit)
5622 serial->restart_ch = ch->unit;
5626 if (serial->locked_ch == ch->unit) {
5627 serial->locked_ch = -1;
5628 if (serial->restart_ch != -1) {
5629 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
5630 serial->restart_ch = -1;
5631 spin_unlock_wr(&serial->locked_mtx);
5642 res = serial->locked_ch;
5643 spin_unlock_wr(&serial->locked_mtx);
5648 ata_print_cable(device_t dev, u_int8_t *who)
5651 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
5655 ata_atapi(device_t dev)
5657 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5658 struct ata_device *atadev = device_get_softc(dev);
5660 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
5661 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
5665 ata_check_80pin(device_t dev, int mode)
5667 struct ata_device *atadev = device_get_softc(dev);
5669 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
5670 ata_print_cable(dev, "device");
5677 ata_mode2idx(int mode)
5679 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
5680 return (mode & ATA_MODE_MASK) + 8;
5681 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
5682 return (mode & ATA_MODE_MASK) + 5;
5683 return (mode & ATA_MODE_MASK) - ATA_PIO0;