2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <linux/slab.h>
33 #include <video/mipi_display.h>
34 #include <video/mipi_display.h>
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
40 struct drm_panel panel;
41 struct intel_dsi *intel_dsi;
44 static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
46 return container_of(panel, struct vbt_panel, panel);
49 #define MIPI_TRANSFER_MODE_SHIFT 0
50 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
51 #define MIPI_PORT_SHIFT 3
53 #define PREPARE_CNT_MAX 0x3F
54 #define EXIT_ZERO_CNT_MAX 0x3F
55 #define CLK_ZERO_CNT_MAX 0xFF
56 #define TRAIL_CNT_MAX 0x1F
58 #define NS_KHZ_RATIO 1000000
60 /* base offsets for gpio pads */
61 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
62 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
63 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
64 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
65 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
66 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
67 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
68 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
69 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
70 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
71 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
72 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
74 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
75 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
82 static struct gpio_map vlv_gpio_table[] = {
83 { VLV_GPIO_NC_0_HV_DDI0_HPD },
84 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
85 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
86 { VLV_GPIO_NC_3_PANEL0_VDDEN },
87 { VLV_GPIO_NC_4_PANEL0_BKLTEN },
88 { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
89 { VLV_GPIO_NC_6_HV_DDI1_HPD },
90 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
91 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
92 { VLV_GPIO_NC_9_PANEL1_VDDEN },
93 { VLV_GPIO_NC_10_PANEL1_BKLTEN },
94 { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
97 static inline enum port intel_dsi_seq_port_to_port(u8 port)
99 return port ? PORT_C : PORT_A;
102 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
105 struct mipi_dsi_device *dsi_device;
106 u8 type, flags, seq_port;
113 len = *((const u16 *) data);
116 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
118 /* For DSI single link on Port A & C, the seq_port value which is
119 * parsed from Sequence Block#53 of VBT has been set to 0
120 * Now, read/write of packets for the DSI single link on Port A and
121 * Port C will based on the DVO port from VBT block 2.
123 if (intel_dsi->ports == (1 << PORT_C))
126 port = intel_dsi_seq_port_to_port(seq_port);
128 dsi_device = intel_dsi->dsi_hosts[port]->device;
130 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
134 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
135 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
137 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
139 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
142 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
143 mipi_dsi_generic_write(dsi_device, NULL, 0);
145 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
146 mipi_dsi_generic_write(dsi_device, data, 1);
148 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
149 mipi_dsi_generic_write(dsi_device, data, 2);
151 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
152 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
153 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
154 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
156 case MIPI_DSI_GENERIC_LONG_WRITE:
157 mipi_dsi_generic_write(dsi_device, data, len);
159 case MIPI_DSI_DCS_SHORT_WRITE:
160 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
162 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
163 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
165 case MIPI_DSI_DCS_READ:
166 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
168 case MIPI_DSI_DCS_LONG_WRITE:
169 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
179 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
181 u32 delay = *((const u32 *) data);
183 usleep_range(delay, delay + 10);
189 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
190 u8 gpio_source, u8 gpio_index, bool value)
192 struct gpio_map *map;
197 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
198 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
202 map = &vlv_gpio_table[gpio_index];
204 if (dev_priv->vbt.dsi.seq_version >= 3) {
205 DRM_DEBUG_KMS("GPIO element v3 not supported\n");
208 if (gpio_source == 0) {
209 port = IOSF_PORT_GPIO_NC;
210 } else if (gpio_source == 1) {
211 port = IOSF_PORT_GPIO_SC;
213 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
218 pconf0 = VLV_GPIO_PCONF0(map->base_offset);
219 padval = VLV_GPIO_PAD_VAL(map->base_offset);
221 mutex_lock(&dev_priv->sb_lock);
223 /* FIXME: remove constant below */
224 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
229 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
230 mutex_unlock(&dev_priv->sb_lock);
233 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
235 struct drm_device *dev = intel_dsi->base.base.dev;
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u8 gpio_source, gpio_index;
240 if (dev_priv->vbt.dsi.seq_version >= 3)
243 gpio_index = *data++;
245 /* gpio source in sequence v2 only */
246 if (dev_priv->vbt.dsi.seq_version == 2)
247 gpio_source = (*data >> 1) & 3;
254 if (IS_VALLEYVIEW(dev_priv))
255 vlv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
257 DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
262 static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
264 return data + *(data + 6) + 7;
267 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
269 static const fn_mipi_elem_exec exec_elem[] = {
270 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
271 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
272 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
273 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
277 * MIPI Sequence from VBT #53 parsing logic
278 * We have already separated each seqence during bios parsing
279 * Following is generic execution function for any sequence
282 static const char * const seq_name[] = {
283 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
284 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
285 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
286 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
287 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
288 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
289 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
290 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
291 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
292 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
293 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
296 static const char *sequence_name(enum mipi_seq seq_id)
298 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
299 return seq_name[seq_id];
304 static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
306 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
307 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
308 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
310 fn_mipi_elem_exec mipi_elem_exec;
312 if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
315 data = dev_priv->vbt.dsi.sequence[seq_id];
317 DRM_DEBUG_KMS("MIPI sequence %d - %s not available\n",
318 seq_id, sequence_name(seq_id));
322 WARN_ON(*data != seq_id);
324 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
325 seq_id, sequence_name(seq_id));
327 /* Skip Sequence Byte. */
330 /* Skip Size of Sequence. */
331 if (dev_priv->vbt.dsi.seq_version >= 3)
335 u8 operation_byte = *data++;
336 u8 operation_size = 0;
338 if (operation_byte == MIPI_SEQ_ELEM_END)
341 if (operation_byte < ARRAY_SIZE(exec_elem))
342 mipi_elem_exec = exec_elem[operation_byte];
344 mipi_elem_exec = NULL;
346 /* Size of Operation. */
347 if (dev_priv->vbt.dsi.seq_version >= 3)
348 operation_size = *data++;
350 if (mipi_elem_exec) {
351 data = mipi_elem_exec(intel_dsi, data);
352 } else if (operation_size) {
353 /* We have size, skip. */
354 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
356 data += operation_size;
358 /* No size, can't skip without parsing. */
359 DRM_ERROR("Unsupported MIPI operation byte %u\n",
366 static int vbt_panel_prepare(struct drm_panel *panel)
368 generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
369 generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
374 static int vbt_panel_unprepare(struct drm_panel *panel)
376 generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
381 static int vbt_panel_enable(struct drm_panel *panel)
383 generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON);
388 static int vbt_panel_disable(struct drm_panel *panel)
390 generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF);
395 static int vbt_panel_get_modes(struct drm_panel *panel)
397 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
398 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
399 struct drm_device *dev = intel_dsi->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 struct drm_display_mode *mode;
403 if (!panel->connector)
406 mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
410 mode->type |= DRM_MODE_TYPE_PREFERRED;
412 drm_mode_probed_add(panel->connector, mode);
417 static const struct drm_panel_funcs vbt_panel_funcs = {
418 .disable = vbt_panel_disable,
419 .unprepare = vbt_panel_unprepare,
420 .prepare = vbt_panel_prepare,
421 .enable = vbt_panel_enable,
422 .get_modes = vbt_panel_get_modes,
425 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
427 struct drm_device *dev = intel_dsi->base.base.dev;
428 struct drm_i915_private *dev_priv = dev->dev_private;
429 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
430 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
431 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
432 struct vbt_panel *vbt_panel;
434 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
436 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
437 u32 ths_prepare_ns, tclk_trail_ns;
438 u32 tclk_prepare_clkzero, ths_prepare_hszero;
439 u32 lp_to_hs_switch, hs_to_lp_switch;
440 u32 pclk, computed_ddr;
441 u16 burst_mode_ratio;
446 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
447 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
448 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
449 intel_dsi->pixel_format =
450 pixel_format_from_register_bits(
451 mipi_config->videomode_color_format << 7);
452 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
454 intel_dsi->dual_link = mipi_config->dual_link;
455 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
456 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
457 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
458 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
459 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
460 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
461 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
462 intel_dsi->init_count = mipi_config->master_init_timer;
463 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
464 intel_dsi->video_frmt_cfg_bits =
465 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
469 /* In dual link mode each port needs half of pixel clock */
470 if (intel_dsi->dual_link) {
473 /* we can enable pixel_overlap if needed by panel. In this
474 * case we need to increase the pixelclock for extra pixels
476 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
477 pclk += DIV_ROUND_UP(mode->vtotal *
478 intel_dsi->pixel_overlap *
484 * Target ddr frequency from VBT / non burst ddr freq
485 * multiply by 100 to preserve remainder
487 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
488 if (mipi_config->target_burst_mode_freq) {
489 computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
491 if (mipi_config->target_burst_mode_freq <
493 DRM_ERROR("Burst mode freq is less than computed\n");
497 burst_mode_ratio = DIV_ROUND_UP(
498 mipi_config->target_burst_mode_freq * 100,
501 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
503 DRM_ERROR("Burst mode target is not set\n");
507 burst_mode_ratio = 100;
509 intel_dsi->burst_mode_ratio = burst_mode_ratio;
510 intel_dsi->pclk = pclk;
512 bitrate = (pclk * bpp) / intel_dsi->lane_count;
514 switch (intel_dsi->escape_clk_div) {
530 switch (intel_dsi->lane_count) {
533 extra_byte_count = 2;
536 extra_byte_count = 4;
540 extra_byte_count = 3;
545 * ui(s) = 1/f [f in hz]
546 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
550 ui_num = NS_KHZ_RATIO;
553 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
554 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
558 * LP byte clock = TLPX/ (8UI)
560 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
562 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
564 * Since txddrclkhs_i is 2xUI, all the count values programmed in
565 * DPHY param register are divided by 2
569 ths_prepare_ns = max(mipi_config->ths_prepare,
570 mipi_config->tclk_prepare);
571 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
573 /* exit zero count */
574 exit_zero_cnt = DIV_ROUND_UP(
575 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
580 * Exit zero is unified val ths_zero and ths_exit
581 * minimum value for ths_exit = 110ns
582 * min (exit_zero_cnt * 2) = 110/UI
583 * exit_zero_cnt = 55/UI
585 if (exit_zero_cnt < (55 * ui_den / ui_num))
586 if ((55 * ui_den) % ui_num)
590 clk_zero_cnt = DIV_ROUND_UP(
591 (tclk_prepare_clkzero - ths_prepare_ns)
592 * ui_den, 2 * ui_num);
595 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
596 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
598 if (prepare_cnt > PREPARE_CNT_MAX ||
599 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
600 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
601 trail_cnt > TRAIL_CNT_MAX)
602 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
604 if (prepare_cnt > PREPARE_CNT_MAX)
605 prepare_cnt = PREPARE_CNT_MAX;
607 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
608 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
610 if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
611 clk_zero_cnt = CLK_ZERO_CNT_MAX;
613 if (trail_cnt > TRAIL_CNT_MAX)
614 trail_cnt = TRAIL_CNT_MAX;
617 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
618 clk_zero_cnt << 8 | prepare_cnt;
621 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
622 * + 10UI + Extra Byte Count
624 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
625 * Extra Byte Count is calculated according to number of lanes.
626 * High Low Switch Count is the Max of LP to HS and
627 * HS to LP switch count
630 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
634 * The comment above does not match with the code */
635 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
636 exit_zero_cnt * 2 + 10, 8);
638 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
640 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
641 intel_dsi->hs_to_lp_count += extra_byte_count;
644 /* LP -> HS for clock lanes
645 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
647 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
648 * 2(in UI) + extra byte count
649 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
650 * 8 + extra byte count
652 intel_dsi->clk_lp_to_hs_count =
654 4 * tlpx_ui + prepare_cnt * 2 +
658 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
660 /* HS->LP for Clock Lanes
661 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
663 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
664 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
667 intel_dsi->clk_hs_to_lp_count =
668 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
670 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
672 DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
673 DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
674 "disabled" : "enabled");
675 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
676 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
677 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
678 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
679 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
681 DRM_DEBUG_KMS("Dual link: NONE\n");
682 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
683 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
684 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
685 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
686 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
687 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
688 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
689 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
690 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
691 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
692 DRM_DEBUG_KMS("BTA %s\n",
693 intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
694 "disabled" : "enabled");
696 /* delays in VBT are in unit of 100us, so need to convert
698 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
699 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
700 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
701 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
702 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
703 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
705 /* This is cheating a bit with the cleanup. */
706 vbt_panel = kzalloc(sizeof(*vbt_panel), GFP_KERNEL);
710 vbt_panel->intel_dsi = intel_dsi;
711 drm_panel_init(&vbt_panel->panel);
712 vbt_panel->panel.funcs = &vbt_panel_funcs;
713 drm_panel_add(&vbt_panel->panel);
715 /* a regular driver would get the device in probe */
716 for_each_dsi_port(port, intel_dsi->ports) {
717 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
720 return &vbt_panel->panel;