2 * Copyright 1996 Massachusetts Institute of Technology
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29 * $FreeBSD: src/sys/i386/i386/perfmon.c,v 1.21 1999/09/25 18:24:04 phk Exp $
30 * $DragonFly: src/sys/platform/pc32/i386/perfmon.c,v 1.11 2008/05/10 17:24:07 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/device.h>
38 #include <sys/fcntl.h>
42 #include <machine/cputypes.h>
44 #include <machine/clock.h>
45 #include <machine/perfmon.h>
47 static int perfmon_inuse;
48 static int perfmon_cpuok;
50 static int msr_ctl[NPMC];
52 static int msr_pmc[NPMC];
53 static unsigned int ctl_shadow[NPMC];
54 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
55 static int (*writectl)(int);
57 static int writectl5(int);
58 static int writectl6(int);
61 static d_close_t perfmon_close;
62 static d_open_t perfmon_open;
63 static d_ioctl_t perfmon_ioctl;
65 #define CDEV_MAJOR 2 /* We're really a minor of mem.c */
66 static struct dev_ops perfmon_ops = {
67 { "perfmon", CDEV_MAJOR, 0 },
68 .d_open = perfmon_open,
69 .d_close = perfmon_close,
70 .d_ioctl = perfmon_ioctl,
74 * Initialize the device ops for user access to the perfmon. This must
75 * be done late in the boot sequence.
77 * NOTE: The perfmon is really a minor of the mem major. Perfmon
81 perfmon_driver_init(void *unused __unused)
83 dev_ops_add(&perfmon_ops, 0xf0, 32);
84 make_dev(&perfmon_ops, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
87 SYSINIT(perfmondrv, SI_SUB_DRIVERS, SI_ORDER_ANY, perfmon_driver_init, NULL)
90 * This is called in early boot, after cpu_class has been set up.
103 writectl = writectl5;
111 writectl = writectl6;
124 return perfmon_cpuok;
128 perfmon_setup(int pmc, unsigned int control)
130 if (pmc < 0 || pmc >= NPMC)
133 perfmon_inuse |= (1 << pmc);
134 control &= ~(PMCF_SYS_FLAGS << 16);
135 mpintr_lock(); /* doesn't have to be mpintr_lock YYY */
136 ctl_shadow[pmc] = control;
138 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
144 perfmon_get(int pmc, unsigned int *control)
146 if (pmc < 0 || pmc >= NPMC)
149 if (perfmon_inuse & (1 << pmc)) {
150 *control = ctl_shadow[pmc];
153 return EBUSY; /* XXX reversed sense */
157 perfmon_fini(int pmc)
159 if (pmc < 0 || pmc >= NPMC)
162 if (perfmon_inuse & (1 << pmc)) {
165 perfmon_inuse &= ~(1 << pmc);
168 return EBUSY; /* XXX reversed sense */
172 perfmon_start(int pmc)
174 if (pmc < 0 || pmc >= NPMC)
177 if (perfmon_inuse & (1 << pmc)) {
178 mpintr_lock(); /* doesn't have to be mpintr YYY */
179 ctl_shadow[pmc] |= (PMCF_EN << 16);
180 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
189 perfmon_stop(int pmc)
191 if (pmc < 0 || pmc >= NPMC)
194 if (perfmon_inuse & (1 << pmc)) {
196 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
197 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
206 perfmon_read(int pmc, quad_t *val)
208 if (pmc < 0 || pmc >= NPMC)
211 if (perfmon_inuse & (1 << pmc)) {
212 if (ctl_shadow[pmc] & (PMCF_EN << 16))
213 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
215 *val = pmc_shadow[pmc];
223 perfmon_reset(int pmc)
225 if (pmc < 0 || pmc >= NPMC)
228 if (perfmon_inuse & (1 << pmc)) {
229 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
237 * Unfortunately, the performance-monitoring registers are laid out
238 * differently in the P5 and P6. We keep everything in P6 format
239 * internally (except for the event code), and convert to P5
240 * format as needed on those CPUs. The writectl function pointer
241 * is set up to point to one of these functions by perfmon_init().
246 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
247 wrmsr(msr_ctl[pmc], 0);
249 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
254 #define P5FLAG_P 0x200
255 #define P5FLAG_E 0x100
256 #define P5FLAG_USR 0x80
257 #define P5FLAG_OS 0x40
264 if (ctl_shadow[1] & (PMCF_EN << 16)) {
265 if (ctl_shadow[1] & (PMCF_USR << 16))
266 newval |= P5FLAG_USR << 16;
267 if (ctl_shadow[1] & (PMCF_OS << 16))
268 newval |= P5FLAG_OS << 16;
269 if (!(ctl_shadow[1] & (PMCF_E << 16)))
270 newval |= P5FLAG_E << 16;
271 newval |= (ctl_shadow[1] & 0x3f) << 16;
273 if (ctl_shadow[0] & (PMCF_EN << 16)) {
274 if (ctl_shadow[0] & (PMCF_USR << 16))
275 newval |= P5FLAG_USR;
276 if (ctl_shadow[0] & (PMCF_OS << 16))
278 if (!(ctl_shadow[0] & (PMCF_E << 16)))
280 newval |= ctl_shadow[0] & 0x3f;
283 wrmsr(msr_ctl[0], newval);
284 return 0; /* XXX should check for unimplemented bits */
289 * Now the user-mode interface, called from a subdevice of mem.c.
292 static int writerpmc;
295 perfmon_open(struct dev_open_args *ap)
300 if (ap->a_oflags & FWRITE) {
312 perfmon_close(struct dev_close_args *ap)
314 if (ap->a_fflag & FWRITE) {
317 for (i = 0; i < NPMC; i++) {
318 if (writerpmc & (1 << i))
327 perfmon_ioctl(struct dev_ioctl_args *ap)
329 caddr_t param = ap->a_data;
331 struct pmc_data *pmcd;
332 struct pmc_tstamp *pmct;
338 if (!(ap->a_fflag & FWRITE))
340 pmc = (struct pmc *)param;
342 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
344 writerpmc |= (1 << pmc->pmc_num);
349 pmc = (struct pmc *)param;
350 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
354 if (!(ap->a_fflag & FWRITE))
358 rv = perfmon_start(*ip);
362 if (!(ap->a_fflag & FWRITE))
366 rv = perfmon_stop(*ip);
370 if (!(ap->a_fflag & FWRITE))
374 rv = perfmon_reset(*ip);
378 pmcd = (struct pmc_data *)param;
379 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
383 if (tsc_frequency == 0) {
387 pmct = (struct pmc_tstamp *)param;
388 /* XXX interface loses precision. */
389 pmct->pmct_rate = (int)(tsc_frequency / 1000000);
390 pmct->pmct_value = rdtsc();