2 * Copyright (c) 2011 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/bitops.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
44 #include <bus/pci/pcibus.h>
45 #include <bus/pci/pci_cfgreg.h>
46 #include <bus/pci/pcib_private.h>
52 #include <dev/misc/ecc/ecc_e31200_reg.h>
54 struct ecc_e31200_memctrl {
60 struct ecc_e31200_softc {
63 struct callout ecc_callout;
64 volatile uint8_t *ecc_addr;
67 #define CSR_READ_4(sc, ofs) (*(volatile uint32_t *)((sc)->ecc_addr + (ofs)))
69 #define ecc_printf(sc, fmt, arg...) \
70 device_printf((sc)->ecc_mydev, fmt , ##arg)
72 static int ecc_e31200_probe(device_t);
73 static int ecc_e31200_attach(device_t);
75 static void ecc_e31200_chaninfo(struct ecc_e31200_softc *, uint32_t,
77 static void ecc_e31200_status(struct ecc_e31200_softc *);
78 static void ecc_e31200_callout(void *);
79 static void ecc_e31200_errlog(struct ecc_e31200_softc *);
80 static void ecc_e31200_errlog_ch(struct ecc_e31200_softc *, int, int,
83 static const struct ecc_e31200_memctrl ecc_memctrls[] = {
84 { 0x8086, 0x0108, "Intel E3-1200 memory controller" },
85 { 0, 0, NULL } /* required last entry */
88 static device_method_t ecc_e31200_methods[] = {
89 /* Device interface */
90 DEVMETHOD(device_probe, ecc_e31200_probe),
91 DEVMETHOD(device_attach, ecc_e31200_attach),
92 DEVMETHOD(device_shutdown, bus_generic_shutdown),
93 DEVMETHOD(device_suspend, bus_generic_suspend),
94 DEVMETHOD(device_resume, bus_generic_resume),
98 static driver_t ecc_e31200_driver = {
101 sizeof(struct ecc_e31200_softc)
103 static devclass_t ecc_devclass;
104 DRIVER_MODULE(ecc_e31200, hostb, ecc_e31200_driver, ecc_devclass, NULL, NULL);
105 MODULE_DEPEND(ecc_e31200, pci, 1, 1, 1);
108 ecc_e31200_probe(device_t dev)
110 const struct ecc_e31200_memctrl *mc;
113 vid = pci_get_vendor(dev);
114 did = pci_get_device(dev);
116 for (mc = ecc_memctrls; mc->desc != NULL; ++mc) {
117 if (mc->vid == vid && mc->did == did) {
118 struct ecc_e31200_softc *sc = device_get_softc(dev);
120 device_set_desc(dev, mc->desc);
122 sc->ecc_device = device_get_parent(dev);
130 ecc_e31200_attach(device_t dev)
132 struct ecc_e31200_softc *sc = device_get_softc(dev);
133 uint32_t capa, dmfc, mch_barlo, mch_barhi;
137 dev = sc->ecc_device; /* XXX */
139 bus = pci_get_bus(dev);
140 slot = pci_get_slot(dev);
142 capa = pcib_read_config(dev, bus, slot, 0, PCI_E31200_CAPID0_A, 4);
144 dmfc = __SHIFTOUT(capa, PCI_E31200_CAPID0_A_DMFC);
145 if (dmfc == PCI_E31200_CAPID0_A_DMFC_1333) {
146 ecc_printf(sc, "CAP DDR3 1333 ");
147 } else if (dmfc == PCI_E31200_CAPID0_A_DMFC_1067) {
148 ecc_printf(sc, "CAP DDR3 1067 ");
149 } else if (dmfc == PCI_E31200_CAPID0_A_DMFC_ALL) {
150 ecc_printf(sc, "no CAP ");
152 ecc_printf(sc, "unknown DMFC %#x\n", dmfc);
156 if (capa & PCI_E31200_CAPID0_A_ECCDIS) {
157 kprintf("NON-ECC\n");
163 mch_barlo = pcib_read_config(dev, bus, slot, 0,
164 PCI_E31200_MCHBAR_LO, 4);
165 mch_barhi = pcib_read_config(dev, bus, slot, 0,
166 PCI_E31200_MCHBAR_HI, 4);
168 mch_bar = (uint64_t)mch_barlo | (((uint64_t)mch_barhi) << 32);
170 ecc_printf(sc, "MCHBAR %jx\n", (uintmax_t)mch_bar);
172 if (mch_bar & PCI_E31200_MCHBAR_LO_EN) {
173 uint64_t map_addr = mch_bar & PCI_E31200_MCHBAR_ADDRMASK;
174 uint32_t dimm_ch0, dimm_ch1;
176 sc->ecc_addr = pmap_mapdev_uncacheable(map_addr,
180 ecc_printf(sc, "LOG0_C0 %#x\n",
181 CSR_READ_4(sc, MCH_E31200_ERRLOG0_C0));
182 ecc_printf(sc, "LOG0_C1 %#x\n",
183 CSR_READ_4(sc, MCH_E31200_ERRLOG0_C1));
186 dimm_ch0 = CSR_READ_4(sc, MCH_E31200_DIMM_CH0);
187 dimm_ch1 = CSR_READ_4(sc, MCH_E31200_DIMM_CH1);
190 ecc_e31200_chaninfo(sc, dimm_ch0, "channel0");
191 ecc_e31200_chaninfo(sc, dimm_ch1, "channel1");
194 if (((dimm_ch0 | dimm_ch1) & MCH_E31200_DIMM_ECC) == 0) {
195 ecc_printf(sc, "No ECC active\n");
196 pmap_unmapdev((vm_offset_t)sc->ecc_addr,
202 ecc_e31200_status(sc);
203 callout_init_mp(&sc->ecc_callout);
204 callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
210 ecc_e31200_callout(void *xsc)
212 struct ecc_e31200_softc *sc = xsc;
214 ecc_e31200_status(sc);
215 callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
219 ecc_e31200_status(struct ecc_e31200_softc *sc)
221 device_t dev = sc->ecc_device;
225 bus = pci_get_bus(dev);
226 slot = pci_get_slot(dev);
228 errsts = pcib_read_config(dev, bus, slot, 0, 0xc8, 2);
230 ecc_printf(sc, "Uncorrectable ECC error\n");
231 else if (errsts & 0x1)
232 ecc_printf(sc, "Correctable ECC error\n");
235 if (sc->ecc_addr != NULL)
236 ecc_e31200_errlog(sc);
238 /* Clear pending errors */
239 pcib_write_config(dev, bus, slot, 0, 0xc8, errsts, 2);
244 ecc_e31200_chaninfo(struct ecc_e31200_softc *sc, uint32_t dimm_ch,
247 int size_a, size_b, ecc;
249 size_a = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_A_SIZE);
251 ecc_printf(sc, "%s, DIMM A %dMB %s %s\n", desc,
252 size_a * MCH_E31200_DIMM_SIZE_UNIT,
253 (dimm_ch & MCH_E31200_DIMM_A_X16) ? "X16" : "X8",
254 (dimm_ch & MCH_E31200_DIMM_A_DUAL_RANK) ?
258 size_b = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_B_SIZE);
260 ecc_printf(sc, "%s, DIMM B %dMB %s %s\n", desc,
261 size_b * MCH_E31200_DIMM_SIZE_UNIT,
262 (dimm_ch & MCH_E31200_DIMM_B_X16) ? "X16" : "X8",
263 (dimm_ch & MCH_E31200_DIMM_B_DUAL_RANK) ?
267 if (size_a == 0 && size_b == 0)
270 ecc = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_ECC);
271 if (ecc == MCH_E31200_DIMM_ECC_NONE)
272 ecc_printf(sc, "%s, no ECC active\n", desc);
273 else if (ecc == MCH_E31200_DIMM_ECC_IO)
274 ecc_printf(sc, "%s, ECC active IO\n", desc);
275 else if (ecc == MCH_E31200_DIMM_ECC_LOGIC)
276 ecc_printf(sc, "%s, ECC active logic\n", desc);
278 ecc_printf(sc, "%s, ECC active IO/logic\n", desc);
280 if (dimm_ch & (MCH_E31200_DIMM_ENHI | MCH_E31200_DIMM_RI)) {
281 ecc_printf(sc, "%s", desc);
282 if (dimm_ch & MCH_E31200_DIMM_RI)
283 kprintf(", rank interleave");
284 if (dimm_ch & MCH_E31200_DIMM_ENHI)
285 kprintf(", enhanced interleave");
291 ecc_e31200_errlog(struct ecc_e31200_softc *sc)
293 ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C0, MCH_E31200_ERRLOG1_C0,
295 ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C1, MCH_E31200_ERRLOG1_C1,
300 ecc_e31200_errlog_ch(struct ecc_e31200_softc *sc,
301 int err0_ofs, int err1_ofs, const char *desc)
305 err0 = CSR_READ_4(sc, err0_ofs);
306 if ((err0 & (MCH_E31200_ERRLOG0_CERRSTS | MCH_E31200_ERRLOG0_MERRSTS))
310 err1 = CSR_READ_4(sc, err1_ofs);
312 ecc_printf(sc, "%s error @bank %d, rank %d, chunk %d, syndrome %d, "
313 "row %d, col %d\n", desc,
314 __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRBANK),
315 __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRRANK),
316 __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRCHUNK),
317 __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRSYND),
318 __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRROW),
319 __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRCOL));