3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.7 2005/01/25 19:35:11 dillon Exp $
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
114 #include <sys/param.h>
115 #include <sys/endian.h>
116 #include <sys/systm.h>
117 #include <sys/sockio.h>
118 #include <sys/mbuf.h>
119 #include <sys/malloc.h>
120 #include <sys/module.h>
121 #include <sys/kernel.h>
122 #include <sys/socket.h>
125 #include <net/if_arp.h>
126 #include <net/ethernet.h>
127 #include <net/if_dl.h>
128 #include <net/if_media.h>
129 #include <net/if_types.h>
130 #include <net/vlan/if_vlan_var.h>
134 #include <machine/bus_pio.h>
135 #include <machine/bus_memio.h>
136 #include <machine/bus.h>
137 #include <machine/resource.h>
139 #include <sys/rman.h>
141 #include <dev/netif/mii_layer/mii.h>
142 #include <dev/netif/mii_layer/miivar.h>
144 #include <bus/pci/pcireg.h>
145 #include <bus/pci/pcivar.h>
147 /* "controller miibus0" required. See GENERIC if you get errors here. */
148 #include "miibus_if.h"
150 #include <dev/netif/re/if_rereg.h>
153 * The hardware supports checksumming but, as usual, some chipsets screw it
154 * all up and produce bogus packets, so we disable it by default.
156 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
157 #define RE_DISABLE_HWCSUM
160 * Various supported device vendors/types and their names.
162 static struct re_type re_devs[] = {
163 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS,
164 "RealTek 8139C+ 10/100BaseTX" },
165 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169,
166 "RealTek 8169 Gigabit Ethernet" },
167 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S,
168 "RealTek 8169S Single-chip Gigabit Ethernet" },
169 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S,
170 "RealTek 8110S Single-chip Gigabit Ethernet" },
174 static struct re_hwrev re_hwrevs[] = {
175 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"},
176 { RE_HWREV_8169, RE_8169, "8169"},
177 { RE_HWREV_8169S, RE_8169, "8169S"},
178 { RE_HWREV_8110S, RE_8169, "8110S"},
182 static int re_probe(device_t);
183 static int re_attach(device_t);
184 static int re_detach(device_t);
186 static int re_encap(struct re_softc *, struct mbuf *, int *);
188 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
189 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
191 static int re_allocmem(device_t, struct re_softc *);
192 static int re_newbuf(struct re_softc *, int, struct mbuf *);
193 static int re_rx_list_init(struct re_softc *);
194 static int re_tx_list_init(struct re_softc *);
195 static void re_rxeof(struct re_softc *);
196 static void re_txeof(struct re_softc *);
197 static void re_intr(void *);
198 static void re_tick(void *);
199 static void re_start(struct ifnet *);
200 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
201 static void re_init(void *);
202 static void re_stop(struct re_softc *);
203 static void re_watchdog(struct ifnet *);
204 static int re_suspend(device_t);
205 static int re_resume(device_t);
206 static void re_shutdown(device_t);
207 static int re_ifmedia_upd(struct ifnet *);
208 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
210 static void re_eeprom_putbyte(struct re_softc *, int);
211 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
212 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int);
213 static int re_gmii_readreg(device_t, int, int);
214 static int re_gmii_writereg(device_t, int, int, int);
216 static int re_miibus_readreg(device_t, int, int);
217 static int re_miibus_writereg(device_t, int, int, int);
218 static void re_miibus_statchg(device_t);
220 static void re_setmulti(struct re_softc *);
221 static void re_reset(struct re_softc *);
223 static int re_diag(struct re_softc *);
225 static device_method_t re_methods[] = {
226 /* Device interface */
227 DEVMETHOD(device_probe, re_probe),
228 DEVMETHOD(device_attach, re_attach),
229 DEVMETHOD(device_detach, re_detach),
230 DEVMETHOD(device_suspend, re_suspend),
231 DEVMETHOD(device_resume, re_resume),
232 DEVMETHOD(device_shutdown, re_shutdown),
235 DEVMETHOD(bus_print_child, bus_generic_print_child),
236 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
239 DEVMETHOD(miibus_readreg, re_miibus_readreg),
240 DEVMETHOD(miibus_writereg, re_miibus_writereg),
241 DEVMETHOD(miibus_statchg, re_miibus_statchg),
246 static driver_t re_driver = {
249 sizeof(struct re_softc)
252 static devclass_t re_devclass;
254 DECLARE_DUMMY_MODULE(if_re);
255 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
256 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
257 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
260 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
263 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
266 * Send a read command and address to the EEPROM, check for ACK.
269 re_eeprom_putbyte(struct re_softc *sc, int addr)
273 d = addr | sc->re_eecmd_read;
276 * Feed in each bit and strobe the clock.
278 for (i = 0x400; i != 0; i >>= 1) {
280 EE_SET(RE_EE_DATAIN);
282 EE_CLR(RE_EE_DATAIN);
292 * Read a word of data stored in the EEPROM at address 'addr.'
295 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
300 /* Enter EEPROM access mode. */
301 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
304 * Send address of word we want to read.
306 re_eeprom_putbyte(sc, addr);
308 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
311 * Start reading bits from EEPROM.
313 for (i = 0x8000; i != 0; i >>= 1) {
316 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
322 /* Turn off EEPROM access mode. */
323 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
329 * Read a sequence of words from the EEPROM.
332 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap)
335 uint16_t word = 0, *ptr;
337 for (i = 0; i < cnt; i++) {
338 re_eeprom_getword(sc, off + i, &word);
339 ptr = (u_int16_t *)(dest + (i * 2));
341 *ptr = be16toh(word);
348 re_gmii_readreg(device_t dev, int phy, int reg)
350 struct re_softc *sc = device_get_softc(dev);
357 /* Let the rgephy driver read the GMEDIASTAT register */
359 if (reg == RE_GMEDIASTAT)
360 return(CSR_READ_1(sc, RE_GMEDIASTAT));
362 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
365 for (i = 0; i < RE_TIMEOUT; i++) {
366 rval = CSR_READ_4(sc, RE_PHYAR);
367 if (rval & RE_PHYAR_BUSY)
372 if (i == RE_TIMEOUT) {
373 device_printf(dev, "PHY read failed\n");
377 return(rval & RE_PHYAR_PHYDATA);
381 re_gmii_writereg(device_t dev, int phy, int reg, int data)
383 struct re_softc *sc = device_get_softc(dev);
387 CSR_WRITE_4(sc, RE_PHYAR,
388 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
391 for (i = 0; i < RE_TIMEOUT; i++) {
392 rval = CSR_READ_4(sc, RE_PHYAR);
393 if ((rval & RE_PHYAR_BUSY) == 0)
399 device_printf(dev, "PHY write failed\n");
405 re_miibus_readreg(device_t dev, int phy, int reg)
407 struct re_softc *sc = device_get_softc(dev);
409 uint16_t re8139_reg = 0;
411 if (sc->re_type == RE_8169) {
412 rval = re_gmii_readreg(dev, phy, reg);
416 /* Pretend the internal PHY is only at address 0 */
422 re8139_reg = RE_BMCR;
425 re8139_reg = RE_BMSR;
428 re8139_reg = RE_ANAR;
431 re8139_reg = RE_ANER;
434 re8139_reg = RE_LPAR;
440 * Allow the rlphy driver to read the media status
441 * register. If we have a link partner which does not
442 * support NWAY, this is the register which will tell
443 * us the results of parallel detection.
446 return(CSR_READ_1(sc, RE_MEDIASTAT));
448 device_printf(dev, "bad phy register\n");
451 rval = CSR_READ_2(sc, re8139_reg);
456 re_miibus_writereg(device_t dev, int phy, int reg, int data)
458 struct re_softc *sc= device_get_softc(dev);
459 u_int16_t re8139_reg = 0;
461 if (sc->re_type == RE_8169)
462 return(re_gmii_writereg(dev, phy, reg, data));
464 /* Pretend the internal PHY is only at address 0 */
470 re8139_reg = RE_BMCR;
473 re8139_reg = RE_BMSR;
476 re8139_reg = RE_ANAR;
479 re8139_reg = RE_ANER;
482 re8139_reg = RE_LPAR;
488 device_printf(dev, "bad phy register\n");
491 CSR_WRITE_2(sc, re8139_reg, data);
496 re_miibus_statchg(device_t dev)
501 * Program the 64-bit multicast hash filter.
504 re_setmulti(struct re_softc *sc)
506 struct ifnet *ifp = &sc->arpcom.ac_if;
508 uint32_t hashes[2] = { 0, 0 };
509 struct ifmultiaddr *ifma;
513 rxfilt = CSR_READ_4(sc, RE_RXCFG);
515 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
516 rxfilt |= RE_RXCFG_RX_MULTI;
517 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
518 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
519 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
523 /* first, zot all the existing hash bits */
524 CSR_WRITE_4(sc, RE_MAR0, 0);
525 CSR_WRITE_4(sc, RE_MAR4, 0);
527 /* now program new ones */
528 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
529 if (ifma->ifma_addr->sa_family != AF_LINK)
531 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
532 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
534 hashes[0] |= (1 << h);
536 hashes[1] |= (1 << (h - 32));
541 rxfilt |= RE_RXCFG_RX_MULTI;
543 rxfilt &= ~RE_RXCFG_RX_MULTI;
545 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
546 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
547 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
551 re_reset(struct re_softc *sc)
555 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
557 for (i = 0; i < RE_TIMEOUT; i++) {
559 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
563 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
565 CSR_WRITE_1(sc, 0x82, 1);
569 * The following routine is designed to test for a defect on some
570 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
571 * lines connected to the bus, however for a 32-bit only card, they
572 * should be pulled high. The result of this defect is that the
573 * NIC will not work right if you plug it into a 64-bit slot: DMA
574 * operations will be done with 64-bit transfers, which will fail
575 * because the 64-bit data lines aren't connected.
577 * There's no way to work around this (short of talking a soldering
578 * iron to the board), however we can detect it. The method we use
579 * here is to put the NIC into digital loopback mode, set the receiver
580 * to promiscuous mode, and then try to send a frame. We then compare
581 * the frame data we sent to what was received. If the data matches,
582 * then the NIC is working correctly, otherwise we know the user has
583 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
584 * slot. In the latter case, there's no way the NIC can work correctly,
585 * so we print out a message on the console and abort the device attach.
589 re_diag(struct re_softc *sc)
591 struct ifnet *ifp = &sc->arpcom.ac_if;
593 struct ether_header *eh;
594 struct re_desc *cur_rx;
597 int total_len, i, error = 0;
598 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
599 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
601 /* Allocate a single mbuf */
603 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
608 * Initialize the NIC in test mode. This sets the chip up
609 * so that it can send and receive frames, but performs the
610 * following special functions:
611 * - Puts receiver in promiscuous mode
612 * - Enables digital loopback mode
613 * - Leaves interrupts turned off
616 ifp->if_flags |= IFF_PROMISC;
623 /* Put some data in the mbuf */
625 eh = mtod(m0, struct ether_header *);
626 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
627 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
628 eh->ether_type = htons(ETHERTYPE_IP);
629 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
632 * Queue the packet, start transmission.
633 * Note: IF_HANDOFF() ultimately calls re_start() for us.
636 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
637 IF_HANDOFF(&ifp->if_snd, m0, ifp);
640 /* Wait for it to propagate through the chip */
643 for (i = 0; i < RE_TIMEOUT; i++) {
644 status = CSR_READ_2(sc, RE_ISR);
645 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
646 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
651 if (i == RE_TIMEOUT) {
652 if_printf(ifp, "diagnostic failed to receive packet "
653 "in loopback mode\n");
659 * The packet should have been dumped into the first
660 * entry in the RX DMA ring. Grab it from there.
663 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
664 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
665 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
666 BUS_DMASYNC_POSTWRITE);
667 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
669 m0 = sc->re_ldata.re_rx_mbuf[0];
670 sc->re_ldata.re_rx_mbuf[0] = NULL;
671 eh = mtod(m0, struct ether_header *);
673 cur_rx = &sc->re_ldata.re_rx_list[0];
674 total_len = RE_RXBYTES(cur_rx);
675 rxstat = le32toh(cur_rx->re_cmdstat);
677 if (total_len != ETHER_MIN_LEN) {
678 if_printf(ifp, "diagnostic failed, received short packet\n");
683 /* Test that the received packet data matches what we sent. */
685 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
686 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
687 be16toh(eh->ether_type) != ETHERTYPE_IP) {
688 if_printf(ifp, "WARNING, DMA FAILURE!\n");
689 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
690 dst, ":", src, ":", ETHERTYPE_IP);
691 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
692 eh->ether_dhost, ":", eh->ether_shost, ":",
693 ntohs(eh->ether_type));
694 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
695 "into a 64-bit PCI slot.\n");
696 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
697 "for proper operation.\n");
698 if_printf(ifp, "Read the re(4) man page for more details.\n");
703 /* Turn interface off, release resources */
706 ifp->if_flags &= ~IFF_PROMISC;
715 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
716 * IDs against our list and return a device name if we find a match.
719 re_probe(device_t dev)
725 uint16_t vendor, product;
729 vendor = pci_get_vendor(dev);
730 product = pci_get_device(dev);
732 for (t = re_devs; t->re_name != NULL; t++) {
733 if (product == t->re_did && vendor == t->re_vid)
738 * Check if we found a RealTek device.
740 if (t->re_name == NULL)
744 * Temporarily map the I/O space so we can read the chip ID register.
746 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
748 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
750 if (sc->re_res == NULL) {
751 device_printf(dev, "couldn't map ports/memory\n");
756 sc->re_btag = rman_get_bustag(sc->re_res);
757 sc->re_bhandle = rman_get_bushandle(sc->re_res);
759 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
760 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
764 * and continue matching for the specific chip...
766 for (; t->re_name != NULL; t++) {
767 if (product == t->re_did && vendor == t->re_vid &&
768 t->re_basetype == hwrev) {
769 device_set_desc(dev, t->re_name);
777 * This routine takes the segment list provided as the result of
778 * a bus_dma_map_load() operation and assigns the addresses/lengths
779 * to RealTek DMA descriptors. This can be called either by the RX
780 * code or the TX code. In the RX case, we'll probably wind up mapping
781 * at most one segment. For the TX case, there could be any number of
782 * segments since TX packets may span multiple mbufs. In either case,
783 * if the number of segments is larger than the re_maxsegs limit
784 * specified by the caller, we abort the mapping operation. Sadly,
785 * whoever designed the buffer mapping API did not provide a way to
786 * return an error from here, so we have to fake it a bit.
790 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
791 bus_size_t mapsize, int error)
793 struct re_dmaload_arg *ctx;
794 struct re_desc *d = NULL;
803 /* Signal error to caller if there's too many segments */
804 if (nseg > ctx->re_maxsegs) {
810 * Map the segment array into descriptors. Note that we set the
811 * start-of-frame and end-of-frame markers for either TX or RX, but
812 * they really only have meaning in the TX case. (In the RX case,
813 * it's the chip that tells us where packets begin and end.)
814 * We also keep track of the end of the ring and set the
815 * end-of-ring bits as needed, and we set the ownership bits
816 * in all except the very first descriptor. (The caller will
817 * set this descriptor later when it start transmission or
822 d = &ctx->re_ring[idx];
823 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
827 cmdstat = segs[i].ds_len;
828 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
829 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
831 cmdstat |= RE_TDESC_CMD_SOF;
833 cmdstat |= RE_TDESC_CMD_OWN;
834 if (idx == (RE_RX_DESC_CNT - 1))
835 cmdstat |= RE_TDESC_CMD_EOR;
836 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
843 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
844 ctx->re_maxsegs = nseg;
849 * Map a single buffer address.
853 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
860 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
862 *addr = segs->ds_addr;
866 re_allocmem(device_t dev, struct re_softc *sc)
871 * Allocate map for RX mbufs.
874 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
875 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
876 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
877 &sc->re_ldata.re_mtag);
879 device_printf(dev, "could not allocate dma tag\n");
884 * Allocate map for TX descriptor list.
886 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
887 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
888 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
889 &sc->re_ldata.re_tx_list_tag);
891 device_printf(dev, "could not allocate dma tag\n");
895 /* Allocate DMA'able memory for the TX ring */
897 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
898 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
899 &sc->re_ldata.re_tx_list_map);
901 device_printf(dev, "could not allocate TX ring\n");
905 /* Load the map for the TX ring. */
907 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
908 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
909 RE_TX_LIST_SZ, re_dma_map_addr,
910 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
912 device_printf(dev, "could not get addres of TX ring\n");
916 /* Create DMA maps for TX buffers */
918 for (i = 0; i < RE_TX_DESC_CNT; i++) {
919 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
920 &sc->re_ldata.re_tx_dmamap[i]);
922 device_printf(dev, "can't create DMA map for TX\n");
928 * Allocate map for RX descriptor list.
930 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
931 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
932 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
933 &sc->re_ldata.re_rx_list_tag);
935 device_printf(dev, "could not allocate dma tag\n");
939 /* Allocate DMA'able memory for the RX ring */
941 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
942 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
943 &sc->re_ldata.re_rx_list_map);
945 device_printf(dev, "could not allocate RX ring\n");
949 /* Load the map for the RX ring. */
951 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
952 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
953 RE_TX_LIST_SZ, re_dma_map_addr,
954 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
956 device_printf(dev, "could not get address of RX ring\n");
960 /* Create DMA maps for RX buffers */
962 for (i = 0; i < RE_RX_DESC_CNT; i++) {
963 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
964 &sc->re_ldata.re_rx_dmamap[i]);
966 device_printf(dev, "can't create DMA map for RX\n");
975 * Attach the interface. Allocate softc structures, do ifmedia
976 * setup and ethernet/BPF attach.
979 re_attach(device_t dev)
981 struct re_softc *sc = device_get_softc(dev);
983 struct re_hwrev *hw_rev;
984 uint8_t eaddr[ETHER_ADDR_LEN];
986 u_int16_t re_did = 0;
987 int error = 0, rid, i;
989 callout_init(&sc->re_timer);
993 * Handle power management nonsense.
996 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
997 uint32_t membase, irq;
999 /* Save important PCI config data. */
1000 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1001 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1003 /* Reset the power state. */
1004 device_printf(dev, "chip is is in D%d power mode "
1005 "-- setting to D0\n", pci_get_powerstate(dev));
1007 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1009 /* Restore PCI config data. */
1010 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1011 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1015 * Map control/status registers.
1017 pci_enable_busmaster(dev);
1020 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1023 if (sc->re_res == NULL) {
1024 device_printf(dev, "couldn't map ports/memory\n");
1029 sc->re_btag = rman_get_bustag(sc->re_res);
1030 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1032 /* Allocate interrupt */
1034 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1035 RF_SHAREABLE | RF_ACTIVE);
1037 if (sc->re_irq == NULL) {
1038 device_printf(dev, "couldn't map interrupt\n");
1043 /* Reset the adapter. */
1046 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1047 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1048 if (hw_rev->re_rev == hwrev) {
1049 sc->re_type = hw_rev->re_type;
1054 if (sc->re_type == RE_8169) {
1055 /* Set RX length mask */
1056 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1058 /* Force station address autoload from the EEPROM */
1059 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD);
1060 for (i = 0; i < RE_TIMEOUT; i++) {
1061 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0)
1065 if (i == RE_TIMEOUT)
1066 device_printf(dev, "eeprom autoload timed out\n");
1068 for (i = 0; i < ETHER_ADDR_LEN; i++)
1069 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
1073 /* Set RX length mask */
1074 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1076 sc->re_eecmd_read = RE_EECMD_READ_6BIT;
1077 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1078 if (re_did != 0x8129)
1079 sc->re_eecmd_read = RE_EECMD_READ_8BIT;
1082 * Get station address from the EEPROM.
1084 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0);
1085 for (i = 0; i < 3; i++) {
1086 eaddr[(i * 2) + 0] = as[i] & 0xff;
1087 eaddr[(i * 2) + 1] = as[i] >> 8;
1092 * Allocate the parent bus DMA tag appropriate for PCI.
1094 #define RE_NSEG_NEW 32
1095 error = bus_dma_tag_create(NULL, /* parent */
1096 1, 0, /* alignment, boundary */
1097 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1098 BUS_SPACE_MAXADDR, /* highaddr */
1099 NULL, NULL, /* filter, filterarg */
1100 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1101 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1102 BUS_DMA_ALLOCNOW, /* flags */
1103 &sc->re_parent_tag);
1107 error = re_allocmem(dev, sc);
1113 if (mii_phy_probe(dev, &sc->re_miibus,
1114 re_ifmedia_upd, re_ifmedia_sts)) {
1115 device_printf(dev, "MII without any phy!\n");
1120 ifp = &sc->arpcom.ac_if;
1122 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1123 ifp->if_mtu = ETHERMTU;
1124 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1125 ifp->if_ioctl = re_ioctl;
1126 ifp->if_capabilities = IFCAP_VLAN_MTU;
1127 ifp->if_start = re_start;
1128 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1129 #ifdef DEVICE_POLLING
1130 ifp->if_capabilities |= IFCAP_POLLING;
1132 ifp->if_watchdog = re_watchdog;
1133 ifp->if_init = re_init;
1134 if (sc->re_type == RE_8169)
1135 ifp->if_baudrate = 1000000000;
1137 ifp->if_baudrate = 100000000;
1138 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN;
1139 #ifdef RE_DISABLE_HWCSUM
1140 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1141 ifp->if_hwassist = 0;
1143 ifp->if_capenable = ifp->if_capabilities;
1144 ifp->if_hwassist = RE_CSUM_FEATURES;
1148 * Call MI attach routine.
1150 ether_ifattach(ifp, eaddr);
1152 /* Perform hardware diagnostic. */
1153 error = re_diag(sc);
1156 device_printf(dev, "hardware diagnostic failure\n");
1157 ether_ifdetach(ifp);
1161 /* Hook interrupt last to avoid having to lock softc */
1162 error = bus_setup_intr(dev, sc->re_irq, INTR_TYPE_NET, re_intr, sc,
1166 device_printf(dev, "couldn't set up irq\n");
1167 ether_ifdetach(ifp);
1179 * Shutdown hardware and free up resources. This can be called any
1180 * time after the mutex has been initialized. It is called in both
1181 * the error case in attach and the normal detach case so it needs
1182 * to be careful about only freeing resources that have actually been
1186 re_detach(device_t dev)
1188 struct re_softc *sc = device_get_softc(dev);
1189 struct ifnet *ifp = &sc->arpcom.ac_if;
1194 /* These should only be active if attach succeeded */
1195 if (device_is_attached(dev)) {
1197 ether_ifdetach(ifp);
1200 device_delete_child(dev, sc->re_miibus);
1201 bus_generic_detach(dev);
1203 if (sc->re_intrhand)
1204 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1206 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1208 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1211 /* Unload and free the RX DMA ring memory and map */
1213 if (sc->re_ldata.re_rx_list_tag) {
1214 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1215 sc->re_ldata.re_rx_list_map);
1216 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1217 sc->re_ldata.re_rx_list,
1218 sc->re_ldata.re_rx_list_map);
1219 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1222 /* Unload and free the TX DMA ring memory and map */
1224 if (sc->re_ldata.re_tx_list_tag) {
1225 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1226 sc->re_ldata.re_tx_list_map);
1227 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1228 sc->re_ldata.re_tx_list,
1229 sc->re_ldata.re_tx_list_map);
1230 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1233 /* Destroy all the RX and TX buffer maps */
1235 if (sc->re_ldata.re_mtag) {
1236 for (i = 0; i < RE_TX_DESC_CNT; i++)
1237 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1238 sc->re_ldata.re_tx_dmamap[i]);
1239 for (i = 0; i < RE_RX_DESC_CNT; i++)
1240 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1241 sc->re_ldata.re_rx_dmamap[i]);
1242 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1245 /* Unload and free the stats buffer and map */
1247 if (sc->re_ldata.re_stag) {
1248 bus_dmamap_unload(sc->re_ldata.re_stag,
1249 sc->re_ldata.re_rx_list_map);
1250 bus_dmamem_free(sc->re_ldata.re_stag,
1251 sc->re_ldata.re_stats,
1252 sc->re_ldata.re_smap);
1253 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1256 if (sc->re_parent_tag)
1257 bus_dma_tag_destroy(sc->re_parent_tag);
1265 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1267 struct re_dmaload_arg arg;
1268 struct mbuf *n = NULL;
1272 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1277 m->m_data = m->m_ext.ext_buf;
1280 * Initialize mbuf length fields and fixup
1281 * alignment so that the frame payload is
1284 m->m_len = m->m_pkthdr.len = MCLBYTES;
1285 m_adj(m, ETHER_ALIGN);
1291 arg.re_ring = sc->re_ldata.re_rx_list;
1293 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1294 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1295 &arg, BUS_DMA_NOWAIT);
1296 if (error || arg.re_maxsegs != 1) {
1302 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1303 sc->re_ldata.re_rx_mbuf[idx] = m;
1305 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1306 BUS_DMASYNC_PREREAD);
1312 re_tx_list_init(struct re_softc *sc)
1314 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1315 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1317 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1318 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1319 sc->re_ldata.re_tx_prodidx = 0;
1320 sc->re_ldata.re_tx_considx = 0;
1321 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1327 re_rx_list_init(struct re_softc *sc)
1331 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1332 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1334 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1335 error = re_newbuf(sc, i, NULL);
1340 /* Flush the RX descriptors */
1342 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1343 sc->re_ldata.re_rx_list_map,
1344 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1346 sc->re_ldata.re_rx_prodidx = 0;
1347 sc->re_head = sc->re_tail = NULL;
1353 * RX handler for C+ and 8169. For the gigE chips, we support
1354 * the reception of jumbo frames that have been fragmented
1355 * across multiple 2K mbuf cluster buffers.
1358 re_rxeof(struct re_softc *sc)
1360 struct ifnet *ifp = &sc->arpcom.ac_if;
1362 struct re_desc *cur_rx;
1363 uint32_t rxstat, rxvlan;
1366 /* Invalidate the descriptor memory */
1368 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1369 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1371 for (i = sc->re_ldata.re_rx_prodidx;
1372 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1373 cur_rx = &sc->re_ldata.re_rx_list[i];
1374 m = sc->re_ldata.re_rx_mbuf[i];
1375 total_len = RE_RXBYTES(cur_rx);
1376 rxstat = le32toh(cur_rx->re_cmdstat);
1377 rxvlan = le32toh(cur_rx->re_vlanctl);
1379 /* Invalidate the RX mbuf and unload its map */
1381 bus_dmamap_sync(sc->re_ldata.re_mtag,
1382 sc->re_ldata.re_rx_dmamap[i],
1383 BUS_DMASYNC_POSTWRITE);
1384 bus_dmamap_unload(sc->re_ldata.re_mtag,
1385 sc->re_ldata.re_rx_dmamap[i]);
1387 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1388 m->m_len = MCLBYTES - ETHER_ALIGN;
1389 if (sc->re_head == NULL) {
1390 sc->re_head = sc->re_tail = m;
1392 m->m_flags &= ~M_PKTHDR;
1393 sc->re_tail->m_next = m;
1396 re_newbuf(sc, i, NULL);
1401 * NOTE: for the 8139C+, the frame length field
1402 * is always 12 bits in size, but for the gigE chips,
1403 * it is 13 bits (since the max RX frame length is 16K).
1404 * Unfortunately, all 32 bits in the status word
1405 * were already used, so to make room for the extra
1406 * length bit, RealTek took out the 'frame alignment
1407 * error' bit and shifted the other status bits
1408 * over one slot. The OWN, EOR, FS and LS bits are
1409 * still in the same places. We have already extracted
1410 * the frame length and checked the OWN bit, so rather
1411 * than using an alternate bit mapping, we shift the
1412 * status bits one space to the right so we can evaluate
1413 * them using the 8169 status as though it was in the
1414 * same format as that of the 8139C+.
1416 if (sc->re_type == RE_8169)
1419 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1422 * If this is part of a multi-fragment packet,
1423 * discard all the pieces.
1425 if (sc->re_head != NULL) {
1426 m_freem(sc->re_head);
1427 sc->re_head = sc->re_tail = NULL;
1429 re_newbuf(sc, i, m);
1434 * If allocating a replacement mbuf fails,
1435 * reload the current one.
1438 if (re_newbuf(sc, i, NULL)) {
1440 if (sc->re_head != NULL) {
1441 m_freem(sc->re_head);
1442 sc->re_head = sc->re_tail = NULL;
1444 re_newbuf(sc, i, m);
1448 if (sc->re_head != NULL) {
1449 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1451 * Special case: if there's 4 bytes or less
1452 * in this buffer, the mbuf can be discarded:
1453 * the last 4 bytes is the CRC, which we don't
1454 * care about anyway.
1456 if (m->m_len <= ETHER_CRC_LEN) {
1457 sc->re_tail->m_len -=
1458 (ETHER_CRC_LEN - m->m_len);
1461 m->m_len -= ETHER_CRC_LEN;
1462 m->m_flags &= ~M_PKTHDR;
1463 sc->re_tail->m_next = m;
1466 sc->re_head = sc->re_tail = NULL;
1467 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1469 m->m_pkthdr.len = m->m_len =
1470 (total_len - ETHER_CRC_LEN);
1473 m->m_pkthdr.rcvif = ifp;
1475 /* Do RX checksumming if enabled */
1477 if (ifp->if_capenable & IFCAP_RXCSUM) {
1479 /* Check IP header checksum */
1480 if (rxstat & RE_RDESC_STAT_PROTOID)
1481 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1482 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1483 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1485 /* Check TCP/UDP checksum */
1486 if ((RE_TCPPKT(rxstat) &&
1487 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1488 (RE_UDPPKT(rxstat) &&
1489 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1490 m->m_pkthdr.csum_flags |=
1491 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1492 m->m_pkthdr.csum_data = 0xffff;
1496 if (rxvlan & RE_RDESC_VLANCTL_TAG)
1498 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1500 (*ifp->if_input)(ifp, m);
1503 /* Flush the RX DMA ring */
1505 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1506 sc->re_ldata.re_rx_list_map,
1507 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1509 sc->re_ldata.re_rx_prodidx = i;
1513 re_txeof(struct re_softc *sc)
1515 struct ifnet *ifp = &sc->arpcom.ac_if;
1519 /* Invalidate the TX descriptor list */
1521 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1522 sc->re_ldata.re_tx_list_map,
1523 BUS_DMASYNC_POSTREAD);
1525 for (idx = sc->re_ldata.re_tx_considx;
1526 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) {
1527 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1528 if (txstat & RE_TDESC_CMD_OWN)
1532 * We only stash mbufs in the last descriptor
1533 * in a fragment chain, which also happens to
1534 * be the only place where the TX status bits
1537 if (txstat & RE_TDESC_CMD_EOF) {
1538 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1539 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1540 bus_dmamap_unload(sc->re_ldata.re_mtag,
1541 sc->re_ldata.re_tx_dmamap[idx]);
1542 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1543 RE_TDESC_STAT_COLCNT))
1544 ifp->if_collisions++;
1545 if (txstat & RE_TDESC_STAT_TXERRSUM)
1550 sc->re_ldata.re_tx_free++;
1553 /* No changes made to the TX ring, so no flush needed */
1554 if (idx != sc->re_ldata.re_tx_considx) {
1555 sc->re_ldata.re_tx_considx = idx;
1556 ifp->if_flags &= ~IFF_OACTIVE;
1561 * If not all descriptors have been released reaped yet,
1562 * reload the timer so that we will eventually get another
1563 * interrupt that will cause us to re-enter this routine.
1564 * This is done in case the transmitter has gone idle.
1566 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
1567 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1573 struct re_softc *sc = xsc;
1574 struct mii_data *mii;
1579 mii = device_get_softc(sc->re_miibus);
1582 callout_reset(&sc->re_timer, hz, re_tick, sc);
1586 #ifdef DEVICE_POLLING
1588 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1590 struct re_softc *sc = ifp->if_softc;
1592 if ((ifp->if_capenable & IFCAP_POLLING) == 0) {
1593 ether_poll_deregister(ifp);
1594 cmd = POLL_DEREGISTER;
1596 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1597 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1601 sc->rxcycles = count;
1605 if (ifp->if_snd.ifq_head != NULL)
1606 (*ifp->if_start)(ifp);
1608 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1611 status = CSR_READ_2(sc, RE_ISR);
1612 if (status == 0xffff)
1615 CSR_WRITE_2(sc, RE_ISR, status);
1618 * XXX check behaviour on receiver stalls.
1621 if (status & RE_ISR_SYSTEM_ERR) {
1627 #endif /* DEVICE_POLLING */
1632 struct re_softc *sc = arg;
1633 struct ifnet *ifp = &sc->arpcom.ac_if;
1637 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1640 #ifdef DEVICE_POLLING
1641 if (ifp->if_flags & IFF_POLLING)
1643 if ((ifp->if_capenable & IFCAP_POLLING) &&
1644 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */
1645 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1649 #endif /* DEVICE_POLLING */
1654 status = CSR_READ_2(sc, RE_ISR);
1655 /* If the card has gone away the read returns 0xffff. */
1656 if (status == 0xffff)
1659 CSR_WRITE_2(sc, RE_ISR, status);
1661 if ((status & RE_INTRS_CPLUS) == 0)
1664 if (status & RE_ISR_RX_OK)
1667 if (status & RE_ISR_RX_ERR)
1670 if ((status & RE_ISR_TIMEOUT_EXPIRED) ||
1671 (status & RE_ISR_TX_ERR) ||
1672 (status & RE_ISR_TX_DESC_UNAVAIL))
1675 if (status & RE_ISR_SYSTEM_ERR) {
1680 if (status & RE_ISR_LINKCHG)
1684 if (ifp->if_snd.ifq_head != NULL)
1685 (*ifp->if_start)(ifp);
1691 re_encap(sc, m_head, idx)
1692 struct re_softc *sc;
1693 struct mbuf *m_head;
1696 struct ifnet *ifp = &sc->arpcom.ac_if;
1697 struct mbuf *m_new = NULL;
1698 struct re_dmaload_arg arg;
1702 if (sc->re_ldata.re_tx_free <= 4)
1706 * Set up checksum offload. Note: checksum offload bits must
1707 * appear in all descriptors of a multi-descriptor transmit
1708 * attempt. (This is according to testing done with an 8169
1709 * chip. I'm not sure if this is a requirement or a bug.)
1714 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1715 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1716 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1717 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1718 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1719 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1723 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1724 if (arg.re_maxsegs > 4)
1725 arg.re_maxsegs -= 4;
1726 arg.re_ring = sc->re_ldata.re_tx_list;
1728 map = sc->re_ldata.re_tx_dmamap[*idx];
1729 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1730 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1732 if (error && error != EFBIG) {
1733 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1737 /* Too many segments to map, coalesce into a single mbuf */
1739 if (error || arg.re_maxsegs == 0) {
1740 m_new = m_defrag(m_head, MB_DONTWAIT);
1748 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1749 arg.re_ring = sc->re_ldata.re_tx_list;
1751 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1752 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1754 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1760 * Insure that the map for this transmission
1761 * is placed at the array index of the last descriptor
1764 sc->re_ldata.re_tx_dmamap[*idx] =
1765 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1766 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1768 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m_head;
1769 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1772 * Set up hardware VLAN tagging. Note: vlan tag info must
1773 * appear in the first descriptor of a multi-descriptor
1774 * transmission attempt.
1777 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1778 m_head->m_pkthdr.rcvif != NULL &&
1779 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1781 ifv = m_head->m_pkthdr.rcvif->if_softc;
1783 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1784 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1787 /* Transfer ownership of packet to the chip. */
1789 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1790 htole32(RE_TDESC_CMD_OWN);
1791 if (*idx != arg.re_idx)
1792 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1793 htole32(RE_TDESC_CMD_OWN);
1795 RE_DESC_INC(arg.re_idx);
1802 * Main transmit routine for C+ and gigE NICs.
1806 re_start(struct ifnet *ifp)
1808 struct re_softc *sc = ifp->if_softc;
1809 struct mbuf *m_head = NULL;
1814 idx = sc->re_ldata.re_tx_prodidx;
1816 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1817 IF_DEQUEUE(&ifp->if_snd, m_head);
1821 if (re_encap(sc, m_head, &idx)) {
1822 IF_PREPEND(&ifp->if_snd, m_head);
1823 ifp->if_flags |= IFF_OACTIVE;
1828 * If there's a BPF listener, bounce a copy of this frame
1831 BPF_MTAP(ifp, m_head);
1834 /* Flush the TX descriptors */
1835 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1836 sc->re_ldata.re_tx_list_map,
1837 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1839 sc->re_ldata.re_tx_prodidx = idx;
1842 * RealTek put the TX poll request register in a different
1843 * location on the 8169 gigE chip. I don't know why.
1845 if (sc->re_type == RE_8169)
1846 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START);
1848 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START);
1851 * Use the countdown timer for interrupt moderation.
1852 * 'TX done' interrupts are disabled. Instead, we reset the
1853 * countdown timer, which will begin counting until it hits
1854 * the value in the TIMERINT register, and then trigger an
1855 * interrupt. Each time we write to the TIMERCNT register,
1856 * the timer count is reset to 0.
1858 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1863 * Set a timeout in case the chip goes out to lunch.
1871 struct re_softc *sc = xsc;
1872 struct ifnet *ifp = &sc->arpcom.ac_if;
1873 struct mii_data *mii;
1878 mii = device_get_softc(sc->re_miibus);
1881 * Cancel pending I/O and free all RX/TX buffers.
1886 * Enable C+ RX and TX mode, as well as VLAN stripping and
1887 * RX checksum offload. We must configure the C+ register
1888 * before all others.
1890 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
1891 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
1892 (ifp->if_capenable & IFCAP_RXCSUM ?
1893 RE_CPLUSCMD_RXCSUM_ENB : 0));
1896 * Init our MAC address. Even though the chipset
1897 * documentation doesn't mention it, we need to enter "Config
1898 * register write enable" mode to modify the ID registers.
1900 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
1901 CSR_WRITE_STREAM_4(sc, RE_IDR0,
1902 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1903 CSR_WRITE_STREAM_4(sc, RE_IDR4,
1904 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1905 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
1908 * For C+ mode, initialize the RX descriptors and mbufs.
1910 re_rx_list_init(sc);
1911 re_tx_list_init(sc);
1914 * Enable transmit and receive.
1916 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1919 * Set the initial TX and RX configuration.
1921 if (sc->re_testmode) {
1922 if (sc->re_type == RE_8169)
1923 CSR_WRITE_4(sc, RE_TXCFG,
1924 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
1926 CSR_WRITE_4(sc, RE_TXCFG,
1927 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
1929 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
1930 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
1932 /* Set the individual bit to receive frames for this host only. */
1933 rxcfg = CSR_READ_4(sc, RE_RXCFG);
1934 rxcfg |= RE_RXCFG_RX_INDIV;
1936 /* If we want promiscuous mode, set the allframes bit. */
1937 if (ifp->if_flags & IFF_PROMISC) {
1938 rxcfg |= RE_RXCFG_RX_ALLPHYS;
1939 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1941 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
1942 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1946 * Set capture broadcast bit to capture broadcast frames.
1948 if (ifp->if_flags & IFF_BROADCAST) {
1949 rxcfg |= RE_RXCFG_RX_BROAD;
1950 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1952 rxcfg &= ~RE_RXCFG_RX_BROAD;
1953 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1957 * Program the multicast filter, if necessary.
1961 #ifdef DEVICE_POLLING
1963 * Disable interrupts if we are polling.
1965 if (ifp->if_flags & IFF_POLLING)
1966 CSR_WRITE_2(sc, RE_IMR, 0);
1967 else /* otherwise ... */
1968 #endif /* DEVICE_POLLING */
1970 * Enable interrupts.
1972 if (sc->re_testmode)
1973 CSR_WRITE_2(sc, RE_IMR, 0);
1975 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1977 /* Set initial TX threshold */
1978 sc->re_txthresh = RE_TX_THRESH_INIT;
1980 /* Start RX/TX process. */
1981 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
1983 /* Enable receiver and transmitter. */
1984 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1987 * Load the addresses of the RX and TX lists into the chip.
1990 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
1991 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
1992 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
1993 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
1995 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
1996 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
1997 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
1998 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2000 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2003 * Initialize the timer interrupt register so that
2004 * a timer interrupt will be generated once the timer
2005 * reaches a certain number of ticks. The timer is
2006 * reloaded on each transmit. This gives us TX interrupt
2007 * moderation, which dramatically improves TX frame rate.
2010 if (sc->re_type == RE_8169)
2011 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2013 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2016 * For 8169 gigE NICs, set the max allowed RX packet
2017 * size so we can receive jumbo frames.
2019 if (sc->re_type == RE_8169)
2020 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2022 if (sc->re_testmode) {
2029 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2031 ifp->if_flags |= IFF_RUNNING;
2032 ifp->if_flags &= ~IFF_OACTIVE;
2034 callout_reset(&sc->re_timer, hz, re_tick, sc);
2039 * Set media options.
2042 re_ifmedia_upd(struct ifnet *ifp)
2044 struct re_softc *sc = ifp->if_softc;
2045 struct mii_data *mii;
2047 mii = device_get_softc(sc->re_miibus);
2054 * Report current media status.
2057 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2059 struct re_softc *sc = ifp->if_softc;
2060 struct mii_data *mii;
2062 mii = device_get_softc(sc->re_miibus);
2065 ifmr->ifm_active = mii->mii_media_active;
2066 ifmr->ifm_status = mii->mii_media_status;
2070 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2072 struct re_softc *sc = ifp->if_softc;
2073 struct ifreq *ifr = (struct ifreq *) data;
2074 struct mii_data *mii;
2081 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2083 ifp->if_mtu = ifr->ifr_mtu;
2086 if (ifp->if_flags & IFF_UP)
2088 else if (ifp->if_flags & IFF_RUNNING)
2099 mii = device_get_softc(sc->re_miibus);
2100 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2103 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING);
2104 ifp->if_capenable |=
2105 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING);
2106 if (ifp->if_capenable & IFCAP_TXCSUM)
2107 ifp->if_hwassist = RE_CSUM_FEATURES;
2109 ifp->if_hwassist = 0;
2110 if (ifp->if_flags & IFF_RUNNING)
2114 error = ether_ioctl(ifp, command, data);
2124 re_watchdog(struct ifnet *ifp)
2126 struct re_softc *sc = ifp->if_softc;
2130 if_printf(ifp, "watchdog timeout\n");
2142 * Stop the adapter and free any mbufs allocated to the
2146 re_stop(struct re_softc *sc)
2148 struct ifnet *ifp = &sc->arpcom.ac_if;
2153 callout_stop(&sc->re_timer);
2155 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2156 #ifdef DEVICE_POLLING
2157 ether_poll_deregister(ifp);
2158 #endif /* DEVICE_POLLING */
2160 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2161 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2163 if (sc->re_head != NULL) {
2164 m_freem(sc->re_head);
2165 sc->re_head = sc->re_tail = NULL;
2168 /* Free the TX list buffers. */
2169 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2170 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2171 bus_dmamap_unload(sc->re_ldata.re_mtag,
2172 sc->re_ldata.re_tx_dmamap[i]);
2173 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2174 sc->re_ldata.re_tx_mbuf[i] = NULL;
2178 /* Free the RX list buffers. */
2179 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2180 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2181 bus_dmamap_unload(sc->re_ldata.re_mtag,
2182 sc->re_ldata.re_rx_dmamap[i]);
2183 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2184 sc->re_ldata.re_rx_mbuf[i] = NULL;
2192 * Device suspend routine. Stop the interface and save some PCI
2193 * settings in case the BIOS doesn't restore them properly on
2197 re_suspend(device_t dev)
2199 #ifndef BURN_BRIDGES
2202 struct re_softc *sc = device_get_softc(dev);
2206 #ifndef BURN_BRIDGES
2207 for (i = 0; i < 5; i++)
2208 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2209 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2210 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2211 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2212 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2221 * Device resume routine. Restore some PCI settings in case the BIOS
2222 * doesn't, re-enable busmastering, and restart the interface if
2226 re_resume(device_t dev)
2228 struct re_softc *sc = device_get_softc(dev);
2229 struct ifnet *ifp = &sc->arpcom.ac_if;
2230 #ifndef BURN_BRIDGES
2234 #ifndef BURN_BRIDGES
2235 /* better way to do this? */
2236 for (i = 0; i < 5; i++)
2237 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2238 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2239 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2240 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2241 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2243 /* reenable busmastering */
2244 pci_enable_busmaster(dev);
2245 pci_enable_io(dev, SYS_RES_IOPORT);
2248 /* reinitialize interface if necessary */
2249 if (ifp->if_flags & IFF_UP)
2258 * Stop all chip I/O so that the kernel's probe routines don't
2259 * get confused by errant DMAs when rebooting.
2262 re_shutdown(device_t dev)
2264 struct re_softc *sc = device_get_softc(dev);