sys/dev/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define KBUILD_MODNAME  "i915"
  30
  31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32
  33 #include <linux/sysrq.h>
  34 #include <linux/slab.h>
  35 #include <linux/circ_buf.h>
  36 #include <drm/drmP.h>
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "intel_drv.h"
  41
  42 /**
  43  * DOC: interrupt handling
  44  *
  45  * These functions provide the basic support for enabling and disabling the
  46  * interrupt handling support. There's a lot more functionality in i915_irq.c
  47  * and related files, but that will be described in separate chapters.
  48  */
  49
  50 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  51         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  52 };
  53
  54 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  55         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  56 };
  57
  58 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  59         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  60 };
  61
  62 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  63         [HPD_CRT] = SDE_CRT_HOTPLUG,
  64         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  65         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  66         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  67         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  68 };
  69
  70 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  71         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  72         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  73         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  74         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  75         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  76 };
  77
  78 static const u32 hpd_spt[HPD_NUM_PINS] = {
  79         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  80         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  81         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  82         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  83         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  84 };
  85
  86 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  87         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  88         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  89         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  90         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  91         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  92         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  93 };
  94
  95 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  96         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  97         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  98         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  99         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 100         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 101         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 102 };
 103
 104 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 105         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 106         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 107         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 108         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 109         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 110         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 111 };
 112
 113 /* BXT hpd list */
 114 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 115         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 116         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 117         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 118 };
 119
 120 /* IIR can theoretically queue up two events. Be paranoid. */
 121 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 122         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 123         POSTING_READ(GEN8_##type##_IMR(which)); \
 124         I915_WRITE(GEN8_##type##_IER(which), 0); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 128         POSTING_READ(GEN8_##type##_IIR(which)); \
 129 } while (0)
 130
 131 #define GEN5_IRQ_RESET(type) do { \
 132         I915_WRITE(type##IMR, 0xffffffff); \
 133         POSTING_READ(type##IMR); \
 134         I915_WRITE(type##IER, 0); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137         I915_WRITE(type##IIR, 0xffffffff); \
 138         POSTING_READ(type##IIR); \
 139 } while (0)
 140
 141 /*
 142  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 143  */
 144 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 145                                     i915_reg_t reg)
 146 {
 147         u32 val = I915_READ(reg);
 148
 149         if (val == 0)
 150                 return;
 151
 152         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 153              i915_mmio_reg_offset(reg), val);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156         I915_WRITE(reg, 0xffffffff);
 157         POSTING_READ(reg);
 158 }
 159
 160 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 161         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 162         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 163         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 164         POSTING_READ(GEN8_##type##_IMR(which)); \
 165 } while (0)
 166
 167 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 168         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 169         I915_WRITE(type##IER, (ier_val)); \
 170         I915_WRITE(type##IMR, (imr_val)); \
 171         POSTING_READ(type##IMR); \
 172 } while (0)
 173
 174 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 175
 176 /* For display hotplug interrupt */
 177 static inline void
 178 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 179                                      uint32_t mask,
 180                                      uint32_t bits)
 181 {
 182         uint32_t val;
 183
 184         assert_spin_locked(&dev_priv->irq_lock);
 185         WARN_ON(bits & ~mask);
 186
 187         val = I915_READ(PORT_HOTPLUG_EN);
 188         val &= ~mask;
 189         val |= bits;
 190         I915_WRITE(PORT_HOTPLUG_EN, val);
 191 }
 192
 193 /**
 194  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 195  * @dev_priv: driver private
 196  * @mask: bits to update
 197  * @bits: bits to enable
 198  * NOTE: the HPD enable bits are modified both inside and outside
 199  * of an interrupt context. To avoid that read-modify-write cycles
 200  * interfer, these bits are protected by a spinlock. Since this
 201  * function is usually not called from a context where the lock is
 202  * held already, this function acquires the lock itself. A non-locking
 203  * version is also available.
 204  */
 205 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 206                                    uint32_t mask,
 207                                    uint32_t bits)
 208 {
 209         spin_lock_irq(&dev_priv->irq_lock);
 210         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 211         spin_unlock_irq(&dev_priv->irq_lock);
 212 }
 213
 214 /**
 215  * ilk_update_display_irq - update DEIMR
 216  * @dev_priv: driver private
 217  * @interrupt_mask: mask of interrupt bits to update
 218  * @enabled_irq_mask: mask of interrupt bits to enable
 219  */
 220 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 221                             uint32_t interrupt_mask,
 222                             uint32_t enabled_irq_mask)
 223 {
 224         uint32_t new_val;
 225
 226         assert_spin_locked(&dev_priv->irq_lock);
 227
 228         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 229
 230         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 231                 return;
 232
 233         new_val = dev_priv->irq_mask;
 234         new_val &= ~interrupt_mask;
 235         new_val |= (~enabled_irq_mask & interrupt_mask);
 236
 237         if (new_val != dev_priv->irq_mask) {
 238                 dev_priv->irq_mask = new_val;
 239                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 240                 POSTING_READ(DEIMR);
 241         }
 242 }
 243
 244 /**
 245  * ilk_update_gt_irq - update GTIMR
 246  * @dev_priv: driver private
 247  * @interrupt_mask: mask of interrupt bits to update
 248  * @enabled_irq_mask: mask of interrupt bits to enable
 249  */
 250 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 251                               uint32_t interrupt_mask,
 252                               uint32_t enabled_irq_mask)
 253 {
 254         assert_spin_locked(&dev_priv->irq_lock);
 255
 256         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 257
 258         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 259                 return;
 260
 261         dev_priv->gt_irq_mask &= ~interrupt_mask;
 262         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 263         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 264 }
 265
 266 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 267 {
 268         ilk_update_gt_irq(dev_priv, mask, mask);
 269         POSTING_READ_FW(GTIMR);
 270 }
 271
 272 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 273 {
 274         ilk_update_gt_irq(dev_priv, mask, 0);
 275 }
 276
 277 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 278 {
 279         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 280 }
 281
 282 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 283 {
 284         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 285 }
 286
 287 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 288 {
 289         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 290 }
 291
 292 /**
 293  * snb_update_pm_irq - update GEN6_PMIMR
 294  * @dev_priv: driver private
 295  * @interrupt_mask: mask of interrupt bits to update
 296  * @enabled_irq_mask: mask of interrupt bits to enable
 297  */
 298 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 299                               uint32_t interrupt_mask,
 300                               uint32_t enabled_irq_mask)
 301 {
 302         uint32_t new_val;
 303
 304         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 305
 306         assert_spin_locked(&dev_priv->irq_lock);
 307
 308         new_val = dev_priv->pm_irq_mask;
 309         new_val &= ~interrupt_mask;
 310         new_val |= (~enabled_irq_mask & interrupt_mask);
 311
 312         if (new_val != dev_priv->pm_irq_mask) {
 313                 dev_priv->pm_irq_mask = new_val;
 314                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 315                 POSTING_READ(gen6_pm_imr(dev_priv));
 316         }
 317 }
 318
 319 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 320 {
 321         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 322                 return;
 323
 324         snb_update_pm_irq(dev_priv, mask, mask);
 325 }
 326
 327 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 328                                   uint32_t mask)
 329 {
 330         snb_update_pm_irq(dev_priv, mask, 0);
 331 }
 332
 333 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 334 {
 335         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 336                 return;
 337
 338         __gen6_disable_pm_irq(dev_priv, mask);
 339 }
 340
 341 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 342 {
 343         i915_reg_t reg = gen6_pm_iir(dev_priv);
 344
 345         spin_lock_irq(&dev_priv->irq_lock);
 346         I915_WRITE(reg, dev_priv->pm_rps_events);
 347         I915_WRITE(reg, dev_priv->pm_rps_events);
 348         POSTING_READ(reg);
 349         dev_priv->rps.pm_iir = 0;
 350         spin_unlock_irq(&dev_priv->irq_lock);
 351 }
 352
 353 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 354 {
 355         spin_lock_irq(&dev_priv->irq_lock);
 356         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 357         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 358         dev_priv->rps.interrupts_enabled = true;
 359         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 360                                 dev_priv->pm_rps_events);
 361         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 362
 363         spin_unlock_irq(&dev_priv->irq_lock);
 364 }
 365
 366 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 367 {
 368         return (mask & ~dev_priv->rps.pm_intr_keep);
 369 }
 370
 371 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 372 {
 373         spin_lock_irq(&dev_priv->irq_lock);
 374         dev_priv->rps.interrupts_enabled = false;
 375
 376         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 377
 378         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 379         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 380                                 ~dev_priv->pm_rps_events);
 381
 382         spin_unlock_irq(&dev_priv->irq_lock);
 383         synchronize_irq(dev_priv->drm.irq);
 384
 385         /* Now that we will not be generating any more work, flush any
 386          * outsanding tasks. As we are called on the RPS idle path,
 387          * we will reset the GPU to minimum frequencies, so the current
 388          * state of the worker can be discarded.
 389          */
 390         cancel_work_sync(&dev_priv->rps.work);
 391         gen6_reset_rps_interrupts(dev_priv);
 392 }
 393
 394 /**
 395  * bdw_update_port_irq - update DE port interrupt
 396  * @dev_priv: driver private
 397  * @interrupt_mask: mask of interrupt bits to update
 398  * @enabled_irq_mask: mask of interrupt bits to enable
 399  */
 400 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 401                                 uint32_t interrupt_mask,
 402                                 uint32_t enabled_irq_mask)
 403 {
 404         uint32_t new_val;
 405         uint32_t old_val;
 406
 407         assert_spin_locked(&dev_priv->irq_lock);
 408
 409         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 410
 411         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 412                 return;
 413
 414         old_val = I915_READ(GEN8_DE_PORT_IMR);
 415
 416         new_val = old_val;
 417         new_val &= ~interrupt_mask;
 418         new_val |= (~enabled_irq_mask & interrupt_mask);
 419
 420         if (new_val != old_val) {
 421                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 422                 POSTING_READ(GEN8_DE_PORT_IMR);
 423         }
 424 }
 425
 426 /**
 427  * bdw_update_pipe_irq - update DE pipe interrupt
 428  * @dev_priv: driver private
 429  * @pipe: pipe whose interrupt to update
 430  * @interrupt_mask: mask of interrupt bits to update
 431  * @enabled_irq_mask: mask of interrupt bits to enable
 432  */
 433 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 434                          enum i915_pipe pipe,
 435                          uint32_t interrupt_mask,
 436                          uint32_t enabled_irq_mask)
 437 {
 438         uint32_t new_val;
 439
 440         assert_spin_locked(&dev_priv->irq_lock);
 441
 442         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 443
 444         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 445                 return;
 446
 447         new_val = dev_priv->de_irq_mask[pipe];
 448         new_val &= ~interrupt_mask;
 449         new_val |= (~enabled_irq_mask & interrupt_mask);
 450
 451         if (new_val != dev_priv->de_irq_mask[pipe]) {
 452                 dev_priv->de_irq_mask[pipe] = new_val;
 453                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 454                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 455         }
 456 }
 457
 458 /**
 459  * ibx_display_interrupt_update - update SDEIMR
 460  * @dev_priv: driver private
 461  * @interrupt_mask: mask of interrupt bits to update
 462  * @enabled_irq_mask: mask of interrupt bits to enable
 463  */
 464 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 465                                   uint32_t interrupt_mask,
 466                                   uint32_t enabled_irq_mask)
 467 {
 468         uint32_t sdeimr = I915_READ(SDEIMR);
 469         sdeimr &= ~interrupt_mask;
 470         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 471
 472         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 473
 474         assert_spin_locked(&dev_priv->irq_lock);
 475
 476         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 477                 return;
 478
 479         I915_WRITE(SDEIMR, sdeimr);
 480         POSTING_READ(SDEIMR);
 481 }
 482
 483 static void
 484 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
 485                        u32 enable_mask, u32 status_mask)
 486 {
 487         i915_reg_t reg = PIPESTAT(pipe);
 488         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 489
 490         assert_spin_locked(&dev_priv->irq_lock);
 491         WARN_ON(!intel_irqs_enabled(dev_priv));
 492
 493         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 494                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 495                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 496                       pipe_name(pipe), enable_mask, status_mask))
 497                 return;
 498
 499         if ((pipestat & enable_mask) == enable_mask)
 500                 return;
 501
 502         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 503
 504         /* Enable the interrupt, clear any pending status */
 505         pipestat |= enable_mask | status_mask;
 506         I915_WRITE(reg, pipestat);
 507         POSTING_READ(reg);
 508 }
 509
 510 static void
 511 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
 512                         u32 enable_mask, u32 status_mask)
 513 {
 514         i915_reg_t reg = PIPESTAT(pipe);
 515         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 516
 517         assert_spin_locked(&dev_priv->irq_lock);
 518         WARN_ON(!intel_irqs_enabled(dev_priv));
 519
 520         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 521                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 522                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 523                       pipe_name(pipe), enable_mask, status_mask))
 524                 return;
 525
 526         if ((pipestat & enable_mask) == 0)
 527                 return;
 528
 529         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 530
 531         pipestat &= ~enable_mask;
 532         I915_WRITE(reg, pipestat);
 533         POSTING_READ(reg);
 534 }
 535
 536 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 537 {
 538         u32 enable_mask = status_mask << 16;
 539
 540         /*
 541          * On pipe A we don't support the PSR interrupt yet,
 542          * on pipe B and C the same bit MBZ.
 543          */
 544         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 545                 return 0;
 546         /*
 547          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 548          * A the same bit is for perf counters which we don't use either.
 549          */
 550         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 551                 return 0;
 552
 553         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 554                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 555                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 556         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 557                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 558         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 559                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 560
 561         return enable_mask;
 562 }
 563
 564 void
 565 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
 566                      u32 status_mask)
 567 {
 568         u32 enable_mask;
 569
 570         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 571                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 572                                                            status_mask);
 573         else
 574                 enable_mask = status_mask << 16;
 575         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 576 }
 577
 578 void
 579 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
 580                       u32 status_mask)
 581 {
 582         u32 enable_mask;
 583
 584         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 585                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 586                                                            status_mask);
 587         else
 588                 enable_mask = status_mask << 16;
 589         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 590 }
 591
 592 /**
 593  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 594  * @dev_priv: i915 device private
 595  */
 596 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 597 {
 598         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 599                 return;
 600
 601         spin_lock_irq(&dev_priv->irq_lock);
 602
 603         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 604         if (INTEL_GEN(dev_priv) >= 4)
 605                 i915_enable_pipestat(dev_priv, PIPE_A,
 606                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 607
 608         spin_unlock_irq(&dev_priv->irq_lock);
 609 }
 610
 611 /*
 612  * This timing diagram depicts the video signal in and
 613  * around the vertical blanking period.
 614  *
 615  * Assumptions about the fictitious mode used in this example:
 616  *  vblank_start >= 3
 617  *  vsync_start = vblank_start + 1
 618  *  vsync_end = vblank_start + 2
 619  *  vtotal = vblank_start + 3
 620  *
 621  *           start of vblank:
 622  *           latch double buffered registers
 623  *           increment frame counter (ctg+)
 624  *           generate start of vblank interrupt (gen4+)
 625  *           |
 626  *           |          frame start:
 627  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 628  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 629  *           |          |
 630  *           |          |  start of vsync:
 631  *           |          |  generate vsync interrupt
 632  *           |          |  |
 633  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 634  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 635  * ----va---> <-----------------vb--------------------> <--------va-------------
 636  *       |          |       <----vs----->                     |
 637  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 638  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 639  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 640  *       |          |                                         |
 641  *       last visible pixel                                   first visible pixel
 642  *                  |                                         increment frame counter (gen3/4)
 643  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 644  *
 645  * x  = horizontal active
 646  * _  = horizontal blanking
 647  * hs = horizontal sync
 648  * va = vertical active
 649  * vb = vertical blanking
 650  * vs = vertical sync
 651  * vbs = vblank_start (number)
 652  *
 653  * Summary:
 654  * - most events happen at the start of horizontal sync
 655  * - frame start happens at the start of horizontal blank, 1-4 lines
 656  *   (depending on PIPECONF settings) after the start of vblank
 657  * - gen3/4 pixel and frame counter are synchronized with the start
 658  *   of horizontal active on the first line of vertical active
 659  */
 660
 661 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 662 {
 663         /* Gen2 doesn't have a hardware frame counter */
 664         return 0;
 665 }
 666
 667 /* Called from drm generic code, passed a 'crtc', which
 668  * we use as a pipe index
 669  */
 670 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 671 {
 672         struct drm_i915_private *dev_priv = to_i915(dev);
 673         i915_reg_t high_frame, low_frame;
 674         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 675         struct intel_crtc *intel_crtc =
 676                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 677         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 678
 679         htotal = mode->crtc_htotal;
 680         hsync_start = mode->crtc_hsync_start;
 681         vbl_start = mode->crtc_vblank_start;
 682         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 683                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 684
 685         /* Convert to pixel count */
 686         vbl_start *= htotal;
 687
 688         /* Start of vblank event occurs at start of hsync */
 689         vbl_start -= htotal - hsync_start;
 690
 691         high_frame = PIPEFRAME(pipe);
 692         low_frame = PIPEFRAMEPIXEL(pipe);
 693
 694         /*
 695          * High & low register fields aren't synchronized, so make sure
 696          * we get a low value that's stable across two reads of the high
 697          * register.
 698          */
 699         do {
 700                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 701                 low   = I915_READ(low_frame);
 702                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 703         } while (high1 != high2);
 704
 705         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 706         pixel = low & PIPE_PIXEL_MASK;
 707         low >>= PIPE_FRAME_LOW_SHIFT;
 708
 709         /*
 710          * The frame counter increments at beginning of active.
 711          * Cook up a vblank counter by also checking the pixel
 712          * counter against vblank start.
 713          */
 714         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 715 }
 716
 717 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 718 {
 719         struct drm_i915_private *dev_priv = to_i915(dev);
 720
 721         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 722 }
 723
 724 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 725 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 726 {
 727         struct drm_device *dev = crtc->base.dev;
 728         struct drm_i915_private *dev_priv = to_i915(dev);
 729         const struct drm_display_mode *mode = &crtc->base.hwmode;
 730         enum i915_pipe pipe = crtc->pipe;
 731         int position, vtotal;
 732
 733         vtotal = mode->crtc_vtotal;
 734         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 735                 vtotal /= 2;
 736
 737         if (IS_GEN2(dev_priv))
 738                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 739         else
 740                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 741
 742         /*
 743          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 744          * read it just before the start of vblank.  So try it again
 745          * so we don't accidentally end up spanning a vblank frame
 746          * increment, causing the pipe_update_end() code to squak at us.
 747          *
 748          * The nature of this problem means we can't simply check the ISR
 749          * bit and return the vblank start value; nor can we use the scanline
 750          * debug register in the transcoder as it appears to have the same
 751          * problem.  We may need to extend this to include other platforms,
 752          * but so far testing only shows the problem on HSW.
 753          */
 754         if (HAS_DDI(dev_priv) && !position) {
 755                 int i, temp;
 756
 757                 for (i = 0; i < 100; i++) {
 758                         udelay(1);
 759                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 760                                 DSL_LINEMASK_GEN3;
 761                         if (temp != position) {
 762                                 position = temp;
 763                                 break;
 764                         }
 765                 }
 766         }
 767
 768         /*
 769          * See update_scanline_offset() for the details on the
 770          * scanline_offset adjustment.
 771          */
 772         return (position + crtc->scanline_offset) % vtotal;
 773 }
 774
 775 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 776                                     unsigned int flags, int *vpos, int *hpos,
 777                                     ktime_t *stime, ktime_t *etime,
 778                                     const struct drm_display_mode *mode)
 779 {
 780         struct drm_i915_private *dev_priv = to_i915(dev);
 781         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 783         int position;
 784         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 785         bool in_vbl = true;
 786         int ret = 0;
 787         unsigned long irqflags;
 788
 789         if (WARN_ON(!mode->crtc_clock)) {
 790                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 791                                  "pipe %c\n", pipe_name(pipe));
 792                 return 0;
 793         }
 794
 795         htotal = mode->crtc_htotal;
 796         hsync_start = mode->crtc_hsync_start;
 797         vtotal = mode->crtc_vtotal;
 798         vbl_start = mode->crtc_vblank_start;
 799         vbl_end = mode->crtc_vblank_end;
 800
 801         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 802                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 803                 vbl_end /= 2;
 804                 vtotal /= 2;
 805         }
 806
 807         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 808
 809         /*
 810          * Lock uncore.lock, as we will do multiple timing critical raw
 811          * register reads, potentially with preemption disabled, so the
 812          * following code must not block on uncore.lock.
 813          */
 814         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 815
 816         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 817
 818         /* Get optional system timestamp before query. */
 819         if (stime)
 820                 *stime = ktime_get();
 821
 822         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 823                 /* No obvious pixelcount register. Only query vertical
 824                  * scanout position from Display scan line register.
 825                  */
 826                 position = __intel_get_crtc_scanline(intel_crtc);
 827         } else {
 828                 /* Have access to pixelcount since start of frame.
 829                  * We can split this into vertical and horizontal
 830                  * scanout position.
 831                  */
 832                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 833
 834                 /* convert to pixel counts */
 835                 vbl_start *= htotal;
 836                 vbl_end *= htotal;
 837                 vtotal *= htotal;
 838
 839                 /*
 840                  * In interlaced modes, the pixel counter counts all pixels,
 841                  * so one field will have htotal more pixels. In order to avoid
 842                  * the reported position from jumping backwards when the pixel
 843                  * counter is beyond the length of the shorter field, just
 844                  * clamp the position the length of the shorter field. This
 845                  * matches how the scanline counter based position works since
 846                  * the scanline counter doesn't count the two half lines.
 847                  */
 848                 if (position >= vtotal)
 849                         position = vtotal - 1;
 850
 851                 /*
 852                  * Start of vblank interrupt is triggered at start of hsync,
 853                  * just prior to the first active line of vblank. However we
 854                  * consider lines to start at the leading edge of horizontal
 855                  * active. So, should we get here before we've crossed into
 856                  * the horizontal active of the first line in vblank, we would
 857                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 858                  * always add htotal-hsync_start to the current pixel position.
 859                  */
 860                 position = (position + htotal - hsync_start) % vtotal;
 861         }
 862
 863         /* Get optional system timestamp after query. */
 864         if (etime)
 865                 *etime = ktime_get();
 866
 867         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 868
 869         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 870
 871         in_vbl = position >= vbl_start && position < vbl_end;
 872
 873         /*
 874          * While in vblank, position will be negative
 875          * counting up towards 0 at vbl_end. And outside
 876          * vblank, position will be positive counting
 877          * up since vbl_end.
 878          */
 879         if (position >= vbl_start)
 880                 position -= vbl_end;
 881         else
 882                 position += vtotal - vbl_end;
 883
 884         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 885                 *vpos = position;
 886                 *hpos = 0;
 887         } else {
 888                 *vpos = position / htotal;
 889                 *hpos = position - (*vpos * htotal);
 890         }
 891
 892         /* In vblank? */
 893         if (in_vbl)
 894                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 895
 896         return ret;
 897 }
 898
 899 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 902         unsigned long irqflags;
 903         int position;
 904
 905         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 906         position = __intel_get_crtc_scanline(crtc);
 907         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 908
 909         return position;
 910 }
 911
 912 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 913                               int *max_error,
 914                               struct timeval *vblank_time,
 915                               unsigned flags)
 916 {
 917         struct drm_crtc *crtc;
 918
 919         if (pipe >= INTEL_INFO(dev)->num_pipes) {
 920                 DRM_ERROR("Invalid crtc %u\n", pipe);
 921                 return -EINVAL;
 922         }
 923
 924         /* Get drm_crtc to timestamp: */
 925         crtc = intel_get_crtc_for_pipe(dev, pipe);
 926         if (crtc == NULL) {
 927                 DRM_ERROR("Invalid crtc %u\n", pipe);
 928                 return -EINVAL;
 929         }
 930
 931         if (!crtc->hwmode.crtc_clock) {
 932                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 933                 return -EBUSY;
 934         }
 935
 936         /* Helper routine in DRM core does all the work: */
 937         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 938                                                      vblank_time, flags,
 939                                                      &crtc->hwmode);
 940 }
 941
 942 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 943 {
 944         u32 busy_up, busy_down, max_avg, min_avg;
 945         u8 new_delay;
 946
 947         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
 948
 949         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 950
 951         new_delay = dev_priv->ips.cur_delay;
 952
 953         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 954         busy_up = I915_READ(RCPREVBSYTUPAVG);
 955         busy_down = I915_READ(RCPREVBSYTDNAVG);
 956         max_avg = I915_READ(RCBMAXAVG);
 957         min_avg = I915_READ(RCBMINAVG);
 958
 959         /* Handle RCS change request from hw */
 960         if (busy_up > max_avg) {
 961                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 962                         new_delay = dev_priv->ips.cur_delay - 1;
 963                 if (new_delay < dev_priv->ips.max_delay)
 964                         new_delay = dev_priv->ips.max_delay;
 965         } else if (busy_down < min_avg) {
 966                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 967                         new_delay = dev_priv->ips.cur_delay + 1;
 968                 if (new_delay > dev_priv->ips.min_delay)
 969                         new_delay = dev_priv->ips.min_delay;
 970         }
 971
 972         if (ironlake_set_drps(dev_priv, new_delay))
 973                 dev_priv->ips.cur_delay = new_delay;
 974
 975         lockmgr(&mchdev_lock, LK_RELEASE);
 976
 977         return;
 978 }
 979
 980 static void notify_ring(struct intel_engine_cs *engine)
 981 {
 982         smp_store_mb(engine->breadcrumbs.irq_posted, true);
 983         if (intel_engine_wakeup(engine)) {
 984                 trace_i915_gem_request_notify(engine);
 985                 engine->breadcrumbs.irq_wakeups++;
 986         }
 987 }
 988
 989 static void vlv_c0_read(struct drm_i915_private *dev_priv,
 990                         struct intel_rps_ei *ei)
 991 {
 992         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
 993         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
 994         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 995 }
 996
 997 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
 998                          const struct intel_rps_ei *old,
 999                          const struct intel_rps_ei *now,
1000                          int threshold)
1001 {
1002         u64 time, c0;
1003         unsigned int mul = 100;
1004
1005         if (old->cz_clock == 0)
1006                 return false;
1007
1008         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1009                 mul <<= 8;
1010
1011         time = now->cz_clock - old->cz_clock;
1012         time *= threshold * dev_priv->czclk_freq;
1013
1014         /* Workload can be split between render + media, e.g. SwapBuffers
1015          * being blitted in X after being rendered in mesa. To account for
1016          * this we need to combine both engines into our activity counter.
1017          */
1018         c0 = now->render_c0 - old->render_c0;
1019         c0 += now->media_c0 - old->media_c0;
1020         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1021
1022         return c0 >= time;
1023 }
1024
1025 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1026 {
1027         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1028         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1029 }
1030
1031 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1032 {
1033         struct intel_rps_ei now;
1034         u32 events = 0;
1035
1036         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1037                 return 0;
1038
1039         vlv_c0_read(dev_priv, &now);
1040         if (now.cz_clock == 0)
1041                 return 0;
1042
1043         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1044                 if (!vlv_c0_above(dev_priv,
1045                                   &dev_priv->rps.down_ei, &now,
1046                                   dev_priv->rps.down_threshold))
1047                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1048                 dev_priv->rps.down_ei = now;
1049         }
1050
1051         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1052                 if (vlv_c0_above(dev_priv,
1053                                  &dev_priv->rps.up_ei, &now,
1054                                  dev_priv->rps.up_threshold))
1055                         events |= GEN6_PM_RP_UP_THRESHOLD;
1056                 dev_priv->rps.up_ei = now;
1057         }
1058
1059         return events;
1060 }
1061
1062 static bool any_waiters(struct drm_i915_private *dev_priv)
1063 {
1064         struct intel_engine_cs *engine;
1065
1066         for_each_engine(engine, dev_priv)
1067                 if (intel_engine_has_waiter(engine))
1068                         return true;
1069
1070         return false;
1071 }
1072
1073 static void gen6_pm_rps_work(struct work_struct *work)
1074 {
1075         struct drm_i915_private *dev_priv =
1076                 container_of(work, struct drm_i915_private, rps.work);
1077         bool client_boost;
1078         int new_delay, adj, min, max;
1079         u32 pm_iir;
1080
1081         spin_lock_irq(&dev_priv->irq_lock);
1082         /* Speed up work cancelation during disabling rps interrupts. */
1083         if (!dev_priv->rps.interrupts_enabled) {
1084                 spin_unlock_irq(&dev_priv->irq_lock);
1085                 return;
1086         }
1087
1088         pm_iir = dev_priv->rps.pm_iir;
1089         dev_priv->rps.pm_iir = 0;
1090         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1091         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1092         client_boost = dev_priv->rps.client_boost;
1093         dev_priv->rps.client_boost = false;
1094         spin_unlock_irq(&dev_priv->irq_lock);
1095
1096         /* Make sure we didn't queue anything we're not going to process. */
1097         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1098
1099         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1100                 return;
1101
1102         mutex_lock(&dev_priv->rps.hw_lock);
1103
1104         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1105
1106         adj = dev_priv->rps.last_adj;
1107         new_delay = dev_priv->rps.cur_freq;
1108         min = dev_priv->rps.min_freq_softlimit;
1109         max = dev_priv->rps.max_freq_softlimit;
1110         if (client_boost || any_waiters(dev_priv))
1111                 max = dev_priv->rps.max_freq;
1112         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1113                 new_delay = dev_priv->rps.boost_freq;
1114                 adj = 0;
1115         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1116                 if (adj > 0)
1117                         adj *= 2;
1118                 else /* CHV needs even encode values */
1119                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1120                 /*
1121                  * For better performance, jump directly
1122                  * to RPe if we're below it.
1123                  */
1124                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1125                         new_delay = dev_priv->rps.efficient_freq;
1126                         adj = 0;
1127                 }
1128         } else if (client_boost || any_waiters(dev_priv)) {
1129                 adj = 0;
1130         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1131                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1132                         new_delay = dev_priv->rps.efficient_freq;
1133                 else
1134                         new_delay = dev_priv->rps.min_freq_softlimit;
1135                 adj = 0;
1136         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1137                 if (adj < 0)
1138                         adj *= 2;
1139                 else /* CHV needs even encode values */
1140                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1141         } else { /* unknown event */
1142                 adj = 0;
1143         }
1144
1145         dev_priv->rps.last_adj = adj;
1146
1147         /* sysfs frequency interfaces may have snuck in while servicing the
1148          * interrupt
1149          */
1150         new_delay += adj;
1151         new_delay = clamp_t(int, new_delay, min, max);
1152
1153         intel_set_rps(dev_priv, new_delay);
1154
1155         mutex_unlock(&dev_priv->rps.hw_lock);
1156 }
1157
1158
1159 /**
1160  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1161  * occurred.
1162  * @work: workqueue struct
1163  *
1164  * Doesn't actually do anything except notify userspace. As a consequence of
1165  * this event, userspace should try to remap the bad rows since statistically
1166  * it is likely the same row is more likely to go bad again.
1167  */
1168 static void ivybridge_parity_work(struct work_struct *work)
1169 {
1170         struct drm_i915_private *dev_priv =
1171                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1172         u32 error_status, row, bank, subbank;
1173         char *parity_event[6];
1174         uint32_t misccpctl;
1175         uint8_t slice = 0;
1176
1177         /* We must turn off DOP level clock gating to access the L3 registers.
1178          * In order to prevent a get/put style interface, acquire struct mutex
1179          * any time we access those registers.
1180          */
1181         mutex_lock(&dev_priv->drm.struct_mutex);
1182
1183         /* If we've screwed up tracking, just let the interrupt fire again */
1184         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1185                 goto out;
1186
1187         misccpctl = I915_READ(GEN7_MISCCPCTL);
1188         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1189         POSTING_READ(GEN7_MISCCPCTL);
1190
1191         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1192                 i915_reg_t reg;
1193
1194                 slice--;
1195                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1196                         break;
1197
1198                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1199
1200                 reg = GEN7_L3CDERRST1(slice);
1201
1202                 error_status = I915_READ(reg);
1203                 row = GEN7_PARITY_ERROR_ROW(error_status);
1204                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1205                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1206
1207                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1208                 POSTING_READ(reg);
1209
1210                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1211                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1212                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1213                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1214                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1215                 parity_event[5] = NULL;
1216
1217                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1218                                    KOBJ_CHANGE, parity_event);
1219
1220                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1221                           slice, row, bank, subbank);
1222
1223                 kfree(parity_event[4]);
1224                 kfree(parity_event[3]);
1225                 kfree(parity_event[2]);
1226                 kfree(parity_event[1]);
1227         }
1228
1229         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1230
1231 out:
1232         WARN_ON(dev_priv->l3_parity.which_slice);
1233         spin_lock_irq(&dev_priv->irq_lock);
1234         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1235         spin_unlock_irq(&dev_priv->irq_lock);
1236
1237         mutex_unlock(&dev_priv->drm.struct_mutex);
1238 }
1239
1240 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1241                                                u32 iir)
1242 {
1243         if (!HAS_L3_DPF(dev_priv))
1244                 return;
1245
1246         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1247         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1248         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1249
1250         iir &= GT_PARITY_ERROR(dev_priv);
1251         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1252                 dev_priv->l3_parity.which_slice |= 1 << 1;
1253
1254         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1255                 dev_priv->l3_parity.which_slice |= 1 << 0;
1256
1257         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1258 }
1259
1260 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1261                                u32 gt_iir)
1262 {
1263         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1264                 notify_ring(&dev_priv->engine[RCS]);
1265         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1266                 notify_ring(&dev_priv->engine[VCS]);
1267 }
1268
1269 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1270                                u32 gt_iir)
1271 {
1272         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1273                 notify_ring(&dev_priv->engine[RCS]);
1274         if (gt_iir & GT_BSD_USER_INTERRUPT)
1275                 notify_ring(&dev_priv->engine[VCS]);
1276         if (gt_iir & GT_BLT_USER_INTERRUPT)
1277                 notify_ring(&dev_priv->engine[BCS]);
1278
1279         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1280                       GT_BSD_CS_ERROR_INTERRUPT |
1281                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1282                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1283
1284         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1285                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1286 }
1287
1288 static __always_inline void
1289 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1290 {
1291         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1292                 notify_ring(engine);
1293         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1294                 tasklet_schedule(&engine->irq_tasklet);
1295 }
1296
1297 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1298                                    u32 master_ctl,
1299                                    u32 gt_iir[4])
1300 {
1301         irqreturn_t ret = IRQ_NONE;
1302
1303         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1304                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1305                 if (gt_iir[0]) {
1306                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1307                         ret = IRQ_HANDLED;
1308                 } else
1309                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1310         }
1311
1312         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1313                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1314                 if (gt_iir[1]) {
1315                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1316                         ret = IRQ_HANDLED;
1317                 } else
1318                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1319         }
1320
1321         if (master_ctl & GEN8_GT_VECS_IRQ) {
1322                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1323                 if (gt_iir[3]) {
1324                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1325                         ret = IRQ_HANDLED;
1326                 } else
1327                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1328         }
1329
1330         if (master_ctl & GEN8_GT_PM_IRQ) {
1331                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1332                 if (gt_iir[2] & dev_priv->pm_rps_events) {
1333                         I915_WRITE_FW(GEN8_GT_IIR(2),
1334                                       gt_iir[2] & dev_priv->pm_rps_events);
1335                         ret = IRQ_HANDLED;
1336                 } else
1337                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1338         }
1339
1340         return ret;
1341 }
1342
1343 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1344                                 u32 gt_iir[4])
1345 {
1346         if (gt_iir[0]) {
1347                 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1348                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1349                 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1350                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1351         }
1352
1353         if (gt_iir[1]) {
1354                 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1355                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1356                 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1357                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1358         }
1359
1360         if (gt_iir[3])
1361                 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1362                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1363
1364         if (gt_iir[2] & dev_priv->pm_rps_events)
1365                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1366 }
1367
1368 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1369 {
1370         switch (port) {
1371         case PORT_A:
1372                 return val & PORTA_HOTPLUG_LONG_DETECT;
1373         case PORT_B:
1374                 return val & PORTB_HOTPLUG_LONG_DETECT;
1375         case PORT_C:
1376                 return val & PORTC_HOTPLUG_LONG_DETECT;
1377         default:
1378                 return false;
1379         }
1380 }
1381
1382 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1383 {
1384         switch (port) {
1385         case PORT_E:
1386                 return val & PORTE_HOTPLUG_LONG_DETECT;
1387         default:
1388                 return false;
1389         }
1390 }
1391
1392 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1393 {
1394         switch (port) {
1395         case PORT_A:
1396                 return val & PORTA_HOTPLUG_LONG_DETECT;
1397         case PORT_B:
1398                 return val & PORTB_HOTPLUG_LONG_DETECT;
1399         case PORT_C:
1400                 return val & PORTC_HOTPLUG_LONG_DETECT;
1401         case PORT_D:
1402                 return val & PORTD_HOTPLUG_LONG_DETECT;
1403         default:
1404                 return false;
1405         }
1406 }
1407
1408 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1409 {
1410         switch (port) {
1411         case PORT_A:
1412                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1413         default:
1414                 return false;
1415         }
1416 }
1417
1418 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1419 {
1420         switch (port) {
1421         case PORT_B:
1422                 return val & PORTB_HOTPLUG_LONG_DETECT;
1423         case PORT_C:
1424                 return val & PORTC_HOTPLUG_LONG_DETECT;
1425         case PORT_D:
1426                 return val & PORTD_HOTPLUG_LONG_DETECT;
1427         default:
1428                 return false;
1429         }
1430 }
1431
1432 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1433 {
1434         switch (port) {
1435         case PORT_B:
1436                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1437         case PORT_C:
1438                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1439         case PORT_D:
1440                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1441         default:
1442                 return false;
1443         }
1444 }
1445
1446 /*
1447  * Get a bit mask of pins that have triggered, and which ones may be long.
1448  * This can be called multiple times with the same masks to accumulate
1449  * hotplug detection results from several registers.
1450  *
1451  * Note that the caller is expected to zero out the masks initially.
1452  */
1453 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1454                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1455                              const u32 hpd[HPD_NUM_PINS],
1456                              bool long_pulse_detect(enum port port, u32 val))
1457 {
1458         enum port port;
1459         int i;
1460
1461         for_each_hpd_pin(i) {
1462                 if ((hpd[i] & hotplug_trigger) == 0)
1463                         continue;
1464
1465                 *pin_mask |= BIT(i);
1466
1467                 if (!intel_hpd_pin_to_port(i, &port))
1468                         continue;
1469
1470                 if (long_pulse_detect(port, dig_hotplug_reg))
1471                         *long_mask |= BIT(i);
1472         }
1473
1474         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1475                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1476
1477 }
1478
1479 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1480 {
1481         wake_up_all(&dev_priv->gmbus_wait_queue);
1482 }
1483
1484 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1485 {
1486         wake_up_all(&dev_priv->gmbus_wait_queue);
1487 }
1488
1489 #if defined(CONFIG_DEBUG_FS)
1490 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1491                                          enum i915_pipe pipe,
1492                                          uint32_t crc0, uint32_t crc1,
1493                                          uint32_t crc2, uint32_t crc3,
1494                                          uint32_t crc4)
1495 {
1496         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1497         struct intel_pipe_crc_entry *entry;
1498         int head, tail;
1499
1500         spin_lock(&pipe_crc->lock);
1501
1502         if (!pipe_crc->entries) {
1503                 spin_unlock(&pipe_crc->lock);
1504                 DRM_DEBUG_KMS("spurious interrupt\n");
1505                 return;
1506         }
1507
1508         head = pipe_crc->head;
1509         tail = pipe_crc->tail;
1510
1511         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1512                 spin_unlock(&pipe_crc->lock);
1513                 DRM_ERROR("CRC buffer overflowing\n");
1514                 return;
1515         }
1516
1517         entry = &pipe_crc->entries[head];
1518
1519         entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1520                                                                  pipe);
1521         entry->crc[0] = crc0;
1522         entry->crc[1] = crc1;
1523         entry->crc[2] = crc2;
1524         entry->crc[3] = crc3;
1525         entry->crc[4] = crc4;
1526
1527         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1528         pipe_crc->head = head;
1529
1530         spin_unlock(&pipe_crc->lock);
1531
1532         wake_up_interruptible(&pipe_crc->wq);
1533 }
1534 #else
1535 static inline void
1536 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1537                              enum i915_pipe pipe,
1538                              uint32_t crc0, uint32_t crc1,
1539                              uint32_t crc2, uint32_t crc3,
1540                              uint32_t crc4) {}
1541 #endif
1542
1543
1544 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1545                                      enum i915_pipe pipe)
1546 {
1547         display_pipe_crc_irq_handler(dev_priv, pipe,
1548                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1549                                      0, 0, 0, 0);
1550 }
1551
1552 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1553                                      enum i915_pipe pipe)
1554 {
1555         display_pipe_crc_irq_handler(dev_priv, pipe,
1556                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1557                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1558                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1559                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1560                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1561 }
1562
1563 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1564                                       enum i915_pipe pipe)
1565 {
1566         uint32_t res1, res2;
1567
1568         if (INTEL_GEN(dev_priv) >= 3)
1569                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1570         else
1571                 res1 = 0;
1572
1573         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1574                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1575         else
1576                 res2 = 0;
1577
1578         display_pipe_crc_irq_handler(dev_priv, pipe,
1579                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1580                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1581                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1582                                      res1, res2);
1583 }
1584
1585 /* The RPS events need forcewake, so we add them to a work queue and mask their
1586  * IMR bits until the work is done. Other interrupts can be processed without
1587  * the work queue. */
1588 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1589 {
1590         if (pm_iir & dev_priv->pm_rps_events) {
1591                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1592                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1593                 if (dev_priv->rps.interrupts_enabled) {
1594                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1595                         schedule_work(&dev_priv->rps.work);
1596                 }
1597                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1598         }
1599
1600         if (INTEL_INFO(dev_priv)->gen >= 8)
1601                 return;
1602
1603         if (HAS_VEBOX(dev_priv)) {
1604                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1605                         notify_ring(&dev_priv->engine[VECS]);
1606
1607                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1608                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1609         }
1610 }
1611
1612 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1613                                      enum i915_pipe pipe)
1614 {
1615         bool ret;
1616
1617         ret = drm_handle_vblank(&dev_priv->drm, pipe);
1618         if (ret)
1619                 intel_finish_page_flip_mmio(dev_priv, pipe);
1620
1621         return ret;
1622 }
1623
1624 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1625                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1626 {
1627         int pipe;
1628
1629         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1630
1631         if (!dev_priv->display_irqs_enabled) {
1632                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1633                 return;
1634         }
1635
1636         for_each_pipe(dev_priv, pipe) {
1637                 i915_reg_t reg;
1638                 u32 mask, iir_bit = 0;
1639
1640                 /*
1641                  * PIPESTAT bits get signalled even when the interrupt is
1642                  * disabled with the mask bits, and some of the status bits do
1643                  * not generate interrupts at all (like the underrun bit). Hence
1644                  * we need to be careful that we only handle what we want to
1645                  * handle.
1646                  */
1647
1648                 /* fifo underruns are filterered in the underrun handler. */
1649                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1650
1651                 switch (pipe) {
1652                 case PIPE_A:
1653                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1654                         break;
1655                 case PIPE_B:
1656                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1657                         break;
1658                 case PIPE_C:
1659                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1660                         break;
1661                 }
1662                 if (iir & iir_bit)
1663                         mask |= dev_priv->pipestat_irq_mask[pipe];
1664
1665                 if (!mask)
1666                         continue;
1667
1668                 reg = PIPESTAT(pipe);
1669                 mask |= PIPESTAT_INT_ENABLE_MASK;
1670                 pipe_stats[pipe] = I915_READ(reg) & mask;
1671
1672                 /*
1673                  * Clear the PIPE*STAT regs before the IIR
1674                  */
1675                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1676                                         PIPESTAT_INT_STATUS_MASK))
1677                         I915_WRITE(reg, pipe_stats[pipe]);
1678         }
1679         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1680 }
1681
1682 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1683                                             u32 pipe_stats[I915_MAX_PIPES])
1684 {
1685         enum i915_pipe pipe;
1686
1687         for_each_pipe(dev_priv, pipe) {
1688                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1689                     intel_pipe_handle_vblank(dev_priv, pipe))
1690                         intel_check_page_flip(dev_priv, pipe);
1691
1692                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1693                         intel_finish_page_flip_cs(dev_priv, pipe);
1694
1695                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1696                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1697
1698                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1699                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1700         }
1701
1702         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1703                 gmbus_irq_handler(dev_priv);
1704 }
1705
1706 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1707 {
1708         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1709
1710         if (hotplug_status)
1711                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1712
1713         return hotplug_status;
1714 }
1715
1716 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1717                                  u32 hotplug_status)
1718 {
1719         u32 pin_mask = 0, long_mask = 0;
1720
1721         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1722             IS_CHERRYVIEW(dev_priv)) {
1723                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1724
1725                 if (hotplug_trigger) {
1726                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1727                                            hotplug_trigger, hpd_status_g4x,
1728                                            i9xx_port_hotplug_long_detect);
1729
1730                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1731                 }
1732
1733                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1734                         dp_aux_irq_handler(dev_priv);
1735         } else {
1736                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1737
1738                 if (hotplug_trigger) {
1739                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1740                                            hotplug_trigger, hpd_status_i915,
1741                                            i9xx_port_hotplug_long_detect);
1742                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1743                 }
1744         }
1745 }
1746
1747 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1748 {
1749         struct drm_device *dev = arg;
1750         struct drm_i915_private *dev_priv = to_i915(dev);
1751         irqreturn_t ret = IRQ_NONE;
1752
1753         if (!intel_irqs_enabled(dev_priv))
1754                 return IRQ_NONE;
1755
1756         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1757         disable_rpm_wakeref_asserts(dev_priv);
1758
1759         do {
1760                 u32 iir, gt_iir, pm_iir;
1761                 u32 pipe_stats[I915_MAX_PIPES] = {};
1762                 u32 hotplug_status = 0;
1763                 u32 ier = 0;
1764
1765                 gt_iir = I915_READ(GTIIR);
1766                 pm_iir = I915_READ(GEN6_PMIIR);
1767                 iir = I915_READ(VLV_IIR);
1768
1769                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1770                         break;
1771
1772                 ret = IRQ_HANDLED;
1773
1774                 /*
1775                  * Theory on interrupt generation, based on empirical evidence:
1776                  *
1777                  * x = ((VLV_IIR & VLV_IER) ||
1778                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1779                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1780                  *
1781                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1782                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1783                  * guarantee the CPU interrupt will be raised again even if we
1784                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1785                  * bits this time around.
1786                  */
1787                 I915_WRITE(VLV_MASTER_IER, 0);
1788                 ier = I915_READ(VLV_IER);
1789                 I915_WRITE(VLV_IER, 0);
1790
1791                 if (gt_iir)
1792                         I915_WRITE(GTIIR, gt_iir);
1793                 if (pm_iir)
1794                         I915_WRITE(GEN6_PMIIR, pm_iir);
1795
1796                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1797                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1798
1799                 /* Call regardless, as some status bits might not be
1800                  * signalled in iir */
1801                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1802
1803                 /*
1804                  * VLV_IIR is single buffered, and reflects the level
1805                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1806                  */
1807                 if (iir)
1808                         I915_WRITE(VLV_IIR, iir);
1809
1810                 I915_WRITE(VLV_IER, ier);
1811                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1812                 POSTING_READ(VLV_MASTER_IER);
1813
1814                 if (gt_iir)
1815                         snb_gt_irq_handler(dev_priv, gt_iir);
1816                 if (pm_iir)
1817                         gen6_rps_irq_handler(dev_priv, pm_iir);
1818
1819                 if (hotplug_status)
1820                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1821
1822                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1823         } while (0);
1824
1825         enable_rpm_wakeref_asserts(dev_priv);
1826
1827         return ret;
1828 }
1829
1830 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1831 {
1832         struct drm_device *dev = arg;
1833         struct drm_i915_private *dev_priv = to_i915(dev);
1834         irqreturn_t ret = IRQ_NONE;
1835
1836         if (!intel_irqs_enabled(dev_priv))
1837                 return IRQ_NONE;
1838
1839         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1840         disable_rpm_wakeref_asserts(dev_priv);
1841
1842         do {
1843                 u32 master_ctl, iir;
1844                 u32 gt_iir[4] = {};
1845                 u32 pipe_stats[I915_MAX_PIPES] = {};
1846                 u32 hotplug_status = 0;
1847                 u32 ier = 0;
1848
1849                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1850                 iir = I915_READ(VLV_IIR);
1851
1852                 if (master_ctl == 0 && iir == 0)
1853                         break;
1854
1855                 ret = IRQ_HANDLED;
1856
1857                 /*
1858                  * Theory on interrupt generation, based on empirical evidence:
1859                  *
1860                  * x = ((VLV_IIR & VLV_IER) ||
1861                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1862                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1863                  *
1864                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1865                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1866                  * guarantee the CPU interrupt will be raised again even if we
1867                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1868                  * bits this time around.
1869                  */
1870                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1871                 ier = I915_READ(VLV_IER);
1872                 I915_WRITE(VLV_IER, 0);
1873
1874                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1875
1876                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1877                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1878
1879                 /* Call regardless, as some status bits might not be
1880                  * signalled in iir */
1881                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1882
1883                 /*
1884                  * VLV_IIR is single buffered, and reflects the level
1885                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1886                  */
1887                 if (iir)
1888                         I915_WRITE(VLV_IIR, iir);
1889
1890                 I915_WRITE(VLV_IER, ier);
1891                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1892                 POSTING_READ(GEN8_MASTER_IRQ);
1893
1894                 gen8_gt_irq_handler(dev_priv, gt_iir);
1895
1896                 if (hotplug_status)
1897                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1898
1899                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1900         } while (0);
1901
1902         enable_rpm_wakeref_asserts(dev_priv);
1903
1904         return ret;
1905 }
1906
1907 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1908                                 u32 hotplug_trigger,
1909                                 const u32 hpd[HPD_NUM_PINS])
1910 {
1911         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1912
1913         /*
1914          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1915          * unless we touch the hotplug register, even if hotplug_trigger is
1916          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1917          * errors.
1918          */
1919         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1920         if (!hotplug_trigger) {
1921                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1922                         PORTD_HOTPLUG_STATUS_MASK |
1923                         PORTC_HOTPLUG_STATUS_MASK |
1924                         PORTB_HOTPLUG_STATUS_MASK;
1925                 dig_hotplug_reg &= ~mask;
1926         }
1927
1928         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1929         if (!hotplug_trigger)
1930                 return;
1931
1932         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1933                            dig_hotplug_reg, hpd,
1934                            pch_port_hotplug_long_detect);
1935
1936         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1937 }
1938
1939 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1940 {
1941         int pipe;
1942         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1943
1944         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1945
1946         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1947                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1948                                SDE_AUDIO_POWER_SHIFT);
1949                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1950                                  port_name(port));
1951         }
1952
1953         if (pch_iir & SDE_AUX_MASK)
1954                 dp_aux_irq_handler(dev_priv);
1955
1956         if (pch_iir & SDE_GMBUS)
1957                 gmbus_irq_handler(dev_priv);
1958
1959         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1960                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1961
1962         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1963                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1964
1965         if (pch_iir & SDE_POISON)
1966                 DRM_ERROR("PCH poison interrupt\n");
1967
1968         if (pch_iir & SDE_FDI_MASK)
1969                 for_each_pipe(dev_priv, pipe)
1970                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1971                                          pipe_name(pipe),
1972                                          I915_READ(FDI_RX_IIR(pipe)));
1973
1974         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1975                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1976
1977         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1978                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1979
1980         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1981                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1982
1983         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1984                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1985 }
1986
1987 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1988 {
1989         u32 err_int = I915_READ(GEN7_ERR_INT);
1990         enum i915_pipe pipe;
1991
1992         if (err_int & ERR_INT_POISON)
1993                 DRM_ERROR("Poison interrupt\n");
1994
1995         for_each_pipe(dev_priv, pipe) {
1996                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1997                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1998
1999                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2000                         if (IS_IVYBRIDGE(dev_priv))
2001                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2002                         else
2003                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2004                 }
2005         }
2006
2007         I915_WRITE(GEN7_ERR_INT, err_int);
2008 }
2009
2010 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2011 {
2012         u32 serr_int = I915_READ(SERR_INT);
2013
2014         if (serr_int & SERR_INT_POISON)
2015                 DRM_ERROR("PCH poison interrupt\n");
2016
2017         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2018                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2019
2020         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2021                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2022
2023         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2024                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2025
2026         I915_WRITE(SERR_INT, serr_int);
2027 }
2028
2029 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2030 {
2031         int pipe;
2032         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2033
2034         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2035
2036         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2037                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2038                                SDE_AUDIO_POWER_SHIFT_CPT);
2039                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2040                                  port_name(port));
2041         }
2042
2043         if (pch_iir & SDE_AUX_MASK_CPT)
2044                 dp_aux_irq_handler(dev_priv);
2045
2046         if (pch_iir & SDE_GMBUS_CPT)
2047                 gmbus_irq_handler(dev_priv);
2048
2049         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2050                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2051
2052         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2053                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2054
2055         if (pch_iir & SDE_FDI_MASK_CPT)
2056                 for_each_pipe(dev_priv, pipe)
2057                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2058                                          pipe_name(pipe),
2059                                          I915_READ(FDI_RX_IIR(pipe)));
2060
2061         if (pch_iir & SDE_ERROR_CPT)
2062                 cpt_serr_int_handler(dev_priv);
2063 }
2064
2065 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2066 {
2067         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2068                 ~SDE_PORTE_HOTPLUG_SPT;
2069         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2070         u32 pin_mask = 0, long_mask = 0;
2071
2072         if (hotplug_trigger) {
2073                 u32 dig_hotplug_reg;
2074
2075                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2076                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2077
2078                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2079                                    dig_hotplug_reg, hpd_spt,
2080                                    spt_port_hotplug_long_detect);
2081         }
2082
2083         if (hotplug2_trigger) {
2084                 u32 dig_hotplug_reg;
2085
2086                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2087                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2088
2089                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2090                                    dig_hotplug_reg, hpd_spt,
2091                                    spt_port_hotplug2_long_detect);
2092         }
2093
2094         if (pin_mask)
2095                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2096
2097         if (pch_iir & SDE_GMBUS_CPT)
2098                 gmbus_irq_handler(dev_priv);
2099 }
2100
2101 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2102                                 u32 hotplug_trigger,
2103                                 const u32 hpd[HPD_NUM_PINS])
2104 {
2105         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2106
2107         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2108         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2109
2110         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2111                            dig_hotplug_reg, hpd,
2112                            ilk_port_hotplug_long_detect);
2113
2114         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2115 }
2116
2117 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2118                                     u32 de_iir)
2119 {
2120         enum i915_pipe pipe;
2121         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2122
2123         if (hotplug_trigger)
2124                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2125
2126         if (de_iir & DE_AUX_CHANNEL_A)
2127                 dp_aux_irq_handler(dev_priv);
2128
2129         if (de_iir & DE_GSE)
2130                 intel_opregion_asle_intr(dev_priv);
2131
2132         if (de_iir & DE_POISON)
2133                 DRM_ERROR("Poison interrupt\n");
2134
2135         for_each_pipe(dev_priv, pipe) {
2136                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2137                     intel_pipe_handle_vblank(dev_priv, pipe))
2138                         intel_check_page_flip(dev_priv, pipe);
2139
2140                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2141                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2142
2143                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2144                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2145
2146                 /* plane/pipes map 1:1 on ilk+ */
2147                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2148                         intel_finish_page_flip_cs(dev_priv, pipe);
2149         }
2150
2151         /* check event from PCH */
2152         if (de_iir & DE_PCH_EVENT) {
2153                 u32 pch_iir = I915_READ(SDEIIR);
2154
2155                 if (HAS_PCH_CPT(dev_priv))
2156                         cpt_irq_handler(dev_priv, pch_iir);
2157                 else
2158                         ibx_irq_handler(dev_priv, pch_iir);
2159
2160                 /* should clear PCH hotplug event before clear CPU irq */
2161                 I915_WRITE(SDEIIR, pch_iir);
2162         }
2163
2164         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2165                 ironlake_rps_change_irq_handler(dev_priv);
2166 }
2167
2168 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2169                                     u32 de_iir)
2170 {
2171         enum i915_pipe pipe;
2172         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2173
2174         if (hotplug_trigger)
2175                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2176
2177         if (de_iir & DE_ERR_INT_IVB)
2178                 ivb_err_int_handler(dev_priv);
2179
2180         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2181                 dp_aux_irq_handler(dev_priv);
2182
2183         if (de_iir & DE_GSE_IVB)
2184                 intel_opregion_asle_intr(dev_priv);
2185
2186         for_each_pipe(dev_priv, pipe) {
2187                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2188                     intel_pipe_handle_vblank(dev_priv, pipe))
2189                         intel_check_page_flip(dev_priv, pipe);
2190
2191                 /* plane/pipes map 1:1 on ilk+ */
2192                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2193                         intel_finish_page_flip_cs(dev_priv, pipe);
2194         }
2195
2196         /* check event from PCH */
2197         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2198                 u32 pch_iir = I915_READ(SDEIIR);
2199
2200                 cpt_irq_handler(dev_priv, pch_iir);
2201
2202                 /* clear PCH hotplug event before clear CPU irq */
2203                 I915_WRITE(SDEIIR, pch_iir);
2204         }
2205 }
2206
2207 /*
2208  * To handle irqs with the minimum potential races with fresh interrupts, we:
2209  * 1 - Disable Master Interrupt Control.
2210  * 2 - Find the source(s) of the interrupt.
2211  * 3 - Clear the Interrupt Identity bits (IIR).
2212  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2213  * 5 - Re-enable Master Interrupt Control.
2214  */
2215 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2216 {
2217         struct drm_device *dev = arg;
2218         struct drm_i915_private *dev_priv = to_i915(dev);
2219         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2220         irqreturn_t ret = IRQ_NONE;
2221
2222         if (!intel_irqs_enabled(dev_priv))
2223                 return IRQ_NONE;
2224
2225         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2226         disable_rpm_wakeref_asserts(dev_priv);
2227
2228         /* disable master interrupt before clearing iir  */
2229         de_ier = I915_READ(DEIER);
2230         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2231         POSTING_READ(DEIER);
2232
2233         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2234          * interrupts will will be stored on its back queue, and then we'll be
2235          * able to process them after we restore SDEIER (as soon as we restore
2236          * it, we'll get an interrupt if SDEIIR still has something to process
2237          * due to its back queue). */
2238         if (!HAS_PCH_NOP(dev_priv)) {
2239                 sde_ier = I915_READ(SDEIER);
2240                 I915_WRITE(SDEIER, 0);
2241                 POSTING_READ(SDEIER);
2242         }
2243
2244         /* Find, clear, then process each source of interrupt */
2245
2246         gt_iir = I915_READ(GTIIR);
2247         if (gt_iir) {
2248                 I915_WRITE(GTIIR, gt_iir);
2249                 ret = IRQ_HANDLED;
2250                 if (INTEL_GEN(dev_priv) >= 6)
2251                         snb_gt_irq_handler(dev_priv, gt_iir);
2252                 else
2253                         ilk_gt_irq_handler(dev_priv, gt_iir);
2254         }
2255
2256         de_iir = I915_READ(DEIIR);
2257         if (de_iir) {
2258                 I915_WRITE(DEIIR, de_iir);
2259                 ret = IRQ_HANDLED;
2260                 if (INTEL_GEN(dev_priv) >= 7)
2261                         ivb_display_irq_handler(dev_priv, de_iir);
2262                 else
2263                         ilk_display_irq_handler(dev_priv, de_iir);
2264         }
2265
2266         if (INTEL_GEN(dev_priv) >= 6) {
2267                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2268                 if (pm_iir) {
2269                         I915_WRITE(GEN6_PMIIR, pm_iir);
2270                         ret = IRQ_HANDLED;
2271                         gen6_rps_irq_handler(dev_priv, pm_iir);
2272                 }
2273         }
2274
2275         I915_WRITE(DEIER, de_ier);
2276         POSTING_READ(DEIER);
2277         if (!HAS_PCH_NOP(dev_priv)) {
2278                 I915_WRITE(SDEIER, sde_ier);
2279                 POSTING_READ(SDEIER);
2280         }
2281
2282         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2283         enable_rpm_wakeref_asserts(dev_priv);
2284
2285         return ret;
2286 }
2287
2288 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2289                                 u32 hotplug_trigger,
2290                                 const u32 hpd[HPD_NUM_PINS])
2291 {
2292         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2293
2294         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2295         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2296
2297         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2298                            dig_hotplug_reg, hpd,
2299                            bxt_port_hotplug_long_detect);
2300
2301         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2302 }
2303
2304 static irqreturn_t
2305 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2306 {
2307         irqreturn_t ret = IRQ_NONE;
2308         u32 iir;
2309         enum i915_pipe pipe;
2310
2311         if (master_ctl & GEN8_DE_MISC_IRQ) {
2312                 iir = I915_READ(GEN8_DE_MISC_IIR);
2313                 if (iir) {
2314                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2315                         ret = IRQ_HANDLED;
2316                         if (iir & GEN8_DE_MISC_GSE)
2317                                 intel_opregion_asle_intr(dev_priv);
2318                         else
2319                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2320                 }
2321                 else
2322                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2323         }
2324
2325         if (master_ctl & GEN8_DE_PORT_IRQ) {
2326                 iir = I915_READ(GEN8_DE_PORT_IIR);
2327                 if (iir) {
2328                         u32 tmp_mask;
2329                         bool found = false;
2330
2331                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2332                         ret = IRQ_HANDLED;
2333
2334                         tmp_mask = GEN8_AUX_CHANNEL_A;
2335                         if (INTEL_INFO(dev_priv)->gen >= 9)
2336                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2337                                             GEN9_AUX_CHANNEL_C |
2338                                             GEN9_AUX_CHANNEL_D;
2339
2340                         if (iir & tmp_mask) {
2341                                 dp_aux_irq_handler(dev_priv);
2342                                 found = true;
2343                         }
2344
2345                         if (IS_BROXTON(dev_priv)) {
2346                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2347                                 if (tmp_mask) {
2348                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2349                                                             hpd_bxt);
2350                                         found = true;
2351                                 }
2352                         } else if (IS_BROADWELL(dev_priv)) {
2353                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2354                                 if (tmp_mask) {
2355                                         ilk_hpd_irq_handler(dev_priv,
2356                                                             tmp_mask, hpd_bdw);
2357                                         found = true;
2358                                 }
2359                         }
2360
2361                         if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2362                                 gmbus_irq_handler(dev_priv);
2363                                 found = true;
2364                         }
2365
2366                         if (!found)
2367                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2368                 }
2369                 else
2370                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2371         }
2372
2373         for_each_pipe(dev_priv, pipe) {
2374                 u32 flip_done, fault_errors;
2375
2376                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2377                         continue;
2378
2379                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2380                 if (!iir) {
2381                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2382                         continue;
2383                 }
2384
2385                 ret = IRQ_HANDLED;
2386                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2387
2388                 if (iir & GEN8_PIPE_VBLANK &&
2389                     intel_pipe_handle_vblank(dev_priv, pipe))
2390                         intel_check_page_flip(dev_priv, pipe);
2391
2392                 flip_done = iir;
2393                 if (INTEL_INFO(dev_priv)->gen >= 9)
2394                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2395                 else
2396                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2397
2398                 if (flip_done)
2399                         intel_finish_page_flip_cs(dev_priv, pipe);
2400
2401                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2402                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2403
2404                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2405                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2406
2407                 fault_errors = iir;
2408                 if (INTEL_INFO(dev_priv)->gen >= 9)
2409                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2410                 else
2411                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2412
2413                 if (fault_errors)
2414                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2415                                   pipe_name(pipe),
2416                                   fault_errors);
2417         }
2418
2419         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2420             master_ctl & GEN8_DE_PCH_IRQ) {
2421                 /*
2422                  * FIXME(BDW): Assume for now that the new interrupt handling
2423                  * scheme also closed the SDE interrupt handling race we've seen
2424                  * on older pch-split platforms. But this needs testing.
2425                  */
2426                 iir = I915_READ(SDEIIR);
2427                 if (iir) {
2428                         I915_WRITE(SDEIIR, iir);
2429                         ret = IRQ_HANDLED;
2430
2431                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2432                                 spt_irq_handler(dev_priv, iir);
2433                         else
2434                                 cpt_irq_handler(dev_priv, iir);
2435                 } else {
2436                         /*
2437                          * Like on previous PCH there seems to be something
2438                          * fishy going on with forwarding PCH interrupts.
2439                          */
2440                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2441                 }
2442         }
2443
2444         return ret;
2445 }
2446
2447 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2448 {
2449         struct drm_device *dev = arg;
2450         struct drm_i915_private *dev_priv = to_i915(dev);
2451         u32 master_ctl;
2452         u32 gt_iir[4] = {};
2453         irqreturn_t ret;
2454
2455         if (!intel_irqs_enabled(dev_priv))
2456                 return IRQ_NONE;
2457
2458         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2459         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2460         if (!master_ctl)
2461                 return IRQ_NONE;
2462
2463         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2464
2465         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2466         disable_rpm_wakeref_asserts(dev_priv);
2467
2468         /* Find, clear, then process each source of interrupt */
2469         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2470         gen8_gt_irq_handler(dev_priv, gt_iir);
2471         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2472
2473         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2474         POSTING_READ_FW(GEN8_MASTER_IRQ);
2475
2476         enable_rpm_wakeref_asserts(dev_priv);
2477
2478         return ret;
2479 }
2480
2481 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2482 {
2483         /*
2484          * Notify all waiters for GPU completion events that reset state has
2485          * been changed, and that they need to restart their wait after
2486          * checking for potential errors (and bail out to drop locks if there is
2487          * a gpu reset pending so that i915_error_work_func can acquire them).
2488          */
2489
2490         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2491         wake_up_all(&dev_priv->gpu_error.wait_queue);
2492
2493         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2494         wake_up_all(&dev_priv->pending_flip_queue);
2495 }
2496
2497 /**
2498  * i915_reset_and_wakeup - do process context error handling work
2499  * @dev_priv: i915 device private
2500  *
2501  * Fire an error uevent so userspace can see that a hang or error
2502  * was detected.
2503  */
2504 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2505 {
2506         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2507         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2508         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2509         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2510         int ret;
2511
2512         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2513
2514         /*
2515          * Note that there's only one work item which does gpu resets, so we
2516          * need not worry about concurrent gpu resets potentially incrementing
2517          * error->reset_counter twice. We only need to take care of another
2518          * racing irq/hangcheck declaring the gpu dead for a second time. A
2519          * quick check for that is good enough: schedule_work ensures the
2520          * correct ordering between hang detection and this work item, and since
2521          * the reset in-progress bit is only ever set by code outside of this
2522          * work we don't need to worry about any other races.
2523          */
2524         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2525                 DRM_DEBUG_DRIVER("resetting chip\n");
2526                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2527
2528                 /*
2529                  * In most cases it's guaranteed that we get here with an RPM
2530                  * reference held, for example because there is a pending GPU
2531                  * request that won't finish until the reset is done. This
2532                  * isn't the case at least when we get here by doing a
2533                  * simulated reset via debugs, so get an RPM reference.
2534                  */
2535                 intel_runtime_pm_get(dev_priv);
2536
2537                 intel_prepare_reset(dev_priv);
2538
2539                 /*
2540                  * All state reset _must_ be completed before we update the
2541                  * reset counter, for otherwise waiters might miss the reset
2542                  * pending state and not properly drop locks, resulting in
2543                  * deadlocks with the reset work.
2544                  */
2545                 ret = i915_reset(dev_priv);
2546
2547                 intel_finish_reset(dev_priv);
2548
2549                 intel_runtime_pm_put(dev_priv);
2550
2551                 if (ret == 0)
2552                         kobject_uevent_env(kobj,
2553                                            KOBJ_CHANGE, reset_done_event);
2554
2555                 /*
2556                  * Note: The wake_up also serves as a memory barrier so that
2557                  * waiters see the update value of the reset counter atomic_t.
2558                  */
2559                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2560         }
2561 }
2562
2563 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2564 {
2565         uint32_t instdone[I915_NUM_INSTDONE_REG];
2566         u32 eir = I915_READ(EIR);
2567         int pipe, i;
2568
2569         if (!eir)
2570                 return;
2571
2572         pr_err("render error detected, EIR: 0x%08x\n", eir);
2573
2574         i915_get_extra_instdone(dev_priv, instdone);
2575
2576         if (IS_G4X(dev_priv)) {
2577                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2578                         u32 ipeir = I915_READ(IPEIR_I965);
2579
2580                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2581                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2582                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2583                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2584                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2585                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2586                         I915_WRITE(IPEIR_I965, ipeir);
2587                         POSTING_READ(IPEIR_I965);
2588                 }
2589                 if (eir & GM45_ERROR_PAGE_TABLE) {
2590                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2591                         pr_err("page table error\n");
2592                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2593                         I915_WRITE(PGTBL_ER, pgtbl_err);
2594                         POSTING_READ(PGTBL_ER);
2595                 }
2596         }
2597
2598         if (!IS_GEN2(dev_priv)) {
2599                 if (eir & I915_ERROR_PAGE_TABLE) {
2600                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2601                         pr_err("page table error\n");
2602                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2603                         I915_WRITE(PGTBL_ER, pgtbl_err);
2604                         POSTING_READ(PGTBL_ER);
2605                 }
2606         }
2607
2608         if (eir & I915_ERROR_MEMORY_REFRESH) {
2609                 pr_err("memory refresh error:\n");
2610                 for_each_pipe(dev_priv, pipe)
2611                         pr_err("pipe %c stat: 0x%08x\n",
2612                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2613                 /* pipestat has already been acked */
2614         }
2615         if (eir & I915_ERROR_INSTRUCTION) {
2616                 pr_err("instruction error\n");
2617                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2618                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2619                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2620                 if (INTEL_GEN(dev_priv) < 4) {
2621                         u32 ipeir = I915_READ(IPEIR);
2622
2623                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2624                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2625                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2626                         I915_WRITE(IPEIR, ipeir);
2627                         POSTING_READ(IPEIR);
2628                 } else {
2629                         u32 ipeir = I915_READ(IPEIR_I965);
2630
2631                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2632                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2633                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2634                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2635                         I915_WRITE(IPEIR_I965, ipeir);
2636                         POSTING_READ(IPEIR_I965);
2637                 }
2638         }
2639
2640         I915_WRITE(EIR, eir);
2641         POSTING_READ(EIR);
2642         eir = I915_READ(EIR);
2643         if (eir) {
2644                 /*
2645                  * some errors might have become stuck,
2646                  * mask them.
2647                  */
2648                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2649                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2650                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2651         }
2652 }
2653
2654 /**
2655  * i915_handle_error - handle a gpu error
2656  * @dev_priv: i915 device private
2657  * @engine_mask: mask representing engines that are hung
2658  * Do some basic checking of register state at error time and
2659  * dump it to the syslog.  Also call i915_capture_error_state() to make
2660  * sure we get a record and make it available in debugfs.  Fire a uevent
2661  * so userspace knows something bad happened (should trigger collection
2662  * of a ring dump etc.).
2663  * @fmt: Error message format string
2664  */
2665 void i915_handle_error(struct drm_i915_private *dev_priv,
2666                        u32 engine_mask,
2667                        const char *fmt, ...)
2668 {
2669         va_list args;
2670         char error_msg[80];
2671
2672         va_start(args, fmt);
2673         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2674         va_end(args);
2675
2676         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2677         i915_report_and_clear_eir(dev_priv);
2678
2679         if (engine_mask) {
2680                 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2681                                 &dev_priv->gpu_error.reset_counter);
2682
2683                 /*
2684                  * Wakeup waiting processes so that the reset function
2685                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2686                  * various locks. By bumping the reset counter first, the woken
2687                  * processes will see a reset in progress and back off,
2688                  * releasing their locks and then wait for the reset completion.
2689                  * We must do this for _all_ gpu waiters that might hold locks
2690                  * that the reset work needs to acquire.
2691                  *
2692                  * Note: The wake_up serves as the required memory barrier to
2693                  * ensure that the waiters see the updated value of the reset
2694                  * counter atomic_t.
2695                  */
2696                 i915_error_wake_up(dev_priv);
2697         }
2698
2699         i915_reset_and_wakeup(dev_priv);
2700 }
2701
2702 /* Called from drm generic code, passed 'crtc' which
2703  * we use as a pipe index
2704  */
2705 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2706 {
2707         struct drm_i915_private *dev_priv = to_i915(dev);
2708         unsigned long irqflags;
2709
2710         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2711         if (INTEL_INFO(dev)->gen >= 4)
2712                 i915_enable_pipestat(dev_priv, pipe,
2713                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2714         else
2715                 i915_enable_pipestat(dev_priv, pipe,
2716                                      PIPE_VBLANK_INTERRUPT_STATUS);
2717         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2718
2719         return 0;
2720 }
2721
2722 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2723 {
2724         struct drm_i915_private *dev_priv = to_i915(dev);
2725         unsigned long irqflags;
2726         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2727                                                      DE_PIPE_VBLANK(pipe);
2728
2729         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2730         ilk_enable_display_irq(dev_priv, bit);
2731         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2732
2733         return 0;
2734 }
2735
2736 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2737 {
2738         struct drm_i915_private *dev_priv = to_i915(dev);
2739         unsigned long irqflags;
2740
2741         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2742         i915_enable_pipestat(dev_priv, pipe,
2743                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2744         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2745
2746         return 0;
2747 }
2748
2749 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2750 {
2751         struct drm_i915_private *dev_priv = to_i915(dev);
2752         unsigned long irqflags;
2753
2754         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2755         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2756         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2757
2758         return 0;
2759 }
2760
2761 /* Called from drm generic code, passed 'crtc' which
2762  * we use as a pipe index
2763  */
2764 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2765 {
2766         struct drm_i915_private *dev_priv = to_i915(dev);
2767         unsigned long irqflags;
2768
2769         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2770         i915_disable_pipestat(dev_priv, pipe,
2771                               PIPE_VBLANK_INTERRUPT_STATUS |
2772                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2773         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2774 }
2775
2776 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2777 {
2778         struct drm_i915_private *dev_priv = to_i915(dev);
2779         unsigned long irqflags;
2780         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2781                                                      DE_PIPE_VBLANK(pipe);
2782
2783         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2784         ilk_disable_display_irq(dev_priv, bit);
2785         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2786 }
2787
2788 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2789 {
2790         struct drm_i915_private *dev_priv = to_i915(dev);
2791         unsigned long irqflags;
2792
2793         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2794         i915_disable_pipestat(dev_priv, pipe,
2795                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2796         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2797 }
2798
2799 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2800 {
2801         struct drm_i915_private *dev_priv = to_i915(dev);
2802         unsigned long irqflags;
2803
2804         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2805         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2806         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2807 }
2808
2809 static bool
2810 ring_idle(struct intel_engine_cs *engine, u32 seqno)
2811 {
2812         return i915_seqno_passed(seqno,
2813                                  READ_ONCE(engine->last_submitted_seqno));
2814 }
2815
2816 static bool
2817 ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2818 {
2819         if (INTEL_GEN(engine->i915) >= 8) {
2820                 return (ipehr >> 23) == 0x1c;
2821         } else {
2822                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2823                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2824                                  MI_SEMAPHORE_REGISTER);
2825         }
2826 }
2827
2828 static struct intel_engine_cs *
2829 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2830                                  u64 offset)
2831 {
2832         struct drm_i915_private *dev_priv = engine->i915;
2833         struct intel_engine_cs *signaller;
2834
2835         if (INTEL_GEN(dev_priv) >= 8) {
2836                 for_each_engine(signaller, dev_priv) {
2837                         if (engine == signaller)
2838                                 continue;
2839
2840                         if (offset == signaller->semaphore.signal_ggtt[engine->id])
2841                                 return signaller;
2842                 }
2843         } else {
2844                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2845
2846                 for_each_engine(signaller, dev_priv) {
2847                         if(engine == signaller)
2848                                 continue;
2849
2850                         if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2851                                 return signaller;
2852                 }
2853         }
2854
2855         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2856                   engine->id, ipehr, offset);
2857
2858         return NULL;
2859 }
2860
2861 static struct intel_engine_cs *
2862 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2863 {
2864         struct drm_i915_private *dev_priv = engine->i915;
2865         void __iomem *vaddr;
2866         u32 cmd, ipehr, head;
2867         u64 offset = 0;
2868         int i, backwards;
2869
2870         /*
2871          * This function does not support execlist mode - any attempt to
2872          * proceed further into this function will result in a kernel panic
2873          * when dereferencing ring->buffer, which is not set up in execlist
2874          * mode.
2875          *
2876          * The correct way of doing it would be to derive the currently
2877          * executing ring buffer from the current context, which is derived
2878          * from the currently running request. Unfortunately, to get the
2879          * current request we would have to grab the struct_mutex before doing
2880          * anything else, which would be ill-advised since some other thread
2881          * might have grabbed it already and managed to hang itself, causing
2882          * the hang checker to deadlock.
2883          *
2884          * Therefore, this function does not support execlist mode in its
2885          * current form. Just return NULL and move on.
2886          */
2887         if (engine->buffer == NULL)
2888                 return NULL;
2889
2890         ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2891         if (!ipehr_is_semaphore_wait(engine, ipehr))
2892                 return NULL;
2893
2894         /*
2895          * HEAD is likely pointing to the dword after the actual command,
2896          * so scan backwards until we find the MBOX. But limit it to just 3
2897          * or 4 dwords depending on the semaphore wait command size.
2898          * Note that we don't care about ACTHD here since that might
2899          * point at at batch, and semaphores are always emitted into the
2900          * ringbuffer itself.
2901          */
2902         head = I915_READ_HEAD(engine) & HEAD_ADDR;
2903         backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2904         vaddr = (void __iomem *)engine->buffer->vaddr;
2905
2906         for (i = backwards; i; --i) {
2907                 /*
2908                  * Be paranoid and presume the hw has gone off into the wild -
2909                  * our ring is smaller than what the hardware (and hence
2910                  * HEAD_ADDR) allows. Also handles wrap-around.
2911                  */
2912                 head &= engine->buffer->size - 1;
2913
2914                 /* This here seems to blow up */
2915                 cmd = ioread32(vaddr + head);
2916                 if (cmd == ipehr)
2917                         break;
2918
2919                 head -= 4;
2920         }
2921
2922         if (!i)
2923                 return NULL;
2924
2925         *seqno = ioread32(vaddr + head + 4) + 1;
2926         if (INTEL_GEN(dev_priv) >= 8) {
2927                 offset = ioread32(vaddr + head + 12);
2928                 offset <<= 32;
2929                 offset |= ioread32(vaddr + head + 8);
2930         }
2931         return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2932 }
2933
2934 static int semaphore_passed(struct intel_engine_cs *engine)
2935 {
2936         struct drm_i915_private *dev_priv = engine->i915;
2937         struct intel_engine_cs *signaller;
2938         u32 seqno;
2939
2940         engine->hangcheck.deadlock++;
2941
2942         signaller = semaphore_waits_for(engine, &seqno);
2943         if (signaller == NULL)
2944                 return -1;
2945
2946         /* Prevent pathological recursion due to driver bugs */
2947         if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2948                 return -1;
2949
2950         if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2951                 return 1;
2952
2953         /* cursory check for an unkickable deadlock */
2954         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2955             semaphore_passed(signaller) < 0)
2956                 return -1;
2957
2958         return 0;
2959 }
2960
2961 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2962 {
2963         struct intel_engine_cs *engine;
2964
2965         for_each_engine(engine, dev_priv)
2966                 engine->hangcheck.deadlock = 0;
2967 }
2968
2969 static bool subunits_stuck(struct intel_engine_cs *engine)
2970 {
2971         u32 instdone[I915_NUM_INSTDONE_REG];
2972         bool stuck;
2973         int i;
2974
2975         if (engine->id != RCS)
2976                 return true;
2977
2978         i915_get_extra_instdone(engine->i915, instdone);
2979
2980         /* There might be unstable subunit states even when
2981          * actual head is not moving. Filter out the unstable ones by
2982          * accumulating the undone -> done transitions and only
2983          * consider those as progress.
2984          */
2985         stuck = true;
2986         for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2987                 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2988
2989                 if (tmp != engine->hangcheck.instdone[i])
2990                         stuck = false;
2991
2992                 engine->hangcheck.instdone[i] |= tmp;
2993         }
2994
2995         return stuck;
2996 }
2997
2998 static enum intel_ring_hangcheck_action
2999 head_stuck(struct intel_engine_cs *engine, u64 acthd)
3000 {
3001         if (acthd != engine->hangcheck.acthd) {
3002
3003                 /* Clear subunit states on head movement */
3004                 memset(engine->hangcheck.instdone, 0,
3005                        sizeof(engine->hangcheck.instdone));
3006
3007                 return HANGCHECK_ACTIVE;
3008         }
3009
3010         if (!subunits_stuck(engine))
3011                 return HANGCHECK_ACTIVE;
3012
3013         return HANGCHECK_HUNG;
3014 }
3015
3016 static enum intel_ring_hangcheck_action
3017 ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3018 {
3019         struct drm_i915_private *dev_priv = engine->i915;
3020         enum intel_ring_hangcheck_action ha;
3021         u32 tmp;
3022
3023         ha = head_stuck(engine, acthd);
3024         if (ha != HANGCHECK_HUNG)
3025                 return ha;
3026
3027         if (IS_GEN2(dev_priv))
3028                 return HANGCHECK_HUNG;
3029
3030         /* Is the chip hanging on a WAIT_FOR_EVENT?
3031          * If so we can simply poke the RB_WAIT bit
3032          * and break the hang. This should work on
3033          * all but the second generation chipsets.
3034          */
3035         tmp = I915_READ_CTL(engine);
3036         if (tmp & RING_WAIT) {
3037                 i915_handle_error(dev_priv, 0,
3038                                   "Kicking stuck wait on %s",
3039                                   engine->name);
3040                 I915_WRITE_CTL(engine, tmp);
3041                 return HANGCHECK_KICK;
3042         }
3043
3044         if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3045                 switch (semaphore_passed(engine)) {
3046                 default:
3047                         return HANGCHECK_HUNG;
3048                 case 1:
3049                         i915_handle_error(dev_priv, 0,
3050                                           "Kicking stuck semaphore on %s",
3051                                           engine->name);
3052                         I915_WRITE_CTL(engine, tmp);
3053                         return HANGCHECK_KICK;
3054                 case 0:
3055                         return HANGCHECK_WAIT;
3056                 }
3057         }
3058
3059         return HANGCHECK_HUNG;
3060 }
3061
3062 static unsigned long kick_waiters(struct intel_engine_cs *engine)
3063 {
3064         struct drm_i915_private *i915 = engine->i915;
3065         unsigned long irq_count = READ_ONCE(engine->breadcrumbs.irq_wakeups);
3066
3067         if (engine->hangcheck.user_interrupts == irq_count &&
3068             !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3069                 if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
3070                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3071                                   engine->name);
3072
3073                 intel_engine_enable_fake_irq(engine);
3074         }
3075
3076         return irq_count;
3077 }
3078 /*
3079  * This is called when the chip hasn't reported back with completed
3080  * batchbuffers in a long time. We keep track per ring seqno progress and
3081  * if there are no progress, hangcheck score for that ring is increased.
3082  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3083  * we kick the ring. If we see no progress on three subsequent calls
3084  * we assume chip is wedged and try to fix it by resetting the chip.
3085  */
3086 static void i915_hangcheck_elapsed(struct work_struct *work)
3087 {
3088         struct drm_i915_private *dev_priv =
3089                 container_of(work, typeof(*dev_priv),
3090                              gpu_error.hangcheck_work.work);
3091         struct intel_engine_cs *engine;
3092         unsigned int hung = 0, stuck = 0;
3093         int busy_count = 0;
3094 #define BUSY 1
3095 #define KICK 5
3096 #define HUNG 20
3097 #define ACTIVE_DECAY 15
3098
3099         if (!i915.enable_hangcheck)
3100                 return;
3101
3102         if (!READ_ONCE(dev_priv->gt.awake))
3103                 return;
3104
3105         /* As enabling the GPU requires fairly extensive mmio access,
3106          * periodically arm the mmio checker to see if we are triggering
3107          * any invalid access.
3108          */
3109         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3110
3111         for_each_engine(engine, dev_priv) {
3112                 bool busy = intel_engine_has_waiter(engine);
3113                 u64 acthd;
3114                 u32 seqno;
3115                 unsigned user_interrupts;
3116
3117                 semaphore_clear_deadlocks(dev_priv);
3118
3119                 /* We don't strictly need an irq-barrier here, as we are not
3120                  * serving an interrupt request, be paranoid in case the
3121                  * barrier has side-effects (such as preventing a broken
3122                  * cacheline snoop) and so be sure that we can see the seqno
3123                  * advance. If the seqno should stick, due to a stale
3124                  * cacheline, we would erroneously declare the GPU hung.
3125                  */
3126                 if (engine->irq_seqno_barrier)
3127                         engine->irq_seqno_barrier(engine);
3128
3129                 acthd = intel_ring_get_active_head(engine);
3130                 seqno = intel_engine_get_seqno(engine);
3131
3132                 /* Reset stuck interrupts between batch advances */
3133                 user_interrupts = 0;
3134
3135                 if (engine->hangcheck.seqno == seqno) {
3136                         if (ring_idle(engine, seqno)) {
3137                                 engine->hangcheck.action = HANGCHECK_IDLE;
3138                                 if (busy) {
3139                                         /* Safeguard against driver failure */
3140                                         user_interrupts = kick_waiters(engine);
3141                                         engine->hangcheck.score += BUSY;
3142                                 }
3143                         } else {
3144                                 /* We always increment the hangcheck score
3145                                  * if the ring is busy and still processing
3146                                  * the same request, so that no single request
3147                                  * can run indefinitely (such as a chain of
3148                                  * batches). The only time we do not increment
3149                                  * the hangcheck score on this ring, if this
3150                                  * ring is in a legitimate wait for another
3151                                  * ring. In that case the waiting ring is a
3152                                  * victim and we want to be sure we catch the
3153                                  * right culprit. Then every time we do kick
3154                                  * the ring, add a small increment to the
3155                                  * score so that we can catch a batch that is
3156                                  * being repeatedly kicked and so responsible
3157                                  * for stalling the machine.
3158                                  */
3159                                 engine->hangcheck.action = ring_stuck(engine,
3160                                                                       acthd);
3161
3162                                 switch (engine->hangcheck.action) {
3163                                 case HANGCHECK_IDLE:
3164                                 case HANGCHECK_WAIT:
3165                                         break;
3166                                 case HANGCHECK_ACTIVE:
3167                                         engine->hangcheck.score += BUSY;
3168                                         break;
3169                                 case HANGCHECK_KICK:
3170                                         engine->hangcheck.score += KICK;
3171                                         break;
3172                                 case HANGCHECK_HUNG:
3173                                         engine->hangcheck.score += HUNG;
3174                                         break;
3175                                 }
3176                         }
3177
3178                         if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3179                                 hung |= intel_engine_flag(engine);
3180                                 if (engine->hangcheck.action != HANGCHECK_HUNG)
3181                                         stuck |= intel_engine_flag(engine);
3182                         }
3183                 } else {
3184                         engine->hangcheck.action = HANGCHECK_ACTIVE;
3185
3186                         /* Gradually reduce the count so that we catch DoS
3187                          * attempts across multiple batches.
3188                          */
3189                         if (engine->hangcheck.score > 0)
3190                                 engine->hangcheck.score -= ACTIVE_DECAY;
3191                         if (engine->hangcheck.score < 0)
3192                                 engine->hangcheck.score = 0;
3193
3194                         /* Clear head and subunit states on seqno movement */
3195                         acthd = 0;
3196
3197                         memset(engine->hangcheck.instdone, 0,
3198                                sizeof(engine->hangcheck.instdone));
3199                 }
3200
3201                 engine->hangcheck.seqno = seqno;
3202                 engine->hangcheck.acthd = acthd;
3203                 engine->hangcheck.user_interrupts = user_interrupts;
3204                 busy_count += busy;
3205         }
3206
3207         if (hung) {
3208                 char msg[80];
3209                 int len;
3210
3211                 /* If some rings hung but others were still busy, only
3212                  * blame the hanging rings in the synopsis.
3213                  */
3214                 if (stuck != hung)
3215                         hung &= ~stuck;
3216                 len = scnprintf(msg, sizeof(msg),
3217                                 "%s on ", stuck == hung ? "No progress" : "Hang");
3218                 for_each_engine_masked(engine, dev_priv, hung)
3219                         len += scnprintf(msg + len, sizeof(msg) - len,
3220                                          "%s, ", engine->name);
3221                 msg[len-2] = '\0';
3222
3223                 return i915_handle_error(dev_priv, hung, msg);
3224         }
3225
3226         /* Reset timer in case GPU hangs without another request being added */
3227         if (busy_count)
3228                 i915_queue_hangcheck(dev_priv);
3229 }
3230
3231 static void ibx_irq_reset(struct drm_device *dev)
3232 {
3233         struct drm_i915_private *dev_priv = to_i915(dev);
3234
3235         if (HAS_PCH_NOP(dev))
3236                 return;
3237
3238         GEN5_IRQ_RESET(SDE);
3239
3240         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3241                 I915_WRITE(SERR_INT, 0xffffffff);
3242 }
3243
3244 /*
3245  * SDEIER is also touched by the interrupt handler to work around missed PCH
3246  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3247  * instead we unconditionally enable all PCH interrupt sources here, but then
3248  * only unmask them as needed with SDEIMR.
3249  *
3250  * This function needs to be called before interrupts are enabled.
3251  */
3252 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3253 {
3254         struct drm_i915_private *dev_priv = to_i915(dev);
3255
3256         if (HAS_PCH_NOP(dev))
3257                 return;
3258
3259         WARN_ON(I915_READ(SDEIER) != 0);
3260         I915_WRITE(SDEIER, 0xffffffff);
3261         POSTING_READ(SDEIER);
3262 }
3263
3264 static void gen5_gt_irq_reset(struct drm_device *dev)
3265 {
3266         struct drm_i915_private *dev_priv = to_i915(dev);
3267
3268         GEN5_IRQ_RESET(GT);
3269         if (INTEL_INFO(dev)->gen >= 6)
3270                 GEN5_IRQ_RESET(GEN6_PM);
3271 }
3272
3273 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3274 {
3275         enum i915_pipe pipe;
3276
3277         if (IS_CHERRYVIEW(dev_priv))
3278                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3279         else
3280                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3281
3282         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3283         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3284
3285         for_each_pipe(dev_priv, pipe) {
3286                 I915_WRITE(PIPESTAT(pipe),
3287                            PIPE_FIFO_UNDERRUN_STATUS |
3288                            PIPESTAT_INT_STATUS_MASK);
3289                 dev_priv->pipestat_irq_mask[pipe] = 0;
3290         }
3291
3292         GEN5_IRQ_RESET(VLV_);
3293         dev_priv->irq_mask = ~0;
3294 }
3295
3296 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3297 {
3298         u32 pipestat_mask;
3299         u32 enable_mask;
3300         enum i915_pipe pipe;
3301
3302         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3303                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3304
3305         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3306         for_each_pipe(dev_priv, pipe)
3307                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3308
3309         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3310                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3311                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3312         if (IS_CHERRYVIEW(dev_priv))
3313                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3314
3315         WARN_ON(dev_priv->irq_mask != ~0);
3316
3317         dev_priv->irq_mask = ~enable_mask;
3318
3319         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3320 }
3321
3322 /* drm_dma.h hooks
3323 */
3324 static void ironlake_irq_reset(struct drm_device *dev)
3325 {
3326         struct drm_i915_private *dev_priv = to_i915(dev);
3327
3328         I915_WRITE(HWSTAM, 0xffffffff);
3329
3330         GEN5_IRQ_RESET(DE);
3331         if (IS_GEN7(dev))
3332                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3333
3334         gen5_gt_irq_reset(dev);
3335
3336         ibx_irq_reset(dev);
3337 }
3338
3339 static void valleyview_irq_preinstall(struct drm_device *dev)
3340 {
3341         struct drm_i915_private *dev_priv = to_i915(dev);
3342
3343         I915_WRITE(VLV_MASTER_IER, 0);
3344         POSTING_READ(VLV_MASTER_IER);
3345
3346         gen5_gt_irq_reset(dev);
3347
3348         spin_lock_irq(&dev_priv->irq_lock);
3349         if (dev_priv->display_irqs_enabled)
3350                 vlv_display_irq_reset(dev_priv);
3351         spin_unlock_irq(&dev_priv->irq_lock);
3352 }
3353
3354 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3355 {
3356         GEN8_IRQ_RESET_NDX(GT, 0);
3357         GEN8_IRQ_RESET_NDX(GT, 1);
3358         GEN8_IRQ_RESET_NDX(GT, 2);
3359         GEN8_IRQ_RESET_NDX(GT, 3);
3360 }
3361
3362 static void gen8_irq_reset(struct drm_device *dev)
3363 {
3364         struct drm_i915_private *dev_priv = to_i915(dev);
3365         int pipe;
3366
3367         I915_WRITE(GEN8_MASTER_IRQ, 0);
3368         POSTING_READ(GEN8_MASTER_IRQ);
3369
3370         gen8_gt_irq_reset(dev_priv);
3371
3372         for_each_pipe(dev_priv, pipe)
3373                 if (intel_display_power_is_enabled(dev_priv,
3374                                                    POWER_DOMAIN_PIPE(pipe)))
3375                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3376
3377         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3378         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3379         GEN5_IRQ_RESET(GEN8_PCU_);
3380
3381         if (HAS_PCH_SPLIT(dev))
3382                 ibx_irq_reset(dev);
3383 }
3384
3385 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3386                                      unsigned int pipe_mask)
3387 {
3388         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3389         enum i915_pipe pipe;
3390
3391         spin_lock_irq(&dev_priv->irq_lock);
3392         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3393                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3394                                   dev_priv->de_irq_mask[pipe],
3395                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3396         spin_unlock_irq(&dev_priv->irq_lock);
3397 }
3398
3399 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3400                                      unsigned int pipe_mask)
3401 {
3402         enum i915_pipe pipe;
3403
3404         spin_lock_irq(&dev_priv->irq_lock);
3405         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3406                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3407         spin_unlock_irq(&dev_priv->irq_lock);
3408
3409         /* make sure we're done processing display irqs */
3410         synchronize_irq(dev_priv->drm.irq);
3411 }
3412
3413 static void cherryview_irq_preinstall(struct drm_device *dev)
3414 {
3415         struct drm_i915_private *dev_priv = to_i915(dev);
3416
3417         I915_WRITE(GEN8_MASTER_IRQ, 0);
3418         POSTING_READ(GEN8_MASTER_IRQ);
3419
3420         gen8_gt_irq_reset(dev_priv);
3421
3422         GEN5_IRQ_RESET(GEN8_PCU_);
3423
3424         spin_lock_irq(&dev_priv->irq_lock);
3425         if (dev_priv->display_irqs_enabled)
3426                 vlv_display_irq_reset(dev_priv);
3427         spin_unlock_irq(&dev_priv->irq_lock);
3428 }
3429
3430 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3431                                   const u32 hpd[HPD_NUM_PINS])
3432 {
3433         struct intel_encoder *encoder;
3434         u32 enabled_irqs = 0;
3435
3436         for_each_intel_encoder(&dev_priv->drm, encoder)
3437                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3438                         enabled_irqs |= hpd[encoder->hpd_pin];
3439
3440         return enabled_irqs;
3441 }
3442
3443 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3444 {
3445         u32 hotplug_irqs, hotplug, enabled_irqs;
3446
3447         if (HAS_PCH_IBX(dev_priv)) {
3448                 hotplug_irqs = SDE_HOTPLUG_MASK;
3449                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3450         } else {
3451                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3452                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3453         }
3454
3455         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3456
3457         /*
3458          * Enable digital hotplug on the PCH, and configure the DP short pulse
3459          * duration to 2ms (which is the minimum in the Display Port spec).
3460          * The pulse duration bits are reserved on LPT+.
3461          */
3462         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3463         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3464         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3465         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3466         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3467         /*
3468          * When CPU and PCH are on the same package, port A
3469          * HPD must be enabled in both north and south.
3470          */
3471         if (HAS_PCH_LPT_LP(dev_priv))
3472                 hotplug |= PORTA_HOTPLUG_ENABLE;
3473         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3474 }
3475
3476 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3477 {
3478         u32 hotplug_irqs, hotplug, enabled_irqs;
3479
3480         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3481         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3482
3483         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3484
3485         /* Enable digital hotplug on the PCH */
3486         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3487         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3488                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3489         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3490
3491         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3492         hotplug |= PORTE_HOTPLUG_ENABLE;
3493         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3494 }
3495
3496 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3497 {
3498         u32 hotplug_irqs, hotplug, enabled_irqs;
3499
3500         if (INTEL_GEN(dev_priv) >= 8) {
3501                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3502                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3503
3504                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3505         } else if (INTEL_GEN(dev_priv) >= 7) {
3506                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3507                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3508
3509                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3510         } else {
3511                 hotplug_irqs = DE_DP_A_HOTPLUG;
3512                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3513
3514                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3515         }
3516
3517         /*
3518          * Enable digital hotplug on the CPU, and configure the DP short pulse
3519          * duration to 2ms (which is the minimum in the Display Port spec)
3520          * The pulse duration bits are reserved on HSW+.
3521          */
3522         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3523         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3524         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3525         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3526
3527         ibx_hpd_irq_setup(dev_priv);
3528 }
3529
3530 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3531 {
3532         u32 hotplug_irqs, hotplug, enabled_irqs;
3533
3534         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3535         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3536
3537         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3538
3539         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3540         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3541                 PORTA_HOTPLUG_ENABLE;
3542
3543         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3544                       hotplug, enabled_irqs);
3545         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3546
3547         /*
3548          * For BXT invert bit has to be set based on AOB design
3549          * for HPD detection logic, update it based on VBT fields.
3550          */
3551
3552         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3553             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3554                 hotplug |= BXT_DDIA_HPD_INVERT;
3555         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3556             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3557                 hotplug |= BXT_DDIB_HPD_INVERT;
3558         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3559             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3560                 hotplug |= BXT_DDIC_HPD_INVERT;
3561
3562         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3563 }
3564
3565 static void ibx_irq_postinstall(struct drm_device *dev)
3566 {
3567         struct drm_i915_private *dev_priv = to_i915(dev);
3568         u32 mask;
3569
3570         if (HAS_PCH_NOP(dev))
3571                 return;
3572
3573         if (HAS_PCH_IBX(dev))
3574                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3575         else
3576                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3577
3578         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3579         I915_WRITE(SDEIMR, ~mask);
3580 }
3581
3582 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3583 {
3584         struct drm_i915_private *dev_priv = to_i915(dev);
3585         u32 pm_irqs, gt_irqs;
3586
3587         pm_irqs = gt_irqs = 0;
3588
3589         dev_priv->gt_irq_mask = ~0;
3590         if (HAS_L3_DPF(dev)) {
3591                 /* L3 parity interrupt is always unmasked. */
3592                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3593                 gt_irqs |= GT_PARITY_ERROR(dev);
3594         }
3595
3596         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3597         if (IS_GEN5(dev)) {
3598                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3599         } else {
3600                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3601         }
3602
3603         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3604
3605         if (INTEL_INFO(dev)->gen >= 6) {
3606                 /*
3607                  * RPS interrupts will get enabled/disabled on demand when RPS
3608                  * itself is enabled/disabled.
3609                  */
3610                 if (HAS_VEBOX(dev))
3611                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3612
3613                 dev_priv->pm_irq_mask = 0xffffffff;
3614                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3615         }
3616 }
3617
3618 static int ironlake_irq_postinstall(struct drm_device *dev)
3619 {
3620         struct drm_i915_private *dev_priv = to_i915(dev);
3621         u32 display_mask, extra_mask;
3622
3623         if (INTEL_INFO(dev)->gen >= 7) {
3624                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3625                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3626                                 DE_PLANEB_FLIP_DONE_IVB |
3627                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3628                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3629                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3630                               DE_DP_A_HOTPLUG_IVB);
3631         } else {
3632                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3633                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3634                                 DE_AUX_CHANNEL_A |
3635                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3636                                 DE_POISON);
3637                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3638                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3639                               DE_DP_A_HOTPLUG);
3640         }
3641
3642         dev_priv->irq_mask = ~display_mask;
3643
3644         I915_WRITE(HWSTAM, 0xeffe);
3645
3646         ibx_irq_pre_postinstall(dev);
3647
3648         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3649
3650         gen5_gt_irq_postinstall(dev);
3651
3652         ibx_irq_postinstall(dev);
3653
3654         if (IS_IRONLAKE_M(dev)) {
3655                 /* Enable PCU event interrupts
3656                  *
3657                  * spinlocking not required here for correctness since interrupt
3658                  * setup is guaranteed to run in single-threaded context. But we
3659                  * need it to make the assert_spin_locked happy. */
3660                 spin_lock_irq(&dev_priv->irq_lock);
3661                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3662                 spin_unlock_irq(&dev_priv->irq_lock);
3663         }
3664
3665         return 0;
3666 }
3667
3668 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3669 {
3670         assert_spin_locked(&dev_priv->irq_lock);
3671
3672         if (dev_priv->display_irqs_enabled)
3673                 return;
3674
3675         dev_priv->display_irqs_enabled = true;
3676
3677         if (intel_irqs_enabled(dev_priv)) {
3678                 vlv_display_irq_reset(dev_priv);
3679                 vlv_display_irq_postinstall(dev_priv);
3680         }
3681 }
3682
3683 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3684 {
3685         assert_spin_locked(&dev_priv->irq_lock);
3686
3687         if (!dev_priv->display_irqs_enabled)
3688                 return;
3689
3690         dev_priv->display_irqs_enabled = false;
3691
3692         if (intel_irqs_enabled(dev_priv))
3693                 vlv_display_irq_reset(dev_priv);
3694 }
3695
3696
3697 static int valleyview_irq_postinstall(struct drm_device *dev)
3698 {
3699         struct drm_i915_private *dev_priv = to_i915(dev);
3700
3701         gen5_gt_irq_postinstall(dev);
3702
3703         spin_lock_irq(&dev_priv->irq_lock);
3704         if (dev_priv->display_irqs_enabled)
3705                 vlv_display_irq_postinstall(dev_priv);
3706         spin_unlock_irq(&dev_priv->irq_lock);
3707
3708         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3709         POSTING_READ(VLV_MASTER_IER);
3710
3711         return 0;
3712 }
3713
3714 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3715 {
3716         /* These are interrupts we'll toggle with the ring mask register */
3717         uint32_t gt_interrupts[] = {
3718                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3719                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3720                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3721                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3722                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3723                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3724                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3725                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3726                 0,
3727                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3728                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3729                 };
3730
3731         if (HAS_L3_DPF(dev_priv))
3732                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3733
3734         dev_priv->pm_irq_mask = 0xffffffff;
3735         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3736         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3737         /*
3738          * RPS interrupts will get enabled/disabled on demand when RPS itself
3739          * is enabled/disabled.
3740          */
3741         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3742         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3743 }
3744
3745 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3746 {
3747         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3748         uint32_t de_pipe_enables;
3749         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3750         u32 de_port_enables;
3751         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3752         enum i915_pipe pipe;
3753
3754         if (INTEL_INFO(dev_priv)->gen >= 9) {
3755                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3756                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3757                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3758                                   GEN9_AUX_CHANNEL_D;
3759                 if (IS_BROXTON(dev_priv))
3760                         de_port_masked |= BXT_DE_PORT_GMBUS;
3761         } else {
3762                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3763                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3764         }
3765
3766         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3767                                            GEN8_PIPE_FIFO_UNDERRUN;
3768
3769         de_port_enables = de_port_masked;
3770         if (IS_BROXTON(dev_priv))
3771                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3772         else if (IS_BROADWELL(dev_priv))
3773                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3774
3775         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3776         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3777         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3778
3779         for_each_pipe(dev_priv, pipe)
3780                 if (intel_display_power_is_enabled(dev_priv,
3781                                 POWER_DOMAIN_PIPE(pipe)))
3782                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3783                                           dev_priv->de_irq_mask[pipe],
3784                                           de_pipe_enables);
3785
3786         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3787         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3788 }
3789
3790 static int gen8_irq_postinstall(struct drm_device *dev)
3791 {
3792         struct drm_i915_private *dev_priv = to_i915(dev);
3793
3794         if (HAS_PCH_SPLIT(dev))
3795                 ibx_irq_pre_postinstall(dev);
3796
3797         gen8_gt_irq_postinstall(dev_priv);
3798         gen8_de_irq_postinstall(dev_priv);
3799
3800         if (HAS_PCH_SPLIT(dev))
3801                 ibx_irq_postinstall(dev);
3802
3803         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3804         POSTING_READ(GEN8_MASTER_IRQ);
3805
3806         return 0;
3807 }
3808
3809 static int cherryview_irq_postinstall(struct drm_device *dev)
3810 {
3811         struct drm_i915_private *dev_priv = to_i915(dev);
3812
3813         gen8_gt_irq_postinstall(dev_priv);
3814
3815         spin_lock_irq(&dev_priv->irq_lock);
3816         if (dev_priv->display_irqs_enabled)
3817                 vlv_display_irq_postinstall(dev_priv);
3818         spin_unlock_irq(&dev_priv->irq_lock);
3819
3820         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3821         POSTING_READ(GEN8_MASTER_IRQ);
3822
3823         return 0;
3824 }
3825
3826 static void gen8_irq_uninstall(struct drm_device *dev)
3827 {
3828         struct drm_i915_private *dev_priv = to_i915(dev);
3829
3830         if (!dev_priv)
3831                 return;
3832
3833         gen8_irq_reset(dev);
3834 }
3835
3836 static void valleyview_irq_uninstall(struct drm_device *dev)
3837 {
3838         struct drm_i915_private *dev_priv = to_i915(dev);
3839
3840         if (!dev_priv)
3841                 return;
3842
3843         I915_WRITE(VLV_MASTER_IER, 0);
3844         POSTING_READ(VLV_MASTER_IER);
3845
3846         gen5_gt_irq_reset(dev);
3847
3848         I915_WRITE(HWSTAM, 0xffffffff);
3849
3850         spin_lock_irq(&dev_priv->irq_lock);
3851         if (dev_priv->display_irqs_enabled)
3852                 vlv_display_irq_reset(dev_priv);
3853         spin_unlock_irq(&dev_priv->irq_lock);
3854 }
3855
3856 static void cherryview_irq_uninstall(struct drm_device *dev)
3857 {
3858         struct drm_i915_private *dev_priv = to_i915(dev);
3859
3860         if (!dev_priv)
3861                 return;
3862
3863         I915_WRITE(GEN8_MASTER_IRQ, 0);
3864         POSTING_READ(GEN8_MASTER_IRQ);
3865
3866         gen8_gt_irq_reset(dev_priv);
3867
3868         GEN5_IRQ_RESET(GEN8_PCU_);
3869
3870         spin_lock_irq(&dev_priv->irq_lock);
3871         if (dev_priv->display_irqs_enabled)
3872                 vlv_display_irq_reset(dev_priv);
3873         spin_unlock_irq(&dev_priv->irq_lock);
3874 }
3875
3876 static void ironlake_irq_uninstall(struct drm_device *dev)
3877 {
3878         struct drm_i915_private *dev_priv = to_i915(dev);
3879
3880         if (!dev_priv)
3881                 return;
3882
3883         ironlake_irq_reset(dev);
3884 }
3885
3886 static void i8xx_irq_preinstall(struct drm_device * dev)
3887 {
3888         struct drm_i915_private *dev_priv = to_i915(dev);
3889         int pipe;
3890
3891         for_each_pipe(dev_priv, pipe)
3892                 I915_WRITE(PIPESTAT(pipe), 0);
3893         I915_WRITE16(IMR, 0xffff);
3894         I915_WRITE16(IER, 0x0);
3895         POSTING_READ16(IER);
3896 }
3897
3898 static int i8xx_irq_postinstall(struct drm_device *dev)
3899 {
3900         struct drm_i915_private *dev_priv = to_i915(dev);
3901
3902         I915_WRITE16(EMR,
3903                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3904
3905         /* Unmask the interrupts that we always want on. */
3906         dev_priv->irq_mask =
3907                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3908                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3909                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3910                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3911         I915_WRITE16(IMR, dev_priv->irq_mask);
3912
3913         I915_WRITE16(IER,
3914                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3915                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3916                      I915_USER_INTERRUPT);
3917         POSTING_READ16(IER);
3918
3919         /* Interrupt setup is already guaranteed to be single-threaded, this is
3920          * just to make the assert_spin_locked check happy. */
3921         spin_lock_irq(&dev_priv->irq_lock);
3922         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3923         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3924         spin_unlock_irq(&dev_priv->irq_lock);
3925
3926         return 0;
3927 }
3928
3929 /*
3930  * Returns true when a page flip has completed.
3931  */
3932 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3933                                int plane, int pipe, u32 iir)
3934 {
3935         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3936
3937         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3938                 return false;
3939
3940         if ((iir & flip_pending) == 0)
3941                 goto check_page_flip;
3942
3943         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3944          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3945          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3946          * the flip is completed (no longer pending). Since this doesn't raise
3947          * an interrupt per se, we watch for the change at vblank.
3948          */
3949         if (I915_READ16(ISR) & flip_pending)
3950                 goto check_page_flip;
3951
3952         intel_finish_page_flip_cs(dev_priv, pipe);
3953         return true;
3954
3955 check_page_flip:
3956         intel_check_page_flip(dev_priv, pipe);
3957         return false;
3958 }
3959
3960 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3961 {
3962         struct drm_device *dev = arg;
3963         struct drm_i915_private *dev_priv = to_i915(dev);
3964         u16 iir, new_iir;
3965         u32 pipe_stats[2];
3966         int pipe;
3967         u16 flip_mask =
3968                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3969                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3970         irqreturn_t ret;
3971
3972         if (!intel_irqs_enabled(dev_priv))
3973                 return IRQ_NONE;
3974
3975         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3976         disable_rpm_wakeref_asserts(dev_priv);
3977
3978         ret = IRQ_NONE;
3979         iir = I915_READ16(IIR);
3980         if (iir == 0)
3981                 goto out;
3982
3983         while (iir & ~flip_mask) {
3984                 /* Can't rely on pipestat interrupt bit in iir as it might
3985                  * have been cleared after the pipestat interrupt was received.
3986                  * It doesn't set the bit in iir again, but it still produces
3987                  * interrupts (for non-MSI).
3988                  */
3989                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
3990                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3991                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3992
3993                 for_each_pipe(dev_priv, pipe) {
3994                         i915_reg_t reg = PIPESTAT(pipe);
3995                         pipe_stats[pipe] = I915_READ(reg);
3996
3997                         /*
3998                          * Clear the PIPE*STAT regs before the IIR
3999                          */
4000                         if (pipe_stats[pipe] & 0x8000ffff)
4001                                 I915_WRITE(reg, pipe_stats[pipe]);
4002                 }
4003                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
4004
4005                 I915_WRITE16(IIR, iir & ~flip_mask);
4006                 new_iir = I915_READ16(IIR); /* Flush posted writes */
4007
4008                 if (iir & I915_USER_INTERRUPT)
4009                         notify_ring(&dev_priv->engine[RCS]);
4010
4011                 for_each_pipe(dev_priv, pipe) {
4012                         int plane = pipe;
4013                         if (HAS_FBC(dev_priv))
4014                                 plane = !plane;
4015
4016                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4017                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4018                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4019
4020                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4021                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4022
4023                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4024                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4025                                                                     pipe);
4026                 }
4027
4028                 iir = new_iir;
4029         }
4030         ret = IRQ_HANDLED;
4031
4032 out:
4033         enable_rpm_wakeref_asserts(dev_priv);
4034
4035         return ret;
4036 }
4037
4038 static void i8xx_irq_uninstall(struct drm_device * dev)
4039 {
4040         struct drm_i915_private *dev_priv = to_i915(dev);
4041         int pipe;
4042
4043         for_each_pipe(dev_priv, pipe) {
4044                 /* Clear enable bits; then clear status bits */
4045                 I915_WRITE(PIPESTAT(pipe), 0);
4046                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4047         }
4048         I915_WRITE16(IMR, 0xffff);
4049         I915_WRITE16(IER, 0x0);
4050         I915_WRITE16(IIR, I915_READ16(IIR));
4051 }
4052
4053 static void i915_irq_preinstall(struct drm_device * dev)
4054 {
4055         struct drm_i915_private *dev_priv = to_i915(dev);
4056         int pipe;
4057
4058         if (I915_HAS_HOTPLUG(dev)) {
4059                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4060                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4061         }
4062
4063         I915_WRITE16(HWSTAM, 0xeffe);
4064         for_each_pipe(dev_priv, pipe)
4065                 I915_WRITE(PIPESTAT(pipe), 0);
4066         I915_WRITE(IMR, 0xffffffff);
4067         I915_WRITE(IER, 0x0);
4068         POSTING_READ(IER);
4069 }
4070
4071 static int i915_irq_postinstall(struct drm_device *dev)
4072 {
4073         struct drm_i915_private *dev_priv = to_i915(dev);
4074         u32 enable_mask;
4075
4076         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4077
4078         /* Unmask the interrupts that we always want on. */
4079         dev_priv->irq_mask =
4080                 ~(I915_ASLE_INTERRUPT |
4081                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4082                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4083                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4084                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4085
4086         enable_mask =
4087                 I915_ASLE_INTERRUPT |
4088                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4089                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4090                 I915_USER_INTERRUPT;
4091
4092         if (I915_HAS_HOTPLUG(dev)) {
4093                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4094                 POSTING_READ(PORT_HOTPLUG_EN);
4095
4096                 /* Enable in IER... */
4097                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4098                 /* and unmask in IMR */
4099                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4100         }
4101
4102         I915_WRITE(IMR, dev_priv->irq_mask);
4103         I915_WRITE(IER, enable_mask);
4104         POSTING_READ(IER);
4105
4106         i915_enable_asle_pipestat(dev_priv);
4107
4108         /* Interrupt setup is already guaranteed to be single-threaded, this is
4109          * just to make the assert_spin_locked check happy. */
4110         spin_lock_irq(&dev_priv->irq_lock);
4111         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4112         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4113         spin_unlock_irq(&dev_priv->irq_lock);
4114
4115         return 0;
4116 }
4117
4118 /*
4119  * Returns true when a page flip has completed.
4120  */
4121 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4122                                int plane, int pipe, u32 iir)
4123 {
4124         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4125
4126         if (!intel_pipe_handle_vblank(dev_priv, pipe))
4127                 return false;
4128
4129         if ((iir & flip_pending) == 0)
4130                 goto check_page_flip;
4131
4132         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4133          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4134          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4135          * the flip is completed (no longer pending). Since this doesn't raise
4136          * an interrupt per se, we watch for the change at vblank.
4137          */
4138         if (I915_READ(ISR) & flip_pending)
4139                 goto check_page_flip;
4140
4141         intel_finish_page_flip_cs(dev_priv, pipe);
4142         return true;
4143
4144 check_page_flip:
4145         intel_check_page_flip(dev_priv, pipe);
4146         return false;
4147 }
4148
4149 static irqreturn_t i915_irq_handler(int irq, void *arg)
4150 {
4151         struct drm_device *dev = arg;
4152         struct drm_i915_private *dev_priv = to_i915(dev);
4153         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4154         u32 flip_mask =
4155                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4156                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4157         int pipe, ret = IRQ_NONE;
4158
4159         if (!intel_irqs_enabled(dev_priv))
4160                 return IRQ_NONE;
4161
4162         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4163         disable_rpm_wakeref_asserts(dev_priv);
4164
4165         iir = I915_READ(IIR);
4166         do {
4167                 bool irq_received = (iir & ~flip_mask) != 0;
4168                 bool blc_event = false;
4169
4170                 /* Can't rely on pipestat interrupt bit in iir as it might
4171                  * have been cleared after the pipestat interrupt was received.
4172                  * It doesn't set the bit in iir again, but it still produces
4173                  * interrupts (for non-MSI).
4174                  */
4175                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
4176                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4177                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4178
4179                 for_each_pipe(dev_priv, pipe) {
4180                         i915_reg_t reg = PIPESTAT(pipe);
4181                         pipe_stats[pipe] = I915_READ(reg);
4182
4183                         /* Clear the PIPE*STAT regs before the IIR */
4184                         if (pipe_stats[pipe] & 0x8000ffff) {
4185                                 I915_WRITE(reg, pipe_stats[pipe]);
4186                                 irq_received = true;
4187                         }
4188                 }
4189                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
4190
4191                 if (!irq_received)
4192                         break;
4193
4194                 /* Consume port.  Then clear IIR or we'll miss events */
4195                 if (I915_HAS_HOTPLUG(dev_priv) &&
4196                     iir & I915_DISPLAY_PORT_INTERRUPT) {
4197                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4198                         if (hotplug_status)
4199                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4200                 }
4201
4202                 I915_WRITE(IIR, iir & ~flip_mask);
4203                 new_iir = I915_READ(IIR); /* Flush posted writes */
4204
4205                 if (iir & I915_USER_INTERRUPT)
4206                         notify_ring(&dev_priv->engine[RCS]);
4207
4208                 for_each_pipe(dev_priv, pipe) {
4209                         int plane = pipe;
4210                         if (HAS_FBC(dev_priv))
4211                                 plane = !plane;
4212
4213                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4214                             i915_handle_vblank(dev_priv, plane, pipe, iir))
4215                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4216
4217                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4218                                 blc_event = true;
4219
4220                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4221                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4222
4223                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4224                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4225                                                                     pipe);
4226                 }
4227
4228                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4229                         intel_opregion_asle_intr(dev_priv);
4230
4231                 /* With MSI, interrupts are only generated when iir
4232                  * transitions from zero to nonzero.  If another bit got
4233                  * set while we were handling the existing iir bits, then
4234                  * we would never get another interrupt.
4235                  *
4236                  * This is fine on non-MSI as well, as if we hit this path
4237                  * we avoid exiting the interrupt handler only to generate
4238                  * another one.
4239                  *
4240                  * Note that for MSI this could cause a stray interrupt report
4241                  * if an interrupt landed in the time between writing IIR and
4242                  * the posting read.  This should be rare enough to never
4243                  * trigger the 99% of 100,000 interrupts test for disabling
4244                  * stray interrupts.
4245                  */
4246                 ret = IRQ_HANDLED;
4247                 iir = new_iir;
4248         } while (iir & ~flip_mask);
4249
4250         enable_rpm_wakeref_asserts(dev_priv);
4251
4252         return ret;
4253 }
4254
4255 static void i915_irq_uninstall(struct drm_device * dev)
4256 {
4257         struct drm_i915_private *dev_priv = to_i915(dev);
4258         int pipe;
4259
4260         if (I915_HAS_HOTPLUG(dev)) {
4261                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4262                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4263         }
4264
4265         I915_WRITE16(HWSTAM, 0xffff);
4266         for_each_pipe(dev_priv, pipe) {
4267                 /* Clear enable bits; then clear status bits */
4268                 I915_WRITE(PIPESTAT(pipe), 0);
4269                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4270         }
4271         I915_WRITE(IMR, 0xffffffff);
4272         I915_WRITE(IER, 0x0);
4273
4274         I915_WRITE(IIR, I915_READ(IIR));
4275 }
4276
4277 static void i965_irq_preinstall(struct drm_device * dev)
4278 {
4279         struct drm_i915_private *dev_priv = to_i915(dev);
4280         int pipe;
4281
4282         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4283         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4284
4285         I915_WRITE(HWSTAM, 0xeffe);
4286         for_each_pipe(dev_priv, pipe)
4287                 I915_WRITE(PIPESTAT(pipe), 0);
4288         I915_WRITE(IMR, 0xffffffff);
4289         I915_WRITE(IER, 0x0);
4290         POSTING_READ(IER);
4291 }
4292
4293 static int i965_irq_postinstall(struct drm_device *dev)
4294 {
4295         struct drm_i915_private *dev_priv = to_i915(dev);
4296         u32 enable_mask;
4297         u32 error_mask;
4298
4299         /* Unmask the interrupts that we always want on. */
4300         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4301                                I915_DISPLAY_PORT_INTERRUPT |
4302                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4303                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4304                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4305                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4306                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4307
4308         enable_mask = ~dev_priv->irq_mask;
4309         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4310                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4311         enable_mask |= I915_USER_INTERRUPT;
4312
4313         if (IS_G4X(dev_priv))
4314                 enable_mask |= I915_BSD_USER_INTERRUPT;
4315
4316         /* Interrupt setup is already guaranteed to be single-threaded, this is
4317          * just to make the assert_spin_locked check happy. */
4318         spin_lock_irq(&dev_priv->irq_lock);
4319         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4320         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4321         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4322         spin_unlock_irq(&dev_priv->irq_lock);
4323
4324         /*
4325          * Enable some error detection, note the instruction error mask
4326          * bit is reserved, so we leave it masked.
4327          */
4328         if (IS_G4X(dev_priv)) {
4329                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4330                                GM45_ERROR_MEM_PRIV |
4331                                GM45_ERROR_CP_PRIV |
4332                                I915_ERROR_MEMORY_REFRESH);
4333         } else {
4334                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4335                                I915_ERROR_MEMORY_REFRESH);
4336         }
4337         I915_WRITE(EMR, error_mask);
4338
4339         I915_WRITE(IMR, dev_priv->irq_mask);
4340         I915_WRITE(IER, enable_mask);
4341         POSTING_READ(IER);
4342
4343         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4344         POSTING_READ(PORT_HOTPLUG_EN);
4345
4346         i915_enable_asle_pipestat(dev_priv);
4347
4348         return 0;
4349 }
4350
4351 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4352 {
4353         u32 hotplug_en;
4354
4355         assert_spin_locked(&dev_priv->irq_lock);
4356
4357         /* Note HDMI and DP share hotplug bits */
4358         /* enable bits are the same for all generations */
4359         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4360         /* Programming the CRT detection parameters tends
4361            to generate a spurious hotplug event about three
4362            seconds later.  So just do it once.
4363         */
4364         if (IS_G4X(dev_priv))
4365                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4366         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4367
4368         /* Ignore TV since it's buggy */
4369         i915_hotplug_interrupt_update_locked(dev_priv,
4370                                              HOTPLUG_INT_EN_MASK |
4371                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4372                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4373                                              hotplug_en);
4374 }
4375
4376 static irqreturn_t i965_irq_handler(int irq, void *arg)
4377 {
4378         struct drm_device *dev = arg;
4379         struct drm_i915_private *dev_priv = to_i915(dev);
4380         u32 iir, new_iir;
4381         u32 pipe_stats[I915_MAX_PIPES];
4382         int ret = IRQ_NONE, pipe;
4383         u32 flip_mask =
4384                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4385                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4386
4387         if (!intel_irqs_enabled(dev_priv))
4388                 return IRQ_NONE;
4389
4390         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4391         disable_rpm_wakeref_asserts(dev_priv);
4392
4393         iir = I915_READ(IIR);
4394
4395         for (;;) {
4396                 bool irq_received = (iir & ~flip_mask) != 0;
4397                 bool blc_event = false;
4398
4399                 /* Can't rely on pipestat interrupt bit in iir as it might
4400                  * have been cleared after the pipestat interrupt was received.
4401                  * It doesn't set the bit in iir again, but it still produces
4402                  * interrupts (for non-MSI).
4403                  */
4404                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
4405                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4406                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4407
4408                 for_each_pipe(dev_priv, pipe) {
4409                         i915_reg_t reg = PIPESTAT(pipe);
4410                         pipe_stats[pipe] = I915_READ(reg);
4411
4412                         /*
4413                          * Clear the PIPE*STAT regs before the IIR
4414                          */
4415                         if (pipe_stats[pipe] & 0x8000ffff) {
4416                                 I915_WRITE(reg, pipe_stats[pipe]);
4417                                 irq_received = true;
4418                         }
4419                 }
4420                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
4421
4422                 if (!irq_received)
4423                         break;
4424
4425                 ret = IRQ_HANDLED;
4426
4427                 /* Consume port.  Then clear IIR or we'll miss events */
4428                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4429                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4430                         if (hotplug_status)
4431                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4432                 }
4433
4434                 I915_WRITE(IIR, iir & ~flip_mask);
4435                 new_iir = I915_READ(IIR); /* Flush posted writes */
4436
4437                 if (iir & I915_USER_INTERRUPT)
4438                         notify_ring(&dev_priv->engine[RCS]);
4439                 if (iir & I915_BSD_USER_INTERRUPT)
4440                         notify_ring(&dev_priv->engine[VCS]);
4441
4442                 for_each_pipe(dev_priv, pipe) {
4443                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4444                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4445                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4446
4447                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4448                                 blc_event = true;
4449
4450                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4451                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4452
4453                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4454                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4455                 }
4456
4457                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4458                         intel_opregion_asle_intr(dev_priv);
4459
4460                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4461                         gmbus_irq_handler(dev_priv);
4462
4463                 /* With MSI, interrupts are only generated when iir
4464                  * transitions from zero to nonzero.  If another bit got
4465                  * set while we were handling the existing iir bits, then
4466                  * we would never get another interrupt.
4467                  *
4468                  * This is fine on non-MSI as well, as if we hit this path
4469                  * we avoid exiting the interrupt handler only to generate
4470                  * another one.
4471                  *
4472                  * Note that for MSI this could cause a stray interrupt report
4473                  * if an interrupt landed in the time between writing IIR and
4474                  * the posting read.  This should be rare enough to never
4475                  * trigger the 99% of 100,000 interrupts test for disabling
4476                  * stray interrupts.
4477                  */
4478                 iir = new_iir;
4479         }
4480
4481         enable_rpm_wakeref_asserts(dev_priv);
4482
4483         return ret;
4484 }
4485
4486 static void i965_irq_uninstall(struct drm_device * dev)
4487 {
4488         struct drm_i915_private *dev_priv = to_i915(dev);
4489         int pipe;
4490
4491         if (!dev_priv)
4492                 return;
4493
4494         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4495         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4496
4497         I915_WRITE(HWSTAM, 0xffffffff);
4498         for_each_pipe(dev_priv, pipe)
4499                 I915_WRITE(PIPESTAT(pipe), 0);
4500         I915_WRITE(IMR, 0xffffffff);
4501         I915_WRITE(IER, 0x0);
4502
4503         for_each_pipe(dev_priv, pipe)
4504                 I915_WRITE(PIPESTAT(pipe),
4505                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4506         I915_WRITE(IIR, I915_READ(IIR));
4507 }
4508
4509 /**
4510  * intel_irq_init - initializes irq support
4511  * @dev_priv: i915 device instance
4512  *
4513  * This function initializes all the irq support including work items, timers
4514  * and all the vtables. It does not setup the interrupt itself though.
4515  */
4516 void intel_irq_init(struct drm_i915_private *dev_priv)
4517 {
4518         struct drm_device *dev = &dev_priv->drm;
4519
4520         intel_hpd_init_work(dev_priv);
4521
4522         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4523         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4524
4525         /* Let's track the enabled rps events */
4526         if (IS_VALLEYVIEW(dev_priv))
4527                 /* WaGsvRC0ResidencyMethod:vlv */
4528                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4529         else
4530                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4531
4532         dev_priv->rps.pm_intr_keep = 0;
4533
4534         /*
4535          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4536          * if GEN6_PM_UP_EI_EXPIRED is masked.
4537          *
4538          * TODO: verify if this can be reproduced on VLV,CHV.
4539          */
4540         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4541                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4542
4543         if (INTEL_INFO(dev_priv)->gen >= 8)
4544                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
4545
4546         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4547                           i915_hangcheck_elapsed);
4548
4549         if (IS_GEN2(dev_priv)) {
4550                 dev->max_vblank_count = 0;
4551                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4552         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4553                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4554                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4555         } else {
4556                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4557                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4558         }
4559
4560         /*
4561          * Opt out of the vblank disable timer on everything except gen2.
4562          * Gen2 doesn't have a hardware frame counter and so depends on
4563          * vblank interrupts to produce sane vblank seuquence numbers.
4564          */
4565         if (!IS_GEN2(dev_priv))
4566                 dev->vblank_disable_immediate = true;
4567
4568         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4569         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4570
4571         if (IS_CHERRYVIEW(dev_priv)) {
4572                 dev->driver->irq_handler = cherryview_irq_handler;
4573                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4574                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4575                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4576                 dev->driver->enable_vblank = valleyview_enable_vblank;
4577                 dev->driver->disable_vblank = valleyview_disable_vblank;
4578                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4579         } else if (IS_VALLEYVIEW(dev_priv)) {
4580                 dev->driver->irq_handler = valleyview_irq_handler;
4581                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4582                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4583                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4584                 dev->driver->enable_vblank = valleyview_enable_vblank;
4585                 dev->driver->disable_vblank = valleyview_disable_vblank;
4586                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4587         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4588                 dev->driver->irq_handler = gen8_irq_handler;
4589                 dev->driver->irq_preinstall = gen8_irq_reset;
4590                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4591                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4592                 dev->driver->enable_vblank = gen8_enable_vblank;
4593                 dev->driver->disable_vblank = gen8_disable_vblank;
4594                 if (IS_BROXTON(dev))
4595                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4596                 else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
4597                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4598                 else
4599                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4600         } else if (HAS_PCH_SPLIT(dev)) {
4601                 dev->driver->irq_handler = ironlake_irq_handler;
4602                 dev->driver->irq_preinstall = ironlake_irq_reset;
4603                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4604                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4605                 dev->driver->enable_vblank = ironlake_enable_vblank;
4606                 dev->driver->disable_vblank = ironlake_disable_vblank;
4607                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4608         } else {
4609                 if (IS_GEN2(dev_priv)) {
4610                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4611                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4612                         dev->driver->irq_handler = i8xx_irq_handler;
4613                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4614                 } else if (IS_GEN3(dev_priv)) {
4615                         dev->driver->irq_preinstall = i915_irq_preinstall;
4616                         dev->driver->irq_postinstall = i915_irq_postinstall;
4617                         dev->driver->irq_uninstall = i915_irq_uninstall;
4618                         dev->driver->irq_handler = i915_irq_handler;
4619                 } else {
4620                         dev->driver->irq_preinstall = i965_irq_preinstall;
4621                         dev->driver->irq_postinstall = i965_irq_postinstall;
4622                         dev->driver->irq_uninstall = i965_irq_uninstall;
4623                         dev->driver->irq_handler = i965_irq_handler;
4624                 }
4625                 if (I915_HAS_HOTPLUG(dev_priv))
4626                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4627                 dev->driver->enable_vblank = i915_enable_vblank;
4628                 dev->driver->disable_vblank = i915_disable_vblank;
4629         }
4630 }
4631
4632 /**
4633  * intel_irq_install - enables the hardware interrupt
4634  * @dev_priv: i915 device instance
4635  *
4636  * This function enables the hardware interrupt handling, but leaves the hotplug
4637  * handling still disabled. It is called after intel_irq_init().
4638  *
4639  * In the driver load and resume code we need working interrupts in a few places
4640  * but don't want to deal with the hassle of concurrent probe and hotplug
4641  * workers. Hence the split into this two-stage approach.
4642  */
4643 int intel_irq_install(struct drm_i915_private *dev_priv)
4644 {
4645         /*
4646          * We enable some interrupt sources in our postinstall hooks, so mark
4647          * interrupts as enabled _before_ actually enabling them to avoid
4648          * special cases in our ordering checks.
4649          */
4650         dev_priv->pm.irqs_enabled = true;
4651
4652         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4653 }
4654
4655 /**
4656  * intel_irq_uninstall - finilizes all irq handling
4657  * @dev_priv: i915 device instance
4658  *
4659  * This stops interrupt and hotplug handling and unregisters and frees all
4660  * resources acquired in the init functions.
4661  */
4662 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4663 {
4664         drm_irq_uninstall(&dev_priv->drm);
4665         intel_hpd_cancel_work(dev_priv);
4666         dev_priv->pm.irqs_enabled = false;
4667 }
4668
4669 /**
4670  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4671  * @dev_priv: i915 device instance
4672  *
4673  * This function is used to disable interrupts at runtime, both in the runtime
4674  * pm and the system suspend/resume code.
4675  */
4676 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4677 {
4678         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4679         dev_priv->pm.irqs_enabled = false;
4680         synchronize_irq(dev_priv->drm.irq);
4681 }
4682
4683 /**
4684  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4685  * @dev_priv: i915 device instance
4686  *
4687  * This function is used to enable interrupts at runtime, both in the runtime
4688  * pm and the system suspend/resume code.
4689  */
4690 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4691 {
4692         dev_priv->pm.irqs_enabled = true;
4693         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4694         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4695 }