2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.47 2005/11/28 17:13:41 dillon Exp $
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
48 * Accton EN1217 (www.accton.com)
49 * Conexant LANfinity (www.conexant.com)
51 * Datasheets for the 21143 are available at developer.intel.com.
52 * Datasheets for the clone parts can be found at their respective sites.
53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
54 * The PNIC II is essentially a Macronix 98715A chip; the only difference
55 * worth noting is that its multicast hash table is only 128 bits wide
58 * Written by Bill Paul <wpaul@ee.columbia.edu>
59 * Electrical Engineering Department
60 * Columbia University, New York City
64 * The Intel 21143 is the successor to the DEC 21140. It is basically
65 * the same as the 21140 but with a few new features. The 21143 supports
66 * three kinds of media attachments:
68 * o MII port, for 10Mbps and 100Mbps support and NWAY
69 * autonegotiation provided by an external PHY.
70 * o SYM port, for symbol mode 100Mbps support.
74 * The 100Mbps SYM port and 10baseT port can be used together in
75 * combination with the internal NWAY support to create a 10/100
76 * autosensing configuration.
78 * Note that not all tulip workalikes are handled in this driver: we only
79 * deal with those which are relatively well behaved. The Winbond is
80 * handled separately due to its different register offsets and the
81 * special handling needed for its various bugs. The PNIC is handled
82 * here, but I'm not thrilled about it.
84 * All of the workalike chips use some form of MII transceiver support
85 * with the exception of the Macronix chips, which also have a SYM port.
86 * The ASIX AX88140A is also documented to have a SYM port, but all
87 * the cards I've seen use an MII transceiver, probably because the
88 * AX88140A doesn't support internal NWAY.
91 #include "opt_polling.h"
93 #include <sys/param.h>
94 #include <sys/systm.h>
95 #include <sys/sockio.h>
97 #include <sys/malloc.h>
98 #include <sys/kernel.h>
99 #include <sys/socket.h>
100 #include <sys/sysctl.h>
101 #include <sys/thread2.h>
104 #include <net/ifq_var.h>
105 #include <net/if_arp.h>
106 #include <net/ethernet.h>
107 #include <net/if_dl.h>
108 #include <net/if_media.h>
109 #include <net/if_types.h>
110 #include <net/vlan/if_vlan_var.h>
114 #include <vm/vm.h> /* for vtophys */
115 #include <vm/pmap.h> /* for vtophys */
116 #include <machine/bus_pio.h>
117 #include <machine/bus_memio.h>
118 #include <machine/bus.h>
119 #include <machine/resource.h>
121 #include <sys/rman.h>
123 #include "../mii_layer/mii.h"
124 #include "../mii_layer/miivar.h"
126 #include <bus/pci/pcireg.h>
127 #include <bus/pci/pcivar.h>
129 #define DC_USEIOSPACE
131 #include "if_dcreg.h"
133 /* "controller miibus0" required. See GENERIC if you get errors here. */
134 #include "miibus_if.h"
137 * Various supported device vendors/types and their names.
139 static const struct dc_type dc_devs[] = {
140 { DC_VENDORID_DEC, DC_DEVICEID_21143,
141 "Intel 21143 10/100BaseTX" },
142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
143 "Davicom DM9009 10/100BaseTX" },
144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
145 "Davicom DM9100 10/100BaseTX" },
146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
147 "Davicom DM9102 10/100BaseTX" },
148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
149 "Davicom DM9102A 10/100BaseTX" },
150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
151 "ADMtek AL981 10/100BaseTX" },
152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
153 "ADMtek AN985 10/100BaseTX" },
154 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
155 "ADMtek ADM9511 10/100BaseTX" },
156 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
157 "ADMtek ADM9513 10/100BaseTX" },
158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
159 "ASIX AX88140A 10/100BaseTX" },
160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
161 "ASIX AX88141 10/100BaseTX" },
162 { DC_VENDORID_MX, DC_DEVICEID_98713,
163 "Macronix 98713 10/100BaseTX" },
164 { DC_VENDORID_MX, DC_DEVICEID_98713,
165 "Macronix 98713A 10/100BaseTX" },
166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
167 "Compex RL100-TX 10/100BaseTX" },
168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
169 "Compex RL100-TX 10/100BaseTX" },
170 { DC_VENDORID_MX, DC_DEVICEID_987x5,
171 "Macronix 98715/98715A 10/100BaseTX" },
172 { DC_VENDORID_MX, DC_DEVICEID_987x5,
173 "Macronix 98715AEC-C 10/100BaseTX" },
174 { DC_VENDORID_MX, DC_DEVICEID_987x5,
175 "Macronix 98725 10/100BaseTX" },
176 { DC_VENDORID_MX, DC_DEVICEID_98727,
177 "Macronix 98727/98732 10/100BaseTX" },
178 { DC_VENDORID_LO, DC_DEVICEID_82C115,
179 "LC82C115 PNIC II 10/100BaseTX" },
180 { DC_VENDORID_LO, DC_DEVICEID_82C168,
181 "82c168 PNIC 10/100BaseTX" },
182 { DC_VENDORID_LO, DC_DEVICEID_82C168,
183 "82c169 PNIC 10/100BaseTX" },
184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
185 "Accton EN1217 10/100BaseTX" },
186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
187 "Accton EN2242 MiniPCI 10/100BaseTX" },
188 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
189 "Conexant LANfinity MiniPCI 10/100BaseTX" },
190 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
191 "3Com OfficeConnect 10/100B" },
195 static int dc_probe (device_t);
196 static int dc_attach (device_t);
197 static int dc_detach (device_t);
198 static int dc_suspend (device_t);
199 static int dc_resume (device_t);
200 static void dc_acpi (device_t);
201 static const struct dc_type *dc_devtype (device_t);
202 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
203 static int dc_encap (struct dc_softc *, struct mbuf *,
205 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
206 static int dc_rx_resync (struct dc_softc *);
207 static void dc_rxeof (struct dc_softc *);
208 static void dc_txeof (struct dc_softc *);
209 static void dc_tick (void *);
210 static void dc_tx_underrun (struct dc_softc *);
211 static void dc_intr (void *);
212 static void dc_start (struct ifnet *);
213 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
215 #ifdef DEVICE_POLLING
216 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd,
219 static void dc_init (void *);
220 static void dc_stop (struct dc_softc *);
221 static void dc_watchdog (struct ifnet *);
222 static void dc_shutdown (device_t);
223 static int dc_ifmedia_upd (struct ifnet *);
224 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
226 static void dc_delay (struct dc_softc *);
227 static void dc_eeprom_idle (struct dc_softc *);
228 static void dc_eeprom_putbyte (struct dc_softc *, int);
229 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
230 static void dc_eeprom_getword_pnic
231 (struct dc_softc *, int, u_int16_t *);
232 static void dc_eeprom_width (struct dc_softc *);
233 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
236 static void dc_mii_writebit (struct dc_softc *, int);
237 static int dc_mii_readbit (struct dc_softc *);
238 static void dc_mii_sync (struct dc_softc *);
239 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
240 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
241 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
242 static int dc_miibus_readreg (device_t, int, int);
243 static int dc_miibus_writereg (device_t, int, int, int);
244 static void dc_miibus_statchg (device_t);
245 static void dc_miibus_mediainit (device_t);
247 static u_int32_t dc_crc_mask (struct dc_softc *);
248 static void dc_setcfg (struct dc_softc *, int);
249 static void dc_setfilt_21143 (struct dc_softc *);
250 static void dc_setfilt_asix (struct dc_softc *);
251 static void dc_setfilt_admtek (struct dc_softc *);
253 static void dc_setfilt (struct dc_softc *);
255 static void dc_reset (struct dc_softc *);
256 static int dc_list_rx_init (struct dc_softc *);
257 static int dc_list_tx_init (struct dc_softc *);
259 static void dc_read_srom (struct dc_softc *, int);
260 static void dc_parse_21143_srom (struct dc_softc *);
261 static void dc_decode_leaf_sia (struct dc_softc *,
262 struct dc_eblock_sia *);
263 static void dc_decode_leaf_mii (struct dc_softc *,
264 struct dc_eblock_mii *);
265 static void dc_decode_leaf_sym (struct dc_softc *,
266 struct dc_eblock_sym *);
267 static void dc_apply_fixup (struct dc_softc *, int);
270 #define DC_RES SYS_RES_IOPORT
271 #define DC_RID DC_PCI_CFBIO
273 #define DC_RES SYS_RES_MEMORY
274 #define DC_RID DC_PCI_CFBMA
277 static device_method_t dc_methods[] = {
278 /* Device interface */
279 DEVMETHOD(device_probe, dc_probe),
280 DEVMETHOD(device_attach, dc_attach),
281 DEVMETHOD(device_detach, dc_detach),
282 DEVMETHOD(device_suspend, dc_suspend),
283 DEVMETHOD(device_resume, dc_resume),
284 DEVMETHOD(device_shutdown, dc_shutdown),
287 DEVMETHOD(bus_print_child, bus_generic_print_child),
288 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
291 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
292 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
293 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
294 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
299 static driver_t dc_driver = {
302 sizeof(struct dc_softc)
305 static devclass_t dc_devclass;
308 static int dc_quick=1;
309 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
310 &dc_quick,0,"do not mdevget in dc driver");
313 DECLARE_DUMMY_MODULE(if_dc);
314 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
315 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
317 #define DC_SETBIT(sc, reg, x) \
318 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
320 #define DC_CLRBIT(sc, reg, x) \
321 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
323 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
324 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
327 dc_delay(struct dc_softc *sc)
331 for (idx = (300 / 33) + 1; idx > 0; idx--)
332 CSR_READ_4(sc, DC_BUSCTL);
336 dc_eeprom_width(struct dc_softc *sc)
340 /* Force EEPROM to idle state. */
343 /* Enter EEPROM access mode. */
344 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
346 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
361 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
365 for (i = 1; i <= 12; i++) {
366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
368 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
377 /* Turn off EEPROM access mode. */
385 /* Enter EEPROM access mode. */
386 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
388 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
392 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
395 /* Turn off EEPROM access mode. */
400 dc_eeprom_idle(struct dc_softc *sc)
404 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
406 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
410 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
413 for (i = 0; i < 25; i++) {
414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
416 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
424 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
430 * Send a read command and address to the EEPROM, check for ACK.
433 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
437 d = DC_EECMD_READ >> 6;
440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451 * Feed in each bit and strobe the clock.
453 for (i = sc->dc_romwidth; i--;) {
454 if (addr & (1 << i)) {
455 SIO_SET(DC_SIO_EE_DATAIN);
457 SIO_CLR(DC_SIO_EE_DATAIN);
460 SIO_SET(DC_SIO_EE_CLK);
462 SIO_CLR(DC_SIO_EE_CLK);
470 * Read a word of data stored in the EEPROM at address 'addr.'
471 * The PNIC 82c168/82c169 has its own non-standard way to read
475 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
480 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
482 for (i = 0; i < DC_TIMEOUT; i++) {
484 r = CSR_READ_4(sc, DC_SIO);
485 if (!(r & DC_PN_SIOCTL_BUSY)) {
486 *dest = (u_int16_t)(r & 0xFFFF);
495 * Read a word of data stored in the EEPROM at address 'addr.'
498 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
503 /* Force EEPROM to idle state. */
506 /* Enter EEPROM access mode. */
507 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
509 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
511 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
513 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
517 * Send address of word we want to read.
519 dc_eeprom_putbyte(sc, addr);
522 * Start reading bits from EEPROM.
524 for (i = 0x8000; i; i >>= 1) {
525 SIO_SET(DC_SIO_EE_CLK);
527 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
530 SIO_CLR(DC_SIO_EE_CLK);
534 /* Turn off EEPROM access mode. */
543 * Read a sequence of words from the EEPROM.
546 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap)
549 u_int16_t word = 0, *ptr;
551 for (i = 0; i < cnt; i++) {
553 dc_eeprom_getword_pnic(sc, off + i, &word);
555 dc_eeprom_getword(sc, off + i, &word);
556 ptr = (u_int16_t *)(dest + (i * 2));
567 * The following two routines are taken from the Macronix 98713
568 * Application Notes pp.19-21.
571 * Write a bit to the MII bus.
574 dc_mii_writebit(struct dc_softc *sc, int bit)
577 CSR_WRITE_4(sc, DC_SIO,
578 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
580 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
582 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
583 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
589 * Read a bit from the MII bus.
592 dc_mii_readbit(struct dc_softc *sc)
594 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
595 CSR_READ_4(sc, DC_SIO);
596 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
597 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
598 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
605 * Sync the PHYs by setting data bit and strobing the clock 32 times.
608 dc_mii_sync(struct dc_softc *sc)
612 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
614 for (i = 0; i < 32; i++)
615 dc_mii_writebit(sc, 1);
621 * Clock a series of bits through the MII.
624 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
628 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
629 dc_mii_writebit(sc, bits & i);
633 * Read an PHY register through the MII.
636 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
641 * Set up frame for RX.
643 frame->mii_stdelim = DC_MII_STARTDELIM;
644 frame->mii_opcode = DC_MII_READOP;
645 frame->mii_turnaround = 0;
654 * Send command/address info.
656 dc_mii_send(sc, frame->mii_stdelim, 2);
657 dc_mii_send(sc, frame->mii_opcode, 2);
658 dc_mii_send(sc, frame->mii_phyaddr, 5);
659 dc_mii_send(sc, frame->mii_regaddr, 5);
663 dc_mii_writebit(sc, 1);
664 dc_mii_writebit(sc, 0);
668 ack = dc_mii_readbit(sc);
671 * Now try reading data bits. If the ack failed, we still
672 * need to clock through 16 cycles to keep the PHY(s) in sync.
675 for(i = 0; i < 16; i++) {
681 for (i = 0x8000; i; i >>= 1) {
683 if (dc_mii_readbit(sc))
684 frame->mii_data |= i;
690 dc_mii_writebit(sc, 0);
691 dc_mii_writebit(sc, 0);
699 * Write to a PHY register through the MII.
702 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
705 * Set up frame for TX.
708 frame->mii_stdelim = DC_MII_STARTDELIM;
709 frame->mii_opcode = DC_MII_WRITEOP;
710 frame->mii_turnaround = DC_MII_TURNAROUND;
717 dc_mii_send(sc, frame->mii_stdelim, 2);
718 dc_mii_send(sc, frame->mii_opcode, 2);
719 dc_mii_send(sc, frame->mii_phyaddr, 5);
720 dc_mii_send(sc, frame->mii_regaddr, 5);
721 dc_mii_send(sc, frame->mii_turnaround, 2);
722 dc_mii_send(sc, frame->mii_data, 16);
725 dc_mii_writebit(sc, 0);
726 dc_mii_writebit(sc, 0);
732 dc_miibus_readreg(device_t dev, int phy, int reg)
734 struct dc_mii_frame frame;
736 int i, rval, phy_reg = 0;
738 sc = device_get_softc(dev);
739 bzero((char *)&frame, sizeof(frame));
742 * Note: both the AL981 and AN985 have internal PHYs,
743 * however the AL981 provides direct access to the PHY
744 * registers while the AN985 uses a serial MII interface.
745 * The AN985's MII interface is also buggy in that you
746 * can read from any MII address (0 to 31), but only address 1
747 * behaves normally. To deal with both cases, we pretend
748 * that the PHY is at MII address 1.
750 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
754 * Note: the ukphy probes of the RS7112 report a PHY at
755 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
756 * so we only respond to correct one.
758 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
761 if (sc->dc_pmode != DC_PMODE_MII) {
762 if (phy == (MII_NPHY - 1)) {
766 * Fake something to make the probe
767 * code think there's a PHY here.
769 return(BMSR_MEDIAMASK);
773 return(DC_VENDORID_LO);
774 return(DC_VENDORID_DEC);
778 return(DC_DEVICEID_82C168);
779 return(DC_DEVICEID_21143);
789 if (DC_IS_PNIC(sc)) {
790 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
791 (phy << 23) | (reg << 18));
792 for (i = 0; i < DC_TIMEOUT; i++) {
794 rval = CSR_READ_4(sc, DC_PN_MII);
795 if (!(rval & DC_PN_MII_BUSY)) {
797 return(rval == 0xFFFF ? 0 : rval);
803 if (DC_IS_COMET(sc)) {
806 phy_reg = DC_AL_BMCR;
809 phy_reg = DC_AL_BMSR;
812 phy_reg = DC_AL_VENID;
815 phy_reg = DC_AL_DEVID;
818 phy_reg = DC_AL_ANAR;
821 phy_reg = DC_AL_LPAR;
824 phy_reg = DC_AL_ANER;
827 if_printf(&sc->arpcom.ac_if,
828 "phy_read: bad phy register %x\n", reg);
833 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
840 frame.mii_phyaddr = phy;
841 frame.mii_regaddr = reg;
842 if (sc->dc_type == DC_TYPE_98713) {
843 phy_reg = CSR_READ_4(sc, DC_NETCFG);
844 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
846 dc_mii_readreg(sc, &frame);
847 if (sc->dc_type == DC_TYPE_98713)
848 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
850 return(frame.mii_data);
854 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
857 struct dc_mii_frame frame;
860 sc = device_get_softc(dev);
861 bzero((char *)&frame, sizeof(frame));
863 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
866 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
869 if (DC_IS_PNIC(sc)) {
870 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
871 (phy << 23) | (reg << 10) | data);
872 for (i = 0; i < DC_TIMEOUT; i++) {
873 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
879 if (DC_IS_COMET(sc)) {
882 phy_reg = DC_AL_BMCR;
885 phy_reg = DC_AL_BMSR;
888 phy_reg = DC_AL_VENID;
891 phy_reg = DC_AL_DEVID;
894 phy_reg = DC_AL_ANAR;
897 phy_reg = DC_AL_LPAR;
900 phy_reg = DC_AL_ANER;
903 if_printf(&sc->arpcom.ac_if,
904 "phy_write: bad phy register %x\n", reg);
909 CSR_WRITE_4(sc, phy_reg, data);
913 frame.mii_phyaddr = phy;
914 frame.mii_regaddr = reg;
915 frame.mii_data = data;
917 if (sc->dc_type == DC_TYPE_98713) {
918 phy_reg = CSR_READ_4(sc, DC_NETCFG);
919 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
921 dc_mii_writereg(sc, &frame);
922 if (sc->dc_type == DC_TYPE_98713)
923 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
929 dc_miibus_statchg(device_t dev)
932 struct mii_data *mii;
935 sc = device_get_softc(dev);
936 if (DC_IS_ADMTEK(sc))
939 mii = device_get_softc(sc->dc_miibus);
940 ifm = &mii->mii_media;
941 if (DC_IS_DAVICOM(sc) &&
942 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
943 dc_setcfg(sc, ifm->ifm_media);
944 sc->dc_if_media = ifm->ifm_media;
946 dc_setcfg(sc, mii->mii_media_active);
947 sc->dc_if_media = mii->mii_media_active;
954 * Special support for DM9102A cards with HomePNA PHYs. Note:
955 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
956 * to be impossible to talk to the management interface of the DM9801
957 * PHY (its MDIO pin is not connected to anything). Consequently,
958 * the driver has to just 'know' about the additional mode and deal
959 * with it itself. *sigh*
962 dc_miibus_mediainit(device_t dev)
965 struct mii_data *mii;
969 rev = pci_get_revid(dev);
971 sc = device_get_softc(dev);
972 mii = device_get_softc(sc->dc_miibus);
973 ifm = &mii->mii_media;
975 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
976 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
981 #define DC_BITS_512 9
982 #define DC_BITS_128 7
986 dc_crc_mask(struct dc_softc *sc)
989 * The hash table on the PNIC II and the MX98715AEC-C/D/E
990 * chips is only 128 bits wide.
992 if (sc->dc_flags & DC_128BIT_HASH)
993 return ((1 << DC_BITS_128) - 1);
995 /* The hash table on the MX98715BEC is only 64 bits wide. */
996 if (sc->dc_flags & DC_64BIT_HASH)
997 return ((1 << DC_BITS_64) - 1);
999 return ((1 << DC_BITS_512) - 1);
1003 * 21143-style RX filter setup routine. Filter programming is done by
1004 * downloading a special setup frame into the TX engine. 21143, Macronix,
1005 * PNIC, PNIC II and Davicom chips are programmed this way.
1007 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1008 * address (our node address) and a 512-bit hash filter for multicast
1009 * frames. We also sneak the broadcast address into the hash filter since
1013 dc_setfilt_21143(struct dc_softc *sc)
1015 struct dc_desc *sframe;
1016 u_int32_t h, crc_mask, *sp;
1017 struct ifmultiaddr *ifma;
1021 ifp = &sc->arpcom.ac_if;
1023 i = sc->dc_cdata.dc_tx_prod;
1024 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1025 sc->dc_cdata.dc_tx_cnt++;
1026 sframe = &sc->dc_ldata->dc_tx_list[i];
1027 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1028 bzero((char *)sp, DC_SFRAME_LEN);
1030 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1031 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1032 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1034 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1036 /* If we want promiscuous mode, set the allframes bit. */
1037 if (ifp->if_flags & IFF_PROMISC)
1038 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1040 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1042 if (ifp->if_flags & IFF_ALLMULTI)
1043 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1045 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1047 crc_mask = dc_crc_mask(sc);
1048 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1049 if (ifma->ifma_addr->sa_family != AF_LINK)
1052 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1053 ETHER_ADDR_LEN) & crc_mask;
1054 sp[h >> 4] |= 1 << (h & 0xF);
1057 if (ifp->if_flags & IFF_BROADCAST) {
1058 h = ether_crc32_le(ifp->if_broadcastaddr,
1059 ETHER_ADDR_LEN) & crc_mask;
1060 sp[h >> 4] |= 1 << (h & 0xF);
1063 /* Set our MAC address */
1064 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1065 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1066 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1068 sframe->dc_status = DC_TXSTAT_OWN;
1069 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1072 * The PNIC takes an exceedingly long time to process its
1073 * setup frame; wait 10ms after posting the setup frame
1074 * before proceeding, just so it has time to swallow its
1085 dc_setfilt_admtek(struct dc_softc *sc)
1090 u_int32_t hashes[2] = { 0, 0 };
1091 struct ifmultiaddr *ifma;
1093 ifp = &sc->arpcom.ac_if;
1095 /* Init our MAC address */
1096 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1097 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1099 /* If we want promiscuous mode, set the allframes bit. */
1100 if (ifp->if_flags & IFF_PROMISC)
1101 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1103 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1105 if (ifp->if_flags & IFF_ALLMULTI)
1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1110 /* first, zot all the existing hash bits */
1111 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1112 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1115 * If we're already in promisc or allmulti mode, we
1116 * don't have to bother programming the multicast filter.
1118 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1121 /* now program new ones */
1122 if (DC_IS_CENTAUR(sc))
1123 crc_mask = dc_crc_mask(sc);
1126 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1127 if (ifma->ifma_addr->sa_family != AF_LINK)
1129 if (DC_IS_CENTAUR(sc)) {
1131 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1132 ETHER_ADDR_LEN) & crc_mask;
1135 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1137 h = (h >> 26) & crc_mask;
1140 hashes[0] |= (1 << h);
1142 hashes[1] |= (1 << (h - 32));
1145 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1146 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1152 dc_setfilt_asix(struct dc_softc *sc)
1156 u_int32_t hashes[2] = { 0, 0 };
1157 struct ifmultiaddr *ifma;
1159 ifp = &sc->arpcom.ac_if;
1161 /* Init our MAC address */
1162 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1163 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1164 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1165 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1166 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1167 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1169 /* If we want promiscuous mode, set the allframes bit. */
1170 if (ifp->if_flags & IFF_PROMISC)
1171 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1173 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1175 if (ifp->if_flags & IFF_ALLMULTI)
1176 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1178 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1181 * The ASIX chip has a special bit to enable reception
1182 * of broadcast frames.
1184 if (ifp->if_flags & IFF_BROADCAST)
1185 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1187 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1189 /* first, zot all the existing hash bits */
1190 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1191 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1192 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1193 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1196 * If we're already in promisc or allmulti mode, we
1197 * don't have to bother programming the multicast filter.
1199 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1202 /* now program new ones */
1203 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1204 if (ifma->ifma_addr->sa_family != AF_LINK)
1207 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1209 h = (h >> 26) & 0x3f;
1211 hashes[0] |= (1 << h);
1213 hashes[1] |= (1 << (h - 32));
1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1217 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1218 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1219 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1225 dc_setfilt(struct dc_softc *sc)
1227 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1228 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1229 dc_setfilt_21143(sc);
1232 dc_setfilt_asix(sc);
1234 if (DC_IS_ADMTEK(sc))
1235 dc_setfilt_admtek(sc);
1241 * In order to fiddle with the
1242 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1243 * first have to put the transmit and/or receive logic in the idle state.
1246 dc_setcfg(struct dc_softc *sc, int media)
1251 if (IFM_SUBTYPE(media) == IFM_NONE)
1254 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1256 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1258 for (i = 0; i < DC_TIMEOUT; i++) {
1259 isr = CSR_READ_4(sc, DC_ISR);
1260 if ((isr & DC_ISR_TX_IDLE) &&
1261 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1262 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1267 if (i == DC_TIMEOUT) {
1268 if_printf(&sc->arpcom.ac_if,
1269 "failed to force tx and rx to idle state\n");
1273 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1274 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1275 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1276 if (sc->dc_pmode == DC_PMODE_MII) {
1279 if (DC_IS_INTEL(sc)) {
1280 /* there's a write enable bit here that reads as 1 */
1281 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1282 watchdogreg &= ~DC_WDOG_CTLWREN;
1283 watchdogreg |= DC_WDOG_JABBERDIS;
1284 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1286 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1288 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1289 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1290 if (sc->dc_type == DC_TYPE_98713)
1291 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1292 DC_NETCFG_SCRAMBLER));
1293 if (!DC_IS_DAVICOM(sc))
1294 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1295 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1296 if (DC_IS_INTEL(sc))
1297 dc_apply_fixup(sc, IFM_AUTO);
1299 if (DC_IS_PNIC(sc)) {
1300 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1301 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1302 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1304 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1305 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1306 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1307 if (DC_IS_INTEL(sc))
1309 (media & IFM_GMASK) == IFM_FDX ?
1310 IFM_100_TX|IFM_FDX : IFM_100_TX);
1314 if (IFM_SUBTYPE(media) == IFM_10_T) {
1315 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1316 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1317 if (sc->dc_pmode == DC_PMODE_MII) {
1320 /* there's a write enable bit here that reads as 1 */
1321 if (DC_IS_INTEL(sc)) {
1322 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1323 watchdogreg &= ~DC_WDOG_CTLWREN;
1324 watchdogreg |= DC_WDOG_JABBERDIS;
1325 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1327 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1329 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1330 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1331 if (sc->dc_type == DC_TYPE_98713)
1332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1333 if (!DC_IS_DAVICOM(sc))
1334 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1335 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1336 if (DC_IS_INTEL(sc))
1337 dc_apply_fixup(sc, IFM_AUTO);
1339 if (DC_IS_PNIC(sc)) {
1340 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1341 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1342 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1344 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1345 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1346 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1347 if (DC_IS_INTEL(sc)) {
1348 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1349 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1350 if ((media & IFM_GMASK) == IFM_FDX)
1351 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1353 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1354 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1355 DC_CLRBIT(sc, DC_10BTCTRL,
1356 DC_TCTL_AUTONEGENBL);
1358 (media & IFM_GMASK) == IFM_FDX ?
1359 IFM_10_T|IFM_FDX : IFM_10_T);
1366 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1367 * PHY and we want HomePNA mode, set the portsel bit to turn
1368 * on the external MII port.
1370 if (DC_IS_DAVICOM(sc)) {
1371 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1372 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1375 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1379 if ((media & IFM_GMASK) == IFM_FDX) {
1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1381 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1382 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1384 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1385 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1386 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1390 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1396 dc_reset(struct dc_softc *sc)
1400 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1402 for (i = 0; i < DC_TIMEOUT; i++) {
1404 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1408 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) {
1410 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1414 if (i == DC_TIMEOUT)
1415 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
1417 /* Wait a little while for the chip to get its brains in order. */
1420 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1421 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1422 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1425 * Bring the SIA out of reset. In some cases, it looks
1426 * like failing to unreset the SIA soon enough gets it
1427 * into a state where it will never come out of reset
1428 * until we reset the whole chip again.
1430 if (DC_IS_INTEL(sc)) {
1431 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1432 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1433 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1439 static const struct dc_type *
1440 dc_devtype(device_t dev)
1442 const struct dc_type *t;
1447 while(t->dc_name != NULL) {
1448 if ((pci_get_vendor(dev) == t->dc_vid) &&
1449 (pci_get_device(dev) == t->dc_did)) {
1450 /* Check the PCI revision */
1451 rev = pci_get_revid(dev);
1452 if (t->dc_did == DC_DEVICEID_98713 &&
1453 rev >= DC_REVISION_98713A)
1455 if (t->dc_did == DC_DEVICEID_98713_CP &&
1456 rev >= DC_REVISION_98713A)
1458 if (t->dc_did == DC_DEVICEID_987x5 &&
1459 rev >= DC_REVISION_98715AEC_C)
1461 if (t->dc_did == DC_DEVICEID_987x5 &&
1462 rev >= DC_REVISION_98725)
1464 if (t->dc_did == DC_DEVICEID_AX88140A &&
1465 rev >= DC_REVISION_88141)
1467 if (t->dc_did == DC_DEVICEID_82C168 &&
1468 rev >= DC_REVISION_82C169)
1470 if (t->dc_did == DC_DEVICEID_DM9102 &&
1471 rev >= DC_REVISION_DM9102A)
1482 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1483 * IDs against our list and return a device name if we find a match.
1484 * We do a little bit of extra work to identify the exact type of
1485 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1486 * but different revision IDs. The same is true for 98715/98715A
1487 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1488 * cases, the exact chip revision affects driver behavior.
1491 dc_probe(device_t dev)
1493 const struct dc_type *t;
1495 t = dc_devtype(dev);
1497 struct dc_softc *sc = device_get_softc(dev);
1499 /* Need this info to decide on a chip type. */
1501 device_set_desc(dev, t->dc_name);
1509 dc_acpi(device_t dev)
1511 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1512 uint32_t iobase, membase, irq;
1513 struct dc_softc *sc;
1515 /* Save important PCI config data. */
1516 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1517 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1518 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1520 sc = device_get_softc(dev);
1521 /* Reset the power state. */
1522 if_printf(&sc->arpcom.ac_if,
1523 "chip is in D%d power mode "
1524 "-- setting to D0\n", pci_get_powerstate(dev));
1525 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1527 /* Restore PCI config data. */
1528 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1529 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1530 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1535 dc_apply_fixup(struct dc_softc *sc, int media)
1537 struct dc_mediainfo *m;
1545 if (m->dc_media == media)
1553 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1554 reg = (p[0] | (p[1] << 8)) << 16;
1555 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1558 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1559 reg = (p[0] | (p[1] << 8)) << 16;
1560 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1567 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1569 struct dc_mediainfo *m;
1571 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1572 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){
1573 case DC_SIA_CODE_10BT:
1574 m->dc_media = IFM_10_T;
1577 case DC_SIA_CODE_10BT_FDX:
1578 m->dc_media = IFM_10_T|IFM_FDX;
1581 case DC_SIA_CODE_10B2:
1582 m->dc_media = IFM_10_2;
1585 case DC_SIA_CODE_10B5:
1586 m->dc_media = IFM_10_5;
1589 if (l->dc_sia_code & DC_SIA_CODE_EXT){
1592 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1596 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1599 m->dc_next = sc->dc_mi;
1602 sc->dc_pmode = DC_PMODE_SIA;
1608 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1610 struct dc_mediainfo *m;
1612 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1613 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1614 m->dc_media = IFM_100_TX;
1616 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1617 m->dc_media = IFM_100_TX|IFM_FDX;
1620 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1622 m->dc_next = sc->dc_mi;
1625 sc->dc_pmode = DC_PMODE_SYM;
1631 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1634 struct dc_mediainfo *m;
1636 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1637 /* We abuse IFM_AUTO to represent MII. */
1638 m->dc_media = IFM_AUTO;
1639 m->dc_gp_len = l->dc_gpr_len;
1642 p += sizeof(struct dc_eblock_mii);
1644 p += 2 * l->dc_gpr_len;
1645 m->dc_reset_len = *p;
1647 m->dc_reset_ptr = p;
1649 m->dc_next = sc->dc_mi;
1656 dc_read_srom(struct dc_softc *sc, int bits)
1661 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT);
1662 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1666 dc_parse_21143_srom(struct dc_softc *sc)
1668 struct dc_leaf_hdr *lhdr;
1669 struct dc_eblock_hdr *hdr;
1675 loff = sc->dc_srom[27];
1676 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1679 ptr += sizeof(struct dc_leaf_hdr) - 1;
1681 * Look if we got a MII media block.
1683 for (i = 0; i < lhdr->dc_mcnt; i++) {
1684 hdr = (struct dc_eblock_hdr *)ptr;
1685 if (hdr->dc_type == DC_EBLOCK_MII)
1688 ptr += (hdr->dc_len & 0x7F);
1693 * Do the same thing again. Only use SIA and SYM media
1694 * blocks if no MII media block is available.
1697 ptr += sizeof(struct dc_leaf_hdr) - 1;
1698 for (i = 0; i < lhdr->dc_mcnt; i++) {
1699 hdr = (struct dc_eblock_hdr *)ptr;
1700 switch(hdr->dc_type) {
1702 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1706 dc_decode_leaf_sia(sc,
1707 (struct dc_eblock_sia *)hdr);
1711 dc_decode_leaf_sym(sc,
1712 (struct dc_eblock_sym *)hdr);
1715 /* Don't care. Yet. */
1718 ptr += (hdr->dc_len & 0x7F);
1726 * Attach the interface. Allocate softc structures, do ifmedia
1727 * setup and ethernet/BPF attach.
1730 dc_attach(device_t dev)
1733 u_char eaddr[ETHER_ADDR_LEN];
1735 struct dc_softc *sc;
1738 int error = 0, rid, mac_offset;
1740 sc = device_get_softc(dev);
1741 callout_init(&sc->dc_stat_timer);
1743 ifp = &sc->arpcom.ac_if;
1744 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1747 * Handle power management nonsense.
1752 * Map control/status registers.
1754 pci_enable_busmaster(dev);
1757 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1759 if (sc->dc_res == NULL) {
1760 device_printf(dev, "couldn't map ports/memory\n");
1765 sc->dc_btag = rman_get_bustag(sc->dc_res);
1766 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1768 /* Allocate interrupt */
1770 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1771 RF_SHAREABLE | RF_ACTIVE);
1773 if (sc->dc_irq == NULL) {
1774 device_printf(dev, "couldn't map interrupt\n");
1779 revision = pci_get_revid(dev);
1781 /* Get the eeprom width, but PNIC has diff eeprom */
1782 if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
1783 dc_eeprom_width(sc);
1785 switch(sc->dc_info->dc_did) {
1786 case DC_DEVICEID_21143:
1787 sc->dc_type = DC_TYPE_21143;
1788 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1789 sc->dc_flags |= DC_REDUCED_MII_POLL;
1790 /* Save EEPROM contents so we can parse them later. */
1791 dc_read_srom(sc, sc->dc_romwidth);
1793 case DC_DEVICEID_DM9009:
1794 case DC_DEVICEID_DM9100:
1795 case DC_DEVICEID_DM9102:
1796 sc->dc_type = DC_TYPE_DM9102;
1797 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1798 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1799 sc->dc_flags |= DC_TX_ALIGN;
1800 sc->dc_pmode = DC_PMODE_MII;
1801 /* Increase the latency timer value. */
1802 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1803 command &= 0xFFFF00FF;
1804 command |= 0x00008000;
1805 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1807 case DC_DEVICEID_AL981:
1808 sc->dc_type = DC_TYPE_AL981;
1809 sc->dc_flags |= DC_TX_USE_TX_INTR;
1810 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1811 sc->dc_pmode = DC_PMODE_MII;
1812 dc_read_srom(sc, sc->dc_romwidth);
1814 case DC_DEVICEID_AN985:
1815 case DC_DEVICEID_ADM9511:
1816 case DC_DEVICEID_ADM9513:
1817 case DC_DEVICEID_EN2242:
1818 case DC_DEVICEID_3CSOHOB:
1819 sc->dc_type = DC_TYPE_AN985;
1820 sc->dc_flags |= DC_64BIT_HASH;
1821 sc->dc_flags |= DC_TX_USE_TX_INTR;
1822 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1823 sc->dc_pmode = DC_PMODE_MII;
1825 case DC_DEVICEID_98713:
1826 case DC_DEVICEID_98713_CP:
1827 if (revision < DC_REVISION_98713A) {
1828 sc->dc_type = DC_TYPE_98713;
1830 if (revision >= DC_REVISION_98713A) {
1831 sc->dc_type = DC_TYPE_98713A;
1832 sc->dc_flags |= DC_21143_NWAY;
1834 sc->dc_flags |= DC_REDUCED_MII_POLL;
1835 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1837 case DC_DEVICEID_987x5:
1838 case DC_DEVICEID_EN1217:
1840 * Macronix MX98715AEC-C/D/E parts have only a
1841 * 128-bit hash table. We need to deal with these
1842 * in the same manner as the PNIC II so that we
1843 * get the right number of bits out of the
1846 if (revision >= DC_REVISION_98715AEC_C &&
1847 revision < DC_REVISION_98725)
1848 sc->dc_flags |= DC_128BIT_HASH;
1849 sc->dc_type = DC_TYPE_987x5;
1850 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1851 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1853 case DC_DEVICEID_98727:
1854 sc->dc_type = DC_TYPE_987x5;
1855 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1856 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1858 case DC_DEVICEID_82C115:
1859 sc->dc_type = DC_TYPE_PNICII;
1860 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1861 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1863 case DC_DEVICEID_82C168:
1864 sc->dc_type = DC_TYPE_PNIC;
1865 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1866 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1867 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1868 if (revision < DC_REVISION_82C169)
1869 sc->dc_pmode = DC_PMODE_SYM;
1871 case DC_DEVICEID_AX88140A:
1872 sc->dc_type = DC_TYPE_ASIX;
1873 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1874 sc->dc_flags |= DC_REDUCED_MII_POLL;
1875 sc->dc_pmode = DC_PMODE_MII;
1877 case DC_DEVICEID_RS7112:
1878 sc->dc_type = DC_TYPE_CONEXANT;
1879 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1880 sc->dc_flags |= DC_REDUCED_MII_POLL;
1881 sc->dc_pmode = DC_PMODE_MII;
1882 dc_read_srom(sc, sc->dc_romwidth);
1885 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
1889 /* Save the cache line size. */
1890 if (DC_IS_DAVICOM(sc))
1891 sc->dc_cachesize = 0;
1893 sc->dc_cachesize = pci_read_config(dev,
1894 DC_PCI_CFLT, 4) & 0xFF;
1896 /* Reset the adapter. */
1899 /* Take 21143 out of snooze mode */
1900 if (DC_IS_INTEL(sc)) {
1901 command = pci_read_config(dev, DC_PCI_CFDD, 4);
1902 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
1903 pci_write_config(dev, DC_PCI_CFDD, command, 4);
1907 * Try to learn something about the supported media.
1908 * We know that ASIX and ADMtek and Davicom devices
1909 * will *always* be using MII media, so that's a no-brainer.
1910 * The tricky ones are the Macronix/PNIC II and the
1913 if (DC_IS_INTEL(sc))
1914 dc_parse_21143_srom(sc);
1915 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
1916 if (sc->dc_type == DC_TYPE_98713)
1917 sc->dc_pmode = DC_PMODE_MII;
1919 sc->dc_pmode = DC_PMODE_SYM;
1920 } else if (!sc->dc_pmode)
1921 sc->dc_pmode = DC_PMODE_MII;
1924 * Get station address from the EEPROM.
1926 switch(sc->dc_type) {
1928 case DC_TYPE_98713A:
1930 case DC_TYPE_PNICII:
1931 dc_read_eeprom(sc, (caddr_t)&mac_offset,
1932 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
1933 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
1936 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
1938 case DC_TYPE_DM9102:
1941 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
1945 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0);
1946 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1);
1948 case DC_TYPE_CONEXANT:
1949 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
1952 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
1956 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
1957 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1959 if (sc->dc_ldata == NULL) {
1960 device_printf(dev, "no memory for list buffers!\n");
1965 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
1968 ifp->if_mtu = ETHERMTU;
1969 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1970 ifp->if_ioctl = dc_ioctl;
1971 ifp->if_start = dc_start;
1972 #ifdef DEVICE_POLLING
1973 ifp->if_poll = dc_poll;
1975 ifp->if_watchdog = dc_watchdog;
1976 ifp->if_init = dc_init;
1977 ifp->if_baudrate = 10000000;
1978 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
1979 ifq_set_ready(&ifp->if_snd);
1982 * Do MII setup. If this is a 21143, check for a PHY on the
1983 * MII bus after applying any necessary fixups to twiddle the
1984 * GPIO bits. If we don't end up finding a PHY, restore the
1985 * old selection (SIA only or SIA/SYM) and attach the dcphy
1988 if (DC_IS_INTEL(sc)) {
1989 dc_apply_fixup(sc, IFM_AUTO);
1991 sc->dc_pmode = DC_PMODE_MII;
1994 error = mii_phy_probe(dev, &sc->dc_miibus,
1995 dc_ifmedia_upd, dc_ifmedia_sts);
1997 if (error && DC_IS_INTEL(sc)) {
1999 if (sc->dc_pmode != DC_PMODE_SIA)
2000 sc->dc_pmode = DC_PMODE_SYM;
2001 sc->dc_flags |= DC_21143_NWAY;
2002 mii_phy_probe(dev, &sc->dc_miibus,
2003 dc_ifmedia_upd, dc_ifmedia_sts);
2005 * For non-MII cards, we need to have the 21143
2006 * drive the LEDs. Except there are some systems
2007 * like the NEC VersaPro NoteBook PC which have no
2008 * LEDs, and twiddling these bits has adverse effects
2009 * on them. (I.e. you suddenly can't get a link.)
2011 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2012 sc->dc_flags |= DC_TULIP_LEDS;
2017 device_printf(dev, "MII without any PHY!\n");
2023 * Call MI attach routine.
2025 ether_ifattach(ifp, eaddr, NULL);
2027 if (DC_IS_ADMTEK(sc)) {
2029 * Set automatic TX underrun recovery for the ADMtek chips
2031 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2035 * Tell the upper layer(s) we support long frames.
2037 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2039 error = bus_setup_intr(dev, sc->dc_irq, INTR_NETSAFE,
2040 dc_intr, sc, &sc->dc_intrhand,
2041 ifp->if_serializer);
2043 ether_ifdetach(ifp);
2044 device_printf(dev, "couldn't set up irq\n");
2056 dc_detach(device_t dev)
2058 struct dc_softc *sc = device_get_softc(dev);
2059 struct ifnet *ifp = &sc->arpcom.ac_if;
2060 struct dc_mediainfo *m;
2062 lwkt_serialize_enter(ifp->if_serializer);
2064 if (device_is_attached(dev)) {
2066 ether_ifdetach(ifp);
2070 device_delete_child(dev, sc->dc_miibus);
2071 bus_generic_detach(dev);
2073 if (sc->dc_intrhand)
2074 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2077 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2079 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2082 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2083 if (sc->dc_pnic_rx_buf != NULL)
2084 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2086 while(sc->dc_mi != NULL) {
2087 m = sc->dc_mi->dc_next;
2088 free(sc->dc_mi, M_DEVBUF);
2093 free(sc->dc_srom, M_DEVBUF);
2095 lwkt_serialize_exit(ifp->if_serializer);
2100 * Initialize the transmit descriptors.
2103 dc_list_tx_init(struct dc_softc *sc)
2105 struct dc_chain_data *cd;
2106 struct dc_list_data *ld;
2111 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2112 if (i == (DC_TX_LIST_CNT - 1)) {
2113 ld->dc_tx_list[i].dc_next =
2114 vtophys(&ld->dc_tx_list[0]);
2116 ld->dc_tx_list[i].dc_next =
2117 vtophys(&ld->dc_tx_list[i + 1]);
2119 cd->dc_tx_chain[i] = NULL;
2120 ld->dc_tx_list[i].dc_data = 0;
2121 ld->dc_tx_list[i].dc_ctl = 0;
2124 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2131 * Initialize the RX descriptors and allocate mbufs for them. Note that
2132 * we arrange the descriptors in a closed ring, so that the last descriptor
2133 * points back to the first.
2136 dc_list_rx_init(struct dc_softc *sc)
2138 struct dc_chain_data *cd;
2139 struct dc_list_data *ld;
2145 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2146 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2148 if (i == (DC_RX_LIST_CNT - 1)) {
2149 ld->dc_rx_list[i].dc_next =
2150 vtophys(&ld->dc_rx_list[0]);
2152 ld->dc_rx_list[i].dc_next =
2153 vtophys(&ld->dc_rx_list[i + 1]);
2163 * Initialize an RX descriptor and attach an MBUF cluster.
2166 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m)
2168 struct mbuf *m_new = NULL;
2171 c = &sc->dc_ldata->dc_rx_list[i];
2174 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2177 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2180 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2181 m_new->m_data = m_new->m_ext.ext_buf;
2184 m_adj(m_new, sizeof(u_int64_t));
2187 * If this is a PNIC chip, zero the buffer. This is part
2188 * of the workaround for the receive bug in the 82c168 and
2191 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2192 bzero((char *)mtod(m_new, char *), m_new->m_len);
2194 sc->dc_cdata.dc_rx_chain[i] = m_new;
2195 c->dc_data = vtophys(mtod(m_new, caddr_t));
2196 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2197 c->dc_status = DC_RXSTAT_OWN;
2204 * The PNIC chip has a terrible bug in it that manifests itself during
2205 * periods of heavy activity. The exact mode of failure if difficult to
2206 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2207 * will happen on slow machines. The bug is that sometimes instead of
2208 * uploading one complete frame during reception, it uploads what looks
2209 * like the entire contents of its FIFO memory. The frame we want is at
2210 * the end of the whole mess, but we never know exactly how much data has
2211 * been uploaded, so salvaging the frame is hard.
2213 * There is only one way to do it reliably, and it's disgusting.
2214 * Here's what we know:
2216 * - We know there will always be somewhere between one and three extra
2217 * descriptors uploaded.
2219 * - We know the desired received frame will always be at the end of the
2220 * total data upload.
2222 * - We know the size of the desired received frame because it will be
2223 * provided in the length field of the status word in the last descriptor.
2225 * Here's what we do:
2227 * - When we allocate buffers for the receive ring, we bzero() them.
2228 * This means that we know that the buffer contents should be all
2229 * zeros, except for data uploaded by the chip.
2231 * - We also force the PNIC chip to upload frames that include the
2232 * ethernet CRC at the end.
2234 * - We gather all of the bogus frame data into a single buffer.
2236 * - We then position a pointer at the end of this buffer and scan
2237 * backwards until we encounter the first non-zero byte of data.
2238 * This is the end of the received frame. We know we will encounter
2239 * some data at the end of the frame because the CRC will always be
2240 * there, so even if the sender transmits a packet of all zeros,
2241 * we won't be fooled.
2243 * - We know the size of the actual received frame, so we subtract
2244 * that value from the current pointer location. This brings us
2245 * to the start of the actual received packet.
2247 * - We copy this into an mbuf and pass it on, along with the actual
2250 * The performance hit is tremendous, but it beats dropping frames all
2254 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2256 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2258 struct dc_desc *cur_rx;
2259 struct dc_desc *c = NULL;
2260 struct mbuf *m = NULL;
2263 u_int32_t rxstat = 0;
2265 i = sc->dc_pnic_rx_bug_save;
2266 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2267 ptr = sc->dc_pnic_rx_buf;
2268 bzero(ptr, DC_RXLEN * 5);
2270 /* Copy all the bytes from the bogus buffers. */
2272 c = &sc->dc_ldata->dc_rx_list[i];
2273 rxstat = c->dc_status;
2274 m = sc->dc_cdata.dc_rx_chain[i];
2275 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2277 /* If this is the last buffer, break out. */
2278 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2280 dc_newbuf(sc, i, m);
2281 DC_INC(i, DC_RX_LIST_CNT);
2284 /* Find the length of the actual receive frame. */
2285 total_len = DC_RXBYTES(rxstat);
2287 /* Scan backwards until we hit a non-zero byte. */
2292 if ((uintptr_t)(ptr) & 0x3)
2295 /* Now find the start of the frame. */
2297 if (ptr < sc->dc_pnic_rx_buf)
2298 ptr = sc->dc_pnic_rx_buf;
2301 * Now copy the salvaged frame to the last mbuf and fake up
2302 * the status word to make it look like a successful
2305 dc_newbuf(sc, i, m);
2306 bcopy(ptr, mtod(m, char *), total_len);
2307 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2313 * This routine searches the RX ring for dirty descriptors in the
2314 * event that the rxeof routine falls out of sync with the chip's
2315 * current descriptor pointer. This may happen sometimes as a result
2316 * of a "no RX buffer available" condition that happens when the chip
2317 * consumes all of the RX buffers before the driver has a chance to
2318 * process the RX ring. This routine may need to be called more than
2319 * once to bring the driver back in sync with the chip, however we
2320 * should still be getting RX DONE interrupts to drive the search
2321 * for new packets in the RX ring, so we should catch up eventually.
2324 dc_rx_resync(struct dc_softc *sc)
2327 struct dc_desc *cur_rx;
2329 pos = sc->dc_cdata.dc_rx_prod;
2331 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2332 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2333 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2335 DC_INC(pos, DC_RX_LIST_CNT);
2338 /* If the ring really is empty, then just return. */
2339 if (i == DC_RX_LIST_CNT)
2342 /* We've fallen behing the chip: catch it. */
2343 sc->dc_cdata.dc_rx_prod = pos;
2349 * A frame has been uploaded: pass the resulting mbuf chain up to
2350 * the higher level protocols.
2353 dc_rxeof(struct dc_softc *sc)
2357 struct dc_desc *cur_rx;
2358 int i, total_len = 0;
2361 ifp = &sc->arpcom.ac_if;
2362 i = sc->dc_cdata.dc_rx_prod;
2364 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2366 #ifdef DEVICE_POLLING
2367 if (ifp->if_flags & IFF_POLLING) {
2368 if (sc->rxcycles <= 0)
2372 #endif /* DEVICE_POLLING */
2373 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2374 rxstat = cur_rx->dc_status;
2375 m = sc->dc_cdata.dc_rx_chain[i];
2376 total_len = DC_RXBYTES(rxstat);
2378 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2379 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2380 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2381 sc->dc_pnic_rx_bug_save = i;
2382 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2383 DC_INC(i, DC_RX_LIST_CNT);
2386 dc_pnic_rx_bug_war(sc, i);
2387 rxstat = cur_rx->dc_status;
2388 total_len = DC_RXBYTES(rxstat);
2392 sc->dc_cdata.dc_rx_chain[i] = NULL;
2395 * If an error occurs, update stats, clear the
2396 * status word and leave the mbuf cluster in place:
2397 * it should simply get re-used next time this descriptor
2398 * comes up in the ring. However, don't report long
2399 * frames as errors since they could be vlans
2401 if ((rxstat & DC_RXSTAT_RXERR)){
2402 if (!(rxstat & DC_RXSTAT_GIANT) ||
2403 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2404 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2405 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2407 if (rxstat & DC_RXSTAT_COLLSEEN)
2408 ifp->if_collisions++;
2409 dc_newbuf(sc, i, m);
2410 if (rxstat & DC_RXSTAT_CRCERR) {
2411 DC_INC(i, DC_RX_LIST_CNT);
2420 /* No errors; receive the packet. */
2421 total_len -= ETHER_CRC_LEN;
2425 * On the x86 we do not have alignment problems, so try to
2426 * allocate a new buffer for the receive ring, and pass up
2427 * the one where the packet is already, saving the expensive
2428 * copy done in m_devget().
2429 * If we are on an architecture with alignment problems, or
2430 * if the allocation fails, then use m_devget and leave the
2431 * existing buffer in the receive ring.
2433 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2434 m->m_pkthdr.rcvif = ifp;
2435 m->m_pkthdr.len = m->m_len = total_len;
2436 DC_INC(i, DC_RX_LIST_CNT);
2442 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2443 total_len + ETHER_ALIGN, 0, ifp, NULL);
2444 dc_newbuf(sc, i, m);
2445 DC_INC(i, DC_RX_LIST_CNT);
2450 m_adj(m0, ETHER_ALIGN);
2455 ifp->if_input(ifp, m);
2458 sc->dc_cdata.dc_rx_prod = i;
2462 * A frame was downloaded to the chip. It's safe for us to clean up
2467 dc_txeof(struct dc_softc *sc)
2469 struct dc_desc *cur_tx = NULL;
2473 ifp = &sc->arpcom.ac_if;
2476 * Go through our tx list and free mbufs for those
2477 * frames that have been transmitted.
2479 idx = sc->dc_cdata.dc_tx_cons;
2480 while(idx != sc->dc_cdata.dc_tx_prod) {
2483 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2484 txstat = cur_tx->dc_status;
2486 if (txstat & DC_TXSTAT_OWN)
2489 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2490 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2491 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2493 * Yes, the PNIC is so brain damaged
2494 * that it will sometimes generate a TX
2495 * underrun error while DMAing the RX
2496 * filter setup frame. If we detect this,
2497 * we have to send the setup frame again,
2498 * or else the filter won't be programmed
2501 if (DC_IS_PNIC(sc)) {
2502 if (txstat & DC_TXSTAT_ERRSUM)
2505 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2507 sc->dc_cdata.dc_tx_cnt--;
2508 DC_INC(idx, DC_TX_LIST_CNT);
2512 if (DC_IS_CONEXANT(sc)) {
2514 * For some reason Conexant chips like
2515 * setting the CARRLOST flag even when
2516 * the carrier is there. In CURRENT we
2517 * have the same problem for Xircom
2520 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2521 sc->dc_pmode == DC_PMODE_MII &&
2522 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2523 DC_TXSTAT_NOCARRIER)))
2524 txstat &= ~DC_TXSTAT_ERRSUM;
2526 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2527 sc->dc_pmode == DC_PMODE_MII &&
2528 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2529 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2530 txstat &= ~DC_TXSTAT_ERRSUM;
2533 if (txstat & DC_TXSTAT_ERRSUM) {
2535 if (txstat & DC_TXSTAT_EXCESSCOLL)
2536 ifp->if_collisions++;
2537 if (txstat & DC_TXSTAT_LATECOLL)
2538 ifp->if_collisions++;
2539 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2545 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2548 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2549 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2550 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2553 sc->dc_cdata.dc_tx_cnt--;
2554 DC_INC(idx, DC_TX_LIST_CNT);
2557 if (idx != sc->dc_cdata.dc_tx_cons) {
2558 /* some buffers have been freed */
2559 sc->dc_cdata.dc_tx_cons = idx;
2560 ifp->if_flags &= ~IFF_OACTIVE;
2562 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2570 struct dc_softc *sc = xsc;
2571 struct ifnet *ifp = &sc->arpcom.ac_if;
2572 struct mii_data *mii;
2575 lwkt_serialize_enter(ifp->if_serializer);
2577 mii = device_get_softc(sc->dc_miibus);
2579 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2580 if (sc->dc_flags & DC_21143_NWAY) {
2581 r = CSR_READ_4(sc, DC_10BTSTAT);
2582 if (IFM_SUBTYPE(mii->mii_media_active) ==
2583 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2587 if (IFM_SUBTYPE(mii->mii_media_active) ==
2588 IFM_10_T && (r & DC_TSTAT_LS10)) {
2592 if (sc->dc_link == 0)
2595 r = CSR_READ_4(sc, DC_ISR);
2596 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2597 sc->dc_cdata.dc_tx_cnt == 0) {
2599 if (!(mii->mii_media_status & IFM_ACTIVE))
2608 * When the init routine completes, we expect to be able to send
2609 * packets right away, and in fact the network code will send a
2610 * gratuitous ARP the moment the init routine marks the interface
2611 * as running. However, even though the MAC may have been initialized,
2612 * there may be a delay of a few seconds before the PHY completes
2613 * autonegotiation and the link is brought up. Any transmissions
2614 * made during that delay will be lost. Dealing with this is tricky:
2615 * we can't just pause in the init routine while waiting for the
2616 * PHY to come ready since that would bring the whole system to
2617 * a screeching halt for several seconds.
2619 * What we do here is prevent the TX start routine from sending
2620 * any packets until a link has been established. After the
2621 * interface has been initialized, the tick routine will poll
2622 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2623 * that time, packets will stay in the send queue, and once the
2624 * link comes up, they will be flushed out to the wire.
2628 if (mii->mii_media_status & IFM_ACTIVE &&
2629 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2631 if (!ifq_is_empty(&ifp->if_snd))
2636 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2637 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2639 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2641 lwkt_serialize_exit(ifp->if_serializer);
2645 * A transmit underrun has occurred. Back off the transmit threshold,
2646 * or switch to store and forward mode if we have to.
2649 dc_tx_underrun(struct dc_softc *sc)
2654 if (DC_IS_DAVICOM(sc))
2657 if (DC_IS_INTEL(sc)) {
2659 * The real 21143 requires that the transmitter be idle
2660 * in order to change the transmit threshold or store
2661 * and forward state.
2663 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2665 for (i = 0; i < DC_TIMEOUT; i++) {
2666 isr = CSR_READ_4(sc, DC_ISR);
2667 if (isr & DC_ISR_TX_IDLE)
2671 if (i == DC_TIMEOUT) {
2672 if_printf(&sc->arpcom.ac_if,
2673 "failed to force tx to idle state\n");
2678 if_printf(&sc->arpcom.ac_if, "TX underrun -- ");
2679 sc->dc_txthresh += DC_TXTHRESH_INC;
2680 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2681 printf("using store and forward mode\n");
2682 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2684 printf("increasing TX threshold\n");
2685 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2686 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2689 if (DC_IS_INTEL(sc))
2690 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2695 #ifdef DEVICE_POLLING
2698 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2700 struct dc_softc *sc = ifp->if_softc;
2705 /* Disable interrupts */
2706 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2708 case POLL_DEREGISTER:
2709 /* Re-enable interrupts. */
2710 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2713 sc->rxcycles = count;
2716 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2719 case POLL_AND_CHECK_STATUS:
2720 sc->rxcycles = count;
2723 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2725 status = CSR_READ_4(sc, DC_ISR);
2726 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2727 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2731 /* ack what we have */
2732 CSR_WRITE_4(sc, DC_ISR, status);
2734 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2735 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2736 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2738 if (dc_rx_resync(sc))
2741 /* restart transmit unit if necessary */
2742 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2743 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2745 if (status & DC_ISR_TX_UNDERRUN)
2748 if (status & DC_ISR_BUS_ERR) {
2749 if_printf(ifp, "dc_poll: bus error\n");
2756 #endif /* DEVICE_POLLING */
2761 struct dc_softc *sc;
2767 if (sc->suspended) {
2771 ifp = &sc->arpcom.ac_if;
2773 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2776 /* Suppress unwanted interrupts */
2777 if (!(ifp->if_flags & IFF_UP)) {
2778 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2783 /* Disable interrupts. */
2784 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2786 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
2788 CSR_WRITE_4(sc, DC_ISR, status);
2790 if (status & DC_ISR_RX_OK) {
2792 curpkts = ifp->if_ipackets;
2794 if (curpkts == ifp->if_ipackets) {
2795 while(dc_rx_resync(sc))
2800 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2803 if (status & DC_ISR_TX_IDLE) {
2805 if (sc->dc_cdata.dc_tx_cnt) {
2806 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2807 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2811 if (status & DC_ISR_TX_UNDERRUN)
2814 if ((status & DC_ISR_RX_WATDOGTIMEO)
2815 || (status & DC_ISR_RX_NOBUF)) {
2817 curpkts = ifp->if_ipackets;
2819 if (curpkts == ifp->if_ipackets) {
2820 while(dc_rx_resync(sc))
2825 if (status & DC_ISR_BUS_ERR) {
2831 /* Re-enable interrupts. */
2832 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2834 if (!ifq_is_empty(&ifp->if_snd))
2841 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2842 * pointers to the fragment pointers.
2845 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
2847 struct dc_desc *f = NULL;
2849 int frag, cur, cnt = 0;
2852 * Start packing the mbufs in this chain into
2853 * the fragment pointers. Stop when we run out
2854 * of fragments or hit the end of the mbuf chain.
2857 cur = frag = *txidx;
2859 for (m = m_head; m != NULL; m = m->m_next) {
2860 if (m->m_len != 0) {
2861 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2862 if (*txidx != sc->dc_cdata.dc_tx_prod &&
2863 frag == (DC_TX_LIST_CNT - 1))
2866 if ((DC_TX_LIST_CNT -
2867 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
2870 f = &sc->dc_ldata->dc_tx_list[frag];
2871 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
2874 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
2876 f->dc_status = DC_TXSTAT_OWN;
2877 f->dc_data = vtophys(mtod(m, vm_offset_t));
2879 DC_INC(frag, DC_TX_LIST_CNT);
2887 sc->dc_cdata.dc_tx_cnt += cnt;
2888 sc->dc_cdata.dc_tx_chain[cur] = m_head;
2889 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
2890 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
2891 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
2892 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
2893 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
2894 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
2895 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
2896 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
2903 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2904 * to the mbuf data regions directly in the transmit lists. We also save a
2905 * copy of the pointers since the transmit list fragment pointers are
2906 * physical addresses.
2910 dc_start(struct ifnet *ifp)
2912 struct dc_softc *sc;
2913 struct mbuf *m_head;
2914 struct mbuf *m_defragged;
2915 int idx, need_trans;
2922 if (ifp->if_flags & IFF_OACTIVE)
2925 idx = sc->dc_cdata.dc_tx_prod;
2928 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
2930 m_head = ifq_poll(&ifp->if_snd);
2934 if (sc->dc_flags & DC_TX_COALESCE &&
2935 (m_head->m_next != NULL ||
2936 sc->dc_flags & DC_TX_ALIGN)){
2938 * Check first if coalescing allows us to queue
2939 * the packet. We don't want to loose it if
2940 * the TX queue is full.
2942 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
2943 idx != sc->dc_cdata.dc_tx_prod &&
2944 idx == (DC_TX_LIST_CNT - 1)) {
2945 ifp->if_flags |= IFF_OACTIVE;
2948 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
2949 ifp->if_flags |= IFF_OACTIVE;
2953 /* only coalesce if have >1 mbufs */
2954 m_defragged = m_defrag_nofree(m_head, MB_DONTWAIT);
2955 if (m_defragged == NULL) {
2956 ifp->if_flags |= IFF_OACTIVE;
2961 if (dc_encap(sc, (m_defragged ? m_defragged : m_head), &idx)) {
2964 * Throw away the original packet if the
2965 * defragged packet could not be encapsulated,
2966 * as well as the defragged packet.
2968 ifq_dequeue(&ifp->if_snd, m_head);
2970 m_freem(m_defragged);
2972 ifp->if_flags |= IFF_OACTIVE;
2976 ifq_dequeue(&ifp->if_snd, m_head);
2981 * If there's a BPF listener, bounce a copy of this frame
2984 BPF_MTAP(ifp, (m_defragged ? m_defragged : m_head));
2987 * If we defragged the packet, m_head is not the one we
2988 * encapsulated so we can throw it away.
2993 if (sc->dc_flags & DC_TX_ONE) {
2994 ifp->if_flags |= IFF_OACTIVE;
3003 sc->dc_cdata.dc_tx_prod = idx;
3004 if (!(sc->dc_flags & DC_TX_POLL))
3005 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3008 * Set a timeout in case the chip goes out to lunch.
3016 struct dc_softc *sc = xsc;
3017 struct ifnet *ifp = &sc->arpcom.ac_if;
3018 struct mii_data *mii;
3020 mii = device_get_softc(sc->dc_miibus);
3023 * Cancel pending I/O and free all RX/TX buffers.
3029 * Set cache alignment and burst length.
3031 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3032 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3034 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3036 * Evenly share the bus between receive and transmit process.
3038 if (DC_IS_INTEL(sc))
3039 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3040 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3041 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3043 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3045 if (sc->dc_flags & DC_TX_POLL)
3046 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3047 switch(sc->dc_cachesize) {
3049 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3052 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3055 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3059 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3063 if (sc->dc_flags & DC_TX_STORENFWD)
3064 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3066 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3069 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3070 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3074 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3075 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3077 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3079 * The app notes for the 98713 and 98715A say that
3080 * in order to have the chips operate properly, a magic
3081 * number must be written to CSR16. Macronix does not
3082 * document the meaning of these bits so there's no way
3083 * to know exactly what they do. The 98713 has a magic
3084 * number all its own; the rest all use a different one.
3086 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3087 if (sc->dc_type == DC_TYPE_98713)
3088 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3090 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3093 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3094 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3096 /* Init circular RX list. */
3097 if (dc_list_rx_init(sc) == ENOBUFS) {
3098 if_printf(ifp, "initialization failed: no "
3099 "memory for rx buffers\n");
3105 * Init tx descriptors.
3107 dc_list_tx_init(sc);
3110 * Load the address of the RX list.
3112 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3113 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3116 * Enable interrupts.
3118 #ifdef DEVICE_POLLING
3120 * ... but only if we are not polling, and make sure they are off in
3121 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3124 if (ifp->if_flags & IFF_POLLING)
3125 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3128 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3129 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3131 /* Enable transmitter. */
3132 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3135 * If this is an Intel 21143 and we're not using the
3136 * MII port, program the LED control pins so we get
3137 * link and activity indications.
3139 if (sc->dc_flags & DC_TULIP_LEDS) {
3140 CSR_WRITE_4(sc, DC_WATCHDOG,
3141 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3142 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3146 * Load the RX/multicast filter. We do this sort of late
3147 * because the filter programming scheme on the 21143 and
3148 * some clones requires DMAing a setup frame via the TX
3149 * engine, and we need the transmitter enabled for that.
3153 /* Enable receiver. */
3154 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3155 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3158 dc_setcfg(sc, sc->dc_if_media);
3160 ifp->if_flags |= IFF_RUNNING;
3161 ifp->if_flags &= ~IFF_OACTIVE;
3163 /* Don't start the ticker if this is a homePNA link. */
3164 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3167 if (sc->dc_flags & DC_21143_NWAY)
3168 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3170 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3177 * Set media options.
3180 dc_ifmedia_upd(struct ifnet *ifp)
3182 struct dc_softc *sc;
3183 struct mii_data *mii;
3184 struct ifmedia *ifm;
3187 mii = device_get_softc(sc->dc_miibus);
3189 ifm = &mii->mii_media;
3191 if (DC_IS_DAVICOM(sc) &&
3192 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3193 dc_setcfg(sc, ifm->ifm_media);
3201 * Report current media status.
3204 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3206 struct dc_softc *sc;
3207 struct mii_data *mii;
3208 struct ifmedia *ifm;
3211 mii = device_get_softc(sc->dc_miibus);
3213 ifm = &mii->mii_media;
3214 if (DC_IS_DAVICOM(sc)) {
3215 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3216 ifmr->ifm_active = ifm->ifm_media;
3217 ifmr->ifm_status = 0;
3221 ifmr->ifm_active = mii->mii_media_active;
3222 ifmr->ifm_status = mii->mii_media_status;
3228 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3230 struct dc_softc *sc = ifp->if_softc;
3231 struct ifreq *ifr = (struct ifreq *) data;
3232 struct mii_data *mii;
3237 if (ifp->if_flags & IFF_UP) {
3238 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3239 (IFF_PROMISC | IFF_ALLMULTI);
3240 if (ifp->if_flags & IFF_RUNNING) {
3244 sc->dc_txthresh = 0;
3248 if (ifp->if_flags & IFF_RUNNING)
3251 sc->dc_if_flags = ifp->if_flags;
3261 mii = device_get_softc(sc->dc_miibus);
3262 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3265 error = ether_ioctl(ifp, command, data);
3273 dc_watchdog(struct ifnet *ifp)
3275 struct dc_softc *sc;
3280 if_printf(ifp, "watchdog timeout\n");
3286 if (!ifq_is_empty(&ifp->if_snd))
3293 * Stop the adapter and free any mbufs allocated to the
3297 dc_stop(struct dc_softc *sc)
3302 ifp = &sc->arpcom.ac_if;
3305 callout_stop(&sc->dc_stat_timer);
3307 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3309 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3310 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3311 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3312 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3316 * Free data in the RX lists.
3318 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3319 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3320 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3321 sc->dc_cdata.dc_rx_chain[i] = NULL;
3324 bzero((char *)&sc->dc_ldata->dc_rx_list,
3325 sizeof(sc->dc_ldata->dc_rx_list));
3328 * Free the TX list buffers.
3330 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3331 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3332 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3334 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3335 DC_TXCTL_LASTFRAG)) {
3336 sc->dc_cdata.dc_tx_chain[i] = NULL;
3339 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3340 sc->dc_cdata.dc_tx_chain[i] = NULL;
3344 bzero((char *)&sc->dc_ldata->dc_tx_list,
3345 sizeof(sc->dc_ldata->dc_tx_list));
3351 * Stop all chip I/O so that the kernel's probe routines don't
3352 * get confused by errant DMAs when rebooting.
3355 dc_shutdown(device_t dev)
3357 struct dc_softc *sc;
3360 sc = device_get_softc(dev);
3361 ifp = &sc->arpcom.ac_if;
3362 lwkt_serialize_enter(ifp->if_serializer);
3366 lwkt_serialize_exit(ifp->if_serializer);
3370 * Device suspend routine. Stop the interface and save some PCI
3371 * settings in case the BIOS doesn't restore them properly on
3375 dc_suspend(device_t dev)
3377 struct dc_softc *sc = device_get_softc(dev);
3378 struct ifnet *ifp = &sc->arpcom.ac_if;
3380 lwkt_serialize_enter(ifp->if_serializer);
3383 for (i = 0; i < 5; i++)
3384 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3385 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3386 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3387 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3388 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3392 lwkt_serialize_exit(ifp->if_serializer);
3397 * Device resume routine. Restore some PCI settings in case the BIOS
3398 * doesn't, re-enable busmastering, and restart the interface if
3402 dc_resume(device_t dev)
3404 struct dc_softc *sc = device_get_softc(dev);
3405 struct ifnet *ifp = &sc->arpcom.ac_if;
3408 lwkt_serialize_enter(ifp->if_serializer);
3411 /* better way to do this? */
3412 for (i = 0; i < 5; i++)
3413 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3414 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3415 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3416 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3417 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3419 /* reenable busmastering */
3420 pci_enable_busmaster(dev);
3421 pci_enable_io(dev, DC_RES);
3423 /* reinitialize interface if necessary */
3424 if (ifp->if_flags & IFF_UP)
3428 lwkt_serialize_exit(ifp->if_serializer);