2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/i386/i386/initcpu.c,v 1.19.2.9 2003/04/05 13:47:19 dwmalone Exp $
30 * $DragonFly: src/sys/platform/pc32/i386/initcpu.c,v 1.10 2006/12/23 00:27:03 swildner Exp $
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
44 void initializecpu(void);
45 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
46 void enable_K5_wt_alloc(void);
47 void enable_K6_wt_alloc(void);
48 void enable_K6_2_wt_alloc(void);
52 static void init_5x86(void);
53 static void init_bluelightning(void);
54 static void init_486dlc(void);
55 static void init_cy486dx(void);
56 #ifdef CPU_I486_ON_386
57 static void init_i486_on_386(void);
59 static void init_6x86(void);
63 static void init_6x86MX(void);
64 static void init_ppro(void);
65 static void init_mendocino(void);
68 static int hw_instruction_sse;
69 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
70 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
72 /* Must *NOT* be BSS or locore will bzero these after setting them */
73 int cpu = 0; /* Are we 386, 386sx, 486, etc? */
74 u_int cpu_feature = 0; /* Feature flags */
75 u_int cpu_feature2 = 0; /* Feature flags */
76 u_int amd_feature = 0; /* AMD feature flags */
77 u_int amd_feature2 = 0; /* AMD feature flags */
78 u_int amd_pminfo = 0; /* AMD advanced power management info */
79 u_int via_feature_rng = 0; /* VIA RNG features */
80 u_int via_feature_xcrypt = 0; /* VIA ACE features */
81 u_int cpu_high = 0; /* Highest arg to CPUID */
82 u_int cpu_id = 0; /* Stepping ID */
83 u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
84 u_int cpu_procinfo2 = 0; /* Multicore info */
85 char cpu_vendor[20] = ""; /* CPU Origin code */
86 u_int cpu_vendor_id = 0; /* CPU vendor ID */
88 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
89 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");
90 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
91 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU");
93 #ifndef CPU_DISABLE_SSE
94 u_int cpu_fxsr; /* SSE enabled */
102 init_bluelightning(void)
106 eflags = read_eflags();
109 load_cr0(rcr0() | CR0_CD | CR0_NW);
112 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
113 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
115 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
117 /* Enables 13MB and 0-640KB cache. */
118 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
119 #ifdef CPU_BLUELIGHTNING_3X
120 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
122 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
125 /* Enable caching in CR0. */
126 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
128 write_eflags(eflags);
132 * Cyrix 486SLC/DLC/SR/DR series
140 eflags = read_eflags();
144 ccr0 = read_cyrix_reg(CCR0);
145 #ifndef CYRIX_CACHE_WORKS
146 ccr0 |= CCR0_NC1 | CCR0_BARB;
147 write_cyrix_reg(CCR0, ccr0);
151 #ifndef CYRIX_CACHE_REALLY_WORKS
152 ccr0 |= CCR0_NC1 | CCR0_BARB;
156 #ifdef CPU_DIRECT_MAPPED_CACHE
157 ccr0 |= CCR0_CO; /* Direct mapped mode. */
159 write_cyrix_reg(CCR0, ccr0);
161 /* Clear non-cacheable region. */
162 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
163 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
164 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
165 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
167 write_cyrix_reg(0, 0); /* dummy write */
169 /* Enable caching in CR0. */
170 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
172 #endif /* !CYRIX_CACHE_WORKS */
173 write_eflags(eflags);
178 * Cyrix 486S/DX series
186 eflags = read_eflags();
190 ccr2 = read_cyrix_reg(CCR2);
192 ccr2 |= CCR2_SUSP_HLT;
195 write_cyrix_reg(CCR2, ccr2);
196 write_eflags(eflags);
207 u_char ccr2, ccr3, ccr4, pcr0;
209 eflags = read_eflags();
212 load_cr0(rcr0() | CR0_CD | CR0_NW);
215 read_cyrix_reg(CCR3); /* dummy */
217 /* Initialize CCR2. */
218 ccr2 = read_cyrix_reg(CCR2);
221 ccr2 |= CCR2_SUSP_HLT;
223 ccr2 &= ~CCR2_SUSP_HLT;
226 write_cyrix_reg(CCR2, ccr2);
228 /* Initialize CCR4. */
229 ccr3 = read_cyrix_reg(CCR3);
230 write_cyrix_reg(CCR3, CCR3_MAPEN0);
232 ccr4 = read_cyrix_reg(CCR4);
235 #ifdef CPU_FASTER_5X86_FPU
236 ccr4 |= CCR4_FASTFPE;
238 ccr4 &= ~CCR4_FASTFPE;
240 ccr4 &= ~CCR4_IOMASK;
241 /********************************************************************
242 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
243 * should be 0 for errata fix.
244 ********************************************************************/
246 ccr4 |= CPU_IORT & CCR4_IOMASK;
248 write_cyrix_reg(CCR4, ccr4);
250 /* Initialize PCR0. */
251 /****************************************************************
252 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
253 * BTB_EN might make your system unstable.
254 ****************************************************************/
255 pcr0 = read_cyrix_reg(PCR0);
272 /****************************************************************
273 * WARNING: if you use a memory mapped I/O device, don't use
274 * DISABLE_5X86_LSSER option, which may reorder memory mapped
276 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
277 ****************************************************************/
278 #ifdef CPU_DISABLE_5X86_LSSER
283 write_cyrix_reg(PCR0, pcr0);
286 write_cyrix_reg(CCR3, ccr3);
288 read_cyrix_reg(0x80); /* dummy */
290 /* Unlock NW bit in CR0. */
291 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
292 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
293 /* Lock NW bit in CR0. */
294 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
296 write_eflags(eflags);
299 #ifdef CPU_I486_ON_386
301 * There are i486 based upgrade products for i386 machines.
302 * In this case, BIOS doesn't enables CPU cache.
305 init_i486_on_386(void)
309 eflags = read_eflags();
312 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
314 write_eflags(eflags);
321 * XXX - What should I do here? Please let me know.
329 eflags = read_eflags();
332 load_cr0(rcr0() | CR0_CD | CR0_NW);
335 /* Initialize CCR0. */
336 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
338 /* Initialize CCR1. */
339 #ifdef CPU_CYRIX_NO_LOCK
340 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
342 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
345 /* Initialize CCR2. */
347 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
349 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
352 ccr3 = read_cyrix_reg(CCR3);
353 write_cyrix_reg(CCR3, CCR3_MAPEN0);
355 /* Initialize CCR4. */
356 ccr4 = read_cyrix_reg(CCR4);
358 ccr4 &= ~CCR4_IOMASK;
360 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
362 write_cyrix_reg(CCR4, ccr4 | 7);
365 /* Initialize CCR5. */
367 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
371 write_cyrix_reg(CCR3, ccr3);
373 /* Unlock NW bit in CR0. */
374 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
377 * Earlier revision of the 6x86 CPU could crash the system if
378 * L1 cache is in write-back mode.
380 if ((cyrix_did & 0xff00) > 0x1600)
381 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
383 /* Revision 2.6 and lower. */
384 #ifdef CYRIX_CACHE_REALLY_WORKS
385 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
387 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
391 /* Lock NW bit in CR0. */
392 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
394 write_eflags(eflags);
396 #endif /* I486_CPU */
400 * Cyrix 6x86MX (code-named M2)
402 * XXX - What should I do here? Please let me know.
410 eflags = read_eflags();
413 load_cr0(rcr0() | CR0_CD | CR0_NW);
416 /* Initialize CCR0. */
417 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
419 /* Initialize CCR1. */
420 #ifdef CPU_CYRIX_NO_LOCK
421 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
423 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
426 /* Initialize CCR2. */
428 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
430 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
433 ccr3 = read_cyrix_reg(CCR3);
434 write_cyrix_reg(CCR3, CCR3_MAPEN0);
436 /* Initialize CCR4. */
437 ccr4 = read_cyrix_reg(CCR4);
438 ccr4 &= ~CCR4_IOMASK;
440 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
442 write_cyrix_reg(CCR4, ccr4 | 7);
445 /* Initialize CCR5. */
447 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
451 write_cyrix_reg(CCR3, ccr3);
453 /* Unlock NW bit in CR0. */
454 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
456 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
458 /* Lock NW bit in CR0. */
459 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
461 write_eflags(eflags);
471 * Local APIC should be diabled in UP kernel.
473 apicbase = rdmsr(0x1b);
474 apicbase &= ~0x800LL;
475 wrmsr(0x1b, apicbase);
480 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
486 #ifdef CPU_PPRO2CELERON
488 u_int64_t bbl_cr_ctl3;
490 eflags = read_eflags();
493 load_cr0(rcr0() | CR0_CD | CR0_NW);
496 bbl_cr_ctl3 = rdmsr(0x11e);
498 /* If the L2 cache is configured, do nothing. */
499 if (!(bbl_cr_ctl3 & 1)) {
500 bbl_cr_ctl3 = 0x134052bLL;
502 /* Set L2 Cache Latency (Default: 5). */
503 #ifdef CPU_CELERON_L2_LATENCY
504 #if CPU_L2_LATENCY > 15
505 #error invalid CPU_L2_LATENCY.
507 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
509 bbl_cr_ctl3 |= 5 << 1;
511 wrmsr(0x11e, bbl_cr_ctl3);
514 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
515 write_eflags(eflags);
516 #endif /* CPU_PPRO2CELERON */
520 * Initialize special VIA C3/C7 features
528 do_cpuid(0xc0000000, regs);
530 if (val >= 0xc0000001) {
531 do_cpuid(0xc0000001, regs);
536 /* Enable RNG if present and disabled */
537 if (val & VIA_CPUID_HAS_RNG) {
538 if (!(val & VIA_CPUID_DO_RNG)) {
539 msreg = rdmsr(0x110B);
541 wrmsr(0x110B, msreg);
543 via_feature_rng = VIA_HAS_RNG;
545 /* Enable AES engine if present and disabled */
546 if (val & VIA_CPUID_HAS_ACE) {
547 if (!(val & VIA_CPUID_DO_ACE)) {
548 msreg = rdmsr(0x1107);
549 msreg |= (0x01 << 28);
550 wrmsr(0x1107, msreg);
552 via_feature_xcrypt |= VIA_HAS_AES;
554 /* Enable ACE2 engine if present and disabled */
555 if (val & VIA_CPUID_HAS_ACE2) {
556 if (!(val & VIA_CPUID_DO_ACE2)) {
557 msreg = rdmsr(0x1107);
558 msreg |= (0x01 << 28);
559 wrmsr(0x1107, msreg);
561 via_feature_xcrypt |= VIA_HAS_AESCTR;
563 /* Enable SHA engine if present and disabled */
564 if (val & VIA_CPUID_HAS_PHE) {
565 if (!(val & VIA_CPUID_DO_PHE)) {
566 msreg = rdmsr(0x1107);
567 msreg |= (0x01 << 28/**/);
568 wrmsr(0x1107, msreg);
570 via_feature_xcrypt |= VIA_HAS_SHA;
572 /* Enable MM engine if present and disabled */
573 if (val & VIA_CPUID_HAS_PMM) {
574 if (!(val & VIA_CPUID_DO_PMM)) {
575 msreg = rdmsr(0x1107);
576 msreg |= (0x01 << 28/**/);
577 wrmsr(0x1107, msreg);
579 via_feature_xcrypt |= VIA_HAS_MM;
583 #endif /* I686_CPU */
586 * Initialize CR4 (Control register 4) to enable SSE instructions.
591 #ifndef CPU_DISABLE_SSE
592 if ((cpu_feature & CPUID_SSE) && (cpu_feature & CPUID_FXSR)) {
593 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
594 cpu_fxsr = hw_instruction_sse = 1;
604 #ifdef CPU_ATHLON_SSE_HACK
606 * Sometimes the BIOS doesn't enable SSE instructions.
607 * According to AMD document 20734, the mobile
608 * Duron, the (mobile) Athlon 4 and the Athlon MP
609 * support SSE. These correspond to cpu_id 0x66X
612 if ((cpu_feature & CPUID_XMM) == 0 &&
613 ((cpu_id & ~0xf) == 0x660 ||
614 (cpu_id & ~0xf) == 0x670 ||
615 (cpu_id & ~0xf) == 0x680)) {
617 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
619 cpu_feature = regs[3];
622 #ifdef CPU_AMD64X2_INTR_SPAM
624 * Set the LINTEN bit in the HyperTransport Transaction
627 * This will cause EXTINT and NMI interrupts routed over the
628 * hypertransport bus to be fed into the LAPIC LINT0/LINT1. If
629 * the bit isn't set, the interrupts will go to the general cpu
630 * INTR/NMI pins. On a dual-core cpu the interrupt winds up
631 * going to BOTH cpus. The first cpu that does the interrupt ack
632 * cycle will get the correct interrupt. The second cpu that does
633 * it will get a spurious interrupt vector (typically IRQ 7).
635 if ((cpu_id & 0xff0) == 0xf30) {
638 (1 << 31) | /* enable */
639 (0 << 16) | /* bus */
640 (24 << 11) | /* dev (cpu + 24) */
641 (0 << 8) | /* func */
645 if ((tcr & 0x00010000) == 0) {
646 outl(0xcfc, tcr|0x00010000);
647 additional_cpu_info("AMD: Rerouting HyperTransport "
648 "EXTINT/NMI to APIC");
654 #endif /* I686_CPU */
662 init_bluelightning();
673 #ifdef CPU_I486_ON_386
681 #endif /* I486_CPU */
687 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
688 switch (cpu_id & 0xff0) {
696 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
698 } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
699 switch (cpu_id & 0xff0) {
701 if ((cpu_id & 0xf) < 3)
721 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
723 * Enable write allocate feature of AMD processors.
724 * Following two functions require the Maxmem variable being set.
727 enable_K5_wt_alloc(void)
732 * Write allocate is supported only on models 1, 2, and 3, with
733 * a stepping of 4 or greater.
735 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
737 msr = rdmsr(0x83); /* HWCR */
738 wrmsr(0x83, msr & !(0x10));
741 * We have to tell the chip where the top of memory is,
742 * since video cards could have frame bufferes there,
743 * memory-mapped I/O could be there, etc.
749 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
752 * There is no way to know wheter 15-16M hole exists or not.
753 * Therefore, we disable write allocate for this range.
755 wrmsr(0x86, 0x0ff00f0);
756 msr |= AMD_WT_ALLOC_PRE;
760 wrmsr(0x83, msr|0x10); /* enable write allocate */
767 enable_K6_wt_alloc(void)
773 eflags = read_eflags();
777 #ifdef CPU_DISABLE_CACHE
779 * Certain K6-2 box becomes unstable when write allocation is
783 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
784 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
785 * All other bits in TR12 have no effect on the processer's operation.
786 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
789 wrmsr(0x0000000e, (u_int64_t)0x0008);
791 /* Don't assume that memory size is aligned with 4M. */
793 size = ((Maxmem >> 8) + 3) >> 2;
797 /* Limit is 508M bytes. */
800 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
802 #if defined(NO_MEMORY_HOLE)
803 if (whcr & (0x7fLL << 1))
807 * There is no way to know wheter 15-16M hole exists or not.
808 * Therefore, we disable write allocate for this range.
812 wrmsr(0x0c0000082, whcr);
814 write_eflags(eflags);
818 enable_K6_2_wt_alloc(void)
824 eflags = read_eflags();
828 #ifdef CPU_DISABLE_CACHE
830 * Certain K6-2 box becomes unstable when write allocation is
834 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
835 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
836 * All other bits in TR12 have no effect on the processer's operation.
837 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
840 wrmsr(0x0000000e, (u_int64_t)0x0008);
842 /* Don't assume that memory size is aligned with 4M. */
844 size = ((Maxmem >> 8) + 3) >> 2;
848 /* Limit is 4092M bytes. */
851 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
853 #if defined(NO_MEMORY_HOLE)
854 if (whcr & (0x3ffLL << 22))
858 * There is no way to know wheter 15-16M hole exists or not.
859 * Therefore, we disable write allocate for this range.
861 whcr &= ~(1LL << 16);
863 wrmsr(0x0c0000082, whcr);
865 write_eflags(eflags);
867 #endif /* I585_CPU && CPU_WT_ALLOC */
873 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
877 u_char ccr1, ccr2, ccr3;
878 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
881 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
882 eflags = read_eflags();
886 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
887 ccr0 = read_cyrix_reg(CCR0);
889 ccr1 = read_cyrix_reg(CCR1);
890 ccr2 = read_cyrix_reg(CCR2);
891 ccr3 = read_cyrix_reg(CCR3);
892 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
893 write_cyrix_reg(CCR3, CCR3_MAPEN0);
894 ccr4 = read_cyrix_reg(CCR4);
895 if ((cpu == CPU_M1) || (cpu == CPU_M2))
896 ccr5 = read_cyrix_reg(CCR5);
898 pcr0 = read_cyrix_reg(PCR0);
899 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
901 write_eflags(eflags);
903 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
904 kprintf("CCR0=%x, ", (u_int)ccr0);
906 kprintf("CCR1=%x, CCR2=%x, CCR3=%x",
907 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
908 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
909 kprintf(", CCR4=%x, ", (u_int)ccr4);
911 kprintf("PCR0=%x\n", pcr0);
913 kprintf("CCR5=%x\n", ccr5);
916 kprintf("CR0=%x\n", cr0);