2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.20 2005/03/07 17:16:01 joerg Exp $
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * The Rhine has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
72 #include <net/ifq_var.h>
73 #include <net/if_arp.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
80 #include <vm/vm.h> /* for vtophys */
81 #include <vm/pmap.h> /* for vtophys */
82 #include <machine/bus_pio.h>
83 #include <machine/bus_memio.h>
84 #include <machine/bus.h>
85 #include <machine/resource.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include <bus/pci/pcireg.h>
93 #include <bus/pci/pcivar.h>
97 #include <dev/netif/vr/if_vrreg.h>
99 /* "controller miibus0" required. See GENERIC if you get errors here. */
100 #include "miibus_if.h"
105 * Various supported device vendors/types and their names.
107 static struct vr_type vr_devs[] = {
108 { VIA_VENDORID, VIA_DEVICEID_RHINE,
109 "VIA VT3043 Rhine I 10/100BaseTX" },
110 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
111 "VIA VT86C100A Rhine II 10/100BaseTX" },
112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
113 "VIA VT6102 Rhine II 10/100BaseTX" },
114 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
115 "VIA VT6105 Rhine III 10/100BaseTX" },
116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
117 "VIA VT6105M Rhine III 10/100BaseTX" },
118 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
119 "Delta Electronics Rhine II 10/100BaseTX" },
120 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
121 "Addtron Technology Rhine II 10/100BaseTX" },
125 static int vr_probe(device_t);
126 static int vr_attach(device_t);
127 static int vr_detach(device_t);
129 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *,
131 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * );
133 static void vr_rxeof(struct vr_softc *);
134 static void vr_rxeoc(struct vr_softc *);
135 static void vr_txeof(struct vr_softc *);
136 static void vr_txeoc(struct vr_softc *);
137 static void vr_tick(void *);
138 static void vr_intr(void *);
139 static void vr_start(struct ifnet *);
140 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
141 static void vr_init(void *);
142 static void vr_stop(struct vr_softc *);
143 static void vr_watchdog(struct ifnet *);
144 static void vr_shutdown(device_t);
145 static int vr_ifmedia_upd(struct ifnet *);
146 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149 static void vr_mii_sync(struct vr_softc *);
150 static void vr_mii_send(struct vr_softc *, uint32_t, int);
152 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
153 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
154 static int vr_miibus_readreg(device_t, int, int);
155 static int vr_miibus_writereg(device_t, int, int, int);
156 static void vr_miibus_statchg(device_t);
158 static void vr_setcfg(struct vr_softc *, int);
159 static uint8_t vr_calchash(uint8_t *);
160 static void vr_setmulti(struct vr_softc *);
161 static void vr_reset(struct vr_softc *);
162 static int vr_list_rx_init(struct vr_softc *);
163 static int vr_list_tx_init(struct vr_softc *);
166 #define VR_RES SYS_RES_IOPORT
167 #define VR_RID VR_PCI_LOIO
169 #define VR_RES SYS_RES_MEMORY
170 #define VR_RID VR_PCI_LOMEM
173 static device_method_t vr_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, vr_probe),
176 DEVMETHOD(device_attach, vr_attach),
177 DEVMETHOD(device_detach, vr_detach),
178 DEVMETHOD(device_shutdown, vr_shutdown),
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
185 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
186 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
187 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
192 static driver_t vr_driver = {
195 sizeof(struct vr_softc)
198 static devclass_t vr_devclass;
200 DECLARE_DUMMY_MODULE(if_vr);
201 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
202 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
204 #define VR_SETBIT(sc, reg, x) \
205 CSR_WRITE_1(sc, reg, \
206 CSR_READ_1(sc, reg) | (x))
208 #define VR_CLRBIT(sc, reg, x) \
209 CSR_WRITE_1(sc, reg, \
210 CSR_READ_1(sc, reg) & ~(x))
212 #define VR_SETBIT16(sc, reg, x) \
213 CSR_WRITE_2(sc, reg, \
214 CSR_READ_2(sc, reg) | (x))
216 #define VR_CLRBIT16(sc, reg, x) \
217 CSR_WRITE_2(sc, reg, \
218 CSR_READ_2(sc, reg) & ~(x))
220 #define VR_SETBIT32(sc, reg, x) \
221 CSR_WRITE_4(sc, reg, \
222 CSR_READ_4(sc, reg) | (x))
224 #define VR_CLRBIT32(sc, reg, x) \
225 CSR_WRITE_4(sc, reg, \
226 CSR_READ_4(sc, reg) & ~(x))
229 CSR_WRITE_1(sc, VR_MIICMD, \
230 CSR_READ_1(sc, VR_MIICMD) | (x))
233 CSR_WRITE_1(sc, VR_MIICMD, \
234 CSR_READ_1(sc, VR_MIICMD) & ~(x))
238 * Sync the PHYs by setting data bit and strobing the clock 32 times.
241 vr_mii_sync(struct vr_softc *sc)
245 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
247 for (i = 0; i < 32; i++) {
248 SIO_SET(VR_MIICMD_CLK);
250 SIO_CLR(VR_MIICMD_CLK);
256 * Clock a series of bits through the MII.
259 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
263 SIO_CLR(VR_MIICMD_CLK);
265 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
267 SIO_SET(VR_MIICMD_DATAIN);
269 SIO_CLR(VR_MIICMD_DATAIN);
271 SIO_CLR(VR_MIICMD_CLK);
273 SIO_SET(VR_MIICMD_CLK);
279 * Read an PHY register through the MII.
282 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame)
289 /* Set up frame for RX. */
290 frame->mii_stdelim = VR_MII_STARTDELIM;
291 frame->mii_opcode = VR_MII_READOP;
292 frame->mii_turnaround = 0;
295 CSR_WRITE_1(sc, VR_MIICMD, 0);
296 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
298 /* Turn on data xmit. */
299 SIO_SET(VR_MIICMD_DIR);
303 /* Send command/address info. */
304 vr_mii_send(sc, frame->mii_stdelim, 2);
305 vr_mii_send(sc, frame->mii_opcode, 2);
306 vr_mii_send(sc, frame->mii_phyaddr, 5);
307 vr_mii_send(sc, frame->mii_regaddr, 5);
310 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
312 SIO_SET(VR_MIICMD_CLK);
316 SIO_CLR(VR_MIICMD_DIR);
319 SIO_CLR(VR_MIICMD_CLK);
321 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
322 SIO_SET(VR_MIICMD_CLK);
326 * Now try reading data bits. If the ack failed, we still
327 * need to clock through 16 cycles to keep the PHY(s) in sync.
330 for(i = 0; i < 16; i++) {
331 SIO_CLR(VR_MIICMD_CLK);
333 SIO_SET(VR_MIICMD_CLK);
339 for (i = 0x8000; i; i >>= 1) {
340 SIO_CLR(VR_MIICMD_CLK);
343 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
344 frame->mii_data |= i;
347 SIO_SET(VR_MIICMD_CLK);
352 SIO_CLR(VR_MIICMD_CLK);
354 SIO_SET(VR_MIICMD_CLK);
369 /* Set the PHY address. */
370 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
373 /* Set the register address. */
374 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
375 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
377 for (i = 0; i < 10000; i++) {
378 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
382 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
392 * Write to a PHY register through the MII.
395 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame)
402 CSR_WRITE_1(sc, VR_MIICMD, 0);
403 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
405 /* Set up frame for TX. */
406 frame->mii_stdelim = VR_MII_STARTDELIM;
407 frame->mii_opcode = VR_MII_WRITEOP;
408 frame->mii_turnaround = VR_MII_TURNAROUND;
410 /* Turn on data output. */
411 SIO_SET(VR_MIICMD_DIR);
415 vr_mii_send(sc, frame->mii_stdelim, 2);
416 vr_mii_send(sc, frame->mii_opcode, 2);
417 vr_mii_send(sc, frame->mii_phyaddr, 5);
418 vr_mii_send(sc, frame->mii_regaddr, 5);
419 vr_mii_send(sc, frame->mii_turnaround, 2);
420 vr_mii_send(sc, frame->mii_data, 16);
423 SIO_SET(VR_MIICMD_CLK);
425 SIO_CLR(VR_MIICMD_CLK);
429 SIO_CLR(VR_MIICMD_DIR);
441 /* Set the PHY-adress */
442 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
445 /* Set the register address and data to write. */
446 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
447 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
449 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
451 for (i = 0; i < 10000; i++) {
452 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
464 vr_miibus_readreg(device_t dev, int phy, int reg)
466 struct vr_mii_frame frame;
469 sc = device_get_softc(dev);
471 switch (sc->vr_revid) {
472 case REV_ID_VT6102_APOLLO:
480 bzero(&frame, sizeof(frame));
482 frame.mii_phyaddr = phy;
483 frame.mii_regaddr = reg;
484 vr_mii_readreg(sc, &frame);
486 return(frame.mii_data);
490 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
492 struct vr_mii_frame frame;
495 sc = device_get_softc(dev);
497 switch (sc->vr_revid) {
498 case REV_ID_VT6102_APOLLO:
506 bzero(&frame, sizeof(frame));
508 frame.mii_phyaddr = phy;
509 frame.mii_regaddr = reg;
510 frame.mii_data = data;
512 vr_mii_writereg(sc, &frame);
518 vr_miibus_statchg(device_t dev)
520 struct mii_data *mii;
523 sc = device_get_softc(dev);
524 mii = device_get_softc(sc->vr_miibus);
525 vr_setcfg(sc, mii->mii_media_active);
529 * Calculate CRC of a multicast group address, return the lower 6 bits.
532 vr_calchash(uint8_t *addr)
538 /* Compute CRC for the address value. */
539 crc = 0xFFFFFFFF; /* initial value */
541 for (i = 0; i < 6; i++) {
543 for (j = 0; j < 8; j++) {
544 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
548 crc = (crc ^ 0x04c11db6) | carry;
552 /* return the filter bit position */
553 return((crc >> 26) & 0x0000003F);
557 * Program the 64-bit multicast hash filter.
560 vr_setmulti(struct vr_softc *sc)
564 uint32_t hashes[2] = { 0, 0 };
565 struct ifmultiaddr *ifma;
569 ifp = &sc->arpcom.ac_if;
571 rxfilt = CSR_READ_1(sc, VR_RXCFG);
573 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
574 rxfilt |= VR_RXCFG_RX_MULTI;
575 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
576 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
577 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
581 /* First, zero out all the existing hash bits. */
582 CSR_WRITE_4(sc, VR_MAR0, 0);
583 CSR_WRITE_4(sc, VR_MAR1, 0);
585 /* Now program new ones. */
586 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
587 ifma = ifma->ifma_link.le_next) {
588 if (ifma->ifma_addr->sa_family != AF_LINK)
590 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
592 hashes[0] |= (1 << h);
594 hashes[1] |= (1 << (h - 32));
599 rxfilt |= VR_RXCFG_RX_MULTI;
601 rxfilt &= ~VR_RXCFG_RX_MULTI;
603 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
604 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
605 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
609 * In order to fiddle with the
610 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
611 * first have to put the transmit and/or receive logic in the idle state.
614 vr_setcfg(struct vr_softc *sc, int media)
618 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
620 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
623 if ((media & IFM_GMASK) == IFM_FDX)
624 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
626 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
629 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
633 vr_reset(struct vr_softc *sc)
637 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
639 for (i = 0; i < VR_TIMEOUT; i++) {
641 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
644 if (i == VR_TIMEOUT) {
645 struct ifnet *ifp = &sc->arpcom.ac_if;
647 if (sc->vr_revid < REV_ID_VT3065_A) {
648 if_printf(ifp, "reset never completed!\n");
650 /* Use newer force reset command */
651 if_printf(ifp, "Using force reset command.\n");
652 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
656 /* Wait a little while for the chip to get its brains in order. */
661 * Probe for a VIA Rhine chip. Check the PCI vendor and device
662 * IDs against our list and return a device name if we find a match.
665 vr_probe(device_t dev)
671 while(t->vr_name != NULL) {
672 if ((pci_get_vendor(dev) == t->vr_vid) &&
673 (pci_get_device(dev) == t->vr_did)) {
674 device_set_desc(dev, t->vr_name);
684 * Attach the interface. Allocate softc structures, do ifmedia
685 * setup and ethernet/BPF attach.
688 vr_attach(device_t dev)
691 uint8_t eaddr[ETHER_ADDR_LEN];
695 int unit, error = 0, rid;
699 sc = device_get_softc(dev);
700 unit = device_get_unit(dev);
701 callout_init(&sc->vr_stat_timer);
704 * Handle power management nonsense.
707 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF;
708 if (command == 0x01) {
709 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4);
710 if (command & VR_PSTATE_MASK) {
711 uint32_t iobase, membase, irq;
713 /* Save important PCI config data. */
714 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
715 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
716 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
718 /* Reset the power state. */
719 device_printf(dev, "chip is in D%d power mode "
720 "-- setting to D0\n", command & VR_PSTATE_MASK);
721 command &= 0xFFFFFFFC;
722 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4);
724 /* Restore PCI config data. */
725 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
726 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
727 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
732 * Map control/status registers.
734 command = pci_read_config(dev, PCIR_COMMAND, 4);
735 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
736 pci_write_config(dev, PCIR_COMMAND, command, 4);
737 command = pci_read_config(dev, PCIR_COMMAND, 4);
738 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF;
741 if (!(command & PCIM_CMD_PORTEN)) {
742 device_printf(dev, "failed to enable I/O ports!\n");
747 if (!(command & PCIM_CMD_MEMEN)) {
748 device_printf(dev, "failed to enable memory mapping!\n");
754 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE);
756 if (sc->vr_res == NULL) {
757 device_printf(dev, "couldn't map ports/memory\n");
762 sc->vr_btag = rman_get_bustag(sc->vr_res);
763 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
765 /* Allocate interrupt */
767 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
768 RF_SHAREABLE | RF_ACTIVE);
770 if (sc->vr_irq == NULL) {
771 device_printf(dev, "couldn't map interrupt\n");
772 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
777 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET,
778 vr_intr, sc, &sc->vr_intrhand);
781 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
782 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
783 device_printf(dev, "couldn't set up irq\n");
788 * Windows may put the chip in suspend mode when it
789 * shuts down. Be sure to kick it in the head to wake it
792 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
794 /* Reset the adapter. */
798 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
799 * initialization and disable AUTOPOLL.
801 pci_write_config(dev, VR_PCI_MODE,
802 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
803 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
806 * Get station address. The way the Rhine chips work,
807 * you're not allowed to directly access the EEPROM once
808 * they've been programmed a special way. Consequently,
809 * we need to read the node address from the PAR0 and PAR1
812 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
814 for (i = 0; i < ETHER_ADDR_LEN; i++)
815 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
817 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
818 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
820 if (sc->vr_ldata == NULL) {
821 device_printf(dev, "no memory for list buffers!\n");
822 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
823 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
824 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
829 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
831 ifp = &sc->arpcom.ac_if;
833 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
834 ifp->if_mtu = ETHERMTU;
835 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
836 ifp->if_ioctl = vr_ioctl;
837 ifp->if_start = vr_start;
838 ifp->if_watchdog = vr_watchdog;
839 ifp->if_init = vr_init;
840 ifp->if_baudrate = 10000000;
841 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1);
842 ifq_set_ready(&ifp->if_snd);
847 if (mii_phy_probe(dev, &sc->vr_miibus,
848 vr_ifmedia_upd, vr_ifmedia_sts)) {
849 if_printf(ifp, "MII without any phy!\n");
850 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
851 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
852 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
853 contigfree(sc->vr_ldata,
854 sizeof(struct vr_list_data), M_DEVBUF);
859 /* Call MI attach routine. */
860 ether_ifattach(ifp, eaddr);
868 vr_detach(device_t dev)
876 sc = device_get_softc(dev);
877 ifp = &sc->arpcom.ac_if;
882 bus_generic_detach(dev);
883 device_delete_child(dev, sc->vr_miibus);
885 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
886 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
887 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
889 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
897 * Initialize the transmit descriptors.
900 vr_list_tx_init(struct vr_softc *sc)
902 struct vr_chain_data *cd;
903 struct vr_list_data *ld;
908 for (i = 0; i < VR_TX_LIST_CNT; i++) {
909 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
910 if (i == (VR_TX_LIST_CNT - 1))
914 cd->vr_tx_chain[i].vr_nextdesc = &cd->vr_tx_chain[nexti];
917 cd->vr_tx_free = &cd->vr_tx_chain[0];
918 cd->vr_tx_tail = cd->vr_tx_head = NULL;
925 * Initialize the RX descriptors and allocate mbufs for them. Note that
926 * we arrange the descriptors in a closed ring, so that the last descriptor
927 * points back to the first.
930 vr_list_rx_init(struct vr_softc *sc)
932 struct vr_chain_data *cd;
933 struct vr_list_data *ld;
939 for (i = 0; i < VR_RX_LIST_CNT; i++) {
940 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i];
941 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
943 if (i == (VR_RX_LIST_CNT - 1))
947 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti];
948 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]);
951 cd->vr_rx_head = &cd->vr_rx_chain[0];
957 * Initialize an RX descriptor and attach an MBUF cluster.
958 * Note: the length fields are only 11 bits wide, which means the
959 * largest size we can specify is 2047. This is important because
960 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
961 * overflow the field and make a mess.
964 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m)
966 struct mbuf *m_new = NULL;
969 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
973 MCLGET(m_new, MB_DONTWAIT);
974 if (!(m_new->m_flags & M_EXT)) {
978 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
981 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
982 m_new->m_data = m_new->m_ext.ext_buf;
985 m_adj(m_new, sizeof(uint64_t));
988 c->vr_ptr->vr_status = VR_RXSTAT;
989 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
990 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
996 * A frame has been uploaded: pass the resulting mbuf chain up to
997 * the higher level protocols.
1000 vr_rxeof(struct vr_softc *sc)
1004 struct vr_chain_onefrag *cur_rx;
1008 ifp = &sc->arpcom.ac_if;
1010 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
1012 struct mbuf *m0 = NULL;
1014 cur_rx = sc->vr_cdata.vr_rx_head;
1015 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
1016 m = cur_rx->vr_mbuf;
1019 * If an error occurs, update stats, clear the
1020 * status word and leave the mbuf cluster in place:
1021 * it should simply get re-used next time this descriptor
1022 * comes up in the ring.
1024 if (rxstat & VR_RXSTAT_RXERR) {
1026 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff);
1027 if (rxstat & VR_RXSTAT_CRCERR)
1028 printf(" crc error");
1029 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1030 printf(" frame alignment error\n");
1031 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1032 printf(" FIFO overflow");
1033 if (rxstat & VR_RXSTAT_GIANT)
1034 printf(" received giant packet");
1035 if (rxstat & VR_RXSTAT_RUNT)
1036 printf(" received runt packet");
1037 if (rxstat & VR_RXSTAT_BUSERR)
1038 printf(" system bus error");
1039 if (rxstat & VR_RXSTAT_BUFFERR)
1040 printf("rx buffer error");
1042 vr_newbuf(sc, cur_rx, m);
1046 /* No errors; receive the packet. */
1047 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1050 * XXX The VIA Rhine chip includes the CRC with every
1051 * received frame, and there's no way to turn this
1052 * behavior off (at least, I can't find anything in
1053 * the manual that explains how to do it) so we have
1054 * to trim off the CRC manually.
1056 total_len -= ETHER_CRC_LEN;
1058 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1059 total_len + ETHER_ALIGN, 0, ifp, NULL);
1060 vr_newbuf(sc, cur_rx, m);
1065 m_adj(m0, ETHER_ALIGN);
1069 (*ifp->if_input)(ifp, m);
1074 vr_rxeoc(struct vr_softc *sc)
1079 ifp = &sc->arpcom.ac_if;
1083 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1086 /* Wait for receiver to stop */
1088 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1090 ; /* Wait for receiver to stop */
1093 if_printf(ifp, "rx shutdown error!\n");
1094 sc->vr_flags |= VR_F_RESTART;
1100 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1101 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1102 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1106 * A frame was downloaded to the chip. It's safe for us to clean up
1110 vr_txeof(struct vr_softc *sc)
1112 struct vr_chain *cur_tx;
1115 ifp = &sc->arpcom.ac_if;
1117 /* Reset the timeout timer; if_txeoc will clear it. */
1121 if (sc->vr_cdata.vr_tx_head == NULL)
1125 * Go through our tx list and free mbufs for those
1126 * frames that have been transmitted.
1128 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) {
1132 cur_tx = sc->vr_cdata.vr_tx_head;
1133 txstat = cur_tx->vr_ptr->vr_status;
1135 if ((txstat & VR_TXSTAT_ABRT) ||
1136 (txstat & VR_TXSTAT_UDF)) {
1138 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1140 ; /* Wait for chip to shutdown */
1142 if_printf(ifp, "tx shutdown timeout\n");
1143 sc->vr_flags |= VR_F_RESTART;
1146 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1147 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1151 if (txstat & VR_TXSTAT_OWN)
1154 if (txstat & VR_TXSTAT_ERRSUM) {
1156 if (txstat & VR_TXSTAT_DEFER)
1157 ifp->if_collisions++;
1158 if (txstat & VR_TXSTAT_LATECOLL)
1159 ifp->if_collisions++;
1162 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1165 if (cur_tx->vr_mbuf != NULL) {
1166 m_freem(cur_tx->vr_mbuf);
1167 cur_tx->vr_mbuf = NULL;
1170 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) {
1171 sc->vr_cdata.vr_tx_head = NULL;
1172 sc->vr_cdata.vr_tx_tail = NULL;
1176 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc;
1181 * TX 'end of channel' interrupt handler.
1184 vr_txeoc(struct vr_softc *sc)
1188 ifp = &sc->arpcom.ac_if;
1190 if (sc->vr_cdata.vr_tx_head == NULL) {
1191 ifp->if_flags &= ~IFF_OACTIVE;
1192 sc->vr_cdata.vr_tx_tail = NULL;
1200 struct vr_softc *sc;
1201 struct mii_data *mii;
1207 if (sc->vr_flags & VR_F_RESTART) {
1208 if_printf(&sc->arpcom.ac_if, "restarting\n");
1212 sc->vr_flags &= ~VR_F_RESTART;
1215 mii = device_get_softc(sc->vr_miibus);
1218 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1226 struct vr_softc *sc;
1231 ifp = &sc->arpcom.ac_if;
1233 /* Supress unwanted interrupts. */
1234 if (!(ifp->if_flags & IFF_UP)) {
1239 /* Disable interrupts. */
1240 if ((ifp->if_flags & IFF_POLLING) == 0)
1241 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1244 status = CSR_READ_2(sc, VR_ISR);
1246 CSR_WRITE_2(sc, VR_ISR, status);
1248 if ((status & VR_INTRS) == 0)
1251 if (status & VR_ISR_RX_OK)
1254 if (status & VR_ISR_RX_DROPPED) {
1255 if_printf(ifp, "rx packet lost\n");
1259 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1260 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1261 if_printf(ifp, "receive error (%04x)", status);
1262 if (status & VR_ISR_RX_NOBUF)
1263 printf(" no buffers");
1264 if (status & VR_ISR_RX_OFLOW)
1265 printf(" overflow");
1266 if (status & VR_ISR_RX_DROPPED)
1267 printf(" packet lost");
1272 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1278 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1279 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1281 if ((status & VR_ISR_UDFI) ||
1282 (status & VR_ISR_TX_ABRT2) ||
1283 (status & VR_ISR_TX_ABRT)) {
1285 if (sc->vr_cdata.vr_tx_head != NULL) {
1286 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
1287 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1296 /* Re-enable interrupts. */
1297 if ((ifp->if_flags & IFF_POLLING) == 0)
1298 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1300 if (!ifq_is_empty(&ifp->if_snd))
1305 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1306 * pointers to the fragment pointers.
1309 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head)
1312 struct vr_desc *f = NULL;
1319 * The VIA Rhine wants packet buffers to be longword
1320 * aligned, but very often our mbufs aren't. Rather than
1321 * waste time trying to decide when to copy and when not
1322 * to copy, just do it all the time.
1324 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1325 if (m_new == NULL) {
1326 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n");
1329 if (m_head->m_pkthdr.len > MHLEN) {
1330 MCLGET(m_new, MB_DONTWAIT);
1331 if (!(m_new->m_flags & M_EXT)) {
1333 if_printf(&sc->arpcom.ac_if,
1334 "no memory for tx list\n");
1338 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1339 mtod(m_new, caddr_t));
1340 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1342 * The Rhine chip doesn't auto-pad, so we have to make
1343 * sure to pad short frames out to the minimum frame length
1346 if (m_new->m_len < VR_MIN_FRAMELEN) {
1347 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1348 m_new->m_len = m_new->m_pkthdr.len;
1351 f->vr_data = vtophys(mtod(m_new, caddr_t));
1352 f->vr_ctl = total_len = m_new->m_len;
1353 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG;
1358 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT;
1359 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr);
1365 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1366 * to the mbuf data regions directly in the transmit lists. We also save a
1367 * copy of the pointers since the transmit list fragment pointers are
1368 * physical addresses.
1371 vr_start(struct ifnet *ifp)
1373 struct vr_softc *sc;
1374 struct mbuf *m_head = NULL;
1375 struct vr_chain *cur_tx = NULL, *start_tx;
1379 if (ifp->if_flags & IFF_OACTIVE)
1382 /* Check for an available queue slot. If there are none, punt. */
1383 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) {
1384 ifp->if_flags |= IFF_OACTIVE;
1388 start_tx = sc->vr_cdata.vr_tx_free;
1390 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) {
1391 m_head = ifq_poll(&ifp->if_snd);
1395 /* Pick a descriptor off the free list. */
1396 cur_tx = sc->vr_cdata.vr_tx_free;
1397 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
1399 /* Pack the data into the descriptor. */
1400 if (vr_encap(sc, cur_tx, m_head)) {
1401 ifp->if_flags |= IFF_OACTIVE;
1406 m_head = ifq_dequeue(&ifp->if_snd);
1407 if (cur_tx != start_tx)
1408 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1410 BPF_MTAP(ifp, m_head);
1413 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1414 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1417 /* If there are no frames queued, bail. */
1421 sc->vr_cdata.vr_tx_tail = cur_tx;
1423 if (sc->vr_cdata.vr_tx_head == NULL)
1424 sc->vr_cdata.vr_tx_head = start_tx;
1427 * Set a timeout in case the chip goes out to lunch.
1435 struct vr_softc *sc = xsc;
1436 struct ifnet *ifp = &sc->arpcom.ac_if;
1437 struct mii_data *mii;
1442 mii = device_get_softc(sc->vr_miibus);
1444 /* Cancel pending I/O and free all RX/TX buffers. */
1448 /* Set our station address. */
1449 for (i = 0; i < ETHER_ADDR_LEN; i++)
1450 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1453 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1454 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1457 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1458 * so we must set both.
1460 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1461 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1463 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1464 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1466 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1467 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1469 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1470 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1472 /* Init circular RX list. */
1473 if (vr_list_rx_init(sc) == ENOBUFS) {
1474 if_printf(ifp, "initialization failed: no memory for rx buffers\n");
1480 /* Init tx descriptors. */
1481 vr_list_tx_init(sc);
1483 /* If we want promiscuous mode, set the allframes bit. */
1484 if (ifp->if_flags & IFF_PROMISC)
1485 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1487 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1489 /* Set capture broadcast bit to capture broadcast frames. */
1490 if (ifp->if_flags & IFF_BROADCAST)
1491 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1493 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1496 * Program the multicast filter, if necessary.
1501 * Load the address of the RX list.
1503 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1505 /* Enable receiver and transmitter. */
1506 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1507 VR_CMD_TX_ON|VR_CMD_RX_ON|
1510 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1513 * Enable interrupts, unless we are polling.
1515 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1516 if ((ifp->if_flags & IFF_POLLING) == 0)
1517 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1521 ifp->if_flags |= IFF_RUNNING;
1522 ifp->if_flags &= ~IFF_OACTIVE;
1526 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1530 * Set media options.
1533 vr_ifmedia_upd(struct ifnet *ifp)
1535 struct vr_softc *sc;
1539 if (ifp->if_flags & IFF_UP)
1546 * Report current media status.
1549 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1551 struct vr_softc *sc;
1552 struct mii_data *mii;
1555 mii = device_get_softc(sc->vr_miibus);
1557 ifmr->ifm_active = mii->mii_media_active;
1558 ifmr->ifm_status = mii->mii_media_status;
1562 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1564 struct vr_softc *sc = ifp->if_softc;
1565 struct ifreq *ifr = (struct ifreq *) data;
1566 struct mii_data *mii;
1575 error = ether_ioctl(ifp, command, data);
1578 if (ifp->if_flags & IFF_UP) {
1581 if (ifp->if_flags & IFF_RUNNING)
1593 mii = device_get_softc(sc->vr_miibus);
1594 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1606 #ifdef DEVICE_POLLING
1608 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1610 struct vr_softc *sc = ifp->if_softc;
1612 if (cmd == POLL_DEREGISTER)
1613 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1620 vr_watchdog(struct ifnet *ifp)
1622 struct vr_softc *sc;
1627 if_printf(ifp, "watchdog timeout\n");
1629 #ifdef DEVICE_POLLING
1630 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) {
1631 if_printf(ifp, "ints don't seem to be working, "
1632 "emergency switch to polling\n");
1633 emergency_poll_enable("if_vr");
1634 if (ether_poll_register(vr_poll, ifp))
1635 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1644 if (!ifq_is_empty(&ifp->if_snd))
1649 * Stop the adapter and free any mbufs allocated to the
1653 vr_stop(struct vr_softc *sc)
1658 ifp = &sc->arpcom.ac_if;
1661 callout_stop(&sc->vr_stat_timer);
1663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1664 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1665 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1666 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1667 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1670 * Free data in the RX lists.
1672 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1673 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1674 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1675 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1678 bzero((char *)&sc->vr_ldata->vr_rx_list,
1679 sizeof(sc->vr_ldata->vr_rx_list));
1682 * Free the TX list buffers.
1684 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1685 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1686 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1687 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1691 bzero((char *)&sc->vr_ldata->vr_tx_list,
1692 sizeof(sc->vr_ldata->vr_tx_list));
1694 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1698 * Stop all chip I/O so that the kernel's probe routines don't
1699 * get confused by errant DMAs when rebooting.
1702 vr_shutdown(device_t dev)
1704 struct vr_softc *sc;
1706 sc = device_get_softc(dev);