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40 #define IX_MAX_MSIX 64
41 #define IX_MAX_MSIX_82598 16
46 #define IX_MAX_RXRING 16
47 #define IX_MAX_RXRING_X550 64
48 #define IX_MIN_RXRING_RSS 2
53 #define IX_MAX_TXRING 16
54 #define IX_MAX_TXRING_82598 32
55 #define IX_MAX_TXRING_82599 64
56 #define IX_MAX_TXRING_X540 64
57 #define IX_MAX_TXRING_X550 64
60 * Default number of segments received before writing to RX related registers
62 #define IX_DEF_RXWREG_NSEGS 32
65 * Default number of segments sent before writing to TX related registers
67 #define IX_DEF_TXWREG_NSEGS 8
70 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
71 * number of transmit descriptors allocated by the driver. Increasing this
72 * value allows the driver to queue more transmits. Each descriptor is 16
73 * bytes. Performance tests have show the 2K value to be optimal for top
76 #define IX_DEF_TXD 1024
77 #define IX_PERF_TXD 2048
78 #define IX_MAX_TXD 4096
82 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
83 * number of receive descriptors allocated for each RX queue. Increasing this
84 * value allows the driver to buffer more incoming packets. Each descriptor
85 * is 16 bytes. A receive buffer is also allocated for each descriptor.
87 * Note: with 8 rings and a dual port card, it is possible to bump up
88 * against the system mbuf pool limit, you can tune nmbclusters
91 #define IX_DEF_RXD 1024
92 #define IX_PERF_RXD 2048
93 #define IX_MAX_RXD 4096
96 /* Alignment for rings */
97 #define IX_DBA_ALIGN 128
99 #define IX_MAX_FRAME_SIZE 9728
100 #define IX_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN)
101 #define IX_MAX_MTU (IX_MAX_FRAME_SIZE - IX_MTU_HDR)
104 /* Flow control constants */
105 #define IX_FC_PAUSE 0xFFFF
106 #define IX_FC_HI 0x20000
107 #define IX_FC_LO 0x10000
110 * RSS related registers
113 #define IX_RSSRK_SIZE 4
114 #define IX_RSSRK_VAL(key, i) (key[(i) * IX_RSSRK_SIZE] | \
115 key[(i) * IX_RSSRK_SIZE + 1] << 8 | \
116 key[(i) * IX_RSSRK_SIZE + 2] << 16 | \
117 key[(i) * IX_RSSRK_SIZE + 3] << 24)
119 #define IX_NRETA_X550 128
120 #define IX_NRETA_MAX 128
121 #define IX_RETA_SIZE 4
123 #define IX_RDRTABLE_SIZE (IX_NRETA_MAX * IX_RETA_SIZE)
128 #define IX_EITR_INTVL_MASK_82598 0xffff
129 #define IX_EITR_INTVL_MASK 0x0fff
130 #define IX_EITR_INTVL_RSVD_MASK 0x0007
131 #define IX_EITR_INTVL_MIN IXGBE_MIN_EITR
132 #define IX_EITR_INTVL_MAX IXGBE_MAX_EITR
135 * Used for optimizing small rx mbufs. Effort is made to keep the copy
136 * small and aligned for the CPU L1 cache.
138 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting
139 * 32 byte alignment needed for the fast bcopy results in 8 bytes being
140 * wasted. Getting 64 byte alignment, which _should_ be ideal for
141 * modern Intel CPUs, results in 40 bytes wasted and a significant drop
142 * in observed efficiency of the optimization, 97.9% -> 81.8%.
144 #define IX_RX_COPY_LEN 160
145 #define IX_RX_COPY_ALIGN (MHLEN - IX_RX_COPY_LEN)
147 #define IX_MAX_MCASTADDR 128
149 #define IX_MSIX_BAR_82598 3
150 #define IX_MSIX_BAR_82599 4
152 #define IX_TSO_SIZE (IP_MAXPACKET + \
153 sizeof(struct ether_vlan_header))
156 * MUST be less than 38. Though 82598 does not have this limit,
157 * we don't want long TX chain. 33 should be large enough even
158 * for 64K TSO (32 x 2K mbuf cluster and 1 x mbuf header).
161 * - 82599 datasheet 7.2.1.1
162 * - X540 datasheet 7.2.1.1
164 #define IX_MAX_SCATTER 33
165 #define IX_TX_RESERVED 3 /* 1 for TX ctx, 2 reserved */
167 /* MSI and legacy interrupt */
168 #define IX_TX_INTR_VEC 0
169 #define IX_TX_INTR_MASK (1 << IX_TX_INTR_VEC)
170 #define IX_RX0_INTR_VEC 1
171 #define IX_RX0_INTR_MASK (1 << IX_RX0_INTR_VEC)
172 #define IX_RX1_INTR_VEC 2
173 #define IX_RX1_INTR_MASK (1 << IX_RX1_INTR_VEC)
175 #define IX_INTR_RATE 8000
176 #define IX_MSIX_RX_RATE 8000
177 #define IX_MSIX_TX_RATE 6000
179 /* IOCTL define to gather SFP+ Diagnostic data */
180 #define SIOCGI2C SIOCGIFGENERIC
182 /* TX checksum offload */
183 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
185 #define IX_EICR_STATUS (IXGBE_EICR_LSC | IXGBE_EICR_ECC | \
186 IXGBE_EICR_GPI_SDP1 | IXGBE_EICR_GPI_SDP2 | \
189 /* This is used to get SFP+ module data */
209 #define IX_RX_COPY 0x1
215 struct lwkt_serialize tx_serialize;
216 struct ifaltq_subque *tx_ifsq;
217 struct ix_softc *tx_sc;
218 volatile uint32_t *tx_hdr;
219 union ixgbe_adv_tx_desc *tx_base;
220 struct ix_tx_buf *tx_buf;
221 bus_dma_tag_t tx_tag;
223 #define IX_TXFLAG_ENABLED 0x1
227 uint16_t tx_next_avail;
228 uint16_t tx_next_clean;
230 uint16_t tx_wreg_nsegs;
231 uint16_t tx_intr_nsegs;
236 uint32_t tx_eims_val;
237 struct ifsubq_watchdog tx_watchdog;
239 bus_dma_tag_t tx_base_dtag;
240 bus_dmamap_t tx_base_map;
241 bus_addr_t tx_base_paddr;
243 bus_dma_tag_t tx_hdr_dtag;
244 bus_dmamap_t tx_hdr_map;
245 bus_addr_t tx_hdr_paddr;
249 struct lwkt_serialize rx_serialize;
250 struct ix_softc *rx_sc;
251 union ixgbe_adv_rx_desc *rx_base;
252 struct ix_rx_buf *rx_buf;
253 bus_dma_tag_t rx_tag;
254 bus_dmamap_t rx_sparemap;
257 #define IX_RXRING_FLAG_LRO 0x01
258 #define IX_RXRING_FLAG_DISC 0x02
259 uint16_t rx_next_check;
262 uint16_t rx_wreg_nsegs;
265 uint32_t rx_eims_val;
266 struct ix_tx_ring *rx_txr; /* piggybacked TX ring */
272 bus_dma_tag_t rx_base_dtag;
273 bus_dmamap_t rx_base_map;
274 bus_addr_t rx_base_paddr;
277 struct ix_intr_data {
278 struct lwkt_serialize *intr_serialize;
279 driver_intr_t *intr_func;
281 struct resource *intr_res;
287 #define IX_INTR_USE_RXTX 0
288 #define IX_INTR_USE_STATUS 1
289 #define IX_INTR_USE_RX 2
290 #define IX_INTR_USE_TX 3
291 const char *intr_desc;
296 struct arpcom arpcom;
299 struct ixgbe_osdep osdep;
301 struct lwkt_serialize main_serialize;
304 boolean_t link_active;
309 struct ix_rx_ring *rx_rings;
310 struct ix_tx_ring *tx_rings;
312 struct callout timer;
315 int ifm_media; /* IFM_ */
318 boolean_t sfp_probe; /* plyggable optics */
320 struct ixgbe_hw_stats stats;
330 struct ix_intr_data *intr_data;
333 bus_dma_tag_t parent_tag;
334 struct ifmedia media;
336 struct resource *mem_res;
339 struct resource *msix_mem_res;
343 struct lwkt_serialize **serializes;
345 uint8_t *mta; /* Multicast array memory */
348 int advspeed; /* advertised link speeds */
349 uint32_t wufc; /* power management */
350 uint16_t dmac; /* DMA coalescing */
351 uint16_t max_frame_size;
352 int16_t sts_msix_vec; /* status MSI-X vector */
354 struct if_ringmap *tx_rmap;
355 struct if_ringmap *tx_rmap_intr;
356 struct if_ringmap *rx_rmap;
357 struct if_ringmap *rx_rmap_intr;
359 int rdr_table[IX_RDRTABLE_SIZE];
361 struct task wdog_task;
368 #define IX_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1)
369 #define IX_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1)
371 #endif /* _IF_IX_H_ */