sys/dev/drm/radeon/r600_blit_kms.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  * Copyright 2009 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * $FreeBSD: head/sys/dev/drm2/radeon/r600_blit_kms.c 254885 2013-08-25 19:37:15Z dumbbell $
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include <uapi_drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31
  32 #include "r600d.h"
  33 #include "r600_blit_shaders.h"
  34 #include "radeon_blit_common.h"
  35
  36 /* emits 21 on rv770+, 23 on r600 */
  37 static void
  38 set_render_target(struct radeon_device *rdev, int format,
  39                   int w, int h, u64 gpu_addr)
  40 {
  41         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  42         u32 cb_color_info;
  43         int pitch, slice;
  44
  45         h = roundup2(h, 8);
  46         if (h < 8)
  47                 h = 8;
  48
  49         cb_color_info = CB_FORMAT(format) |
  50                 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
  51                 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
  52         pitch = (w / 8) - 1;
  53         slice = ((w * h) / 64) - 1;
  54
  55         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  56         radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  57         radeon_ring_write(ring, gpu_addr >> 8);
  58
  59         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
  60                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
  61                 radeon_ring_write(ring, 2 << 0);
  62         }
  63
  64         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  65         radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  66         radeon_ring_write(ring, (pitch << 0) | (slice << 10));
  67
  68         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  69         radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  70         radeon_ring_write(ring, 0);
  71
  72         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  73         radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  74         radeon_ring_write(ring, cb_color_info);
  75
  76         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  77         radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  78         radeon_ring_write(ring, 0);
  79
  80         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  81         radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  82         radeon_ring_write(ring, 0);
  83
  84         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  85         radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  86         radeon_ring_write(ring, 0);
  87 }
  88
  89 /* emits 5dw */
  90 static void
  91 cp_set_surface_sync(struct radeon_device *rdev,
  92                     u32 sync_type, u32 size,
  93                     u64 mc_addr)
  94 {
  95         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  96         u32 cp_coher_size;
  97
  98         if (size == 0xffffffff)
  99                 cp_coher_size = 0xffffffff;
 100         else
 101                 cp_coher_size = ((size + 255) >> 8);
 102
 103         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
 104         radeon_ring_write(ring, sync_type);
 105         radeon_ring_write(ring, cp_coher_size);
 106         radeon_ring_write(ring, mc_addr >> 8);
 107         radeon_ring_write(ring, 10); /* poll interval */
 108 }
 109
 110 /* emits 21dw + 1 surface sync = 26dw */
 111 static void
 112 set_shaders(struct radeon_device *rdev)
 113 {
 114         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 115         u64 gpu_addr;
 116         u32 sq_pgm_resources;
 117
 118         /* setup shader regs */
 119         sq_pgm_resources = (1 << 0);
 120
 121         /* VS */
 122         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 123         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 124         radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 125         radeon_ring_write(ring, gpu_addr >> 8);
 126
 127         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 128         radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 129         radeon_ring_write(ring, sq_pgm_resources);
 130
 131         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 132         radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 133         radeon_ring_write(ring, 0);
 134
 135         /* PS */
 136         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 137         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 138         radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 139         radeon_ring_write(ring, gpu_addr >> 8);
 140
 141         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 142         radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 143         radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
 144
 145         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 146         radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 147         radeon_ring_write(ring, 2);
 148
 149         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 150         radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 151         radeon_ring_write(ring, 0);
 152
 153         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 154         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 155 }
 156
 157 /* emits 9 + 1 sync (5) = 14*/
 158 static void
 159 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 160 {
 161         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 162         u32 sq_vtx_constant_word2;
 163
 164         sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
 165                 SQ_VTXC_STRIDE(16);
 166 #ifdef __BIG_ENDIAN
 167         sq_vtx_constant_word2 |=  SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 168 #endif
 169
 170         radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
 171         radeon_ring_write(ring, 0x460);
 172         radeon_ring_write(ring, gpu_addr & 0xffffffff);
 173         radeon_ring_write(ring, 48 - 1);
 174         radeon_ring_write(ring, sq_vtx_constant_word2);
 175         radeon_ring_write(ring, 1 << 0);
 176         radeon_ring_write(ring, 0);
 177         radeon_ring_write(ring, 0);
 178         radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
 179
 180         if ((rdev->family == CHIP_RV610) ||
 181             (rdev->family == CHIP_RV620) ||
 182             (rdev->family == CHIP_RS780) ||
 183             (rdev->family == CHIP_RS880) ||
 184             (rdev->family == CHIP_RV710))
 185                 cp_set_surface_sync(rdev,
 186                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 187         else
 188                 cp_set_surface_sync(rdev,
 189                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 190 }
 191
 192 /* emits 9 */
 193 static void
 194 set_tex_resource(struct radeon_device *rdev,
 195                  int format, int w, int h, int pitch,
 196                  u64 gpu_addr, u32 size)
 197 {
 198         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 199         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 200
 201         if (h < 1)
 202                 h = 1;
 203
 204         sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
 205                 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
 206         sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
 207                 S_038000_TEX_WIDTH(w - 1);
 208
 209         sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
 210         sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
 211
 212         sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
 213                 S_038010_DST_SEL_X(SQ_SEL_X) |
 214                 S_038010_DST_SEL_Y(SQ_SEL_Y) |
 215                 S_038010_DST_SEL_Z(SQ_SEL_Z) |
 216                 S_038010_DST_SEL_W(SQ_SEL_W);
 217
 218         cp_set_surface_sync(rdev,
 219                             PACKET3_TC_ACTION_ENA, size, gpu_addr);
 220
 221         radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
 222         radeon_ring_write(ring, 0);
 223         radeon_ring_write(ring, sq_tex_resource_word0);
 224         radeon_ring_write(ring, sq_tex_resource_word1);
 225         radeon_ring_write(ring, gpu_addr >> 8);
 226         radeon_ring_write(ring, gpu_addr >> 8);
 227         radeon_ring_write(ring, sq_tex_resource_word4);
 228         radeon_ring_write(ring, 0);
 229         radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
 230 }
 231
 232 /* emits 12 */
 233 static void
 234 set_scissors(struct radeon_device *rdev, int x1, int y1,
 235              int x2, int y2)
 236 {
 237         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 238         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 239         radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 240         radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
 241         radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
 242
 243         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 244         radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 245         radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
 246         radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
 247
 248         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 249         radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 250         radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
 251         radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
 252 }
 253
 254 /* emits 10 */
 255 static void
 256 draw_auto(struct radeon_device *rdev)
 257 {
 258         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 259         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 260         radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 261         radeon_ring_write(ring, DI_PT_RECTLIST);
 262
 263         radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
 264         radeon_ring_write(ring,
 265 #ifdef __BIG_ENDIAN
 266                           (2 << 2) |
 267 #endif
 268                           DI_INDEX_SIZE_16_BIT);
 269
 270         radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
 271         radeon_ring_write(ring, 1);
 272
 273         radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 274         radeon_ring_write(ring, 3);
 275         radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
 276
 277 }
 278
 279 /* emits 14 */
 280 static void
 281 set_default_state(struct radeon_device *rdev)
 282 {
 283         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 284         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 285         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 286         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
 287         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 288         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 289         u64 gpu_addr;
 290         int dwords;
 291
 292         switch (rdev->family) {
 293         case CHIP_R600:
 294                 num_ps_gprs = 192;
 295                 num_vs_gprs = 56;
 296                 num_temp_gprs = 4;
 297                 num_gs_gprs = 0;
 298                 num_es_gprs = 0;
 299                 num_ps_threads = 136;
 300                 num_vs_threads = 48;
 301                 num_gs_threads = 4;
 302                 num_es_threads = 4;
 303                 num_ps_stack_entries = 128;
 304                 num_vs_stack_entries = 128;
 305                 num_gs_stack_entries = 0;
 306                 num_es_stack_entries = 0;
 307                 break;
 308         case CHIP_RV630:
 309         case CHIP_RV635:
 310                 num_ps_gprs = 84;
 311                 num_vs_gprs = 36;
 312                 num_temp_gprs = 4;
 313                 num_gs_gprs = 0;
 314                 num_es_gprs = 0;
 315                 num_ps_threads = 144;
 316                 num_vs_threads = 40;
 317                 num_gs_threads = 4;
 318                 num_es_threads = 4;
 319                 num_ps_stack_entries = 40;
 320                 num_vs_stack_entries = 40;
 321                 num_gs_stack_entries = 32;
 322                 num_es_stack_entries = 16;
 323                 break;
 324         case CHIP_RV610:
 325         case CHIP_RV620:
 326         case CHIP_RS780:
 327         case CHIP_RS880:
 328         default:
 329                 num_ps_gprs = 84;
 330                 num_vs_gprs = 36;
 331                 num_temp_gprs = 4;
 332                 num_gs_gprs = 0;
 333                 num_es_gprs = 0;
 334                 num_ps_threads = 136;
 335                 num_vs_threads = 48;
 336                 num_gs_threads = 4;
 337                 num_es_threads = 4;
 338                 num_ps_stack_entries = 40;
 339                 num_vs_stack_entries = 40;
 340                 num_gs_stack_entries = 32;
 341                 num_es_stack_entries = 16;
 342                 break;
 343         case CHIP_RV670:
 344                 num_ps_gprs = 144;
 345                 num_vs_gprs = 40;
 346                 num_temp_gprs = 4;
 347                 num_gs_gprs = 0;
 348                 num_es_gprs = 0;
 349                 num_ps_threads = 136;
 350                 num_vs_threads = 48;
 351                 num_gs_threads = 4;
 352                 num_es_threads = 4;
 353                 num_ps_stack_entries = 40;
 354                 num_vs_stack_entries = 40;
 355                 num_gs_stack_entries = 32;
 356                 num_es_stack_entries = 16;
 357                 break;
 358         case CHIP_RV770:
 359                 num_ps_gprs = 192;
 360                 num_vs_gprs = 56;
 361                 num_temp_gprs = 4;
 362                 num_gs_gprs = 0;
 363                 num_es_gprs = 0;
 364                 num_ps_threads = 188;
 365                 num_vs_threads = 60;
 366                 num_gs_threads = 0;
 367                 num_es_threads = 0;
 368                 num_ps_stack_entries = 256;
 369                 num_vs_stack_entries = 256;
 370                 num_gs_stack_entries = 0;
 371                 num_es_stack_entries = 0;
 372                 break;
 373         case CHIP_RV730:
 374         case CHIP_RV740:
 375                 num_ps_gprs = 84;
 376                 num_vs_gprs = 36;
 377                 num_temp_gprs = 4;
 378                 num_gs_gprs = 0;
 379                 num_es_gprs = 0;
 380                 num_ps_threads = 188;
 381                 num_vs_threads = 60;
 382                 num_gs_threads = 0;
 383                 num_es_threads = 0;
 384                 num_ps_stack_entries = 128;
 385                 num_vs_stack_entries = 128;
 386                 num_gs_stack_entries = 0;
 387                 num_es_stack_entries = 0;
 388                 break;
 389         case CHIP_RV710:
 390                 num_ps_gprs = 192;
 391                 num_vs_gprs = 56;
 392                 num_temp_gprs = 4;
 393                 num_gs_gprs = 0;
 394                 num_es_gprs = 0;
 395                 num_ps_threads = 144;
 396                 num_vs_threads = 48;
 397                 num_gs_threads = 0;
 398                 num_es_threads = 0;
 399                 num_ps_stack_entries = 128;
 400                 num_vs_stack_entries = 128;
 401                 num_gs_stack_entries = 0;
 402                 num_es_stack_entries = 0;
 403                 break;
 404         }
 405
 406         if ((rdev->family == CHIP_RV610) ||
 407             (rdev->family == CHIP_RV620) ||
 408             (rdev->family == CHIP_RS780) ||
 409             (rdev->family == CHIP_RS880) ||
 410             (rdev->family == CHIP_RV710))
 411                 sq_config = 0;
 412         else
 413                 sq_config = VC_ENABLE;
 414
 415         sq_config |= (DX9_CONSTS |
 416                       ALU_INST_PREFER_VECTOR |
 417                       PS_PRIO(0) |
 418                       VS_PRIO(1) |
 419                       GS_PRIO(2) |
 420                       ES_PRIO(3));
 421
 422         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 423                                   NUM_VS_GPRS(num_vs_gprs) |
 424                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 425         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 426                                   NUM_ES_GPRS(num_es_gprs));
 427         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 428                                    NUM_VS_THREADS(num_vs_threads) |
 429                                    NUM_GS_THREADS(num_gs_threads) |
 430                                    NUM_ES_THREADS(num_es_threads));
 431         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 432                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 433         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 434                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 435
 436         /* emit an IB pointing at default state */
 437         dwords = roundup2(rdev->r600_blit.state_len, 0x10);
 438         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 439         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 440         radeon_ring_write(ring,
 441 #ifdef __BIG_ENDIAN
 442                           (2 << 0) |
 443 #endif
 444                           (gpu_addr & 0xFFFFFFFC));
 445         radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
 446         radeon_ring_write(ring, dwords);
 447
 448         /* SQ config */
 449         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
 450         radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 451         radeon_ring_write(ring, sq_config);
 452         radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
 453         radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
 454         radeon_ring_write(ring, sq_thread_resource_mgmt);
 455         radeon_ring_write(ring, sq_stack_resource_mgmt_1);
 456         radeon_ring_write(ring, sq_stack_resource_mgmt_2);
 457 }
 458
 459 int r600_blit_init(struct radeon_device *rdev)
 460 {
 461         u32 obj_size;
 462         int i, r, dwords;
 463         void *ptr;
 464         u32 packet2s[16];
 465         int num_packet2s = 0;
 466
 467         rdev->r600_blit.primitives.set_render_target = set_render_target;
 468         rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
 469         rdev->r600_blit.primitives.set_shaders = set_shaders;
 470         rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
 471         rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
 472         rdev->r600_blit.primitives.set_scissors = set_scissors;
 473         rdev->r600_blit.primitives.draw_auto = draw_auto;
 474         rdev->r600_blit.primitives.set_default_state = set_default_state;
 475
 476         rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
 477         rdev->r600_blit.ring_size_common += 40; /* shaders + def state */
 478         rdev->r600_blit.ring_size_common += 5; /* done copy */
 479         rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
 480
 481         rdev->r600_blit.ring_size_per_loop = 76;
 482         /* set_render_target emits 2 extra dwords on rv6xx */
 483         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
 484                 rdev->r600_blit.ring_size_per_loop += 2;
 485
 486         rdev->r600_blit.max_dim = 8192;
 487
 488         rdev->r600_blit.state_offset = 0;
 489
 490         if (rdev->family >= CHIP_RV770)
 491                 rdev->r600_blit.state_len = r7xx_default_size;
 492         else
 493                 rdev->r600_blit.state_len = r6xx_default_size;
 494
 495         dwords = rdev->r600_blit.state_len;
 496         while (dwords & 0xf) {
 497                 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
 498                 dwords++;
 499         }
 500
 501         obj_size = dwords * 4;
 502         obj_size = roundup2(obj_size, 256);
 503
 504         rdev->r600_blit.vs_offset = obj_size;
 505         obj_size += r6xx_vs_size * 4;
 506         obj_size = roundup2(obj_size, 256);
 507
 508         rdev->r600_blit.ps_offset = obj_size;
 509         obj_size += r6xx_ps_size * 4;
 510         obj_size = roundup2(obj_size, 256);
 511
 512         /* pin copy shader into vram if not already initialized */
 513         if (rdev->r600_blit.shader_obj == NULL) {
 514                 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
 515                                      RADEON_GEM_DOMAIN_VRAM,
 516                                      NULL, &rdev->r600_blit.shader_obj);
 517                 if (r) {
 518                         DRM_ERROR("r600 failed to allocate shader\n");
 519                         return r;
 520                 }
 521
 522                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 523                 if (unlikely(r != 0))
 524                         return r;
 525                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 526                                   &rdev->r600_blit.shader_gpu_addr);
 527                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 528                 if (r) {
 529                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 530                         return r;
 531                 }
 532         }
 533
 534         DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
 535                   obj_size,
 536                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 537
 538         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 539         if (unlikely(r != 0))
 540                 return r;
 541         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 542         if (r) {
 543                 DRM_ERROR("failed to map blit object %d\n", r);
 544                 return r;
 545         }
 546         if (rdev->family >= CHIP_RV770)
 547                 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset,
 548                             r7xx_default_state, rdev->r600_blit.state_len * 4);
 549         else
 550                 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset,
 551                             r6xx_default_state, rdev->r600_blit.state_len * 4);
 552         if (num_packet2s)
 553                 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 554                             packet2s, num_packet2s * 4);
 555         for (i = 0; i < r6xx_vs_size; i++)
 556                 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
 557         for (i = 0; i < r6xx_ps_size; i++)
 558                 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
 559         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 560         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 561
 562         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 563         return 0;
 564 }
 565
 566 void r600_blit_fini(struct radeon_device *rdev)
 567 {
 568         int r;
 569
 570         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 571         if (rdev->r600_blit.shader_obj == NULL)
 572                 return;
 573         /* If we can't reserve the bo, unref should be enough to destroy
 574          * it when it becomes idle.
 575          */
 576         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 577         if (!r) {
 578                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
 579                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 580         }
 581         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 582 }
 583
 584 static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
 585                                       int *width, int *height, int max_dim)
 586 {
 587         unsigned max_pages;
 588         unsigned pages = num_gpu_pages;
 589         int w, h;
 590
 591         if (num_gpu_pages == 0) {
 592                 /* not supposed to be called with no pages, but just in case */
 593                 h = 0;
 594                 w = 0;
 595                 pages = 0;
 596                 DRM_ERROR("%s: called with no pages", __func__);
 597         } else {
 598                 int rect_order = 2;
 599                 h = RECT_UNIT_H;
 600                 while (num_gpu_pages / rect_order) {
 601                         h *= 2;
 602                         rect_order *= 4;
 603                         if (h >= max_dim) {
 604                                 h = max_dim;
 605                                 break;
 606                         }
 607                 }
 608                 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
 609                 if (pages > max_pages)
 610                         pages = max_pages;
 611                 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
 612                 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
 613                 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
 614                 KASSERT(pages != 0, ("r600_blit_create_rect: pages == 0"));
 615         }
 616
 617
 618         DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
 619
 620         /* return width and height only of the caller wants it */
 621         if (height)
 622                 *height = h;
 623         if (width)
 624                 *width = w;
 625
 626         return pages;
 627 }
 628
 629
 630 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
 631                            struct radeon_fence **fence, struct radeon_sa_bo **vb,
 632                            struct radeon_semaphore **sem)
 633 {
 634         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 635         int r;
 636         int ring_size;
 637         int num_loops = 0;
 638         int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
 639
 640         /* num loops */
 641         while (num_gpu_pages) {
 642                 num_gpu_pages -=
 643                         r600_blit_create_rect(num_gpu_pages, NULL, NULL,
 644                                               rdev->r600_blit.max_dim);
 645                 num_loops++;
 646         }
 647
 648         /* 48 bytes for vertex per loop */
 649         r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb,
 650                              (num_loops*48)+256, 256, true);
 651         if (r) {
 652                 return r;
 653         }
 654
 655         r = radeon_semaphore_create(rdev, sem);
 656         if (r) {
 657                 radeon_sa_bo_free(rdev, vb, NULL);
 658                 return r;
 659         }
 660
 661         /* calculate number of loops correctly */
 662         ring_size = num_loops * dwords_per_loop;
 663         ring_size += rdev->r600_blit.ring_size_common;
 664         r = radeon_ring_lock(rdev, ring, ring_size);
 665         if (r) {
 666                 radeon_sa_bo_free(rdev, vb, NULL);
 667                 radeon_semaphore_free(rdev, sem, NULL);
 668                 return r;
 669         }
 670
 671         if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) {
 672                 radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
 673                                             RADEON_RING_TYPE_GFX_INDEX);
 674                 radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX);
 675         } else {
 676                 radeon_semaphore_free(rdev, sem, NULL);
 677         }
 678
 679         rdev->r600_blit.primitives.set_default_state(rdev);
 680         rdev->r600_blit.primitives.set_shaders(rdev);
 681         return 0;
 682 }
 683
 684 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
 685                          struct radeon_sa_bo *vb, struct radeon_semaphore *sem)
 686 {
 687         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 688         int r;
 689
 690         r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
 691         if (r) {
 692                 radeon_ring_unlock_undo(rdev, ring);
 693                 return;
 694         }
 695
 696         radeon_ring_unlock_commit(rdev, ring);
 697         radeon_sa_bo_free(rdev, &vb, *fence);
 698         radeon_semaphore_free(rdev, &sem, *fence);
 699 }
 700
 701 void r600_kms_blit_copy(struct radeon_device *rdev,
 702                         u64 src_gpu_addr, u64 dst_gpu_addr,
 703                         unsigned num_gpu_pages,
 704                         struct radeon_sa_bo *vb)
 705 {
 706         u64 vb_gpu_addr;
 707         u32 *vb_cpu_addr;
 708
 709         DRM_DEBUG("emitting copy %16jx %16jx %d\n",
 710                   (uintmax_t)src_gpu_addr, (uintmax_t)dst_gpu_addr, num_gpu_pages);
 711         vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb);
 712         vb_gpu_addr = radeon_sa_bo_gpu_addr(vb);
 713
 714         while (num_gpu_pages) {
 715                 int w, h;
 716                 unsigned size_in_bytes;
 717                 unsigned pages_per_loop =
 718                         r600_blit_create_rect(num_gpu_pages, &w, &h,
 719                                               rdev->r600_blit.max_dim);
 720
 721                 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
 722                 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
 723
 724                 vb_cpu_addr[0] = 0;
 725                 vb_cpu_addr[1] = 0;
 726                 vb_cpu_addr[2] = 0;
 727                 vb_cpu_addr[3] = 0;
 728
 729                 vb_cpu_addr[4] = 0;
 730                 vb_cpu_addr[5] = int2float(h);
 731                 vb_cpu_addr[6] = 0;
 732                 vb_cpu_addr[7] = int2float(h);
 733
 734                 vb_cpu_addr[8] = int2float(w);
 735                 vb_cpu_addr[9] = int2float(h);
 736                 vb_cpu_addr[10] = int2float(w);
 737                 vb_cpu_addr[11] = int2float(h);
 738
 739                 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
 740                                                             w, h, w, src_gpu_addr, size_in_bytes);
 741                 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
 742                                                              w, h, dst_gpu_addr);
 743                 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
 744                 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
 745                 rdev->r600_blit.primitives.draw_auto(rdev);
 746                 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
 747                                     PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 748                                     size_in_bytes, dst_gpu_addr);
 749
 750                 vb_cpu_addr += 12;
 751                 vb_gpu_addr += 4*12;
 752                 src_gpu_addr += size_in_bytes;
 753                 dst_gpu_addr += size_in_bytes;
 754                 num_gpu_pages -= pages_per_loop;
 755         }
 756 }