2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
51 #include "opt_msgbuf.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysproto.h>
57 #include <sys/signalvar.h>
58 #include <sys/kernel.h>
59 #include <sys/linker.h>
60 #include <sys/malloc.h>
64 #include <sys/reboot.h>
66 #include <sys/msgbuf.h>
67 #include <sys/sysent.h>
68 #include <sys/sysctl.h>
69 #include <sys/vmmeter.h>
71 #include <sys/usched.h>
74 #include <sys/ctype.h>
75 #include <sys/serialize.h>
76 #include <sys/systimer.h>
79 #include <vm/vm_param.h>
81 #include <vm/vm_kern.h>
82 #include <vm/vm_object.h>
83 #include <vm/vm_page.h>
84 #include <vm/vm_map.h>
85 #include <vm/vm_pager.h>
86 #include <vm/vm_extern.h>
88 #include <sys/thread2.h>
89 #include <sys/mplock2.h>
90 #include <sys/mutex2.h>
98 #include <machine/cpu.h>
99 #include <machine/clock.h>
100 #include <machine/specialreg.h>
102 #include <machine/bootinfo.h>
104 #include <machine/md_var.h>
105 #include <machine/metadata.h>
106 #include <machine/pc/bios.h>
107 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
108 #include <machine/globaldata.h> /* CPU_prvspace */
109 #include <machine/smp.h>
111 #include <machine/perfmon.h>
113 #include <machine/cputypes.h>
114 #include <machine/intr_machdep.h>
117 #include <bus/isa/isa_device.h>
119 #include <machine_base/isa/isa_intr.h>
120 #include <bus/isa/rtc.h>
121 #include <sys/random.h>
122 #include <sys/ptrace.h>
123 #include <machine/sigframe.h>
125 #include <sys/machintr.h>
126 #include <machine_base/icu/icu_abi.h>
127 #include <machine_base/icu/elcr_var.h>
128 #include <machine_base/apic/lapic.h>
129 #include <machine_base/apic/ioapic.h>
130 #include <machine_base/apic/ioapic_abi.h>
131 #include <machine/mptable.h>
133 #define PHYSMAP_ENTRIES 10
135 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
137 extern void printcpuinfo(void); /* XXX header file */
138 extern void identify_cpu(void);
140 extern void finishidentcpu(void);
142 extern void panicifcpuunsupported(void);
144 static void cpu_startup(void *);
145 static void pic_finish(void *);
146 static void cpu_finish(void *);
148 #ifndef CPU_DISABLE_SSE
149 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
150 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
151 #endif /* CPU_DISABLE_SSE */
153 extern void ffs_rawread_setup(void);
154 #endif /* DIRECTIO */
155 static void init_locks(void);
157 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
158 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
159 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
162 extern vm_offset_t ksym_start, ksym_end;
165 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
167 int _udatasel, _ucodesel, _ucode32sel;
169 int64_t tsc_offsets[MAXCPU];
171 static int cpu_mwait_halt; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
173 #if defined(SWTCH_OPTIM_STATS)
174 extern int swtch_optim_stats;
175 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
176 CTLFLAG_RD, &swtch_optim_stats, 0, "");
177 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
178 CTLFLAG_RD, &tlb_flush_count, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
181 CTLFLAG_RD, &cpu_mwait_halt, 0, "");
182 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
183 "monitor/mwait target state");
185 #define CPU_MWAIT_C1 1
186 #define CPU_MWAIT_C2 2
187 #define CPU_MWAIT_C3 3
188 #define CPU_MWAIT_CX_MAX 8
190 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
191 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
193 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features");
194 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
196 struct cpu_mwait_cx {
199 struct sysctl_ctx_list sysctl_ctx;
200 struct sysctl_oid *sysctl_tree;
202 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
203 static char cpu_mwait_cx_supported[256];
205 static int cpu_mwait_c1_hints_cnt;
206 static int cpu_mwait_hints_cnt;
207 static int *cpu_mwait_hints;
209 static int cpu_mwait_deep_hints_cnt;
210 static int *cpu_mwait_deep_hints;
212 #define CPU_IDLE_REPEAT_DEFAULT 750
214 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
215 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
216 static u_int cpu_mwait_repeat_shift = 1;
218 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
219 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
221 static int cpu_mwait_c3_preamble =
222 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
223 CPU_MWAIT_C3_PREAMBLE_BM_STS;
225 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
226 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
228 static struct lwkt_serialize cpu_mwait_cx_slize = LWKT_SERIALIZE_INITIALIZER;
229 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
231 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
232 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
234 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
235 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
236 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
237 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
238 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
239 &cpu_mwait_repeat_shift, 0, "");
243 u_long ebda_addr = 0;
245 int imcr_present = 0;
247 int naps = 0; /* # of Applications processors */
250 struct mtx dt_lock; /* lock for GDT and LDT */
253 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
255 u_long pmem = ctob(physmem);
257 int error = sysctl_handle_long(oidp, &pmem, 0, req);
261 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
262 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
265 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
267 int error = sysctl_handle_int(oidp, 0,
268 ctob(physmem - vmstats.v_wire_count), req);
272 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
273 0, 0, sysctl_hw_usermem, "IU", "");
276 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
278 int error = sysctl_handle_int(oidp, 0,
279 x86_64_btop(avail_end - avail_start), req);
283 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
284 0, 0, sysctl_hw_availpages, "I", "");
290 * The number of PHYSMAP entries must be one less than the number of
291 * PHYSSEG entries because the PHYSMAP entry that spans the largest
292 * physical address that is accessible by ISA DMA is split into two
295 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
297 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
298 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
300 /* must be 2 less so 0 0 can signal end of chunks */
301 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
302 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
304 static vm_offset_t buffer_sva, buffer_eva;
305 vm_offset_t clean_sva, clean_eva;
306 static vm_offset_t pager_sva, pager_eva;
307 static struct trapframe proc0_tf;
310 cpu_startup(void *dummy)
314 vm_offset_t firstaddr;
317 * Good {morning,afternoon,evening,night}.
319 kprintf("%s", version);
322 panicifcpuunsupported();
326 kprintf("real memory = %ju (%ju MB)\n",
328 (intmax_t)Realmem / 1024 / 1024);
330 * Display any holes after the first chunk of extended memory.
335 kprintf("Physical memory chunk(s):\n");
336 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
337 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
339 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
340 (intmax_t)phys_avail[indx],
341 (intmax_t)phys_avail[indx + 1] - 1,
343 (intmax_t)(size1 / PAGE_SIZE));
348 * Allocate space for system data structures.
349 * The first available kernel virtual address is in "v".
350 * As pages of kernel virtual memory are allocated, "v" is incremented.
351 * As pages of memory are allocated and cleared,
352 * "firstaddr" is incremented.
353 * An index into the kernel page table corresponding to the
354 * virtual memory address maintained in "v" is kept in "mapaddr".
358 * Make two passes. The first pass calculates how much memory is
359 * needed and allocates it. The second pass assigns virtual
360 * addresses to the various data structures.
364 v = (caddr_t)firstaddr;
366 #define valloc(name, type, num) \
367 (name) = (type *)v; v = (caddr_t)((name)+(num))
368 #define valloclim(name, type, num, lim) \
369 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
372 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
373 * For the first 64MB of ram nominally allocate sufficient buffers to
374 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
375 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
376 * the buffer cache we limit the eventual kva reservation to
379 * factor represents the 1/4 x ram conversion.
382 long factor = 4 * BKVASIZE / 1024;
383 long kbytes = physmem * (PAGE_SIZE / 1024);
387 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
389 nbuf += (kbytes - 65536) * 2 / (factor * 5);
390 if (maxbcache && nbuf > maxbcache / BKVASIZE)
391 nbuf = maxbcache / BKVASIZE;
395 * Do not allow the buffer_map to be more then 1/2 the size of the
398 if (nbuf > (virtual_end - virtual_start +
399 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
400 nbuf = (virtual_end - virtual_start +
401 virtual2_end - virtual2_start) / (BKVASIZE * 2);
402 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
406 * Do not allow the buffer_map to use more than 50% of available
407 * physical-equivalent memory. Since the VM pages which back
408 * individual buffers are typically wired, having too many bufs
409 * can prevent the system from paging properly.
411 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
412 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
413 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
417 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
418 * the valloc space which is just the virtual_end - virtual_start
419 * section. We use valloc() to allocate the buf header array.
421 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
422 nbuf = (virtual_end - virtual_start) /
423 sizeof(struct buf) / 2;
424 kprintf("Warning: nbufs capped at %ld due to valloc "
425 "considerations", nbuf);
428 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
430 if (nswbuf < NSWBUF_MIN)
437 valloc(swbuf, struct buf, nswbuf);
438 valloc(buf, struct buf, nbuf);
441 * End of first pass, size has been calculated so allocate memory
443 if (firstaddr == 0) {
444 size = (vm_size_t)(v - firstaddr);
445 firstaddr = kmem_alloc(&kernel_map, round_page(size));
447 panic("startup: no room for tables");
452 * End of second pass, addresses have been assigned
454 * nbuf is an int, make sure we don't overflow the field.
456 * On 64-bit systems we always reserve maximal allocations for
457 * buffer cache buffers and there are no fragmentation issues,
458 * so the KVA segment does not have to be excessively oversized.
460 if ((vm_size_t)(v - firstaddr) != size)
461 panic("startup: table size inconsistency");
463 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
464 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
465 (nswbuf * MAXPHYS) + pager_map_size);
466 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
467 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
468 buffer_map.system_map = 1;
469 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
470 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
471 pager_map.system_map = 1;
473 #if defined(USERCONFIG)
475 cninit(); /* the preferred console may have changed */
478 kprintf("avail memory = %ju (%ju MB)\n",
479 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
480 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
484 struct cpu_idle_stat {
490 u_long mwait_cx[CPU_MWAIT_CX_MAX];
493 #define CPU_IDLE_STAT_HALT -1
494 #define CPU_IDLE_STAT_SPIN -2
496 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
499 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
501 int idx = arg2, cpu, error;
504 if (idx == CPU_IDLE_STAT_HALT) {
505 for (cpu = 0; cpu < ncpus; ++cpu)
506 val += cpu_idle_stats[cpu].halt;
507 } else if (idx == CPU_IDLE_STAT_SPIN) {
508 for (cpu = 0; cpu < ncpus; ++cpu)
509 val += cpu_idle_stats[cpu].spin;
511 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
512 ("invalid index %d", idx));
513 for (cpu = 0; cpu < ncpus; ++cpu)
514 val += cpu_idle_stats[cpu].mwait_cx[idx];
517 error = sysctl_handle_quad(oidp, &val, 0, req);
518 if (error || req->newptr == NULL)
521 if (idx == CPU_IDLE_STAT_HALT) {
522 for (cpu = 0; cpu < ncpus; ++cpu)
523 cpu_idle_stats[cpu].halt = 0;
524 cpu_idle_stats[0].halt = val;
525 } else if (idx == CPU_IDLE_STAT_SPIN) {
526 for (cpu = 0; cpu < ncpus; ++cpu)
527 cpu_idle_stats[cpu].spin = 0;
528 cpu_idle_stats[0].spin = val;
530 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
531 ("invalid index %d", idx));
532 for (cpu = 0; cpu < ncpus; ++cpu)
533 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
534 cpu_idle_stats[0].mwait_cx[idx] = val;
540 cpu_mwait_attach(void)
545 if ((cpu_feature2 & CPUID2_MON) == 0 ||
546 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
549 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
550 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
551 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
552 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
555 atomic_clear_int(&cpu_mwait_c3_preamble,
556 CPU_MWAIT_C3_PREAMBLE_BM_ARB);
558 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts);
560 atomic_clear_int(&cpu_mwait_c3_preamble,
561 CPU_MWAIT_C3_PREAMBLE_BM_STS);
565 sbuf_new(&sb, cpu_mwait_cx_supported,
566 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
568 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
569 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
572 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
574 sysctl_ctx_init(&cx->sysctl_ctx);
575 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
576 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
577 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
578 if (cx->sysctl_tree == NULL)
581 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
582 SYSCTL_ADD_INT(&cx->sysctl_ctx,
583 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
584 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
586 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
587 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
588 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
589 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
591 for (sub = 0; sub < cx->subcnt; ++sub)
592 sbuf_printf(&sb, "C%d/%d ", i, sub);
600 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
601 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
602 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
603 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
607 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
610 subcnt = cpu_mwait_cx_info[i].subcnt;
611 for (j = 0; j < subcnt; ++j) {
612 KASSERT(hint_idx < cpu_mwait_hints_cnt,
613 ("invalid mwait hint index %d", hint_idx));
614 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
618 KASSERT(hint_idx == cpu_mwait_hints_cnt,
619 ("mwait hint count %d != index %d",
620 cpu_mwait_hints_cnt, hint_idx));
623 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
624 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
625 int hint = cpu_mwait_hints[i];
627 kprintf(" C%d/%d hint 0x%04x\n",
628 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
636 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
637 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
638 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
642 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
645 subcnt = cpu_mwait_cx_info[i].subcnt;
646 for (j = 0; j < subcnt; ++j) {
647 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
648 ("invalid mwait deep hint index %d", hint_idx));
649 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
653 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
654 ("mwait deep hint count %d != index %d",
655 cpu_mwait_deep_hints_cnt, hint_idx));
658 kprintf("MWAIT deep hints:\n");
659 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
660 int hint = cpu_mwait_deep_hints[i];
662 kprintf(" C%d/%d hint 0x%04x\n",
663 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
667 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
671 cpu_finish(void *dummy __unused)
678 pic_finish(void *dummy __unused)
680 /* Log ELCR information */
683 /* Log MPTABLE information */
684 mptable_pci_int_dump();
687 MachIntrABI.finalize();
691 * Send an interrupt to process.
693 * Stack is set up to allow sigcode stored
694 * at top to call routine, followed by kcall
695 * to sigreturn routine below. After sigreturn
696 * resets the signal mask, the stack, and the
697 * frame pointer, it returns to the user
701 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
703 struct lwp *lp = curthread->td_lwp;
704 struct proc *p = lp->lwp_proc;
705 struct trapframe *regs;
706 struct sigacts *psp = p->p_sigacts;
707 struct sigframe sf, *sfp;
711 regs = lp->lwp_md.md_regs;
712 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
714 /* Save user context */
715 bzero(&sf, sizeof(struct sigframe));
716 sf.sf_uc.uc_sigmask = *mask;
717 sf.sf_uc.uc_stack = lp->lwp_sigstk;
718 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
719 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
720 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
722 /* Make the size of the saved context visible to userland */
723 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
725 /* Allocate and validate space for the signal handler context. */
726 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
727 SIGISMEMBER(psp->ps_sigonstack, sig)) {
728 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
729 sizeof(struct sigframe));
730 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
732 /* We take red zone into account */
733 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
737 * XXX AVX needs 64-byte alignment but sigframe has other fields and
738 * the embedded ucontext is not at the front, so aligning this won't
739 * help us. Fortunately we bcopy in/out of the sigframe, so the
742 * The problem though is if userland winds up trying to use the
745 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
747 /* Translate the signal is appropriate */
748 if (p->p_sysent->sv_sigtbl) {
749 if (sig <= p->p_sysent->sv_sigsize)
750 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
754 * Build the argument list for the signal handler.
756 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
758 regs->tf_rdi = sig; /* argument 1 */
759 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
761 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
763 * Signal handler installed with SA_SIGINFO.
765 * action(signo, siginfo, ucontext)
767 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
768 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
769 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
771 /* fill siginfo structure */
772 sf.sf_si.si_signo = sig;
773 sf.sf_si.si_code = code;
774 sf.sf_si.si_addr = (void *)regs->tf_addr;
777 * Old FreeBSD-style arguments.
779 * handler (signo, code, [uc], addr)
781 regs->tf_rsi = (register_t)code; /* argument 2 */
782 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
783 sf.sf_ahu.sf_handler = catcher;
787 * If we're a vm86 process, we want to save the segment registers.
788 * We also change eflags to be our emulated eflags, not the actual
792 if (regs->tf_eflags & PSL_VM) {
793 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
794 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
796 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
797 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
798 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
799 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
801 if (vm86->vm86_has_vme == 0)
802 sf.sf_uc.uc_mcontext.mc_eflags =
803 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
804 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
807 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
808 * syscalls made by the signal handler. This just avoids
809 * wasting time for our lazy fixup of such faults. PSL_NT
810 * does nothing in vm86 mode, but vm86 programs can set it
811 * almost legitimately in probes for old cpu types.
813 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
818 * Save the FPU state and reinit the FP unit
820 npxpush(&sf.sf_uc.uc_mcontext);
823 * Copy the sigframe out to the user's stack.
825 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
827 * Something is wrong with the stack pointer.
828 * ...Kill the process.
833 regs->tf_rsp = (register_t)sfp;
834 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
837 * i386 abi specifies that the direction flag must be cleared
840 regs->tf_rflags &= ~(PSL_T|PSL_D);
843 * 64 bit mode has a code and stack selector but
844 * no data or extra selector. %fs and %gs are not
847 regs->tf_cs = _ucodesel;
848 regs->tf_ss = _udatasel;
853 * Sanitize the trapframe for a virtual kernel passing control to a custom
854 * VM context. Remove any items that would otherwise create a privilage
857 * XXX at the moment we allow userland to set the resume flag. Is this a
861 cpu_sanitize_frame(struct trapframe *frame)
863 frame->tf_cs = _ucodesel;
864 frame->tf_ss = _udatasel;
865 /* XXX VM (8086) mode not supported? */
866 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
867 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
873 * Sanitize the tls so loading the descriptor does not blow up
874 * on us. For x86_64 we don't have to do anything.
877 cpu_sanitize_tls(struct savetls *tls)
883 * sigreturn(ucontext_t *sigcntxp)
885 * System call to cleanup state after a signal
886 * has been taken. Reset signal mask and
887 * stack state from context left by sendsig (above).
888 * Return to previous pc and psl as specified by
889 * context left by sendsig. Check carefully to
890 * make sure that the user has not modified the
891 * state to gain improper privileges.
895 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
896 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
899 sys_sigreturn(struct sigreturn_args *uap)
901 struct lwp *lp = curthread->td_lwp;
902 struct trapframe *regs;
910 * We have to copy the information into kernel space so userland
911 * can't modify it while we are sniffing it.
913 regs = lp->lwp_md.md_regs;
914 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
918 rflags = ucp->uc_mcontext.mc_rflags;
920 /* VM (8086) mode not supported */
921 rflags &= ~PSL_VM_UNSUPP;
924 if (eflags & PSL_VM) {
925 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
926 struct vm86_kernel *vm86;
929 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
930 * set up the vm86 area, and we can't enter vm86 mode.
932 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
934 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
935 if (vm86->vm86_inited == 0)
938 /* go back to user mode if both flags are set */
939 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
940 trapsignal(lp, SIGBUS, 0);
942 if (vm86->vm86_has_vme) {
943 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
944 (eflags & VME_USERCHANGE) | PSL_VM;
946 vm86->vm86_eflags = eflags; /* save VIF, VIP */
947 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
948 (eflags & VM_USERCHANGE) | PSL_VM;
950 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
951 tf->tf_eflags = eflags;
952 tf->tf_vm86_ds = tf->tf_ds;
953 tf->tf_vm86_es = tf->tf_es;
954 tf->tf_vm86_fs = tf->tf_fs;
955 tf->tf_vm86_gs = tf->tf_gs;
956 tf->tf_ds = _udatasel;
957 tf->tf_es = _udatasel;
958 tf->tf_fs = _udatasel;
959 tf->tf_gs = _udatasel;
964 * Don't allow users to change privileged or reserved flags.
967 * XXX do allow users to change the privileged flag PSL_RF.
968 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
969 * should sometimes set it there too. tf_eflags is kept in
970 * the signal context during signal handling and there is no
971 * other place to remember it, so the PSL_RF bit may be
972 * corrupted by the signal handler without us knowing.
973 * Corruption of the PSL_RF bit at worst causes one more or
974 * one less debugger trap, so allowing it is fairly harmless.
976 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
977 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
982 * Don't allow users to load a valid privileged %cs. Let the
983 * hardware check for invalid selectors, excess privilege in
984 * other selectors, invalid %eip's and invalid %esp's.
986 cs = ucp->uc_mcontext.mc_cs;
987 if (!CS_SECURE(cs)) {
988 kprintf("sigreturn: cs = 0x%x\n", cs);
989 trapsignal(lp, SIGBUS, T_PROTFLT);
992 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
996 * Restore the FPU state from the frame
999 npxpop(&ucp->uc_mcontext);
1001 if (ucp->uc_mcontext.mc_onstack & 1)
1002 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
1004 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
1006 lp->lwp_sigmask = ucp->uc_sigmask;
1007 SIG_CANTMASK(lp->lwp_sigmask);
1010 return(EJUSTRETURN);
1014 * Machine dependent boot() routine
1016 * I haven't seen anything to put here yet
1017 * Possibly some stuff might be grafted back here from boot()
1025 * Shutdown the CPU as much as possible
1031 __asm__ __volatile("hlt");
1035 * cpu_idle() represents the idle LWKT. You cannot return from this function
1036 * (unless you want to blow things up!). Instead we look for runnable threads
1037 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1039 * The main loop is entered with a critical section held, we must release
1040 * the critical section before doing anything else. lwkt_switch() will
1041 * check for pending interrupts due to entering and exiting its own
1044 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1045 * However, there are cases where the idlethread will be entered with
1046 * the possibility that no IPI will occur and in such cases
1047 * lwkt_switch() sets TDF_IDLE_NOHLT.
1049 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1050 * must occur before it starts using ACPI halt.
1052 static int cpu_idle_hlt = 2;
1053 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1054 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1055 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1056 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1058 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1059 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1060 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1061 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1064 cpu_idle_default_hook(void)
1067 * We must guarentee that hlt is exactly the instruction
1068 * following the sti.
1070 __asm __volatile("sti; hlt");
1073 /* Other subsystems (e.g., ACPI) can hook this later. */
1074 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1077 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1082 if (cpu_mwait_halt >= 0) {
1083 hint = cpu_mwait_halt;
1087 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1088 cpu_mwait_repeat_shift;
1089 if (idx >= cpu_mwait_c1_hints_cnt) {
1090 /* Step up faster, once we walked through all C1 states */
1091 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1093 if (cpu_mwait_halt == CPU_MWAIT_HINT_AUTODEEP) {
1094 if (idx >= cpu_mwait_deep_hints_cnt)
1095 idx = cpu_mwait_deep_hints_cnt - 1;
1096 hint = cpu_mwait_deep_hints[idx];
1098 if (idx >= cpu_mwait_hints_cnt)
1099 idx = cpu_mwait_hints_cnt - 1;
1100 hint = cpu_mwait_hints[idx];
1103 cx_idx = MWAIT_EAX_TO_CX(hint);
1104 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1105 stat->mwait_cx[cx_idx]++;
1112 globaldata_t gd = mycpu;
1113 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1114 struct thread *td __debugvar = gd->gd_curthread;
1118 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1121 KKASSERT(td->td_critcount == 0);
1124 * See if there are any LWKTs ready to go.
1129 * When halting inside a cli we must check for reqflags
1130 * races, particularly [re]schedule requests. Running
1131 * splz() does the job.
1134 * 0 Never halt, just spin
1136 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1137 * This typically eats more power than the
1140 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1141 * use the ACPI halt (default). This is a hybrid
1142 * approach. See machdep.cpu_idle_repeat.
1144 * 3 Always use the ACPI halt. This typically
1145 * eats the least amount of power but the cpu
1146 * will be slow waking up. Slows down e.g.
1147 * compiles and other pipe/event oriented stuff.
1149 * NOTE: Interrupts are enabled and we are not in a critical
1152 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1153 * don't bother capping gd_idle_repeat, it is ok if
1156 if (gd->gd_idle_repeat == 0) {
1157 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1158 if (stat->repeat > cpu_idle_repeat_max)
1159 stat->repeat = cpu_idle_repeat_max;
1160 stat->repeat_last = 0;
1161 stat->repeat_delta = 0;
1163 ++stat->repeat_last;
1165 ++gd->gd_idle_repeat;
1166 reqflags = gd->gd_reqflags;
1167 quick = (cpu_idle_hlt == 1) ||
1168 (cpu_idle_hlt < 3 &&
1169 gd->gd_idle_repeat < cpu_idle_repeat);
1171 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1172 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1174 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1175 cpu_mwait_cx_hint(stat), 0);
1177 } else if (cpu_idle_hlt) {
1178 __asm __volatile("cli");
1180 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1182 cpu_idle_default_hook();
1186 __asm __volatile("sti");
1190 __asm __volatile("sti");
1197 * This routine is called if a spinlock has been held through the
1198 * exponential backoff period and is seriously contested. On a real cpu
1202 cpu_spinlock_contested(void)
1208 * Clear registers on exec
1211 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1213 struct thread *td = curthread;
1214 struct lwp *lp = td->td_lwp;
1215 struct pcb *pcb = td->td_pcb;
1216 struct trapframe *regs = lp->lwp_md.md_regs;
1218 /* was i386_user_cleanup() in NetBSD */
1222 bzero((char *)regs, sizeof(struct trapframe));
1223 regs->tf_rip = entry;
1224 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1225 regs->tf_rdi = stack; /* argv */
1226 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1227 regs->tf_ss = _udatasel;
1228 regs->tf_cs = _ucodesel;
1229 regs->tf_rbx = ps_strings;
1232 * Reset the hardware debug registers if they were in use.
1233 * They won't have any meaning for the newly exec'd process.
1235 if (pcb->pcb_flags & PCB_DBREGS) {
1241 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1242 if (pcb == td->td_pcb) {
1244 * Clear the debug registers on the running
1245 * CPU, otherwise they will end up affecting
1246 * the next process we switch to.
1250 pcb->pcb_flags &= ~PCB_DBREGS;
1254 * Initialize the math emulator (if any) for the current process.
1255 * Actually, just clear the bit that says that the emulator has
1256 * been initialized. Initialization is delayed until the process
1257 * traps to the emulator (if it is done at all) mainly because
1258 * emulators don't provide an entry point for initialization.
1260 pcb->pcb_flags &= ~FP_SOFTFP;
1263 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1264 * gd_npxthread. Otherwise a preemptive interrupt thread
1265 * may panic in npxdna().
1268 load_cr0(rcr0() | CR0_MP);
1271 * NOTE: The MSR values must be correct so we can return to
1272 * userland. gd_user_fs/gs must be correct so the switch
1273 * code knows what the current MSR values are.
1275 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1276 pcb->pcb_gsbase = 0;
1277 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1278 mdcpu->gd_user_gs = 0;
1279 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1280 wrmsr(MSR_KGSBASE, 0);
1282 /* Initialize the npx (if any) for the current process. */
1283 npxinit(__INITIAL_FPUCW__);
1286 pcb->pcb_ds = _udatasel;
1287 pcb->pcb_es = _udatasel;
1288 pcb->pcb_fs = _udatasel;
1289 pcb->pcb_gs = _udatasel;
1298 cr0 |= CR0_NE; /* Done by npxinit() */
1299 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1300 cr0 |= CR0_WP | CR0_AM;
1306 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1309 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1311 if (!error && req->newptr)
1316 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1317 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1319 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1320 CTLFLAG_RW, &disable_rtc_set, 0, "");
1323 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1324 CTLFLAG_RD, &bootinfo, bootinfo, "");
1327 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1328 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1330 extern u_long bootdev; /* not a cdev_t - encoding is different */
1331 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1332 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1335 * Initialize 386 and configure to run kernel
1339 * Initialize segments & interrupt table
1343 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1344 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1346 union descriptor ldt[NLDT]; /* local descriptor table */
1349 /* table descriptors - used to load tables by cpu */
1350 struct region_descriptor r_gdt;
1351 struct region_descriptor r_idt_arr[MAXCPU];
1353 /* JG proc0paddr is a virtual address */
1356 char proc0paddr_buff[LWKT_THREAD_STACK];
1359 /* software prototypes -- in more palatable form */
1360 struct soft_segment_descriptor gdt_segs[] = {
1361 /* GNULL_SEL 0 Null Descriptor */
1362 { 0x0, /* segment base address */
1364 0, /* segment type */
1365 0, /* segment descriptor priority level */
1366 0, /* segment descriptor present */
1368 0, /* default 32 vs 16 bit size */
1369 0 /* limit granularity (byte/page units)*/ },
1370 /* GCODE_SEL 1 Code Descriptor for kernel */
1371 { 0x0, /* segment base address */
1372 0xfffff, /* length - all address space */
1373 SDT_MEMERA, /* segment type */
1374 SEL_KPL, /* segment descriptor priority level */
1375 1, /* segment descriptor present */
1377 0, /* default 32 vs 16 bit size */
1378 1 /* limit granularity (byte/page units)*/ },
1379 /* GDATA_SEL 2 Data Descriptor for kernel */
1380 { 0x0, /* segment base address */
1381 0xfffff, /* length - all address space */
1382 SDT_MEMRWA, /* segment type */
1383 SEL_KPL, /* segment descriptor priority level */
1384 1, /* segment descriptor present */
1386 0, /* default 32 vs 16 bit size */
1387 1 /* limit granularity (byte/page units)*/ },
1388 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1389 { 0x0, /* segment base address */
1390 0xfffff, /* length - all address space */
1391 SDT_MEMERA, /* segment type */
1392 SEL_UPL, /* segment descriptor priority level */
1393 1, /* segment descriptor present */
1395 1, /* default 32 vs 16 bit size */
1396 1 /* limit granularity (byte/page units)*/ },
1397 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1398 { 0x0, /* segment base address */
1399 0xfffff, /* length - all address space */
1400 SDT_MEMRWA, /* segment type */
1401 SEL_UPL, /* segment descriptor priority level */
1402 1, /* segment descriptor present */
1404 1, /* default 32 vs 16 bit size */
1405 1 /* limit granularity (byte/page units)*/ },
1406 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1407 { 0x0, /* segment base address */
1408 0xfffff, /* length - all address space */
1409 SDT_MEMERA, /* segment type */
1410 SEL_UPL, /* segment descriptor priority level */
1411 1, /* segment descriptor present */
1413 0, /* default 32 vs 16 bit size */
1414 1 /* limit granularity (byte/page units)*/ },
1415 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1417 0x0, /* segment base address */
1418 sizeof(struct x86_64tss)-1,/* length - all address space */
1419 SDT_SYSTSS, /* segment type */
1420 SEL_KPL, /* segment descriptor priority level */
1421 1, /* segment descriptor present */
1423 0, /* unused - default 32 vs 16 bit size */
1424 0 /* limit granularity (byte/page units)*/ },
1425 /* Actually, the TSS is a system descriptor which is double size */
1426 { 0x0, /* segment base address */
1428 0, /* segment type */
1429 0, /* segment descriptor priority level */
1430 0, /* segment descriptor present */
1432 0, /* default 32 vs 16 bit size */
1433 0 /* limit granularity (byte/page units)*/ },
1434 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1435 { 0x0, /* segment base address */
1436 0xfffff, /* length - all address space */
1437 SDT_MEMRWA, /* segment type */
1438 SEL_UPL, /* segment descriptor priority level */
1439 1, /* segment descriptor present */
1441 1, /* default 32 vs 16 bit size */
1442 1 /* limit granularity (byte/page units)*/ },
1446 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1450 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1451 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1453 ip->gd_looffset = (uintptr_t)func;
1454 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1460 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1465 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1467 struct gate_descriptor *ip;
1469 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1471 ip = &idt_arr[cpu][idx];
1472 ip->gd_looffset = (uintptr_t)func;
1473 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1479 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1482 #define IDTVEC(name) __CONCAT(X,name)
1485 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1486 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1487 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1488 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1489 IDTVEC(xmm), IDTVEC(dblfault),
1490 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1492 #ifdef DEBUG_INTERRUPTS
1493 extern inthand_t *Xrsvdary[256];
1497 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1499 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1500 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1501 ssd->ssd_type = sd->sd_type;
1502 ssd->ssd_dpl = sd->sd_dpl;
1503 ssd->ssd_p = sd->sd_p;
1504 ssd->ssd_def32 = sd->sd_def32;
1505 ssd->ssd_gran = sd->sd_gran;
1509 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1512 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1513 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1514 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1515 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1516 sd->sd_type = ssd->ssd_type;
1517 sd->sd_dpl = ssd->ssd_dpl;
1518 sd->sd_p = ssd->ssd_p;
1519 sd->sd_long = ssd->ssd_long;
1520 sd->sd_def32 = ssd->ssd_def32;
1521 sd->sd_gran = ssd->ssd_gran;
1525 ssdtosyssd(struct soft_segment_descriptor *ssd,
1526 struct system_segment_descriptor *sd)
1529 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1530 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1531 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1532 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1533 sd->sd_type = ssd->ssd_type;
1534 sd->sd_dpl = ssd->ssd_dpl;
1535 sd->sd_p = ssd->ssd_p;
1536 sd->sd_gran = ssd->ssd_gran;
1540 * Populate the (physmap) array with base/bound pairs describing the
1541 * available physical memory in the system, then test this memory and
1542 * build the phys_avail array describing the actually-available memory.
1544 * If we cannot accurately determine the physical memory map, then use
1545 * value from the 0xE801 call, and failing that, the RTC.
1547 * Total memory size may be set by the kernel environment variable
1548 * hw.physmem or the compile-time define MAXMEM.
1550 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1551 * of PAGE_SIZE. This also greatly reduces the memory test time
1552 * which would otherwise be excessive on machines with > 8G of ram.
1554 * XXX first should be vm_paddr_t.
1557 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1558 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1559 vm_paddr_t physmap[PHYSMAP_SIZE];
1560 struct bios_smap *smapbase, *smap, *smapend;
1564 getmemsize(caddr_t kmdp, u_int64_t first)
1566 int off, physmap_idx, pa_indx, da_indx;
1569 vm_paddr_t msgbuf_size;
1570 u_long physmem_tunable;
1572 quad_t dcons_addr, dcons_size;
1574 bzero(physmap, sizeof(physmap));
1578 * get memory map from INT 15:E820, kindly supplied by the loader.
1580 * subr_module.c says:
1581 * "Consumer may safely assume that size value precedes data."
1582 * ie: an int32_t immediately precedes smap.
1584 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1585 MODINFO_METADATA | MODINFOMD_SMAP);
1586 if (smapbase == NULL)
1587 panic("No BIOS smap info from loader!");
1589 smapsize = *((u_int32_t *)smapbase - 1);
1590 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1592 for (smap = smapbase; smap < smapend; smap++) {
1593 if (boothowto & RB_VERBOSE)
1594 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1595 smap->type, smap->base, smap->length);
1597 if (smap->type != SMAP_TYPE_MEMORY)
1600 if (smap->length == 0)
1603 for (i = 0; i <= physmap_idx; i += 2) {
1604 if (smap->base < physmap[i + 1]) {
1605 if (boothowto & RB_VERBOSE) {
1606 kprintf("Overlapping or non-monotonic "
1607 "memory region, ignoring "
1613 if (i <= physmap_idx)
1616 Realmem += smap->length;
1618 if (smap->base == physmap[physmap_idx + 1]) {
1619 physmap[physmap_idx + 1] += smap->length;
1624 if (physmap_idx == PHYSMAP_SIZE) {
1625 kprintf("Too many segments in the physical "
1626 "address map, giving up\n");
1629 physmap[physmap_idx] = smap->base;
1630 physmap[physmap_idx + 1] = smap->base + smap->length;
1633 base_memory = physmap[1] / 1024;
1634 /* make hole for AP bootstrap code */
1635 physmap[1] = mp_bootaddress(base_memory);
1637 /* Save EBDA address, if any */
1638 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1642 * Maxmem isn't the "maximum memory", it's one larger than the
1643 * highest page of the physical address space. It should be
1644 * called something like "Maxphyspage". We may adjust this
1645 * based on ``hw.physmem'' and the results of the memory test.
1647 Maxmem = atop(physmap[physmap_idx + 1]);
1650 Maxmem = MAXMEM / 4;
1653 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1654 Maxmem = atop(physmem_tunable);
1657 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1660 if (Maxmem > atop(physmap[physmap_idx + 1]))
1661 Maxmem = atop(physmap[physmap_idx + 1]);
1664 * Blowing out the DMAP will blow up the system.
1666 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1667 kprintf("Limiting Maxmem due to DMAP size\n");
1668 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1671 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1672 (boothowto & RB_VERBOSE)) {
1673 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1677 * Call pmap initialization to make new kernel address space
1681 pmap_bootstrap(&first);
1682 physmap[0] = PAGE_SIZE;
1685 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1688 for (i = j = 0; i <= physmap_idx; i += 2) {
1689 if (physmap[i+1] > ptoa(Maxmem))
1690 physmap[i+1] = ptoa(Maxmem);
1691 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1692 ~PHYSMAP_ALIGN_MASK;
1693 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1695 physmap[j] = physmap[i];
1696 physmap[j+1] = physmap[i+1];
1698 if (physmap[i] < physmap[i+1])
1701 physmap_idx = j - 2;
1704 * Align anything else used in the validation loop.
1706 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1709 * Size up each available chunk of physical memory.
1713 phys_avail[pa_indx++] = physmap[0];
1714 phys_avail[pa_indx] = physmap[0];
1715 dump_avail[da_indx] = physmap[0];
1719 * Get dcons buffer address
1721 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1722 kgetenv_quad("dcons.size", &dcons_size) == 0)
1726 * Validate the physical memory. The physical memory segments
1727 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1730 for (i = 0; i <= physmap_idx; i += 2) {
1733 end = physmap[i + 1];
1735 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1736 int tmp, page_bad, full;
1737 int *ptr = (int *)CADDR1;
1741 * block out kernel memory as not available.
1743 if (pa >= 0x200000 && pa < first)
1747 * block out dcons buffer
1750 && pa >= trunc_page(dcons_addr)
1751 && pa < dcons_addr + dcons_size) {
1758 * map page into kernel: valid, read/write,non-cacheable
1761 kernel_pmap.pmap_bits[PG_V_IDX] |
1762 kernel_pmap.pmap_bits[PG_RW_IDX] |
1763 kernel_pmap.pmap_bits[PG_N_IDX];
1768 * Test for alternating 1's and 0's
1770 *(volatile int *)ptr = 0xaaaaaaaa;
1772 if (*(volatile int *)ptr != 0xaaaaaaaa)
1775 * Test for alternating 0's and 1's
1777 *(volatile int *)ptr = 0x55555555;
1779 if (*(volatile int *)ptr != 0x55555555)
1784 *(volatile int *)ptr = 0xffffffff;
1786 if (*(volatile int *)ptr != 0xffffffff)
1791 *(volatile int *)ptr = 0x0;
1793 if (*(volatile int *)ptr != 0x0)
1796 * Restore original value.
1801 * Adjust array of valid/good pages.
1803 if (page_bad == TRUE)
1806 * If this good page is a continuation of the
1807 * previous set of good pages, then just increase
1808 * the end pointer. Otherwise start a new chunk.
1809 * Note that "end" points one higher than end,
1810 * making the range >= start and < end.
1811 * If we're also doing a speculative memory
1812 * test and we at or past the end, bump up Maxmem
1813 * so that we keep going. The first bad page
1814 * will terminate the loop.
1816 if (phys_avail[pa_indx] == pa) {
1817 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1820 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1822 "Too many holes in the physical address space, giving up\n");
1827 phys_avail[pa_indx++] = pa;
1828 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1830 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1832 if (dump_avail[da_indx] == pa) {
1833 dump_avail[da_indx] += PHYSMAP_ALIGN;
1836 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1840 dump_avail[da_indx++] = pa;
1841 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1852 * The last chunk must contain at least one page plus the message
1853 * buffer to avoid complicating other code (message buffer address
1854 * calculation, etc.).
1856 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1858 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1859 msgbuf_size >= phys_avail[pa_indx]) {
1860 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1861 phys_avail[pa_indx--] = 0;
1862 phys_avail[pa_indx--] = 0;
1865 Maxmem = atop(phys_avail[pa_indx]);
1867 /* Trim off space for the message buffer. */
1868 phys_avail[pa_indx] -= msgbuf_size;
1870 avail_end = phys_avail[pa_indx];
1872 /* Map the message buffer. */
1873 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1874 pmap_kenter((vm_offset_t)msgbufp + off,
1875 phys_avail[pa_indx] + off);
1879 struct machintr_abi MachIntrABI;
1890 * 7 Device Not Available (x87)
1892 * 9 Coprocessor Segment overrun (unsupported, reserved)
1894 * 11 Segment not present
1896 * 13 General Protection
1899 * 16 x87 FP Exception pending
1900 * 17 Alignment Check
1902 * 19 SIMD floating point
1904 * 32-255 INTn/external sources
1907 hammer_time(u_int64_t modulep, u_int64_t physfree)
1910 int gsel_tss, x, cpu;
1912 int metadata_missing, off;
1914 struct mdglobaldata *gd;
1918 * Prevent lowering of the ipl if we call tsleep() early.
1920 gd = &CPU_prvspace[0].mdglobaldata;
1921 bzero(gd, sizeof(*gd));
1924 * Note: on both UP and SMP curthread must be set non-NULL
1925 * early in the boot sequence because the system assumes
1926 * that 'curthread' is never NULL.
1929 gd->mi.gd_curthread = &thread0;
1930 thread0.td_gd = &gd->mi;
1932 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1935 metadata_missing = 0;
1936 if (bootinfo.bi_modulep) {
1937 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1938 preload_bootstrap_relocate(KERNBASE);
1940 metadata_missing = 1;
1942 if (bootinfo.bi_envp)
1943 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1946 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1947 preload_bootstrap_relocate(PTOV_OFFSET);
1948 kmdp = preload_search_by_type("elf kernel");
1950 kmdp = preload_search_by_type("elf64 kernel");
1951 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1952 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1954 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1955 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1958 if (boothowto & RB_VERBOSE)
1962 * Default MachIntrABI to ICU
1964 MachIntrABI = MachIntrABI_ICU;
1967 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1968 * and ncpus_fit_mask remain 0.
1973 /* Init basic tunables, hz etc */
1977 * make gdt memory segments
1979 gdt_segs[GPROC0_SEL].ssd_base =
1980 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1982 gd->mi.gd_prvspace = &CPU_prvspace[0];
1984 for (x = 0; x < NGDT; x++) {
1985 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1986 ssdtosd(&gdt_segs[x], &gdt[x]);
1988 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1989 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1991 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1992 r_gdt.rd_base = (long) gdt;
1995 wrmsr(MSR_FSBASE, 0); /* User value */
1996 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1997 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1999 mi_gdinit(&gd->mi, 0);
2001 proc0paddr = proc0paddr_buff;
2002 mi_proc0init(&gd->mi, proc0paddr);
2003 safepri = TDPRI_MAX;
2005 /* spinlocks and the BGL */
2009 for (x = 0; x < NIDT; x++)
2010 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2011 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2012 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2013 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2014 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2015 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2016 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2017 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2018 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2019 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2020 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2021 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2022 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2023 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2024 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2025 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2026 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2027 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2028 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2029 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2031 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2032 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2033 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2036 lidt(&r_idt_arr[0]);
2039 * Initialize the console before we print anything out.
2044 if (metadata_missing)
2045 kprintf("WARNING: loader(8) metadata is missing!\n");
2055 * Initialize IRQ mapping
2058 * SHOULD be after elcr_probe()
2060 MachIntrABI_ICU.initmap();
2061 MachIntrABI_IOAPIC.initmap();
2065 if (boothowto & RB_KDB)
2066 Debugger("Boot flags requested debugger");
2070 finishidentcpu(); /* Final stage of CPU initialization */
2071 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2072 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2074 identify_cpu(); /* Final stage of CPU initialization */
2075 initializecpu(0); /* Initialize CPU registers */
2077 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2078 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2079 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2082 * Some of the virtual machines do not work w/ I/O APIC
2083 * enabled. If the user does not explicitly enable or
2084 * disable the I/O APIC (ioapic_enable < 0), then we
2085 * disable I/O APIC on all virtual machines.
2088 * This must be done after identify_cpu(), which sets
2091 if (ioapic_enable < 0) {
2092 if (cpu_feature2 & CPUID2_VMM)
2098 /* make an initial tss so cpu can get interrupt stack on syscall! */
2099 gd->gd_common_tss.tss_rsp0 =
2100 (register_t)(thread0.td_kstack +
2101 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2102 /* Ensure the stack is aligned to 16 bytes */
2103 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2105 /* double fault stack */
2106 gd->gd_common_tss.tss_ist1 =
2107 (long)&gd->mi.gd_prvspace->idlestack[
2108 sizeof(gd->mi.gd_prvspace->idlestack)];
2110 /* Set the IO permission bitmap (empty due to tss seg limit) */
2111 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2113 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2114 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2115 gd->gd_common_tssd = *gd->gd_tss_gdt;
2118 /* Set up the fast syscall stuff */
2119 msr = rdmsr(MSR_EFER) | EFER_SCE;
2120 wrmsr(MSR_EFER, msr);
2121 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2122 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2123 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2124 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2125 wrmsr(MSR_STAR, msr);
2126 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2128 getmemsize(kmdp, physfree);
2129 init_param2(physmem);
2131 /* now running on new page tables, configured,and u/iom is accessible */
2133 /* Map the message buffer. */
2135 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2136 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2139 msgbufinit(msgbufp, MSGBUF_SIZE);
2142 /* transfer to user mode */
2144 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2145 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2146 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2152 /* setup proc 0's pcb */
2153 thread0.td_pcb->pcb_flags = 0;
2154 thread0.td_pcb->pcb_cr3 = KPML4phys;
2155 thread0.td_pcb->pcb_ext = NULL;
2156 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2158 /* Location of kernel stack for locore */
2159 return ((u_int64_t)thread0.td_pcb);
2163 * Initialize machine-dependant portions of the global data structure.
2164 * Note that the global data area and cpu0's idlestack in the private
2165 * data space were allocated in locore.
2167 * Note: the idlethread's cpl is 0
2169 * WARNING! Called from early boot, 'mycpu' may not work yet.
2172 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2175 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2177 lwkt_init_thread(&gd->mi.gd_idlethread,
2178 gd->mi.gd_prvspace->idlestack,
2179 sizeof(gd->mi.gd_prvspace->idlestack),
2181 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2182 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2183 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2184 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2188 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2190 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2191 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2194 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2200 globaldata_find(int cpu)
2202 KKASSERT(cpu >= 0 && cpu < ncpus);
2203 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2207 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2209 lp->lwp_md.md_regs->tf_rip = addr;
2214 ptrace_single_step(struct lwp *lp)
2216 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2221 fill_regs(struct lwp *lp, struct reg *regs)
2223 struct trapframe *tp;
2225 if ((tp = lp->lwp_md.md_regs) == NULL)
2227 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2232 set_regs(struct lwp *lp, struct reg *regs)
2234 struct trapframe *tp;
2236 tp = lp->lwp_md.md_regs;
2237 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2238 !CS_SECURE(regs->r_cs))
2240 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2245 #ifndef CPU_DISABLE_SSE
2247 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2249 struct env87 *penv_87 = &sv_87->sv_env;
2250 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2253 /* FPU control/status */
2254 penv_87->en_cw = penv_xmm->en_cw;
2255 penv_87->en_sw = penv_xmm->en_sw;
2256 penv_87->en_tw = penv_xmm->en_tw;
2257 penv_87->en_fip = penv_xmm->en_fip;
2258 penv_87->en_fcs = penv_xmm->en_fcs;
2259 penv_87->en_opcode = penv_xmm->en_opcode;
2260 penv_87->en_foo = penv_xmm->en_foo;
2261 penv_87->en_fos = penv_xmm->en_fos;
2264 for (i = 0; i < 8; ++i)
2265 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2269 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2271 struct env87 *penv_87 = &sv_87->sv_env;
2272 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2275 /* FPU control/status */
2276 penv_xmm->en_cw = penv_87->en_cw;
2277 penv_xmm->en_sw = penv_87->en_sw;
2278 penv_xmm->en_tw = penv_87->en_tw;
2279 penv_xmm->en_fip = penv_87->en_fip;
2280 penv_xmm->en_fcs = penv_87->en_fcs;
2281 penv_xmm->en_opcode = penv_87->en_opcode;
2282 penv_xmm->en_foo = penv_87->en_foo;
2283 penv_xmm->en_fos = penv_87->en_fos;
2286 for (i = 0; i < 8; ++i)
2287 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2289 #endif /* CPU_DISABLE_SSE */
2292 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2294 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2296 #ifndef CPU_DISABLE_SSE
2298 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2299 (struct save87 *)fpregs);
2302 #endif /* CPU_DISABLE_SSE */
2303 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2308 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2310 #ifndef CPU_DISABLE_SSE
2312 set_fpregs_xmm((struct save87 *)fpregs,
2313 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2316 #endif /* CPU_DISABLE_SSE */
2317 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2322 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2327 dbregs->dr[0] = rdr0();
2328 dbregs->dr[1] = rdr1();
2329 dbregs->dr[2] = rdr2();
2330 dbregs->dr[3] = rdr3();
2331 dbregs->dr[4] = rdr4();
2332 dbregs->dr[5] = rdr5();
2333 dbregs->dr[6] = rdr6();
2334 dbregs->dr[7] = rdr7();
2337 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2339 dbregs->dr[0] = pcb->pcb_dr0;
2340 dbregs->dr[1] = pcb->pcb_dr1;
2341 dbregs->dr[2] = pcb->pcb_dr2;
2342 dbregs->dr[3] = pcb->pcb_dr3;
2345 dbregs->dr[6] = pcb->pcb_dr6;
2346 dbregs->dr[7] = pcb->pcb_dr7;
2351 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2354 load_dr0(dbregs->dr[0]);
2355 load_dr1(dbregs->dr[1]);
2356 load_dr2(dbregs->dr[2]);
2357 load_dr3(dbregs->dr[3]);
2358 load_dr4(dbregs->dr[4]);
2359 load_dr5(dbregs->dr[5]);
2360 load_dr6(dbregs->dr[6]);
2361 load_dr7(dbregs->dr[7]);
2364 struct ucred *ucred;
2366 uint64_t mask1, mask2;
2369 * Don't let an illegal value for dr7 get set. Specifically,
2370 * check for undefined settings. Setting these bit patterns
2371 * result in undefined behaviour and can lead to an unexpected
2374 /* JG this loop looks unreadable */
2375 /* Check 4 2-bit fields for invalid patterns.
2376 * These fields are R/Wi, for i = 0..3
2378 /* Is 10 in LENi allowed when running in compatibility mode? */
2379 /* Pattern 10 in R/Wi might be used to indicate
2380 * breakpoint on I/O. Further analysis should be
2381 * carried to decide if it is safe and useful to
2382 * provide access to that capability
2384 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2385 i++, mask1 <<= 4, mask2 <<= 4)
2386 if ((dbregs->dr[7] & mask1) == mask2)
2389 pcb = lp->lwp_thread->td_pcb;
2390 ucred = lp->lwp_proc->p_ucred;
2393 * Don't let a process set a breakpoint that is not within the
2394 * process's address space. If a process could do this, it
2395 * could halt the system by setting a breakpoint in the kernel
2396 * (if ddb was enabled). Thus, we need to check to make sure
2397 * that no breakpoints are being enabled for addresses outside
2398 * process's address space, unless, perhaps, we were called by
2401 * XXX - what about when the watched area of the user's
2402 * address space is written into from within the kernel
2403 * ... wouldn't that still cause a breakpoint to be generated
2404 * from within kernel mode?
2407 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2408 if (dbregs->dr[7] & 0x3) {
2409 /* dr0 is enabled */
2410 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2414 if (dbregs->dr[7] & (0x3<<2)) {
2415 /* dr1 is enabled */
2416 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2420 if (dbregs->dr[7] & (0x3<<4)) {
2421 /* dr2 is enabled */
2422 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2426 if (dbregs->dr[7] & (0x3<<6)) {
2427 /* dr3 is enabled */
2428 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2433 pcb->pcb_dr0 = dbregs->dr[0];
2434 pcb->pcb_dr1 = dbregs->dr[1];
2435 pcb->pcb_dr2 = dbregs->dr[2];
2436 pcb->pcb_dr3 = dbregs->dr[3];
2437 pcb->pcb_dr6 = dbregs->dr[6];
2438 pcb->pcb_dr7 = dbregs->dr[7];
2440 pcb->pcb_flags |= PCB_DBREGS;
2447 * Return > 0 if a hardware breakpoint has been hit, and the
2448 * breakpoint was in user space. Return 0, otherwise.
2451 user_dbreg_trap(void)
2453 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2454 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2455 int nbp; /* number of breakpoints that triggered */
2456 caddr_t addr[4]; /* breakpoint addresses */
2460 if ((dr7 & 0xff) == 0) {
2462 * all GE and LE bits in the dr7 register are zero,
2463 * thus the trap couldn't have been caused by the
2464 * hardware debug registers
2475 * None of the breakpoint bits are set meaning this
2476 * trap was not caused by any of the debug registers
2482 * at least one of the breakpoints were hit, check to see
2483 * which ones and if any of them are user space addresses
2487 addr[nbp++] = (caddr_t)rdr0();
2490 addr[nbp++] = (caddr_t)rdr1();
2493 addr[nbp++] = (caddr_t)rdr2();
2496 addr[nbp++] = (caddr_t)rdr3();
2499 for (i=0; i<nbp; i++) {
2501 (caddr_t)VM_MAX_USER_ADDRESS) {
2503 * addr[i] is in user space
2510 * None of the breakpoints are in user space.
2518 Debugger(const char *msg)
2520 kprintf("Debugger(\"%s\") called.\n", msg);
2527 * Provide inb() and outb() as functions. They are normally only
2528 * available as macros calling inlined functions, thus cannot be
2529 * called inside DDB.
2531 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2537 /* silence compiler warnings */
2539 void outb(u_int, u_char);
2546 * We use %%dx and not %1 here because i/o is done at %dx and not at
2547 * %edx, while gcc generates inferior code (movw instead of movl)
2548 * if we tell it to load (u_short) port.
2550 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2555 outb(u_int port, u_char data)
2559 * Use an unnecessary assignment to help gcc's register allocator.
2560 * This make a large difference for gcc-1.40 and a tiny difference
2561 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2562 * best results. gcc-2.6.0 can't handle this.
2565 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2573 * initialize all the SMP locks
2576 /* critical region when masking or unmasking interupts */
2577 struct spinlock_deprecated imen_spinlock;
2579 /* critical region for old style disable_intr/enable_intr */
2580 struct spinlock_deprecated mpintr_spinlock;
2582 /* critical region around INTR() routines */
2583 struct spinlock_deprecated intr_spinlock;
2585 /* lock region used by kernel profiling */
2586 struct spinlock_deprecated mcount_spinlock;
2588 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2589 struct spinlock_deprecated com_spinlock;
2591 /* lock regions around the clock hardware */
2592 struct spinlock_deprecated clock_spinlock;
2598 * Get the initial mplock with a count of 1 for the BSP.
2599 * This uses a LOGICAL cpu ID, ie BSP == 0.
2601 cpu_get_initial_mplock();
2603 spin_lock_init(&mcount_spinlock);
2604 spin_lock_init(&intr_spinlock);
2605 spin_lock_init(&mpintr_spinlock);
2606 spin_lock_init(&imen_spinlock);
2607 spin_lock_init(&com_spinlock);
2608 spin_lock_init(&clock_spinlock);
2610 /* our token pool needs to work early */
2611 lwkt_token_pool_init();
2615 cpu_mwait_hint_valid(uint32_t hint)
2619 cx_idx = MWAIT_EAX_TO_CX(hint);
2620 if (cx_idx >= CPU_MWAIT_CX_MAX)
2623 sub = MWAIT_EAX_TO_CX_SUB(hint);
2624 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2631 cpu_mwait_cx_no_bmsts(void)
2633 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2637 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
2638 boolean_t allow_auto)
2640 int error, cx_idx, old_cx_idx, sub = 0, hint;
2641 char name[16], *ptr, *start;
2645 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2646 sub = MWAIT_EAX_TO_CX_SUB(hint);
2647 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2648 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2649 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2650 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2652 old_cx_idx = CPU_MWAIT_CX_MAX;
2655 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2656 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2657 strlcpy(name, "NONE", sizeof(name));
2658 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2659 strlcpy(name, "AUTO", sizeof(name));
2660 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2661 strlcpy(name, "AUTODEEP", sizeof(name));
2662 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2663 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2664 strlcpy(name, "INVALID", sizeof(name));
2666 ksnprintf(name, sizeof(name), "C%d/%d", old_cx_idx, sub);
2668 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2669 if (error != 0 || req->newptr == NULL)
2672 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2673 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2676 if (allow_auto && strcmp(name, "AUTO") == 0) {
2677 hint = CPU_MWAIT_HINT_AUTO;
2678 cx_idx = CPU_MWAIT_C2;
2681 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2682 hint = CPU_MWAIT_HINT_AUTODEEP;
2683 cx_idx = CPU_MWAIT_C3;
2687 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2692 cx_idx = strtol(start, &ptr, 10);
2693 if (ptr == start || *ptr != '/')
2695 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2701 sub = strtol(start, &ptr, 10);
2704 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2707 hint = MWAIT_EAX_HINT(cx_idx, sub);
2709 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2711 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2712 error = cputimer_intr_powersave_addreq();
2715 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2716 cputimer_intr_powersave_remreq();
2724 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
2728 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2729 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2730 &cpu_mwait_halt, TRUE);
2731 lwkt_serialize_exit(&cpu_mwait_cx_slize);
2736 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
2740 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2741 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2742 &cpu_mwait_spin, FALSE);
2743 lwkt_serialize_exit(&cpu_mwait_cx_slize);