2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_BASE2 (0xe0000)
77 #define BIOS_SIZE (0x10000)
78 #define BIOS_COUNT (BIOS_SIZE/4)
80 #define CMOS_REG (0x70)
81 #define CMOS_DATA (0x71)
82 #define BIOS_RESET (0x0f)
83 #define BIOS_WARM (0x0a)
85 #define PROCENTRY_FLAG_EN 0x01
86 #define PROCENTRY_FLAG_BP 0x02
87 #define IOAPICENTRY_FLAG_EN 0x01
90 /* MP Floating Pointer Structure */
91 typedef struct MPFPS {
104 /* MP Configuration Table Header */
105 typedef struct MPCTH {
107 u_short base_table_length;
111 u_char product_id[12];
112 u_int32_t oem_table_pointer;
113 u_short oem_table_size;
115 u_int32_t apic_address;
116 u_short extended_table_length;
117 u_char extended_table_checksum;
122 typedef struct PROCENTRY {
127 u_int32_t cpu_signature;
128 u_int32_t feature_flags;
133 typedef struct BUSENTRY {
139 typedef struct IOAPICENTRY {
144 u_int32_t apic_address;
145 } *io_apic_entry_ptr;
147 typedef struct INTENTRY {
157 /* descriptions of MP basetable entries */
158 typedef struct BASETABLE_ENTRY {
167 vm_size_t mp_cth_mapsz;
170 typedef int (*mptable_iter_func)(void *, const void *, int);
173 * this code MUST be enabled here and in mpboot.s.
174 * it follows the very early stages of AP boot by placing values in CMOS ram.
175 * it NORMALLY will never be needed and thus the primitive method for enabling.
178 #if defined(CHECK_POINTS)
179 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
180 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
182 #define CHECK_INIT(D); \
183 CHECK_WRITE(0x34, (D)); \
184 CHECK_WRITE(0x35, (D)); \
185 CHECK_WRITE(0x36, (D)); \
186 CHECK_WRITE(0x37, (D)); \
187 CHECK_WRITE(0x38, (D)); \
188 CHECK_WRITE(0x39, (D));
190 #define CHECK_PRINT(S); \
191 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
200 #else /* CHECK_POINTS */
202 #define CHECK_INIT(D)
203 #define CHECK_PRINT(S)
205 #endif /* CHECK_POINTS */
208 * Values to send to the POST hardware.
210 #define MP_BOOTADDRESS_POST 0x10
211 #define MP_PROBE_POST 0x11
212 #define MPTABLE_PASS1_POST 0x12
214 #define MP_START_POST 0x13
215 #define MP_ENABLE_POST 0x14
216 #define MPTABLE_PASS2_POST 0x15
218 #define START_ALL_APS_POST 0x16
219 #define INSTALL_AP_TRAMP_POST 0x17
220 #define START_AP_POST 0x18
222 #define MP_ANNOUNCE_POST 0x19
224 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225 int current_postcode;
227 /** XXX FIXME: what system files declare these??? */
228 extern struct region_descriptor r_gdt, r_idt;
230 int mp_naps; /* # of Applications processors */
232 static int mp_nbusses; /* # of busses */
233 int mp_napics; /* # of IO APICs */
236 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
237 u_int32_t *io_apic_versions;
241 u_int32_t cpu_apic_versions[MAXCPU];
243 extern int64_t tsc_offsets[];
245 extern u_long ebda_addr;
248 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
252 * APIC ID logical/physical mapping structures.
253 * We oversize these to simplify boot-time config.
255 int cpu_num_to_apic_id[NAPICID];
257 int io_num_to_apic_id[NAPICID];
259 int apic_id_to_logical[NAPICID];
261 /* AP uses this during bootstrap. Do not staticize. */
266 * SMP page table page. Setup by locore to point to a page table
267 * page from which we allocate per-cpu privatespace areas io_apics,
271 #define IO_MAPPING_START_INDEX \
272 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
274 extern pt_entry_t *SMPpt;
276 struct pcb stoppcbs[MAXCPU];
278 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
280 static basetable_entry basetable_entry_types[] =
282 {0, 20, "Processor"},
290 * Local data and functions.
293 static u_int boot_address;
294 static u_int base_memory;
295 static int mp_finish;
297 static void mp_enable(u_int boot_addr);
299 static int mptable_iterate_entries(const mpcth_t,
300 mptable_iter_func, void *);
301 static int mptable_probe(void);
302 static int mptable_search(void);
303 static int mptable_check(vm_paddr_t);
304 static long mptable_search_sig(u_int32_t target, int count);
305 static int mptable_hyperthread_fixup(u_int, int);
307 static void mptable_pass1(struct mptable_pos *);
308 static void mptable_pass2(struct mptable_pos *);
309 static void mptable_default(int type);
310 static void mptable_fix(void);
312 static int mptable_map(struct mptable_pos *, vm_paddr_t);
313 static void mptable_unmap(struct mptable_pos *);
314 static void mptable_imcr(struct mptable_pos *);
316 static int mptable_lapic_probe(struct lapic_enumerator *);
317 static void mptable_lapic_enumerate(struct lapic_enumerator *);
318 static void mptable_lapic_default(void);
321 static void setup_apic_irq_mapping(void);
322 static int apic_int_is_bus_type(int intr, int bus_type);
324 static int start_all_aps(u_int boot_addr);
326 static void install_ap_tramp(u_int boot_addr);
328 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
329 static int smitest(void);
331 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
332 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
333 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
334 static u_int bootMP_size;
337 * Calculate usable address in base memory for AP trampoline code.
340 mp_bootaddress(u_int basemem)
342 POSTCODE(MP_BOOTADDRESS_POST);
344 base_memory = basemem;
346 bootMP_size = mptramp_end - mptramp_start;
347 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
348 if (((basemem * 1024) - boot_address) < bootMP_size)
349 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
350 /* 3 levels of page table pages */
351 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
353 return mptramp_pagetables;
362 mpfps_paddr = mptable_search();
363 if (mptable_check(mpfps_paddr))
370 * Look for an Intel MP spec table (ie, SMP capable hardware).
379 * Make sure our SMPpt[] page table is big enough to hold all the
382 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
384 POSTCODE(MP_PROBE_POST);
386 /* see if EBDA exists */
387 if (ebda_addr != 0) {
388 /* search first 1K of EBDA */
389 target = (u_int32_t)ebda_addr;
390 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
393 /* last 1K of base memory, effective 'top of base' passed in */
394 target = (u_int32_t)(base_memory - 0x400);
395 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
399 /* search the BIOS */
400 target = (u_int32_t)BIOS_BASE;
401 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
404 /* search the extended BIOS */
405 target = (u_int32_t)BIOS_BASE2;
406 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
413 struct mptable_check_cbarg {
419 mptable_check_callback(void *xarg, const void *pos, int type)
421 const struct PROCENTRY *ent;
422 struct mptable_check_cbarg *arg = xarg;
428 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
432 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
433 if (arg->found_bsp) {
434 kprintf("more than one BSP in base MP table\n");
443 mptable_check(vm_paddr_t mpfps_paddr)
445 struct mptable_pos mpt;
446 struct mptable_check_cbarg arg;
450 if (mpfps_paddr == 0)
453 error = mptable_map(&mpt, mpfps_paddr);
457 if (mpt.mp_fps->mpfb1 != 0)
465 if (cth->apic_address == 0)
468 bzero(&arg, sizeof(arg));
469 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
471 if (arg.cpu_count == 0) {
472 kprintf("MP table contains no processor entries\n");
474 } else if (!arg.found_bsp) {
475 kprintf("MP table does not contains BSP entry\n");
485 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
487 int count, total_size;
488 const void *position;
490 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
491 total_size = cth->base_table_length - sizeof(struct MPCTH);
492 position = (const uint8_t *)cth + sizeof(struct MPCTH);
493 count = cth->entry_count;
498 KKASSERT(total_size >= 0);
499 if (total_size == 0) {
500 kprintf("invalid base MP table, "
501 "entry count and length mismatch\n");
505 type = *(const uint8_t *)position;
507 case 0: /* processor_entry */
508 case 1: /* bus_entry */
509 case 2: /* io_apic_entry */
510 case 3: /* int_entry */
511 case 4: /* int_entry */
514 kprintf("unknown base MP table entry type %d\n", type);
518 if (total_size < basetable_entry_types[type].length) {
519 kprintf("invalid base MP table length, "
520 "does not contain all entries\n");
523 total_size -= basetable_entry_types[type].length;
525 error = func(arg, position, type);
529 position = (const uint8_t *)position +
530 basetable_entry_types[type].length;
537 * Startup the SMP processors.
542 POSTCODE(MP_START_POST);
543 mp_enable(boot_address);
548 * Print various information about the SMP system hardware and setup.
555 POSTCODE(MP_ANNOUNCE_POST);
557 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
558 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
559 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
560 for (x = 1; x <= mp_naps; ++x) {
561 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
562 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
566 for (x = 0; x < mp_napics; ++x) {
567 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
568 kprintf(", version: 0x%08x", io_apic_versions[x]);
569 kprintf(", at 0x%08lx\n", io_apic_address[x]);
572 kprintf(" Warning: APIC I/O disabled\n");
577 * AP cpu's call this to sync up protected mode.
579 * WARNING! %gs is not set up on entry. This routine sets up %gs.
585 int x, myid = bootAP;
587 struct mdglobaldata *md;
588 struct privatespace *ps;
590 ps = &CPU_prvspace[myid];
592 gdt_segs[GPROC0_SEL].ssd_base =
593 (long) &ps->mdglobaldata.gd_common_tss;
594 ps->mdglobaldata.mi.gd_prvspace = ps;
596 /* We fill the 32-bit segment descriptors */
597 for (x = 0; x < NGDT; x++) {
598 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
599 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
601 /* And now a 64-bit one */
602 ssdtosyssd(&gdt_segs[GPROC0_SEL],
603 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
605 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
606 r_gdt.rd_base = (long) &gdt[myid * NGDT];
607 lgdt(&r_gdt); /* does magic intra-segment return */
609 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
610 wrmsr(MSR_FSBASE, 0); /* User value */
611 wrmsr(MSR_GSBASE, (u_int64_t)ps);
612 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
618 mdcpu->gd_currentldt = _default_ldt;
621 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
622 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
624 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
626 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
628 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
630 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
631 md->gd_common_tssd = *md->gd_tss_gdt;
633 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
638 * Set to a known state:
639 * Set by mpboot.s: CR0_PG, CR0_PE
640 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
643 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
646 /* Set up the fast syscall stuff */
647 msr = rdmsr(MSR_EFER) | EFER_SCE;
648 wrmsr(MSR_EFER, msr);
649 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
650 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
651 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
652 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
653 wrmsr(MSR_STAR, msr);
654 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
656 pmap_set_opt(); /* PSE/4MB pages, etc */
658 /* Initialize the PAT MSR. */
662 /* set up CPU registers and state */
665 /* set up SSE/NX registers */
668 /* set up FPU state on the AP */
669 npxinit(__INITIAL_NPXCW__);
671 /* disable the APIC, just to be SURE */
672 lapic->svr &= ~APIC_SVR_ENABLE;
674 /* data returned to BSP */
675 cpu_apic_versions[0] = lapic->version;
678 /*******************************************************************
679 * local functions and data
683 * start the SMP system
686 mp_enable(u_int boot_addr)
692 vm_paddr_t mpfps_paddr;
693 struct mptable_pos mpt;
695 POSTCODE(MP_ENABLE_POST);
699 mpfps_paddr = mptable_probe();
701 mptable_map(&mpt, mpfps_paddr);
708 panic("no MP table, disable APIC_IO!\n");
710 mptable_map(&mpt, mpfps_paddr);
713 * Examine the MP table for needed info
720 /* Post scan cleanup */
723 setup_apic_irq_mapping();
725 /* fill the LOGICAL io_apic_versions table */
726 for (apic = 0; apic < mp_napics; ++apic) {
727 ux = io_apic_read(apic, IOAPIC_VER);
728 io_apic_versions[apic] = ux;
729 io_apic_set_id(apic, IO_TO_ID(apic));
732 /* program each IO APIC in the system */
733 for (apic = 0; apic < mp_napics; ++apic)
734 if (io_apic_setup(apic) < 0)
735 panic("IO APIC setup failure");
740 * These are required for SMP operation
743 /* install a 'Spurious INTerrupt' vector */
744 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
745 SDT_SYSIGT, SEL_KPL, 0);
747 /* install an inter-CPU IPI for TLB invalidation */
748 setidt(XINVLTLB_OFFSET, Xinvltlb,
749 SDT_SYSIGT, SEL_KPL, 0);
751 /* install an inter-CPU IPI for IPIQ messaging */
752 setidt(XIPIQ_OFFSET, Xipiq,
753 SDT_SYSIGT, SEL_KPL, 0);
755 /* install a timer vector */
756 setidt(XTIMER_OFFSET, Xtimer,
757 SDT_SYSIGT, SEL_KPL, 0);
759 /* install an inter-CPU IPI for CPU stop/restart */
760 setidt(XCPUSTOP_OFFSET, Xcpustop,
761 SDT_SYSIGT, SEL_KPL, 0);
763 /* start each Application Processor */
764 start_all_aps(boot_addr);
769 * look for the MP spec signature
772 /* string defined by the Intel MP Spec as identifying the MP table */
773 #define MP_SIG 0x5f504d5f /* _MP_ */
774 #define NEXT(X) ((X) += 4)
776 mptable_search_sig(u_int32_t target, int count)
782 KKASSERT(target != 0);
784 map_size = count * sizeof(u_int32_t);
785 addr = pmap_mapdev((vm_paddr_t)target, map_size);
788 for (x = 0; x < count; NEXT(x)) {
789 if (addr[x] == MP_SIG) {
790 /* make array index a byte index */
791 ret = target + (x * sizeof(u_int32_t));
796 pmap_unmapdev((vm_offset_t)addr, map_size);
801 typedef struct BUSDATA {
803 enum busTypes bus_type;
806 typedef struct INTDATA {
816 typedef struct BUSTYPENAME {
823 static bus_type_name bus_type_table[] =
829 {UNKNOWN_BUSTYPE, "---"},
832 {UNKNOWN_BUSTYPE, "---"},
833 {UNKNOWN_BUSTYPE, "---"},
834 {UNKNOWN_BUSTYPE, "---"},
835 {UNKNOWN_BUSTYPE, "---"},
836 {UNKNOWN_BUSTYPE, "---"},
838 {UNKNOWN_BUSTYPE, "---"},
839 {UNKNOWN_BUSTYPE, "---"},
840 {UNKNOWN_BUSTYPE, "---"},
841 {UNKNOWN_BUSTYPE, "---"},
843 {UNKNOWN_BUSTYPE, "---"}
846 /* from MP spec v1.4, table 5-1 */
847 static int default_data[7][5] =
849 /* nbus, id0, type0, id1, type1 */
850 {1, 0, ISA, 255, 255},
851 {1, 0, EISA, 255, 255},
852 {1, 0, EISA, 255, 255},
853 {1, 0, MCA, 255, 255},
855 {2, 0, EISA, 1, PCI},
860 static bus_datum *bus_data;
862 /* the IO INT data, one entry per possible APIC INTerrupt */
863 static io_int *io_apic_ints;
868 static int processor_entry (const struct PROCENTRY *entry, int cpu);
870 static int bus_entry (const struct BUSENTRY *entry, int bus);
871 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
872 static int int_entry (const struct INTENTRY *entry, int intr);
873 static int lookup_bus_type (char *name);
879 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
881 const struct IOAPICENTRY *ioapic_ent;
884 case 1: /* bus_entry */
888 case 2: /* io_apic_entry */
890 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
891 io_apic_address[mp_napics++] =
892 (vm_offset_t)ioapic_ent->apic_address;
896 case 3: /* int_entry */
904 * 1st pass on motherboard's Intel MP specification table.
913 mptable_pass1(struct mptable_pos *mpt)
918 POSTCODE(MPTABLE_PASS1_POST);
921 KKASSERT(fps != NULL);
923 /* clear various tables */
924 for (x = 0; x < NAPICID; ++x)
925 io_apic_address[x] = ~0; /* IO APIC address table */
931 /* check for use of 'default' configuration */
932 if (fps->mpfb1 != 0) {
933 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
934 mp_nbusses = default_data[fps->mpfb1 - 1][0];
940 error = mptable_iterate_entries(mpt->mp_cth,
941 mptable_ioapic_pass1_callback, NULL);
943 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
947 struct mptable_ioapic2_cbarg {
954 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
956 struct mptable_ioapic2_cbarg *arg = xarg;
960 if (bus_entry(pos, arg->bus))
965 if (io_apic_entry(pos, arg->apic))
970 if (int_entry(pos, arg->intr))
978 * 2nd pass on motherboard's Intel MP specification table.
981 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
982 * IO_TO_ID(N), logical IO to APIC ID table
987 mptable_pass2(struct mptable_pos *mpt)
989 struct mptable_ioapic2_cbarg arg;
993 POSTCODE(MPTABLE_PASS2_POST);
996 KKASSERT(fps != NULL);
998 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1000 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1001 M_DEVBUF, M_WAITOK | M_ZERO);
1002 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1003 M_DEVBUF, M_WAITOK);
1004 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1005 M_DEVBUF, M_WAITOK);
1007 for (x = 0; x < mp_napics; x++)
1008 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
1010 /* clear various tables */
1011 for (x = 0; x < NAPICID; ++x) {
1012 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1013 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1016 /* clear bus data table */
1017 for (x = 0; x < mp_nbusses; ++x)
1018 bus_data[x].bus_id = 0xff;
1020 /* clear IO APIC INT table */
1021 for (x = 0; x < (nintrs + 1); ++x) {
1022 io_apic_ints[x].int_type = 0xff;
1023 io_apic_ints[x].int_vector = 0xff;
1026 /* check for use of 'default' configuration */
1027 if (fps->mpfb1 != 0) {
1028 mptable_default(fps->mpfb1);
1032 bzero(&arg, sizeof(arg));
1033 error = mptable_iterate_entries(mpt->mp_cth,
1034 mptable_ioapic_pass2_callback, &arg);
1036 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1042 * Check if we should perform a hyperthreading "fix-up" to
1043 * enumerate any logical CPU's that aren't already listed
1046 * XXX: We assume that all of the physical CPUs in the
1047 * system have the same number of logical CPUs.
1049 * XXX: We assume that APIC ID's are allocated such that
1050 * the APIC ID's for a physical processor are aligned
1051 * with the number of logical CPU's in the processor.
1054 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1056 int i, id, lcpus_max, logical_cpus;
1058 if ((cpu_feature & CPUID_HTT) == 0)
1061 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1065 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1067 * INSTRUCTION SET REFERENCE, A-M (#253666)
1068 * Page 3-181, Table 3-20
1069 * "The nearest power-of-2 integer that is not smaller
1070 * than EBX[23:16] is the number of unique initial APIC
1071 * IDs reserved for addressing different logical
1072 * processors in a physical package."
1074 for (i = 0; ; ++i) {
1075 if ((1 << i) >= lcpus_max) {
1082 KKASSERT(cpu_count != 0);
1083 if (cpu_count == lcpus_max) {
1084 /* We have nothing to fix */
1086 } else if (cpu_count == 1) {
1087 /* XXX this may be incorrect */
1088 logical_cpus = lcpus_max;
1090 int cur, prev, dist;
1093 * Calculate the distances between two nearest
1094 * APIC IDs. If all such distances are same,
1095 * then it is the number of missing cpus that
1096 * we are going to fill later.
1098 dist = cur = prev = -1;
1099 for (id = 0; id < MAXCPU; ++id) {
1100 if ((id_mask & 1 << id) == 0)
1105 int new_dist = cur - prev;
1111 * Make sure that all distances
1112 * between two nearest APIC IDs
1115 if (dist != new_dist)
1123 /* Must be power of 2 */
1124 if (dist & (dist - 1))
1127 /* Can't exceed CPU package capacity */
1128 if (dist > lcpus_max)
1129 logical_cpus = lcpus_max;
1131 logical_cpus = dist;
1135 * For each APIC ID of a CPU that is set in the mask,
1136 * scan the other candidate APIC ID's for this
1137 * physical processor. If any of those ID's are
1138 * already in the table, then kill the fixup.
1140 for (id = 0; id < MAXCPU; id++) {
1141 if ((id_mask & 1 << id) == 0)
1143 /* First, make sure we are on a logical_cpus boundary. */
1144 if (id % logical_cpus != 0)
1146 for (i = id + 1; i < id + logical_cpus; i++)
1147 if ((id_mask & 1 << i) != 0)
1150 return logical_cpus;
1154 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1158 vm_size_t cth_mapsz = 0;
1160 bzero(mpt, sizeof(*mpt));
1162 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1163 if (fps->pap != 0) {
1165 * Map configuration table header to get
1166 * the base table size
1168 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1169 cth_mapsz = cth->base_table_length;
1170 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1172 if (cth_mapsz < sizeof(*cth)) {
1173 kprintf("invalid base MP table length %d\n",
1175 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1180 * Map the base table
1182 cth = pmap_mapdev(fps->pap, cth_mapsz);
1187 mpt->mp_cth_mapsz = cth_mapsz;
1193 mptable_unmap(struct mptable_pos *mpt)
1195 if (mpt->mp_cth != NULL) {
1196 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1198 mpt->mp_cth_mapsz = 0;
1200 if (mpt->mp_fps != NULL) {
1201 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1209 assign_apic_irq(int apic, int intpin, int irq)
1213 if (int_to_apicintpin[irq].ioapic != -1)
1214 panic("assign_apic_irq: inconsistent table");
1216 int_to_apicintpin[irq].ioapic = apic;
1217 int_to_apicintpin[irq].int_pin = intpin;
1218 int_to_apicintpin[irq].apic_address = ioapic[apic];
1219 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1221 for (x = 0; x < nintrs; x++) {
1222 if ((io_apic_ints[x].int_type == 0 ||
1223 io_apic_ints[x].int_type == 3) &&
1224 io_apic_ints[x].int_vector == 0xff &&
1225 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1226 io_apic_ints[x].dst_apic_int == intpin)
1227 io_apic_ints[x].int_vector = irq;
1232 revoke_apic_irq(int irq)
1238 if (int_to_apicintpin[irq].ioapic == -1)
1239 panic("revoke_apic_irq: inconsistent table");
1241 oldapic = int_to_apicintpin[irq].ioapic;
1242 oldintpin = int_to_apicintpin[irq].int_pin;
1244 int_to_apicintpin[irq].ioapic = -1;
1245 int_to_apicintpin[irq].int_pin = 0;
1246 int_to_apicintpin[irq].apic_address = NULL;
1247 int_to_apicintpin[irq].redirindex = 0;
1249 for (x = 0; x < nintrs; x++) {
1250 if ((io_apic_ints[x].int_type == 0 ||
1251 io_apic_ints[x].int_type == 3) &&
1252 io_apic_ints[x].int_vector != 0xff &&
1253 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1254 io_apic_ints[x].dst_apic_int == oldintpin)
1255 io_apic_ints[x].int_vector = 0xff;
1263 allocate_apic_irq(int intr)
1269 if (io_apic_ints[intr].int_vector != 0xff)
1270 return; /* Interrupt handler already assigned */
1272 if (io_apic_ints[intr].int_type != 0 &&
1273 (io_apic_ints[intr].int_type != 3 ||
1274 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1275 io_apic_ints[intr].dst_apic_int == 0)))
1276 return; /* Not INT or ExtInt on != (0, 0) */
1279 while (irq < APIC_INTMAPSIZE &&
1280 int_to_apicintpin[irq].ioapic != -1)
1283 if (irq >= APIC_INTMAPSIZE)
1284 return; /* No free interrupt handlers */
1286 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1287 intpin = io_apic_ints[intr].dst_apic_int;
1289 assign_apic_irq(apic, intpin, irq);
1294 swap_apic_id(int apic, int oldid, int newid)
1301 return; /* Nothing to do */
1303 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1304 apic, oldid, newid);
1306 /* Swap physical APIC IDs in interrupt entries */
1307 for (x = 0; x < nintrs; x++) {
1308 if (io_apic_ints[x].dst_apic_id == oldid)
1309 io_apic_ints[x].dst_apic_id = newid;
1310 else if (io_apic_ints[x].dst_apic_id == newid)
1311 io_apic_ints[x].dst_apic_id = oldid;
1314 /* Swap physical APIC IDs in IO_TO_ID mappings */
1315 for (oapic = 0; oapic < mp_napics; oapic++)
1316 if (IO_TO_ID(oapic) == newid)
1319 if (oapic < mp_napics) {
1320 kprintf("Changing APIC ID for IO APIC #%d from "
1321 "%d to %d in MP table\n",
1322 oapic, newid, oldid);
1323 IO_TO_ID(oapic) = oldid;
1325 IO_TO_ID(apic) = newid;
1330 fix_id_to_io_mapping(void)
1334 for (x = 0; x < NAPICID; x++)
1337 for (x = 0; x <= mp_naps; x++)
1338 if (CPU_TO_ID(x) < NAPICID)
1339 ID_TO_IO(CPU_TO_ID(x)) = x;
1341 for (x = 0; x < mp_napics; x++)
1342 if (IO_TO_ID(x) < NAPICID)
1343 ID_TO_IO(IO_TO_ID(x)) = x;
1348 first_free_apic_id(void)
1352 for (freeid = 0; freeid < NAPICID; freeid++) {
1353 for (x = 0; x <= mp_naps; x++)
1354 if (CPU_TO_ID(x) == freeid)
1358 for (x = 0; x < mp_napics; x++)
1359 if (IO_TO_ID(x) == freeid)
1370 io_apic_id_acceptable(int apic, int id)
1372 int cpu; /* Logical CPU number */
1373 int oapic; /* Logical IO APIC number for other IO APIC */
1376 return 0; /* Out of range */
1378 for (cpu = 0; cpu <= mp_naps; cpu++)
1379 if (CPU_TO_ID(cpu) == id)
1380 return 0; /* Conflict with CPU */
1382 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1383 if (IO_TO_ID(oapic) == id)
1384 return 0; /* Conflict with other APIC */
1386 return 1; /* ID is acceptable for IO APIC */
1391 io_apic_find_int_entry(int apic, int pin)
1395 /* search each of the possible INTerrupt sources */
1396 for (x = 0; x < nintrs; ++x) {
1397 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1398 (pin == io_apic_ints[x].dst_apic_int))
1399 return (&io_apic_ints[x]);
1405 * parse an Intel MP specification table
1412 int apic; /* IO APIC unit number */
1413 int freeid; /* Free physical APIC ID */
1414 int physid; /* Current physical IO APIC ID */
1416 int bus_0 = 0; /* Stop GCC warning */
1417 int bus_pci = 0; /* Stop GCC warning */
1421 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1422 * did it wrong. The MP spec says that when more than 1 PCI bus
1423 * exists the BIOS must begin with bus entries for the PCI bus and use
1424 * actual PCI bus numbering. This implies that when only 1 PCI bus
1425 * exists the BIOS can choose to ignore this ordering, and indeed many
1426 * MP motherboards do ignore it. This causes a problem when the PCI
1427 * sub-system makes requests of the MP sub-system based on PCI bus
1428 * numbers. So here we look for the situation and renumber the
1429 * busses and associated INTs in an effort to "make it right".
1432 /* find bus 0, PCI bus, count the number of PCI busses */
1433 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1434 if (bus_data[x].bus_id == 0) {
1437 if (bus_data[x].bus_type == PCI) {
1443 * bus_0 == slot of bus with ID of 0
1444 * bus_pci == slot of last PCI bus encountered
1447 /* check the 1 PCI bus case for sanity */
1448 /* if it is number 0 all is well */
1449 if (num_pci_bus == 1 &&
1450 bus_data[bus_pci].bus_id != 0) {
1452 /* mis-numbered, swap with whichever bus uses slot 0 */
1454 /* swap the bus entry types */
1455 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1456 bus_data[bus_0].bus_type = PCI;
1458 /* swap each relavant INTerrupt entry */
1459 id = bus_data[bus_pci].bus_id;
1460 for (x = 0; x < nintrs; ++x) {
1461 if (io_apic_ints[x].src_bus_id == id) {
1462 io_apic_ints[x].src_bus_id = 0;
1464 else if (io_apic_ints[x].src_bus_id == 0) {
1465 io_apic_ints[x].src_bus_id = id;
1470 /* Assign IO APIC IDs.
1472 * First try the existing ID. If a conflict is detected, try
1473 * the ID in the MP table. If a conflict is still detected, find
1476 * We cannot use the ID_TO_IO table before all conflicts has been
1477 * resolved and the table has been corrected.
1479 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1481 /* First try to use the value set by the BIOS */
1482 physid = io_apic_get_id(apic);
1483 if (io_apic_id_acceptable(apic, physid)) {
1484 if (IO_TO_ID(apic) != physid)
1485 swap_apic_id(apic, IO_TO_ID(apic), physid);
1489 /* Then check if the value in the MP table is acceptable */
1490 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1493 /* Last resort, find a free APIC ID and use it */
1494 freeid = first_free_apic_id();
1495 if (freeid >= NAPICID)
1496 panic("No free physical APIC IDs found");
1498 if (io_apic_id_acceptable(apic, freeid)) {
1499 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1502 panic("Free physical APIC ID not usable");
1504 fix_id_to_io_mapping();
1506 /* detect and fix broken Compaq MP table */
1507 if (apic_int_type(0, 0) == -1) {
1508 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1509 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1510 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1511 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1512 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1513 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1515 } else if (apic_int_type(0, 0) == 0) {
1516 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1517 for (x = 0; x < nintrs; ++x)
1518 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1519 (0 == io_apic_ints[x].dst_apic_int)) {
1520 io_apic_ints[x].int_type = 3;
1521 io_apic_ints[x].int_vector = 0xff;
1527 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1528 * controllers universally come in pairs. If IRQ 14 is specified
1529 * as an ISA interrupt, then IRQ 15 had better be too.
1531 * [ Shuttle XPC / AMD Athlon X2 ]
1532 * The MPTable is missing an entry for IRQ 15. Note that the
1533 * ACPI table has an entry for both 14 and 15.
1535 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1536 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1537 io14 = io_apic_find_int_entry(0, 14);
1538 io_apic_ints[nintrs] = *io14;
1539 io_apic_ints[nintrs].src_bus_irq = 15;
1540 io_apic_ints[nintrs].dst_apic_int = 15;
1545 /* Assign low level interrupt handlers */
1547 setup_apic_irq_mapping(void)
1553 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1554 int_to_apicintpin[x].ioapic = -1;
1555 int_to_apicintpin[x].int_pin = 0;
1556 int_to_apicintpin[x].apic_address = NULL;
1557 int_to_apicintpin[x].redirindex = 0;
1559 /* Default to masked */
1560 int_to_apicintpin[x].flags = AIMI_FLAG_MASKED;
1563 /* First assign ISA/EISA interrupts */
1564 for (x = 0; x < nintrs; x++) {
1565 int_vector = io_apic_ints[x].src_bus_irq;
1566 if (int_vector < APIC_INTMAPSIZE &&
1567 io_apic_ints[x].int_vector == 0xff &&
1568 int_to_apicintpin[int_vector].ioapic == -1 &&
1569 (apic_int_is_bus_type(x, ISA) ||
1570 apic_int_is_bus_type(x, EISA)) &&
1571 io_apic_ints[x].int_type == 0) {
1572 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1573 io_apic_ints[x].dst_apic_int,
1578 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1579 for (x = 0; x < nintrs; x++) {
1580 if (io_apic_ints[x].dst_apic_int == 0 &&
1581 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1582 io_apic_ints[x].int_vector == 0xff &&
1583 int_to_apicintpin[0].ioapic == -1 &&
1584 io_apic_ints[x].int_type == 3) {
1585 assign_apic_irq(0, 0, 0);
1590 /* Assign PCI interrupts */
1591 for (x = 0; x < nintrs; ++x) {
1592 if (io_apic_ints[x].int_type == 0 &&
1593 io_apic_ints[x].int_vector == 0xff &&
1594 apic_int_is_bus_type(x, PCI))
1595 allocate_apic_irq(x);
1602 mp_set_cpuids(int cpu_id, int apic_id)
1604 CPU_TO_ID(cpu_id) = apic_id;
1605 ID_TO_CPU(apic_id) = cpu_id;
1609 processor_entry(const struct PROCENTRY *entry, int cpu)
1613 /* check for usability */
1614 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1617 /* check for BSP flag */
1618 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1619 mp_set_cpuids(0, entry->apic_id);
1620 return 0; /* its already been counted */
1623 /* add another AP to list, if less than max number of CPUs */
1624 else if (cpu < MAXCPU) {
1625 mp_set_cpuids(cpu, entry->apic_id);
1635 bus_entry(const struct BUSENTRY *entry, int bus)
1640 /* encode the name into an index */
1641 for (x = 0; x < 6; ++x) {
1642 if ((c = entry->bus_type[x]) == ' ')
1648 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1649 panic("unknown bus type: '%s'", name);
1651 bus_data[bus].bus_id = entry->bus_id;
1652 bus_data[bus].bus_type = x;
1658 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1660 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1663 IO_TO_ID(apic) = entry->apic_id;
1664 ID_TO_IO(entry->apic_id) = apic;
1670 lookup_bus_type(char *name)
1674 for (x = 0; x < MAX_BUSTYPE; ++x)
1675 if (strcmp(bus_type_table[x].name, name) == 0)
1676 return bus_type_table[x].type;
1678 return UNKNOWN_BUSTYPE;
1682 int_entry(const struct INTENTRY *entry, int intr)
1686 io_apic_ints[intr].int_type = entry->int_type;
1687 io_apic_ints[intr].int_flags = entry->int_flags;
1688 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1689 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1690 if (entry->dst_apic_id == 255) {
1691 /* This signal goes to all IO APICS. Select an IO APIC
1692 with sufficient number of interrupt pins */
1693 for (apic = 0; apic < mp_napics; apic++)
1694 if (((io_apic_read(apic, IOAPIC_VER) &
1695 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1696 entry->dst_apic_int)
1698 if (apic < mp_napics)
1699 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1701 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1703 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1704 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1710 apic_int_is_bus_type(int intr, int bus_type)
1714 for (bus = 0; bus < mp_nbusses; ++bus)
1715 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1716 && ((int) bus_data[bus].bus_type == bus_type))
1723 * Given a traditional ISA INT mask, return an APIC mask.
1726 isa_apic_mask(u_int isa_mask)
1731 #if defined(SKIP_IRQ15_REDIRECT)
1732 if (isa_mask == (1 << 15)) {
1733 kprintf("skipping ISA IRQ15 redirect\n");
1736 #endif /* SKIP_IRQ15_REDIRECT */
1738 isa_irq = ffs(isa_mask); /* find its bit position */
1739 if (isa_irq == 0) /* doesn't exist */
1741 --isa_irq; /* make it zero based */
1743 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1747 return (1 << apic_pin); /* convert pin# to a mask */
1751 * Determine which APIC pin an ISA/EISA INT is attached to.
1753 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1754 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1755 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1756 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1758 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1760 isa_apic_irq(int isa_irq)
1764 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1765 if (INTTYPE(intr) == 0) { /* standard INT */
1766 if (SRCBUSIRQ(intr) == isa_irq) {
1767 if (apic_int_is_bus_type(intr, ISA) ||
1768 apic_int_is_bus_type(intr, EISA)) {
1769 if (INTIRQ(intr) == 0xff)
1770 return -1; /* unassigned */
1771 return INTIRQ(intr); /* found */
1776 return -1; /* NOT found */
1781 * Determine which APIC pin a PCI INT is attached to.
1783 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1784 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1785 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1787 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1791 --pciInt; /* zero based */
1793 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1794 if ((INTTYPE(intr) == 0) /* standard INT */
1795 && (SRCBUSID(intr) == pciBus)
1796 && (SRCBUSDEVICE(intr) == pciDevice)
1797 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1798 if (apic_int_is_bus_type(intr, PCI)) {
1799 if (INTIRQ(intr) == 0xff) {
1800 kprintf("IOAPIC: pci_apic_irq() "
1802 return -1; /* unassigned */
1804 return INTIRQ(intr); /* exact match */
1809 return -1; /* NOT found */
1813 next_apic_irq(int irq)
1820 for (intr = 0; intr < nintrs; intr++) {
1821 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1823 bus = SRCBUSID(intr);
1824 bustype = apic_bus_type(bus);
1825 if (bustype != ISA &&
1831 if (intr >= nintrs) {
1834 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1835 if (INTTYPE(ointr) != 0)
1837 if (bus != SRCBUSID(ointr))
1839 if (bustype == PCI) {
1840 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1842 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1845 if (bustype == ISA || bustype == EISA) {
1846 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1849 if (INTPIN(intr) == INTPIN(ointr))
1853 if (ointr >= nintrs) {
1856 return INTIRQ(ointr);
1871 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1874 * Exactly what this means is unclear at this point. It is a solution
1875 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1876 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1877 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1881 undirect_isa_irq(int rirq)
1885 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1886 /** FIXME: tickle the MB redirector chip */
1890 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1897 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1900 undirect_pci_irq(int rirq)
1904 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1906 /** FIXME: tickle the MB redirector chip */
1910 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1920 * given a bus ID, return:
1921 * the bus type if found
1925 apic_bus_type(int id)
1929 for (x = 0; x < mp_nbusses; ++x)
1930 if (bus_data[x].bus_id == id)
1931 return bus_data[x].bus_type;
1937 * given a LOGICAL APIC# and pin#, return:
1938 * the associated src bus ID if found
1942 apic_src_bus_id(int apic, int pin)
1946 /* search each of the possible INTerrupt sources */
1947 for (x = 0; x < nintrs; ++x)
1948 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1949 (pin == io_apic_ints[x].dst_apic_int))
1950 return (io_apic_ints[x].src_bus_id);
1952 return -1; /* NOT found */
1956 * given a LOGICAL APIC# and pin#, return:
1957 * the associated src bus IRQ if found
1961 apic_src_bus_irq(int apic, int pin)
1965 for (x = 0; x < nintrs; x++)
1966 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1967 (pin == io_apic_ints[x].dst_apic_int))
1968 return (io_apic_ints[x].src_bus_irq);
1970 return -1; /* NOT found */
1975 * given a LOGICAL APIC# and pin#, return:
1976 * the associated INTerrupt type if found
1980 apic_int_type(int apic, int pin)
1984 /* search each of the possible INTerrupt sources */
1985 for (x = 0; x < nintrs; ++x) {
1986 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1987 (pin == io_apic_ints[x].dst_apic_int))
1988 return (io_apic_ints[x].int_type);
1990 return -1; /* NOT found */
1994 * Return the IRQ associated with an APIC pin
1997 apic_irq(int apic, int pin)
2002 for (x = 0; x < nintrs; ++x) {
2003 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2004 (pin == io_apic_ints[x].dst_apic_int)) {
2005 res = io_apic_ints[x].int_vector;
2008 if (apic != int_to_apicintpin[res].ioapic)
2009 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2010 if (pin != int_to_apicintpin[res].int_pin)
2011 panic("apic_irq inconsistent table (2)");
2020 * given a LOGICAL APIC# and pin#, return:
2021 * the associated trigger mode if found
2025 apic_trigger(int apic, int pin)
2029 /* search each of the possible INTerrupt sources */
2030 for (x = 0; x < nintrs; ++x)
2031 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2032 (pin == io_apic_ints[x].dst_apic_int))
2033 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2035 return -1; /* NOT found */
2040 * given a LOGICAL APIC# and pin#, return:
2041 * the associated 'active' level if found
2045 apic_polarity(int apic, int pin)
2049 /* search each of the possible INTerrupt sources */
2050 for (x = 0; x < nintrs; ++x)
2051 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2052 (pin == io_apic_ints[x].dst_apic_int))
2053 return (io_apic_ints[x].int_flags & 0x03);
2055 return -1; /* NOT found */
2059 * set data according to MP defaults
2060 * FIXME: probably not complete yet...
2063 mptable_default(int type)
2069 kprintf(" MP default config type: %d\n", type);
2072 kprintf(" bus: ISA, APIC: 82489DX\n");
2075 kprintf(" bus: EISA, APIC: 82489DX\n");
2078 kprintf(" bus: EISA, APIC: 82489DX\n");
2081 kprintf(" bus: MCA, APIC: 82489DX\n");
2084 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2087 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2090 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2093 kprintf(" future type\n");
2099 /* one and only IO APIC */
2100 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2103 * sanity check, refer to MP spec section 3.6.6, last paragraph
2104 * necessary as some hardware isn't properly setting up the IO APIC
2106 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2107 if (io_apic_id != 2) {
2109 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2110 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2111 io_apic_set_id(0, 2);
2114 IO_TO_ID(0) = io_apic_id;
2115 ID_TO_IO(io_apic_id) = 0;
2117 /* fill out bus entries */
2126 bus_data[0].bus_id = default_data[type - 1][1];
2127 bus_data[0].bus_type = default_data[type - 1][2];
2128 bus_data[1].bus_id = default_data[type - 1][3];
2129 bus_data[1].bus_type = default_data[type - 1][4];
2132 /* case 4: case 7: MCA NOT supported */
2133 default: /* illegal/reserved */
2134 panic("BAD default MP config: %d", type);
2138 /* general cases from MP v1.4, table 5-2 */
2139 for (pin = 0; pin < 16; ++pin) {
2140 io_apic_ints[pin].int_type = 0;
2141 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2142 io_apic_ints[pin].src_bus_id = 0;
2143 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2144 io_apic_ints[pin].dst_apic_id = io_apic_id;
2145 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2148 /* special cases from MP v1.4, table 5-2 */
2150 io_apic_ints[2].int_type = 0xff; /* N/C */
2151 io_apic_ints[13].int_type = 0xff; /* N/C */
2152 #if !defined(APIC_MIXED_MODE)
2154 panic("sorry, can't support type 2 default yet");
2155 #endif /* APIC_MIXED_MODE */
2158 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2161 io_apic_ints[0].int_type = 0xff; /* N/C */
2163 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2166 #endif /* APIC_IO */
2169 * Map a physical memory address representing I/O into KVA. The I/O
2170 * block is assumed not to cross a page boundary.
2173 permanent_io_mapping(vm_paddr_t pa)
2175 KKASSERT(pa < 0x100000000LL);
2177 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2181 * start each AP in our list
2184 start_all_aps(u_int boot_addr)
2186 vm_offset_t va = boot_address + KERNBASE;
2187 u_int64_t *pt4, *pt3, *pt2;
2193 u_char mpbiosreason;
2194 u_long mpbioswarmvec;
2195 struct mdglobaldata *gd;
2196 struct privatespace *ps;
2198 POSTCODE(START_ALL_APS_POST);
2200 /* Initialize BSP's local APIC */
2201 apic_initialize(TRUE);
2203 /* install the AP 1st level boot code */
2204 pmap_kenter(va, boot_address);
2205 cpu_invlpg((void *)va); /* JG XXX */
2206 bcopy(mptramp_start, (void *)va, bootMP_size);
2208 /* Locate the page tables, they'll be below the trampoline */
2209 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2210 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2211 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2213 /* Create the initial 1GB replicated page tables */
2214 for (i = 0; i < 512; i++) {
2215 /* Each slot of the level 4 pages points to the same level 3 page */
2216 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2217 pt4[i] |= PG_V | PG_RW | PG_U;
2219 /* Each slot of the level 3 pages points to the same level 2 page */
2220 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2221 pt3[i] |= PG_V | PG_RW | PG_U;
2223 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2224 pt2[i] = i * (2 * 1024 * 1024);
2225 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2228 /* save the current value of the warm-start vector */
2229 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2230 outb(CMOS_REG, BIOS_RESET);
2231 mpbiosreason = inb(CMOS_DATA);
2233 /* setup a vector to our boot code */
2234 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2235 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2236 outb(CMOS_REG, BIOS_RESET);
2237 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2240 * If we have a TSC we can figure out the SMI interrupt rate.
2241 * The SMI does not necessarily use a constant rate. Spend
2242 * up to 250ms trying to figure it out.
2245 if (cpu_feature & CPUID_TSC) {
2246 set_apic_timer(275000);
2247 smilast = read_apic_timer();
2248 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2249 smicount = smitest();
2250 if (smibest == 0 || smilast - smicount < smibest)
2251 smibest = smilast - smicount;
2254 if (smibest > 250000)
2257 smibest = smibest * (int64_t)1000000 /
2258 get_apic_timer_frequency();
2262 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2263 1000000 / smibest, smibest);
2266 for (x = 1; x <= mp_naps; ++x) {
2268 /* This is a bit verbose, it will go away soon. */
2270 /* first page of AP's private space */
2271 pg = x * x86_64_btop(sizeof(struct privatespace));
2273 /* allocate new private data page(s) */
2274 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2275 MDGLOBALDATA_BASEALLOC_SIZE);
2277 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2278 bzero(gd, sizeof(*gd));
2279 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2281 /* prime data page for it to use */
2282 mi_gdinit(&gd->mi, x);
2284 gd->gd_CMAP1 = &SMPpt[pg + 0];
2285 gd->gd_CMAP2 = &SMPpt[pg + 1];
2286 gd->gd_CMAP3 = &SMPpt[pg + 2];
2287 gd->gd_PMAP1 = &SMPpt[pg + 3];
2288 gd->gd_CADDR1 = ps->CPAGE1;
2289 gd->gd_CADDR2 = ps->CPAGE2;
2290 gd->gd_CADDR3 = ps->CPAGE3;
2291 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2292 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2293 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2295 /* setup a vector to our boot code */
2296 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2297 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2298 outb(CMOS_REG, BIOS_RESET);
2299 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2302 * Setup the AP boot stack
2304 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2307 /* attempt to start the Application Processor */
2308 CHECK_INIT(99); /* setup checkpoints */
2309 if (!start_ap(gd, boot_addr, smibest)) {
2310 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2311 CHECK_PRINT("trace"); /* show checkpoints */
2312 /* better panic as the AP may be running loose */
2313 kprintf("panic y/n? [y] ");
2314 if (cngetc() != 'n')
2317 CHECK_PRINT("trace"); /* show checkpoints */
2319 /* record its version info */
2320 cpu_apic_versions[x] = cpu_apic_versions[0];
2323 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2326 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2327 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2330 ncpus2_shift = shift;
2331 ncpus2 = 1 << shift;
2332 ncpus2_mask = ncpus2 - 1;
2334 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2335 if ((1 << shift) < ncpus)
2337 ncpus_fit = 1 << shift;
2338 ncpus_fit_mask = ncpus_fit - 1;
2340 /* build our map of 'other' CPUs */
2341 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2342 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2343 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2345 /* fill in our (BSP) APIC version */
2346 cpu_apic_versions[0] = lapic->version;
2348 /* restore the warmstart vector */
2349 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2350 outb(CMOS_REG, BIOS_RESET);
2351 outb(CMOS_DATA, mpbiosreason);
2354 * NOTE! The idlestack for the BSP was setup by locore. Finish
2355 * up, clean out the P==V mapping we did earlier.
2359 /* number of APs actually started */
2365 * load the 1st level AP boot code into base memory.
2368 /* targets for relocation */
2369 extern void bigJump(void);
2370 extern void bootCodeSeg(void);
2371 extern void bootDataSeg(void);
2372 extern void MPentry(void);
2373 extern u_int MP_GDT;
2374 extern u_int mp_gdtbase;
2379 install_ap_tramp(u_int boot_addr)
2382 int size = *(int *) ((u_long) & bootMP_size);
2383 u_char *src = (u_char *) ((u_long) bootMP);
2384 u_char *dst = (u_char *) boot_addr + KERNBASE;
2385 u_int boot_base = (u_int) bootMP;
2390 POSTCODE(INSTALL_AP_TRAMP_POST);
2392 for (x = 0; x < size; ++x)
2396 * modify addresses in code we just moved to basemem. unfortunately we
2397 * need fairly detailed info about mpboot.s for this to work. changes
2398 * to mpboot.s might require changes here.
2401 /* boot code is located in KERNEL space */
2402 dst = (u_char *) boot_addr + KERNBASE;
2404 /* modify the lgdt arg */
2405 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2406 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2408 /* modify the ljmp target for MPentry() */
2409 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2410 *dst32 = ((u_int) MPentry - KERNBASE);
2412 /* modify the target for boot code segment */
2413 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2414 dst8 = (u_int8_t *) (dst16 + 1);
2415 *dst16 = (u_int) boot_addr & 0xffff;
2416 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2418 /* modify the target for boot data segment */
2419 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2420 dst8 = (u_int8_t *) (dst16 + 1);
2421 *dst16 = (u_int) boot_addr & 0xffff;
2422 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2428 * This function starts the AP (application processor) identified
2429 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2430 * to accomplish this. This is necessary because of the nuances
2431 * of the different hardware we might encounter. It ain't pretty,
2432 * but it seems to work.
2434 * NOTE: eventually an AP gets to ap_init(), which is called just
2435 * before the AP goes into the LWKT scheduler's idle loop.
2438 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2442 u_long icr_lo, icr_hi;
2444 POSTCODE(START_AP_POST);
2446 /* get the PHYSICAL APIC ID# */
2447 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2449 /* calculate the vector */
2450 vector = (boot_addr >> 12) & 0xff;
2452 /* We don't want anything interfering */
2455 /* Make sure the target cpu sees everything */
2459 * Try to detect when a SMI has occurred, wait up to 200ms.
2461 * If a SMI occurs during an AP reset but before we issue
2462 * the STARTUP command, the AP may brick. To work around
2463 * this problem we hold off doing the AP startup until
2464 * after we have detected the SMI. Hopefully another SMI
2465 * will not occur before we finish the AP startup.
2467 * Retries don't seem to help. SMIs have a window of opportunity
2468 * and if USB->legacy keyboard emulation is enabled in the BIOS
2469 * the interrupt rate can be quite high.
2471 * NOTE: Don't worry about the L1 cache load, it might bloat
2472 * ldelta a little but ndelta will be so huge when the SMI
2473 * occurs the detection logic will still work fine.
2476 set_apic_timer(200000);
2481 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2482 * and running the target CPU. OR this INIT IPI might be latched (P5
2483 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2486 * see apic/apicreg.h for icr bit definitions.
2488 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2492 * Setup the address for the target AP. We can setup
2493 * icr_hi once and then just trigger operations with
2496 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2497 icr_hi |= (physical_cpu << 24);
2498 icr_lo = lapic->icr_lo & 0xfff00000;
2499 lapic->icr_hi = icr_hi;
2502 * Do an INIT IPI: assert RESET
2504 * Use edge triggered mode to assert INIT
2506 lapic->icr_lo = icr_lo | 0x00004500;
2507 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2511 * The spec calls for a 10ms delay but we may have to use a
2512 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2513 * interrupt. We have other loops here too and dividing by 2
2514 * doesn't seem to be enough even after subtracting 350us,
2515 * so we divide by 4.
2517 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2518 * interrupt was detected we use the full 10ms.
2522 else if (smibest < 150 * 4 + 350)
2524 else if ((smibest - 350) / 4 < 10000)
2525 u_sleep((smibest - 350) / 4);
2530 * Do an INIT IPI: deassert RESET
2532 * Use level triggered mode to deassert. It is unclear
2533 * why we need to do this.
2535 lapic->icr_lo = icr_lo | 0x00008500;
2536 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2538 u_sleep(150); /* wait 150us */
2541 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2542 * latched, (P5 bug) this 1st STARTUP would then terminate
2543 * immediately, and the previously started INIT IPI would continue. OR
2544 * the previous INIT IPI has already run. and this STARTUP IPI will
2545 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2548 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2549 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2551 u_sleep(200); /* wait ~200uS */
2554 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2555 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2556 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2557 * recognized after hardware RESET or INIT IPI.
2559 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2560 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2563 /* Resume normal operation */
2566 /* wait for it to start, see ap_init() */
2567 set_apic_timer(5000000);/* == 5 seconds */
2568 while (read_apic_timer()) {
2569 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2570 return 1; /* return SUCCESS */
2573 return 0; /* return FAILURE */
2588 while (read_apic_timer()) {
2590 for (count = 0; count < 100; ++count)
2591 ntsc = rdtsc(); /* force loop to occur */
2593 ndelta = ntsc - ltsc;
2594 if (ldelta > ndelta)
2596 if (ndelta > ldelta * 2)
2599 ldelta = ntsc - ltsc;
2602 return(read_apic_timer());
2606 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2608 * If for some reason we were unable to start all cpus we cannot safely
2609 * use broadcast IPIs.
2615 if (smp_startup_mask == smp_active_mask) {
2616 all_but_self_ipi(XINVLTLB_OFFSET);
2618 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2619 APIC_DELMODE_FIXED);
2625 * When called the executing CPU will send an IPI to all other CPUs
2626 * requesting that they halt execution.
2628 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2630 * - Signals all CPUs in map to stop.
2631 * - Waits for each to stop.
2638 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2639 * from executing at same time.
2642 stop_cpus(u_int map)
2644 map &= smp_active_mask;
2646 /* send the Xcpustop IPI to all CPUs in map */
2647 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2649 while ((stopped_cpus & map) != map)
2657 * Called by a CPU to restart stopped CPUs.
2659 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2661 * - Signals all CPUs in map to restart.
2662 * - Waits for each to restart.
2670 restart_cpus(u_int map)
2672 /* signal other cpus to restart */
2673 started_cpus = map & smp_active_mask;
2675 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2682 * This is called once the mpboot code has gotten us properly relocated
2683 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2684 * and when it returns the scheduler will call the real cpu_idle() main
2685 * loop for the idlethread. Interrupts are disabled on entry and should
2686 * remain disabled at return.
2694 * Adjust smp_startup_mask to signal the BSP that we have started
2695 * up successfully. Note that we do not yet hold the BGL. The BSP
2696 * is waiting for our signal.
2698 * We can't set our bit in smp_active_mask yet because we are holding
2699 * interrupts physically disabled and remote cpus could deadlock
2700 * trying to send us an IPI.
2702 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2706 * Interlock for finalization. Wait until mp_finish is non-zero,
2707 * then get the MP lock.
2709 * Note: We are in a critical section.
2711 * Note: We have to synchronize td_mpcount to our desired MP state
2712 * before calling cpu_try_mplock().
2714 * Note: we are the idle thread, we can only spin.
2716 * Note: The load fence is memory volatile and prevents the compiler
2717 * from improperly caching mp_finish, and the cpu from improperly
2720 while (mp_finish == 0)
2722 ++curthread->td_mpcount;
2723 while (cpu_try_mplock() == 0)
2726 if (cpu_feature & CPUID_TSC) {
2728 * The BSP is constantly updating tsc0_offset, figure out the
2729 * relative difference to synchronize ktrdump.
2731 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2734 /* BSP may have changed PTD while we're waiting for the lock */
2737 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2741 /* Build our map of 'other' CPUs. */
2742 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2744 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2746 /* A quick check from sanity claus */
2747 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2748 if (mycpu->gd_cpuid != apic_id) {
2749 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2750 kprintf("SMP: apic_id = %d\n", apic_id);
2752 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2754 panic("cpuid mismatch! boom!!");
2757 /* Initialize AP's local APIC for irq's */
2758 apic_initialize(FALSE);
2760 /* Set memory range attributes for this CPU to match the BSP */
2761 mem_range_AP_init();
2764 * Once we go active we must process any IPIQ messages that may
2765 * have been queued, because no actual IPI will occur until we
2766 * set our bit in the smp_active_mask. If we don't the IPI
2767 * message interlock could be left set which would also prevent
2770 * The idle loop doesn't expect the BGL to be held and while
2771 * lwkt_switch() normally cleans things up this is a special case
2772 * because we returning almost directly into the idle loop.
2774 * The idle thread is never placed on the runq, make sure
2775 * nothing we've done put it there.
2777 KKASSERT(curthread->td_mpcount == 1);
2778 smp_active_mask |= 1 << mycpu->gd_cpuid;
2781 * Enable interrupts here. idle_restore will also do it, but
2782 * doing it here lets us clean up any strays that got posted to
2783 * the CPU during the AP boot while we are still in a critical
2786 __asm __volatile("sti; pause; pause"::);
2787 mdcpu->gd_fpending = 0;
2789 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2790 lwkt_process_ipiq();
2793 * Releasing the mp lock lets the BSP finish up the SMP init
2796 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2800 * Get SMP fully working before we start initializing devices.
2808 kprintf("Finish MP startup\n");
2809 if (cpu_feature & CPUID_TSC)
2810 tsc0_offset = rdtsc();
2813 while (smp_active_mask != smp_startup_mask) {
2815 if (cpu_feature & CPUID_TSC)
2816 tsc0_offset = rdtsc();
2818 while (try_mplock() == 0)
2821 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2824 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2827 cpu_send_ipiq(int dcpu)
2829 if ((1 << dcpu) & smp_active_mask)
2830 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2833 #if 0 /* single_apic_ipi_passive() not working yet */
2835 * Returns 0 on failure, 1 on success
2838 cpu_send_ipiq_passive(int dcpu)
2841 if ((1 << dcpu) & smp_active_mask) {
2842 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2843 APIC_DELMODE_FIXED);
2849 struct mptable_lapic_cbarg1 {
2852 u_int ht_apicid_mask;
2856 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2858 const struct PROCENTRY *ent;
2859 struct mptable_lapic_cbarg1 *arg = xarg;
2865 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2869 if (ent->apic_id < 32) {
2870 arg->ht_apicid_mask |= 1 << ent->apic_id;
2871 } else if (arg->ht_fixup) {
2872 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2878 struct mptable_lapic_cbarg2 {
2885 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2887 const struct PROCENTRY *ent;
2888 struct mptable_lapic_cbarg2 *arg = xarg;
2894 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2895 KKASSERT(!arg->found_bsp);
2899 if (processor_entry(ent, arg->cpu))
2902 if (arg->logical_cpus) {
2903 struct PROCENTRY proc;
2907 * Create fake mptable processor entries
2908 * and feed them to processor_entry() to
2909 * enumerate the logical CPUs.
2911 bzero(&proc, sizeof(proc));
2913 proc.cpu_flags = PROCENTRY_FLAG_EN;
2914 proc.apic_id = ent->apic_id;
2916 for (i = 1; i < arg->logical_cpus; i++) {
2918 processor_entry(&proc, arg->cpu);
2926 mptable_imcr(struct mptable_pos *mpt)
2928 /* record whether PIC or virtual-wire mode */
2929 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2930 mpt->mp_fps->mpfb2 & 0x80);
2933 struct mptable_lapic_enumerator {
2934 struct lapic_enumerator enumerator;
2935 vm_paddr_t mpfps_paddr;
2939 mptable_lapic_default(void)
2941 int ap_apicid, bsp_apicid;
2943 mp_naps = 1; /* exclude BSP */
2945 /* Map local apic before the id field is accessed */
2946 lapic_init(DEFAULT_APIC_BASE);
2948 bsp_apicid = APIC_ID(lapic->id);
2949 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2952 mp_set_cpuids(0, bsp_apicid);
2953 /* one and only AP */
2954 mp_set_cpuids(1, ap_apicid);
2960 * ID_TO_CPU(N), APIC ID to logical CPU table
2961 * CPU_TO_ID(N), logical CPU to APIC ID table
2964 mptable_lapic_enumerate(struct lapic_enumerator *e)
2966 struct mptable_pos mpt;
2967 struct mptable_lapic_cbarg1 arg1;
2968 struct mptable_lapic_cbarg2 arg2;
2970 int error, logical_cpus = 0;
2971 vm_offset_t lapic_addr;
2972 vm_paddr_t mpfps_paddr;
2974 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
2975 KKASSERT(mpfps_paddr != 0);
2977 error = mptable_map(&mpt, mpfps_paddr);
2979 panic("mptable_lapic_enumerate mptable_map failed\n");
2981 KKASSERT(mpt.mp_fps != NULL);
2984 * Check for use of 'default' configuration
2986 if (mpt.mp_fps->mpfb1 != 0) {
2987 mptable_lapic_default();
2988 mptable_unmap(&mpt);
2993 KKASSERT(cth != NULL);
2995 /* Save local apic address */
2996 lapic_addr = (vm_offset_t)cth->apic_address;
2997 KKASSERT(lapic_addr != 0);
3000 * Find out how many CPUs do we have
3002 bzero(&arg1, sizeof(arg1));
3003 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3005 error = mptable_iterate_entries(cth,
3006 mptable_lapic_pass1_callback, &arg1);
3008 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3009 KKASSERT(arg1.cpu_count != 0);
3011 /* See if we need to fixup HT logical CPUs. */
3012 if (arg1.ht_fixup) {
3013 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3015 if (logical_cpus != 0)
3016 arg1.cpu_count *= logical_cpus;
3018 mp_naps = arg1.cpu_count;
3020 /* Qualify the numbers again, after possible HT fixup */
3021 if (mp_naps > MAXCPU) {
3022 kprintf("Warning: only using %d of %d available CPUs!\n",
3027 --mp_naps; /* subtract the BSP */
3030 * Link logical CPU id to local apic id
3032 bzero(&arg2, sizeof(arg2));
3034 arg2.logical_cpus = logical_cpus;
3036 error = mptable_iterate_entries(cth,
3037 mptable_lapic_pass2_callback, &arg2);
3039 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3040 KKASSERT(arg2.found_bsp);
3042 /* Map local apic */
3043 lapic_init(lapic_addr);
3045 mptable_unmap(&mpt);
3049 mptable_lapic_probe(struct lapic_enumerator *e)
3051 vm_paddr_t mpfps_paddr;
3053 mpfps_paddr = mptable_probe();
3054 if (mpfps_paddr == 0)
3057 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3061 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3063 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3064 .lapic_probe = mptable_lapic_probe,
3065 .lapic_enumerate = mptable_lapic_enumerate
3070 mptable_apic_register(void)
3072 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3074 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);