2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
50 #include "opt_msgbuf.h"
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/sysproto.h>
56 #include <sys/signalvar.h>
57 #include <sys/kernel.h>
58 #include <sys/linker.h>
59 #include <sys/malloc.h>
63 #include <sys/reboot.h>
65 #include <sys/msgbuf.h>
66 #include <sys/sysent.h>
67 #include <sys/sysctl.h>
68 #include <sys/vmmeter.h>
70 #include <sys/usched.h>
73 #include <sys/ctype.h>
74 #include <sys/serialize.h>
75 #include <sys/systimer.h>
78 #include <vm/vm_param.h>
80 #include <vm/vm_kern.h>
81 #include <vm/vm_object.h>
82 #include <vm/vm_page.h>
83 #include <vm/vm_map.h>
84 #include <vm/vm_pager.h>
85 #include <vm/vm_extern.h>
87 #include <sys/thread2.h>
88 #include <sys/mplock2.h>
89 #include <sys/mutex2.h>
97 #include <machine/cpu.h>
98 #include <machine/clock.h>
99 #include <machine/specialreg.h>
101 #include <machine/bootinfo.h>
103 #include <machine/md_var.h>
104 #include <machine/metadata.h>
105 #include <machine/pc/bios.h>
106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
107 #include <machine/globaldata.h> /* CPU_prvspace */
108 #include <machine/smp.h>
110 #include <machine/perfmon.h>
112 #include <machine/cputypes.h>
113 #include <machine/intr_machdep.h>
116 #include <bus/isa/isa_device.h>
118 #include <machine_base/isa/isa_intr.h>
119 #include <bus/isa/rtc.h>
120 #include <sys/random.h>
121 #include <sys/ptrace.h>
122 #include <machine/sigframe.h>
124 #include <sys/machintr.h>
125 #include <machine_base/icu/icu_abi.h>
126 #include <machine_base/icu/elcr_var.h>
127 #include <machine_base/apic/lapic.h>
128 #include <machine_base/apic/ioapic.h>
129 #include <machine_base/apic/ioapic_abi.h>
130 #include <machine/mptable.h>
132 #define PHYSMAP_ENTRIES 10
134 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
136 extern void printcpuinfo(void); /* XXX header file */
137 extern void identify_cpu(void);
139 extern void finishidentcpu(void);
141 extern void panicifcpuunsupported(void);
143 static void cpu_startup(void *);
144 static void pic_finish(void *);
145 static void cpu_finish(void *);
147 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
148 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
150 extern void ffs_rawread_setup(void);
151 #endif /* DIRECTIO */
152 static void init_locks(void);
154 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
155 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
156 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
159 extern vm_offset_t ksym_start, ksym_end;
162 struct privatespace CPU_prvspace_bsp __aligned(4096);
163 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp };
165 int _udatasel, _ucodesel, _ucode32sel;
167 int64_t tsc_offsets[MAXCPU];
169 static int cpu_mwait_halt; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
171 #if defined(SWTCH_OPTIM_STATS)
172 extern int swtch_optim_stats;
173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
174 CTLFLAG_RD, &swtch_optim_stats, 0, "");
175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
176 CTLFLAG_RD, &tlb_flush_count, 0, "");
178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
179 CTLFLAG_RD, &cpu_mwait_halt, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
181 "monitor/mwait target state");
183 #define CPU_MWAIT_C1 1
184 #define CPU_MWAIT_C2 2
185 #define CPU_MWAIT_C3 3
186 #define CPU_MWAIT_CX_MAX 8
188 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
189 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
191 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features");
192 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
194 struct cpu_mwait_cx {
197 struct sysctl_ctx_list sysctl_ctx;
198 struct sysctl_oid *sysctl_tree;
200 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
201 static char cpu_mwait_cx_supported[256];
203 static int cpu_mwait_c1_hints_cnt;
204 static int cpu_mwait_hints_cnt;
205 static int *cpu_mwait_hints;
207 static int cpu_mwait_deep_hints_cnt;
208 static int *cpu_mwait_deep_hints;
210 #define CPU_IDLE_REPEAT_DEFAULT 750
212 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
213 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
214 static u_int cpu_mwait_repeat_shift = 1;
216 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
217 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
219 static int cpu_mwait_c3_preamble =
220 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
221 CPU_MWAIT_C3_PREAMBLE_BM_STS;
223 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
224 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
226 static struct lwkt_serialize cpu_mwait_cx_slize = LWKT_SERIALIZE_INITIALIZER;
227 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
229 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
230 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
232 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
233 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
234 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
235 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
236 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
237 &cpu_mwait_repeat_shift, 0, "");
241 u_long ebda_addr = 0;
243 int imcr_present = 0;
245 int naps = 0; /* # of Applications processors */
248 struct mtx dt_lock; /* lock for GDT and LDT */
251 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
253 u_long pmem = ctob(physmem);
255 int error = sysctl_handle_long(oidp, &pmem, 0, req);
259 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
260 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
263 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
265 int error = sysctl_handle_int(oidp, 0,
266 ctob(physmem - vmstats.v_wire_count), req);
270 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
271 0, 0, sysctl_hw_usermem, "IU", "");
274 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
276 int error = sysctl_handle_int(oidp, 0,
277 x86_64_btop(avail_end - avail_start), req);
281 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
282 0, 0, sysctl_hw_availpages, "I", "");
288 * The number of PHYSMAP entries must be one less than the number of
289 * PHYSSEG entries because the PHYSMAP entry that spans the largest
290 * physical address that is accessible by ISA DMA is split into two
293 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
295 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
296 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
298 /* must be 2 less so 0 0 can signal end of chunks */
299 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
300 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
302 static vm_offset_t buffer_sva, buffer_eva;
303 vm_offset_t clean_sva, clean_eva;
304 static vm_offset_t pager_sva, pager_eva;
305 static struct trapframe proc0_tf;
308 cpu_startup(void *dummy)
312 vm_offset_t firstaddr;
315 * Good {morning,afternoon,evening,night}.
317 kprintf("%s", version);
320 panicifcpuunsupported();
324 kprintf("real memory = %ju (%ju MB)\n",
326 (intmax_t)Realmem / 1024 / 1024);
328 * Display any holes after the first chunk of extended memory.
333 kprintf("Physical memory chunk(s):\n");
334 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
335 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
337 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
338 (intmax_t)phys_avail[indx],
339 (intmax_t)phys_avail[indx + 1] - 1,
341 (intmax_t)(size1 / PAGE_SIZE));
346 * Allocate space for system data structures.
347 * The first available kernel virtual address is in "v".
348 * As pages of kernel virtual memory are allocated, "v" is incremented.
349 * As pages of memory are allocated and cleared,
350 * "firstaddr" is incremented.
351 * An index into the kernel page table corresponding to the
352 * virtual memory address maintained in "v" is kept in "mapaddr".
356 * Make two passes. The first pass calculates how much memory is
357 * needed and allocates it. The second pass assigns virtual
358 * addresses to the various data structures.
362 v = (caddr_t)firstaddr;
364 #define valloc(name, type, num) \
365 (name) = (type *)v; v = (caddr_t)((name)+(num))
366 #define valloclim(name, type, num, lim) \
367 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
370 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
371 * For the first 64MB of ram nominally allocate sufficient buffers to
372 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
373 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
374 * the buffer cache we limit the eventual kva reservation to
377 * factor represents the 1/4 x ram conversion.
380 long factor = 4 * BKVASIZE / 1024;
381 long kbytes = physmem * (PAGE_SIZE / 1024);
385 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
387 nbuf += (kbytes - 65536) * 2 / (factor * 5);
388 if (maxbcache && nbuf > maxbcache / BKVASIZE)
389 nbuf = maxbcache / BKVASIZE;
393 * Do not allow the buffer_map to be more then 1/2 the size of the
396 if (nbuf > (virtual_end - virtual_start +
397 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
398 nbuf = (virtual_end - virtual_start +
399 virtual2_end - virtual2_start) / (BKVASIZE * 2);
400 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
404 * Do not allow the buffer_map to use more than 50% of available
405 * physical-equivalent memory. Since the VM pages which back
406 * individual buffers are typically wired, having too many bufs
407 * can prevent the system from paging properly.
409 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
410 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
411 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
415 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
416 * the valloc space which is just the virtual_end - virtual_start
417 * section. We use valloc() to allocate the buf header array.
419 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
420 nbuf = (virtual_end - virtual_start) /
421 sizeof(struct buf) / 2;
422 kprintf("Warning: nbufs capped at %ld due to valloc "
423 "considerations", nbuf);
426 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
428 if (nswbuf < NSWBUF_MIN)
435 valloc(swbuf, struct buf, nswbuf);
436 valloc(buf, struct buf, nbuf);
439 * End of first pass, size has been calculated so allocate memory
441 if (firstaddr == 0) {
442 size = (vm_size_t)(v - firstaddr);
443 firstaddr = kmem_alloc(&kernel_map, round_page(size));
445 panic("startup: no room for tables");
450 * End of second pass, addresses have been assigned
452 * nbuf is an int, make sure we don't overflow the field.
454 * On 64-bit systems we always reserve maximal allocations for
455 * buffer cache buffers and there are no fragmentation issues,
456 * so the KVA segment does not have to be excessively oversized.
458 if ((vm_size_t)(v - firstaddr) != size)
459 panic("startup: table size inconsistency");
461 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
462 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
463 (nswbuf * MAXPHYS) + pager_map_size);
464 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
465 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
466 buffer_map.system_map = 1;
467 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
468 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
469 pager_map.system_map = 1;
471 #if defined(USERCONFIG)
473 cninit(); /* the preferred console may have changed */
476 kprintf("avail memory = %ju (%ju MB)\n",
477 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
478 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
482 struct cpu_idle_stat {
488 u_long mwait_cx[CPU_MWAIT_CX_MAX];
491 #define CPU_IDLE_STAT_HALT -1
492 #define CPU_IDLE_STAT_SPIN -2
494 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
497 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
499 int idx = arg2, cpu, error;
502 if (idx == CPU_IDLE_STAT_HALT) {
503 for (cpu = 0; cpu < ncpus; ++cpu)
504 val += cpu_idle_stats[cpu].halt;
505 } else if (idx == CPU_IDLE_STAT_SPIN) {
506 for (cpu = 0; cpu < ncpus; ++cpu)
507 val += cpu_idle_stats[cpu].spin;
509 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
510 ("invalid index %d", idx));
511 for (cpu = 0; cpu < ncpus; ++cpu)
512 val += cpu_idle_stats[cpu].mwait_cx[idx];
515 error = sysctl_handle_quad(oidp, &val, 0, req);
516 if (error || req->newptr == NULL)
519 if (idx == CPU_IDLE_STAT_HALT) {
520 for (cpu = 0; cpu < ncpus; ++cpu)
521 cpu_idle_stats[cpu].halt = 0;
522 cpu_idle_stats[0].halt = val;
523 } else if (idx == CPU_IDLE_STAT_SPIN) {
524 for (cpu = 0; cpu < ncpus; ++cpu)
525 cpu_idle_stats[cpu].spin = 0;
526 cpu_idle_stats[0].spin = val;
528 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
529 ("invalid index %d", idx));
530 for (cpu = 0; cpu < ncpus; ++cpu)
531 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
532 cpu_idle_stats[0].mwait_cx[idx] = val;
538 cpu_mwait_attach(void)
543 if ((cpu_feature2 & CPUID2_MON) == 0 ||
544 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
547 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
548 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
549 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
550 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
553 atomic_clear_int(&cpu_mwait_c3_preamble,
554 CPU_MWAIT_C3_PREAMBLE_BM_ARB);
556 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts);
558 atomic_clear_int(&cpu_mwait_c3_preamble,
559 CPU_MWAIT_C3_PREAMBLE_BM_STS);
563 sbuf_new(&sb, cpu_mwait_cx_supported,
564 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
566 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
567 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
570 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
572 sysctl_ctx_init(&cx->sysctl_ctx);
573 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
574 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
575 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
576 if (cx->sysctl_tree == NULL)
579 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
580 SYSCTL_ADD_INT(&cx->sysctl_ctx,
581 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
582 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
584 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
585 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
586 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
587 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
589 for (sub = 0; sub < cx->subcnt; ++sub)
590 sbuf_printf(&sb, "C%d/%d ", i, sub);
598 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
599 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
600 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
601 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
605 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
608 subcnt = cpu_mwait_cx_info[i].subcnt;
609 for (j = 0; j < subcnt; ++j) {
610 KASSERT(hint_idx < cpu_mwait_hints_cnt,
611 ("invalid mwait hint index %d", hint_idx));
612 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
616 KASSERT(hint_idx == cpu_mwait_hints_cnt,
617 ("mwait hint count %d != index %d",
618 cpu_mwait_hints_cnt, hint_idx));
621 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
622 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
623 int hint = cpu_mwait_hints[i];
625 kprintf(" C%d/%d hint 0x%04x\n",
626 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
634 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
635 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
636 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
640 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
643 subcnt = cpu_mwait_cx_info[i].subcnt;
644 for (j = 0; j < subcnt; ++j) {
645 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
646 ("invalid mwait deep hint index %d", hint_idx));
647 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
651 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
652 ("mwait deep hint count %d != index %d",
653 cpu_mwait_deep_hints_cnt, hint_idx));
656 kprintf("MWAIT deep hints:\n");
657 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
658 int hint = cpu_mwait_deep_hints[i];
660 kprintf(" C%d/%d hint 0x%04x\n",
661 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
665 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
669 cpu_finish(void *dummy __unused)
676 pic_finish(void *dummy __unused)
678 /* Log ELCR information */
681 /* Log MPTABLE information */
682 mptable_pci_int_dump();
685 MachIntrABI.finalize();
689 * Send an interrupt to process.
691 * Stack is set up to allow sigcode stored
692 * at top to call routine, followed by kcall
693 * to sigreturn routine below. After sigreturn
694 * resets the signal mask, the stack, and the
695 * frame pointer, it returns to the user
699 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
701 struct lwp *lp = curthread->td_lwp;
702 struct proc *p = lp->lwp_proc;
703 struct trapframe *regs;
704 struct sigacts *psp = p->p_sigacts;
705 struct sigframe sf, *sfp;
709 regs = lp->lwp_md.md_regs;
710 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
712 /* Save user context */
713 bzero(&sf, sizeof(struct sigframe));
714 sf.sf_uc.uc_sigmask = *mask;
715 sf.sf_uc.uc_stack = lp->lwp_sigstk;
716 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
717 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
718 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
720 /* Make the size of the saved context visible to userland */
721 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
723 /* Allocate and validate space for the signal handler context. */
724 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
725 SIGISMEMBER(psp->ps_sigonstack, sig)) {
726 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
727 sizeof(struct sigframe));
728 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
730 /* We take red zone into account */
731 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
735 * XXX AVX needs 64-byte alignment but sigframe has other fields and
736 * the embedded ucontext is not at the front, so aligning this won't
737 * help us. Fortunately we bcopy in/out of the sigframe, so the
740 * The problem though is if userland winds up trying to use the
743 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
745 /* Translate the signal is appropriate */
746 if (p->p_sysent->sv_sigtbl) {
747 if (sig <= p->p_sysent->sv_sigsize)
748 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
752 * Build the argument list for the signal handler.
754 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
756 regs->tf_rdi = sig; /* argument 1 */
757 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
759 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
761 * Signal handler installed with SA_SIGINFO.
763 * action(signo, siginfo, ucontext)
765 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
766 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
767 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
769 /* fill siginfo structure */
770 sf.sf_si.si_signo = sig;
771 sf.sf_si.si_code = code;
772 sf.sf_si.si_addr = (void *)regs->tf_addr;
775 * Old FreeBSD-style arguments.
777 * handler (signo, code, [uc], addr)
779 regs->tf_rsi = (register_t)code; /* argument 2 */
780 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
781 sf.sf_ahu.sf_handler = catcher;
785 * If we're a vm86 process, we want to save the segment registers.
786 * We also change eflags to be our emulated eflags, not the actual
790 if (regs->tf_eflags & PSL_VM) {
791 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
792 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
794 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
795 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
796 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
797 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
799 if (vm86->vm86_has_vme == 0)
800 sf.sf_uc.uc_mcontext.mc_eflags =
801 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
802 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
805 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
806 * syscalls made by the signal handler. This just avoids
807 * wasting time for our lazy fixup of such faults. PSL_NT
808 * does nothing in vm86 mode, but vm86 programs can set it
809 * almost legitimately in probes for old cpu types.
811 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
816 * Save the FPU state and reinit the FP unit
818 npxpush(&sf.sf_uc.uc_mcontext);
821 * Copy the sigframe out to the user's stack.
823 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
825 * Something is wrong with the stack pointer.
826 * ...Kill the process.
831 regs->tf_rsp = (register_t)sfp;
832 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
835 * i386 abi specifies that the direction flag must be cleared
838 regs->tf_rflags &= ~(PSL_T|PSL_D);
841 * 64 bit mode has a code and stack selector but
842 * no data or extra selector. %fs and %gs are not
845 regs->tf_cs = _ucodesel;
846 regs->tf_ss = _udatasel;
851 * Sanitize the trapframe for a virtual kernel passing control to a custom
852 * VM context. Remove any items that would otherwise create a privilage
855 * XXX at the moment we allow userland to set the resume flag. Is this a
859 cpu_sanitize_frame(struct trapframe *frame)
861 frame->tf_cs = _ucodesel;
862 frame->tf_ss = _udatasel;
863 /* XXX VM (8086) mode not supported? */
864 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
865 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
871 * Sanitize the tls so loading the descriptor does not blow up
872 * on us. For x86_64 we don't have to do anything.
875 cpu_sanitize_tls(struct savetls *tls)
881 * sigreturn(ucontext_t *sigcntxp)
883 * System call to cleanup state after a signal
884 * has been taken. Reset signal mask and
885 * stack state from context left by sendsig (above).
886 * Return to previous pc and psl as specified by
887 * context left by sendsig. Check carefully to
888 * make sure that the user has not modified the
889 * state to gain improper privileges.
893 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
894 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
897 sys_sigreturn(struct sigreturn_args *uap)
899 struct lwp *lp = curthread->td_lwp;
900 struct trapframe *regs;
908 * We have to copy the information into kernel space so userland
909 * can't modify it while we are sniffing it.
911 regs = lp->lwp_md.md_regs;
912 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
916 rflags = ucp->uc_mcontext.mc_rflags;
918 /* VM (8086) mode not supported */
919 rflags &= ~PSL_VM_UNSUPP;
922 if (eflags & PSL_VM) {
923 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
924 struct vm86_kernel *vm86;
927 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
928 * set up the vm86 area, and we can't enter vm86 mode.
930 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
932 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
933 if (vm86->vm86_inited == 0)
936 /* go back to user mode if both flags are set */
937 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
938 trapsignal(lp, SIGBUS, 0);
940 if (vm86->vm86_has_vme) {
941 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
942 (eflags & VME_USERCHANGE) | PSL_VM;
944 vm86->vm86_eflags = eflags; /* save VIF, VIP */
945 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
946 (eflags & VM_USERCHANGE) | PSL_VM;
948 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
949 tf->tf_eflags = eflags;
950 tf->tf_vm86_ds = tf->tf_ds;
951 tf->tf_vm86_es = tf->tf_es;
952 tf->tf_vm86_fs = tf->tf_fs;
953 tf->tf_vm86_gs = tf->tf_gs;
954 tf->tf_ds = _udatasel;
955 tf->tf_es = _udatasel;
956 tf->tf_fs = _udatasel;
957 tf->tf_gs = _udatasel;
962 * Don't allow users to change privileged or reserved flags.
965 * XXX do allow users to change the privileged flag PSL_RF.
966 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
967 * should sometimes set it there too. tf_eflags is kept in
968 * the signal context during signal handling and there is no
969 * other place to remember it, so the PSL_RF bit may be
970 * corrupted by the signal handler without us knowing.
971 * Corruption of the PSL_RF bit at worst causes one more or
972 * one less debugger trap, so allowing it is fairly harmless.
974 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
975 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
980 * Don't allow users to load a valid privileged %cs. Let the
981 * hardware check for invalid selectors, excess privilege in
982 * other selectors, invalid %eip's and invalid %esp's.
984 cs = ucp->uc_mcontext.mc_cs;
985 if (!CS_SECURE(cs)) {
986 kprintf("sigreturn: cs = 0x%x\n", cs);
987 trapsignal(lp, SIGBUS, T_PROTFLT);
990 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
994 * Restore the FPU state from the frame
997 npxpop(&ucp->uc_mcontext);
999 if (ucp->uc_mcontext.mc_onstack & 1)
1000 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
1002 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
1004 lp->lwp_sigmask = ucp->uc_sigmask;
1005 SIG_CANTMASK(lp->lwp_sigmask);
1008 return(EJUSTRETURN);
1012 * Machine dependent boot() routine
1014 * I haven't seen anything to put here yet
1015 * Possibly some stuff might be grafted back here from boot()
1023 * Shutdown the CPU as much as possible
1029 __asm__ __volatile("hlt");
1033 * cpu_idle() represents the idle LWKT. You cannot return from this function
1034 * (unless you want to blow things up!). Instead we look for runnable threads
1035 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1037 * The main loop is entered with a critical section held, we must release
1038 * the critical section before doing anything else. lwkt_switch() will
1039 * check for pending interrupts due to entering and exiting its own
1042 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1043 * However, there are cases where the idlethread will be entered with
1044 * the possibility that no IPI will occur and in such cases
1045 * lwkt_switch() sets TDF_IDLE_NOHLT.
1047 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1048 * must occur before it starts using ACPI halt.
1050 static int cpu_idle_hlt = 2;
1051 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1052 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1053 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1054 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1056 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1057 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1058 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1059 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1062 cpu_idle_default_hook(void)
1065 * We must guarentee that hlt is exactly the instruction
1066 * following the sti.
1068 __asm __volatile("sti; hlt");
1071 /* Other subsystems (e.g., ACPI) can hook this later. */
1072 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1075 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1080 if (cpu_mwait_halt >= 0) {
1081 hint = cpu_mwait_halt;
1085 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1086 cpu_mwait_repeat_shift;
1087 if (idx >= cpu_mwait_c1_hints_cnt) {
1088 /* Step up faster, once we walked through all C1 states */
1089 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1091 if (cpu_mwait_halt == CPU_MWAIT_HINT_AUTODEEP) {
1092 if (idx >= cpu_mwait_deep_hints_cnt)
1093 idx = cpu_mwait_deep_hints_cnt - 1;
1094 hint = cpu_mwait_deep_hints[idx];
1096 if (idx >= cpu_mwait_hints_cnt)
1097 idx = cpu_mwait_hints_cnt - 1;
1098 hint = cpu_mwait_hints[idx];
1101 cx_idx = MWAIT_EAX_TO_CX(hint);
1102 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1103 stat->mwait_cx[cx_idx]++;
1110 globaldata_t gd = mycpu;
1111 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1112 struct thread *td __debugvar = gd->gd_curthread;
1116 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1119 KKASSERT(td->td_critcount == 0);
1123 * See if there are any LWKTs ready to go.
1128 * When halting inside a cli we must check for reqflags
1129 * races, particularly [re]schedule requests. Running
1130 * splz() does the job.
1133 * 0 Never halt, just spin
1135 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1136 * This typically eats more power than the
1139 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1140 * use the ACPI halt (default). This is a hybrid
1141 * approach. See machdep.cpu_idle_repeat.
1143 * 3 Always use the ACPI halt. This typically
1144 * eats the least amount of power but the cpu
1145 * will be slow waking up. Slows down e.g.
1146 * compiles and other pipe/event oriented stuff.
1150 * NOTE: Interrupts are enabled and we are not in a critical
1153 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1154 * don't bother capping gd_idle_repeat, it is ok if
1157 if (gd->gd_idle_repeat == 0) {
1158 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1159 if (stat->repeat > cpu_idle_repeat_max)
1160 stat->repeat = cpu_idle_repeat_max;
1161 stat->repeat_last = 0;
1162 stat->repeat_delta = 0;
1164 ++stat->repeat_last;
1166 ++gd->gd_idle_repeat;
1167 reqflags = gd->gd_reqflags;
1168 quick = (cpu_idle_hlt == 1) ||
1169 (cpu_idle_hlt < 3 &&
1170 gd->gd_idle_repeat < cpu_idle_repeat);
1172 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1173 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1175 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1176 cpu_mwait_cx_hint(stat), 0);
1178 } else if (cpu_idle_hlt) {
1179 __asm __volatile("cli");
1181 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1183 cpu_idle_default_hook();
1187 __asm __volatile("sti");
1191 __asm __volatile("sti");
1198 * This routine is called if a spinlock has been held through the
1199 * exponential backoff period and is seriously contested. On a real cpu
1203 cpu_spinlock_contested(void)
1209 * Clear registers on exec
1212 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1214 struct thread *td = curthread;
1215 struct lwp *lp = td->td_lwp;
1216 struct pcb *pcb = td->td_pcb;
1217 struct trapframe *regs = lp->lwp_md.md_regs;
1219 /* was i386_user_cleanup() in NetBSD */
1223 bzero((char *)regs, sizeof(struct trapframe));
1224 regs->tf_rip = entry;
1225 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1226 regs->tf_rdi = stack; /* argv */
1227 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1228 regs->tf_ss = _udatasel;
1229 regs->tf_cs = _ucodesel;
1230 regs->tf_rbx = ps_strings;
1233 * Reset the hardware debug registers if they were in use.
1234 * They won't have any meaning for the newly exec'd process.
1236 if (pcb->pcb_flags & PCB_DBREGS) {
1242 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1243 if (pcb == td->td_pcb) {
1245 * Clear the debug registers on the running
1246 * CPU, otherwise they will end up affecting
1247 * the next process we switch to.
1251 pcb->pcb_flags &= ~PCB_DBREGS;
1255 * Initialize the math emulator (if any) for the current process.
1256 * Actually, just clear the bit that says that the emulator has
1257 * been initialized. Initialization is delayed until the process
1258 * traps to the emulator (if it is done at all) mainly because
1259 * emulators don't provide an entry point for initialization.
1261 pcb->pcb_flags &= ~FP_SOFTFP;
1264 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1265 * gd_npxthread. Otherwise a preemptive interrupt thread
1266 * may panic in npxdna().
1269 load_cr0(rcr0() | CR0_MP);
1272 * NOTE: The MSR values must be correct so we can return to
1273 * userland. gd_user_fs/gs must be correct so the switch
1274 * code knows what the current MSR values are.
1276 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1277 pcb->pcb_gsbase = 0;
1278 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1279 mdcpu->gd_user_gs = 0;
1280 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1281 wrmsr(MSR_KGSBASE, 0);
1283 /* Initialize the npx (if any) for the current process. */
1287 pcb->pcb_ds = _udatasel;
1288 pcb->pcb_es = _udatasel;
1289 pcb->pcb_fs = _udatasel;
1290 pcb->pcb_gs = _udatasel;
1299 cr0 |= CR0_NE; /* Done by npxinit() */
1300 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1301 cr0 |= CR0_WP | CR0_AM;
1307 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1310 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1312 if (!error && req->newptr)
1317 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1318 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1320 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1321 CTLFLAG_RW, &disable_rtc_set, 0, "");
1324 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1325 CTLFLAG_RD, &bootinfo, bootinfo, "");
1328 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1329 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1331 extern u_long bootdev; /* not a cdev_t - encoding is different */
1332 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1333 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1336 * Initialize 386 and configure to run kernel
1340 * Initialize segments & interrupt table
1344 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1345 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1347 union descriptor ldt[NLDT]; /* local descriptor table */
1350 /* table descriptors - used to load tables by cpu */
1351 struct region_descriptor r_gdt;
1352 struct region_descriptor r_idt_arr[MAXCPU];
1354 /* JG proc0paddr is a virtual address */
1357 char proc0paddr_buff[LWKT_THREAD_STACK];
1360 /* software prototypes -- in more palatable form */
1361 struct soft_segment_descriptor gdt_segs[] = {
1362 /* GNULL_SEL 0 Null Descriptor */
1363 { 0x0, /* segment base address */
1365 0, /* segment type */
1366 0, /* segment descriptor priority level */
1367 0, /* segment descriptor present */
1369 0, /* default 32 vs 16 bit size */
1370 0 /* limit granularity (byte/page units)*/ },
1371 /* GCODE_SEL 1 Code Descriptor for kernel */
1372 { 0x0, /* segment base address */
1373 0xfffff, /* length - all address space */
1374 SDT_MEMERA, /* segment type */
1375 SEL_KPL, /* segment descriptor priority level */
1376 1, /* segment descriptor present */
1378 0, /* default 32 vs 16 bit size */
1379 1 /* limit granularity (byte/page units)*/ },
1380 /* GDATA_SEL 2 Data Descriptor for kernel */
1381 { 0x0, /* segment base address */
1382 0xfffff, /* length - all address space */
1383 SDT_MEMRWA, /* segment type */
1384 SEL_KPL, /* segment descriptor priority level */
1385 1, /* segment descriptor present */
1387 0, /* default 32 vs 16 bit size */
1388 1 /* limit granularity (byte/page units)*/ },
1389 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1390 { 0x0, /* segment base address */
1391 0xfffff, /* length - all address space */
1392 SDT_MEMERA, /* segment type */
1393 SEL_UPL, /* segment descriptor priority level */
1394 1, /* segment descriptor present */
1396 1, /* default 32 vs 16 bit size */
1397 1 /* limit granularity (byte/page units)*/ },
1398 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1399 { 0x0, /* segment base address */
1400 0xfffff, /* length - all address space */
1401 SDT_MEMRWA, /* segment type */
1402 SEL_UPL, /* segment descriptor priority level */
1403 1, /* segment descriptor present */
1405 1, /* default 32 vs 16 bit size */
1406 1 /* limit granularity (byte/page units)*/ },
1407 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1408 { 0x0, /* segment base address */
1409 0xfffff, /* length - all address space */
1410 SDT_MEMERA, /* segment type */
1411 SEL_UPL, /* segment descriptor priority level */
1412 1, /* segment descriptor present */
1414 0, /* default 32 vs 16 bit size */
1415 1 /* limit granularity (byte/page units)*/ },
1416 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1418 0x0, /* segment base address */
1419 sizeof(struct x86_64tss)-1,/* length - all address space */
1420 SDT_SYSTSS, /* segment type */
1421 SEL_KPL, /* segment descriptor priority level */
1422 1, /* segment descriptor present */
1424 0, /* unused - default 32 vs 16 bit size */
1425 0 /* limit granularity (byte/page units)*/ },
1426 /* Actually, the TSS is a system descriptor which is double size */
1427 { 0x0, /* segment base address */
1429 0, /* segment type */
1430 0, /* segment descriptor priority level */
1431 0, /* segment descriptor present */
1433 0, /* default 32 vs 16 bit size */
1434 0 /* limit granularity (byte/page units)*/ },
1435 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1436 { 0x0, /* segment base address */
1437 0xfffff, /* length - all address space */
1438 SDT_MEMRWA, /* segment type */
1439 SEL_UPL, /* segment descriptor priority level */
1440 1, /* segment descriptor present */
1442 1, /* default 32 vs 16 bit size */
1443 1 /* limit granularity (byte/page units)*/ },
1447 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1451 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1452 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1454 ip->gd_looffset = (uintptr_t)func;
1455 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1461 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1466 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1468 struct gate_descriptor *ip;
1470 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1472 ip = &idt_arr[cpu][idx];
1473 ip->gd_looffset = (uintptr_t)func;
1474 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1480 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1483 #define IDTVEC(name) __CONCAT(X,name)
1486 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1487 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1488 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1489 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1490 IDTVEC(xmm), IDTVEC(dblfault),
1491 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1493 #ifdef DEBUG_INTERRUPTS
1494 extern inthand_t *Xrsvdary[256];
1498 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1500 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1501 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1502 ssd->ssd_type = sd->sd_type;
1503 ssd->ssd_dpl = sd->sd_dpl;
1504 ssd->ssd_p = sd->sd_p;
1505 ssd->ssd_def32 = sd->sd_def32;
1506 ssd->ssd_gran = sd->sd_gran;
1510 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1513 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1514 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1515 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1516 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1517 sd->sd_type = ssd->ssd_type;
1518 sd->sd_dpl = ssd->ssd_dpl;
1519 sd->sd_p = ssd->ssd_p;
1520 sd->sd_long = ssd->ssd_long;
1521 sd->sd_def32 = ssd->ssd_def32;
1522 sd->sd_gran = ssd->ssd_gran;
1526 ssdtosyssd(struct soft_segment_descriptor *ssd,
1527 struct system_segment_descriptor *sd)
1530 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1531 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1532 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1533 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1534 sd->sd_type = ssd->ssd_type;
1535 sd->sd_dpl = ssd->ssd_dpl;
1536 sd->sd_p = ssd->ssd_p;
1537 sd->sd_gran = ssd->ssd_gran;
1541 * Populate the (physmap) array with base/bound pairs describing the
1542 * available physical memory in the system, then test this memory and
1543 * build the phys_avail array describing the actually-available memory.
1545 * If we cannot accurately determine the physical memory map, then use
1546 * value from the 0xE801 call, and failing that, the RTC.
1548 * Total memory size may be set by the kernel environment variable
1549 * hw.physmem or the compile-time define MAXMEM.
1551 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1552 * of PAGE_SIZE. This also greatly reduces the memory test time
1553 * which would otherwise be excessive on machines with > 8G of ram.
1555 * XXX first should be vm_paddr_t.
1558 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1559 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1560 vm_paddr_t physmap[PHYSMAP_SIZE];
1561 struct bios_smap *smapbase, *smap, *smapend;
1565 getmemsize(caddr_t kmdp, u_int64_t first)
1567 int off, physmap_idx, pa_indx, da_indx;
1570 vm_paddr_t msgbuf_size;
1571 u_long physmem_tunable;
1573 quad_t dcons_addr, dcons_size;
1575 bzero(physmap, sizeof(physmap));
1579 * get memory map from INT 15:E820, kindly supplied by the loader.
1581 * subr_module.c says:
1582 * "Consumer may safely assume that size value precedes data."
1583 * ie: an int32_t immediately precedes smap.
1585 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1586 MODINFO_METADATA | MODINFOMD_SMAP);
1587 if (smapbase == NULL)
1588 panic("No BIOS smap info from loader!");
1590 smapsize = *((u_int32_t *)smapbase - 1);
1591 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1593 for (smap = smapbase; smap < smapend; smap++) {
1594 if (boothowto & RB_VERBOSE)
1595 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1596 smap->type, smap->base, smap->length);
1598 if (smap->type != SMAP_TYPE_MEMORY)
1601 if (smap->length == 0)
1604 for (i = 0; i <= physmap_idx; i += 2) {
1605 if (smap->base < physmap[i + 1]) {
1606 if (boothowto & RB_VERBOSE) {
1607 kprintf("Overlapping or non-monotonic "
1608 "memory region, ignoring "
1614 if (i <= physmap_idx)
1617 Realmem += smap->length;
1619 if (smap->base == physmap[physmap_idx + 1]) {
1620 physmap[physmap_idx + 1] += smap->length;
1625 if (physmap_idx == PHYSMAP_SIZE) {
1626 kprintf("Too many segments in the physical "
1627 "address map, giving up\n");
1630 physmap[physmap_idx] = smap->base;
1631 physmap[physmap_idx + 1] = smap->base + smap->length;
1634 base_memory = physmap[1] / 1024;
1635 /* make hole for AP bootstrap code */
1636 physmap[1] = mp_bootaddress(base_memory);
1638 /* Save EBDA address, if any */
1639 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1643 * Maxmem isn't the "maximum memory", it's one larger than the
1644 * highest page of the physical address space. It should be
1645 * called something like "Maxphyspage". We may adjust this
1646 * based on ``hw.physmem'' and the results of the memory test.
1648 Maxmem = atop(physmap[physmap_idx + 1]);
1651 Maxmem = MAXMEM / 4;
1654 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1655 Maxmem = atop(physmem_tunable);
1658 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1661 if (Maxmem > atop(physmap[physmap_idx + 1]))
1662 Maxmem = atop(physmap[physmap_idx + 1]);
1665 * Blowing out the DMAP will blow up the system.
1667 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1668 kprintf("Limiting Maxmem due to DMAP size\n");
1669 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1672 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1673 (boothowto & RB_VERBOSE)) {
1674 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1678 * Call pmap initialization to make new kernel address space
1682 pmap_bootstrap(&first);
1683 physmap[0] = PAGE_SIZE;
1686 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1689 for (i = j = 0; i <= physmap_idx; i += 2) {
1690 if (physmap[i+1] > ptoa(Maxmem))
1691 physmap[i+1] = ptoa(Maxmem);
1692 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1693 ~PHYSMAP_ALIGN_MASK;
1694 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1696 physmap[j] = physmap[i];
1697 physmap[j+1] = physmap[i+1];
1699 if (physmap[i] < physmap[i+1])
1702 physmap_idx = j - 2;
1705 * Align anything else used in the validation loop.
1707 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1710 * Size up each available chunk of physical memory.
1714 phys_avail[pa_indx++] = physmap[0];
1715 phys_avail[pa_indx] = physmap[0];
1716 dump_avail[da_indx] = physmap[0];
1720 * Get dcons buffer address
1722 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1723 kgetenv_quad("dcons.size", &dcons_size) == 0)
1727 * Validate the physical memory. The physical memory segments
1728 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1731 for (i = 0; i <= physmap_idx; i += 2) {
1734 end = physmap[i + 1];
1736 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1737 int tmp, page_bad, full;
1738 int *ptr = (int *)CADDR1;
1742 * block out kernel memory as not available.
1744 if (pa >= 0x200000 && pa < first)
1748 * block out dcons buffer
1751 && pa >= trunc_page(dcons_addr)
1752 && pa < dcons_addr + dcons_size) {
1759 * map page into kernel: valid, read/write,non-cacheable
1762 kernel_pmap.pmap_bits[PG_V_IDX] |
1763 kernel_pmap.pmap_bits[PG_RW_IDX] |
1764 kernel_pmap.pmap_bits[PG_N_IDX];
1769 * Test for alternating 1's and 0's
1771 *(volatile int *)ptr = 0xaaaaaaaa;
1773 if (*(volatile int *)ptr != 0xaaaaaaaa)
1776 * Test for alternating 0's and 1's
1778 *(volatile int *)ptr = 0x55555555;
1780 if (*(volatile int *)ptr != 0x55555555)
1785 *(volatile int *)ptr = 0xffffffff;
1787 if (*(volatile int *)ptr != 0xffffffff)
1792 *(volatile int *)ptr = 0x0;
1794 if (*(volatile int *)ptr != 0x0)
1797 * Restore original value.
1802 * Adjust array of valid/good pages.
1804 if (page_bad == TRUE)
1807 * If this good page is a continuation of the
1808 * previous set of good pages, then just increase
1809 * the end pointer. Otherwise start a new chunk.
1810 * Note that "end" points one higher than end,
1811 * making the range >= start and < end.
1812 * If we're also doing a speculative memory
1813 * test and we at or past the end, bump up Maxmem
1814 * so that we keep going. The first bad page
1815 * will terminate the loop.
1817 if (phys_avail[pa_indx] == pa) {
1818 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1821 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1823 "Too many holes in the physical address space, giving up\n");
1828 phys_avail[pa_indx++] = pa;
1829 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1831 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1833 if (dump_avail[da_indx] == pa) {
1834 dump_avail[da_indx] += PHYSMAP_ALIGN;
1837 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1841 dump_avail[da_indx++] = pa;
1842 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1853 * The last chunk must contain at least one page plus the message
1854 * buffer to avoid complicating other code (message buffer address
1855 * calculation, etc.).
1857 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1859 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1860 msgbuf_size >= phys_avail[pa_indx]) {
1861 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1862 phys_avail[pa_indx--] = 0;
1863 phys_avail[pa_indx--] = 0;
1866 Maxmem = atop(phys_avail[pa_indx]);
1868 /* Trim off space for the message buffer. */
1869 phys_avail[pa_indx] -= msgbuf_size;
1871 avail_end = phys_avail[pa_indx];
1873 /* Map the message buffer. */
1874 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1875 pmap_kenter((vm_offset_t)msgbufp + off,
1876 phys_avail[pa_indx] + off);
1880 struct machintr_abi MachIntrABI;
1891 * 7 Device Not Available (x87)
1893 * 9 Coprocessor Segment overrun (unsupported, reserved)
1895 * 11 Segment not present
1897 * 13 General Protection
1900 * 16 x87 FP Exception pending
1901 * 17 Alignment Check
1903 * 19 SIMD floating point
1905 * 32-255 INTn/external sources
1908 hammer_time(u_int64_t modulep, u_int64_t physfree)
1911 int gsel_tss, x, cpu;
1913 int metadata_missing, off;
1915 struct mdglobaldata *gd;
1919 * Prevent lowering of the ipl if we call tsleep() early.
1921 gd = &CPU_prvspace[0]->mdglobaldata;
1922 bzero(gd, sizeof(*gd));
1925 * Note: on both UP and SMP curthread must be set non-NULL
1926 * early in the boot sequence because the system assumes
1927 * that 'curthread' is never NULL.
1930 gd->mi.gd_curthread = &thread0;
1931 thread0.td_gd = &gd->mi;
1933 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1936 metadata_missing = 0;
1937 if (bootinfo.bi_modulep) {
1938 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1939 preload_bootstrap_relocate(KERNBASE);
1941 metadata_missing = 1;
1943 if (bootinfo.bi_envp)
1944 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1947 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1948 preload_bootstrap_relocate(PTOV_OFFSET);
1949 kmdp = preload_search_by_type("elf kernel");
1951 kmdp = preload_search_by_type("elf64 kernel");
1952 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1953 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1955 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1956 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1959 if (boothowto & RB_VERBOSE)
1963 * Default MachIntrABI to ICU
1965 MachIntrABI = MachIntrABI_ICU;
1968 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1969 * and ncpus_fit_mask remain 0.
1974 /* Init basic tunables, hz etc */
1978 * make gdt memory segments
1980 gdt_segs[GPROC0_SEL].ssd_base =
1981 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss;
1983 gd->mi.gd_prvspace = CPU_prvspace[0];
1985 for (x = 0; x < NGDT; x++) {
1986 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1987 ssdtosd(&gdt_segs[x], &gdt[x]);
1989 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1990 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1992 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1993 r_gdt.rd_base = (long) gdt;
1996 wrmsr(MSR_FSBASE, 0); /* User value */
1997 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1998 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
2000 mi_gdinit(&gd->mi, 0);
2002 proc0paddr = proc0paddr_buff;
2003 mi_proc0init(&gd->mi, proc0paddr);
2004 safepri = TDPRI_MAX;
2006 /* spinlocks and the BGL */
2010 for (x = 0; x < NIDT; x++)
2011 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2012 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2013 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2014 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2015 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2016 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2017 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2018 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2019 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2020 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2021 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2022 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2023 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2024 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2025 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2026 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2027 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2028 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2029 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2030 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2032 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2033 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2034 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2037 lidt(&r_idt_arr[0]);
2040 * Initialize the console before we print anything out.
2045 if (metadata_missing)
2046 kprintf("WARNING: loader(8) metadata is missing!\n");
2056 * Initialize IRQ mapping
2059 * SHOULD be after elcr_probe()
2061 MachIntrABI_ICU.initmap();
2062 MachIntrABI_IOAPIC.initmap();
2066 if (boothowto & RB_KDB)
2067 Debugger("Boot flags requested debugger");
2071 finishidentcpu(); /* Final stage of CPU initialization */
2072 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2073 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2075 identify_cpu(); /* Final stage of CPU initialization */
2076 initializecpu(0); /* Initialize CPU registers */
2078 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2079 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2080 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2081 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt);
2084 * Some of the virtual machines do not work w/ I/O APIC
2085 * enabled. If the user does not explicitly enable or
2086 * disable the I/O APIC (ioapic_enable < 0), then we
2087 * disable I/O APIC on all virtual machines.
2090 * This must be done after identify_cpu(), which sets
2093 if (ioapic_enable < 0) {
2094 if (cpu_feature2 & CPUID2_VMM)
2100 /* make an initial tss so cpu can get interrupt stack on syscall! */
2101 gd->gd_common_tss.tss_rsp0 =
2102 (register_t)(thread0.td_kstack +
2103 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2104 /* Ensure the stack is aligned to 16 bytes */
2105 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2107 /* double fault stack */
2108 gd->gd_common_tss.tss_ist1 =
2109 (long)&gd->mi.gd_prvspace->idlestack[
2110 sizeof(gd->mi.gd_prvspace->idlestack)];
2112 /* Set the IO permission bitmap (empty due to tss seg limit) */
2113 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2115 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2116 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2117 gd->gd_common_tssd = *gd->gd_tss_gdt;
2120 /* Set up the fast syscall stuff */
2121 msr = rdmsr(MSR_EFER) | EFER_SCE;
2122 wrmsr(MSR_EFER, msr);
2123 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2124 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2125 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2126 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2127 wrmsr(MSR_STAR, msr);
2128 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2130 getmemsize(kmdp, physfree);
2131 init_param2(physmem);
2133 /* now running on new page tables, configured,and u/iom is accessible */
2135 /* Map the message buffer. */
2137 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2138 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2141 msgbufinit(msgbufp, MSGBUF_SIZE);
2144 /* transfer to user mode */
2146 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2147 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2148 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2154 /* setup proc 0's pcb */
2155 thread0.td_pcb->pcb_flags = 0;
2156 thread0.td_pcb->pcb_cr3 = KPML4phys;
2157 thread0.td_pcb->pcb_ext = NULL;
2158 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2160 /* Location of kernel stack for locore */
2161 return ((u_int64_t)thread0.td_pcb);
2165 * Initialize machine-dependant portions of the global data structure.
2166 * Note that the global data area and cpu0's idlestack in the private
2167 * data space were allocated in locore.
2169 * Note: the idlethread's cpl is 0
2171 * WARNING! Called from early boot, 'mycpu' may not work yet.
2174 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2177 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2179 lwkt_init_thread(&gd->mi.gd_idlethread,
2180 gd->mi.gd_prvspace->idlestack,
2181 sizeof(gd->mi.gd_prvspace->idlestack),
2183 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2184 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2185 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2186 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2190 * We only have to check for DMAP bounds, the globaldata space is
2191 * actually part of the kernel_map so we don't have to waste time
2192 * checking CPU_prvspace[*].
2195 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2198 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2199 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2203 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2209 globaldata_find(int cpu)
2211 KKASSERT(cpu >= 0 && cpu < ncpus);
2212 return(&CPU_prvspace[cpu]->mdglobaldata.mi);
2216 * This path should be safe from the SYSRET issue because only stopped threads
2217 * can have their %rip adjusted this way (and all heavy weight thread switches
2218 * clear QUICKREF and thus do not use SYSRET). However, the code path is
2219 * convoluted so add a safety by forcing %rip to be cannonical.
2222 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2224 if (addr & 0x0000800000000000LLU)
2225 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU;
2227 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU;
2232 ptrace_single_step(struct lwp *lp)
2234 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2239 fill_regs(struct lwp *lp, struct reg *regs)
2241 struct trapframe *tp;
2243 if ((tp = lp->lwp_md.md_regs) == NULL)
2245 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2250 set_regs(struct lwp *lp, struct reg *regs)
2252 struct trapframe *tp;
2254 tp = lp->lwp_md.md_regs;
2255 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2256 !CS_SECURE(regs->r_cs))
2258 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2264 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2266 struct env87 *penv_87 = &sv_87->sv_env;
2267 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2270 /* FPU control/status */
2271 penv_87->en_cw = penv_xmm->en_cw;
2272 penv_87->en_sw = penv_xmm->en_sw;
2273 penv_87->en_tw = penv_xmm->en_tw;
2274 penv_87->en_fip = penv_xmm->en_fip;
2275 penv_87->en_fcs = penv_xmm->en_fcs;
2276 penv_87->en_opcode = penv_xmm->en_opcode;
2277 penv_87->en_foo = penv_xmm->en_foo;
2278 penv_87->en_fos = penv_xmm->en_fos;
2281 for (i = 0; i < 8; ++i)
2282 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2286 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2288 struct env87 *penv_87 = &sv_87->sv_env;
2289 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2292 /* FPU control/status */
2293 penv_xmm->en_cw = penv_87->en_cw;
2294 penv_xmm->en_sw = penv_87->en_sw;
2295 penv_xmm->en_tw = penv_87->en_tw;
2296 penv_xmm->en_fip = penv_87->en_fip;
2297 penv_xmm->en_fcs = penv_87->en_fcs;
2298 penv_xmm->en_opcode = penv_87->en_opcode;
2299 penv_xmm->en_foo = penv_87->en_foo;
2300 penv_xmm->en_fos = penv_87->en_fos;
2303 for (i = 0; i < 8; ++i)
2304 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2308 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2310 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2313 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2314 (struct save87 *)fpregs);
2317 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2322 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2325 set_fpregs_xmm((struct save87 *)fpregs,
2326 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2329 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2334 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2339 dbregs->dr[0] = rdr0();
2340 dbregs->dr[1] = rdr1();
2341 dbregs->dr[2] = rdr2();
2342 dbregs->dr[3] = rdr3();
2343 dbregs->dr[4] = rdr4();
2344 dbregs->dr[5] = rdr5();
2345 dbregs->dr[6] = rdr6();
2346 dbregs->dr[7] = rdr7();
2349 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2351 dbregs->dr[0] = pcb->pcb_dr0;
2352 dbregs->dr[1] = pcb->pcb_dr1;
2353 dbregs->dr[2] = pcb->pcb_dr2;
2354 dbregs->dr[3] = pcb->pcb_dr3;
2357 dbregs->dr[6] = pcb->pcb_dr6;
2358 dbregs->dr[7] = pcb->pcb_dr7;
2363 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2366 load_dr0(dbregs->dr[0]);
2367 load_dr1(dbregs->dr[1]);
2368 load_dr2(dbregs->dr[2]);
2369 load_dr3(dbregs->dr[3]);
2370 load_dr4(dbregs->dr[4]);
2371 load_dr5(dbregs->dr[5]);
2372 load_dr6(dbregs->dr[6]);
2373 load_dr7(dbregs->dr[7]);
2376 struct ucred *ucred;
2378 uint64_t mask1, mask2;
2381 * Don't let an illegal value for dr7 get set. Specifically,
2382 * check for undefined settings. Setting these bit patterns
2383 * result in undefined behaviour and can lead to an unexpected
2386 /* JG this loop looks unreadable */
2387 /* Check 4 2-bit fields for invalid patterns.
2388 * These fields are R/Wi, for i = 0..3
2390 /* Is 10 in LENi allowed when running in compatibility mode? */
2391 /* Pattern 10 in R/Wi might be used to indicate
2392 * breakpoint on I/O. Further analysis should be
2393 * carried to decide if it is safe and useful to
2394 * provide access to that capability
2396 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2397 i++, mask1 <<= 4, mask2 <<= 4)
2398 if ((dbregs->dr[7] & mask1) == mask2)
2401 pcb = lp->lwp_thread->td_pcb;
2402 ucred = lp->lwp_proc->p_ucred;
2405 * Don't let a process set a breakpoint that is not within the
2406 * process's address space. If a process could do this, it
2407 * could halt the system by setting a breakpoint in the kernel
2408 * (if ddb was enabled). Thus, we need to check to make sure
2409 * that no breakpoints are being enabled for addresses outside
2410 * process's address space, unless, perhaps, we were called by
2413 * XXX - what about when the watched area of the user's
2414 * address space is written into from within the kernel
2415 * ... wouldn't that still cause a breakpoint to be generated
2416 * from within kernel mode?
2419 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2420 if (dbregs->dr[7] & 0x3) {
2421 /* dr0 is enabled */
2422 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2426 if (dbregs->dr[7] & (0x3<<2)) {
2427 /* dr1 is enabled */
2428 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2432 if (dbregs->dr[7] & (0x3<<4)) {
2433 /* dr2 is enabled */
2434 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2438 if (dbregs->dr[7] & (0x3<<6)) {
2439 /* dr3 is enabled */
2440 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2445 pcb->pcb_dr0 = dbregs->dr[0];
2446 pcb->pcb_dr1 = dbregs->dr[1];
2447 pcb->pcb_dr2 = dbregs->dr[2];
2448 pcb->pcb_dr3 = dbregs->dr[3];
2449 pcb->pcb_dr6 = dbregs->dr[6];
2450 pcb->pcb_dr7 = dbregs->dr[7];
2452 pcb->pcb_flags |= PCB_DBREGS;
2459 * Return > 0 if a hardware breakpoint has been hit, and the
2460 * breakpoint was in user space. Return 0, otherwise.
2463 user_dbreg_trap(void)
2465 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2466 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2467 int nbp; /* number of breakpoints that triggered */
2468 caddr_t addr[4]; /* breakpoint addresses */
2472 if ((dr7 & 0xff) == 0) {
2474 * all GE and LE bits in the dr7 register are zero,
2475 * thus the trap couldn't have been caused by the
2476 * hardware debug registers
2487 * None of the breakpoint bits are set meaning this
2488 * trap was not caused by any of the debug registers
2494 * at least one of the breakpoints were hit, check to see
2495 * which ones and if any of them are user space addresses
2499 addr[nbp++] = (caddr_t)rdr0();
2502 addr[nbp++] = (caddr_t)rdr1();
2505 addr[nbp++] = (caddr_t)rdr2();
2508 addr[nbp++] = (caddr_t)rdr3();
2511 for (i=0; i<nbp; i++) {
2513 (caddr_t)VM_MAX_USER_ADDRESS) {
2515 * addr[i] is in user space
2522 * None of the breakpoints are in user space.
2530 Debugger(const char *msg)
2532 kprintf("Debugger(\"%s\") called.\n", msg);
2539 * Provide inb() and outb() as functions. They are normally only
2540 * available as macros calling inlined functions, thus cannot be
2541 * called inside DDB.
2543 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2549 /* silence compiler warnings */
2551 void outb(u_int, u_char);
2558 * We use %%dx and not %1 here because i/o is done at %dx and not at
2559 * %edx, while gcc generates inferior code (movw instead of movl)
2560 * if we tell it to load (u_short) port.
2562 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2567 outb(u_int port, u_char data)
2571 * Use an unnecessary assignment to help gcc's register allocator.
2572 * This make a large difference for gcc-1.40 and a tiny difference
2573 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2574 * best results. gcc-2.6.0 can't handle this.
2577 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2585 * initialize all the SMP locks
2588 /* critical region when masking or unmasking interupts */
2589 struct spinlock_deprecated imen_spinlock;
2591 /* critical region for old style disable_intr/enable_intr */
2592 struct spinlock_deprecated mpintr_spinlock;
2594 /* critical region around INTR() routines */
2595 struct spinlock_deprecated intr_spinlock;
2597 /* lock region used by kernel profiling */
2598 struct spinlock_deprecated mcount_spinlock;
2600 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2601 struct spinlock_deprecated com_spinlock;
2603 /* lock regions around the clock hardware */
2604 struct spinlock_deprecated clock_spinlock;
2610 * Get the initial mplock with a count of 1 for the BSP.
2611 * This uses a LOGICAL cpu ID, ie BSP == 0.
2613 cpu_get_initial_mplock();
2615 spin_lock_init(&mcount_spinlock);
2616 spin_lock_init(&intr_spinlock);
2617 spin_lock_init(&mpintr_spinlock);
2618 spin_lock_init(&imen_spinlock);
2619 spin_lock_init(&com_spinlock);
2620 spin_lock_init(&clock_spinlock);
2622 /* our token pool needs to work early */
2623 lwkt_token_pool_init();
2627 cpu_mwait_hint_valid(uint32_t hint)
2631 cx_idx = MWAIT_EAX_TO_CX(hint);
2632 if (cx_idx >= CPU_MWAIT_CX_MAX)
2635 sub = MWAIT_EAX_TO_CX_SUB(hint);
2636 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2643 cpu_mwait_cx_no_bmsts(void)
2645 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2649 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
2650 boolean_t allow_auto)
2652 int error, cx_idx, old_cx_idx, sub = 0, hint;
2653 char name[16], *ptr, *start;
2657 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2658 sub = MWAIT_EAX_TO_CX_SUB(hint);
2659 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2660 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2661 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2662 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2664 old_cx_idx = CPU_MWAIT_CX_MAX;
2667 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2668 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2669 strlcpy(name, "NONE", sizeof(name));
2670 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2671 strlcpy(name, "AUTO", sizeof(name));
2672 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2673 strlcpy(name, "AUTODEEP", sizeof(name));
2674 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2675 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2676 strlcpy(name, "INVALID", sizeof(name));
2678 ksnprintf(name, sizeof(name), "C%d/%d", old_cx_idx, sub);
2680 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2681 if (error != 0 || req->newptr == NULL)
2684 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2685 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2688 if (allow_auto && strcmp(name, "AUTO") == 0) {
2689 hint = CPU_MWAIT_HINT_AUTO;
2690 cx_idx = CPU_MWAIT_C2;
2693 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2694 hint = CPU_MWAIT_HINT_AUTODEEP;
2695 cx_idx = CPU_MWAIT_C3;
2699 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2704 cx_idx = strtol(start, &ptr, 10);
2705 if (ptr == start || *ptr != '/')
2707 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2713 sub = strtol(start, &ptr, 10);
2716 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2719 hint = MWAIT_EAX_HINT(cx_idx, sub);
2721 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2723 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2724 error = cputimer_intr_powersave_addreq();
2727 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2728 cputimer_intr_powersave_remreq();
2736 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
2740 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2741 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2742 &cpu_mwait_halt, TRUE);
2743 lwkt_serialize_exit(&cpu_mwait_cx_slize);
2748 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
2752 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2753 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2754 &cpu_mwait_spin, FALSE);
2755 lwkt_serialize_exit(&cpu_mwait_cx_slize);