2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)isa.h 5.7 (Berkeley) 5/9/91
37 * $FreeBSD: src/sys/i386/isa/isa.h,v 1.23 1999/08/28 00:44:54 peter Exp $
40 #ifndef _BUS_ISA_ARCH_ISA_H_
41 #define _BUS_ISA_ARCH_ISA_H_
43 /* BEWARE: Included in both assembler and C code */
50 * Input / Output Port Assignments
53 #define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */
56 #define IO_DMA1 0x000 /* 8237A DMA Controller #1 */
57 #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */
58 #define IO_PMP1 0x026 /* 82347 Power Management Peripheral */
59 #define IO_TIMER1 0x040 /* 8253 Timer #1 */
60 #define IO_TIMER2 0x048 /* 8253 Timer #2 */
61 #define IO_KBD 0x060 /* 8042 Keyboard */
62 #define IO_PPI 0x061 /* Programmable Peripheral Interface */
63 #define IO_RTC 0x070 /* RTC */
64 #define IO_NMI IO_RTC /* NMI Control */
65 #define IO_DMAPG 0x080 /* DMA Page Registers */
66 #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */
67 #define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */
68 #define IO_NPX 0x0F0 /* Numeric Coprocessor */
71 /* 0x100 - 0x16F Open */
73 #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */
75 #define IO_PMP2 0x178 /* 82347 Power Management Peripheral */
77 /* 0x17A - 0x1EF Open */
79 #define IO_WD1 0x1F0 /* Primary Fixed Disk Controller */
80 #define IO_GAME 0x201 /* Game Controller */
82 /* 0x202 - 0x22A Open */
84 #define IO_ASC2 0x22B /* AmiScan addr.grp. 2 */
86 /* 0x230 - 0x26A Open */
88 #define IO_ASC3 0x26B /* AmiScan addr.grp. 3 */
89 #define IO_GSC1 0x270 /* -- 0x27B! GeniScan GS-4500 addr.grp. 1 */
90 #define IO_LPT2 0x278 /* Parallel Port #2 */
92 /* 0x280 - 0x2AA Open */
94 #define IO_ASC4 0x2AB /* AmiScan addr.grp. 4 */
96 /* 0x2B0 - 0x2DF Open */
98 #define IO_GSC2 0x2E0 /* GeniScan GS-4500 addr.grp. 2 */
99 #define IO_COM4 0x2E8 /* COM4 i/o address */
100 #define IO_ASC5 0x2EB /* AmiScan addr.grp. 5 */
102 /* 0x2F0 - 0x2F7 Open */
104 #define IO_COM2 0x2F8 /* COM2 i/o address */
106 /* 0x300 - 0x32A Open */
108 #define IO_ASC6 0x32B /* AmiScan addr.grp. 6 */
109 #define IO_AHA0 0x330 /* adaptec 1542 default addr. */
110 #define IO_BT0 0x330 /* bustek 742a default addr. */
111 #define IO_UHA0 0x330 /* ultrastore 14f default addr. */
112 #define IO_AHA1 0x334 /* adaptec 1542 default addr. */
113 #define IO_BT1 0x334 /* bustek 742a default addr. */
115 /* 0x340 - 0x36A Open */
117 #define IO_ASC7 0x36B /* AmiScan addr.grp. 7 */
118 #define IO_GSC3 0x370 /* GeniScan GS-4500 addr.grp. 3 */
119 #define IO_FD2 0x370 /* secondary base i/o address */
120 #define IO_LPT1 0x378 /* Parallel Port #1 */
122 /* 0x380 - 0x3AA Open */
124 #define IO_ASC8 0x3AB /* AmiScan addr.grp. 8 */
125 #define IO_MDA 0x3B0 /* Monochome Adapter */
126 #define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */
127 #define IO_VGA 0x3C0 /* E/VGA Ports */
128 #define IO_CGA 0x3D0 /* CGA Ports */
129 #define IO_GSC4 0x3E0 /* GeniScan GS-4500 addr.grp. 4 */
130 #define IO_COM3 0x3E8 /* COM3 i/o address */
131 #define IO_ASC1 0x3EB /* AmiScan addr.grp. 1 */
132 #define IO_FD1 0x3F0 /* primary base i/o address */
133 #define IO_COM1 0x3F8 /* COM1 i/o address */
135 #define IO_ISAEND 0x3FF /* End (actually Max) of I/O Regs */
136 #endif /* !IO_ISABEGIN */
139 * Input / Output Port Sizes - these are from several sources, and tend
140 * to be the larger of what was found.
145 #define IO_ASCSIZE 5 /* AmiScan GI1904-based hand scanner */
146 #define IO_CGASIZE 12 /* CGA controllers */
147 #define IO_COMSIZE 8 /* 8250, 16x50 com controllers */
148 #define IO_DMASIZE 16 /* 8237 DMA controllers */
149 #define IO_DPGSIZE 32 /* 74LS612 DMA page registers */
150 #define IO_EISASIZE 256 /* EISA controllers */
151 #define IO_FDCSIZE 8 /* Nec765 floppy controllers */
152 #define IO_GAMSIZE 16 /* AT compatible game controllers */
153 #define IO_GSCSIZE 8 /* GeniScan GS-4500G hand scanner */
154 #define IO_ICUSIZE 16 /* 8259A interrupt controllers */
155 #define IO_KBDSIZE 16 /* 8042 Keyboard controllers */
156 #define IO_LPTSIZE 8 /* LPT controllers, some use only 4 */
157 #define IO_MDASIZE 12 /* Monochrome display controllers */
158 #define IO_NPXSIZE 16 /* 80387/80487 NPX registers */
159 #define IO_PMPSIZE 2 /* 82347 power management peripheral */
160 #define IO_PSMSIZE 5 /* 8042 Keyboard controllers */
161 #define IO_RTCSIZE 16 /* CMOS real time clock, NMI control */
162 #define IO_TMRSIZE 16 /* 8253 programmable timers */
163 #define IO_VGASIZE 16 /* VGA controllers */
164 #define IO_WDCSIZE 8 /* WD compatible disk controllers */
166 #endif /* !IO_ISASIZES */
169 * Input / Output Memory Physical Addresses
172 #define IOM_BEGIN 0x0A0000 /* Start of I/O Memory "hole" */
173 #define IOM_END 0x100000 /* End of I/O Memory "hole" */
174 #define IOM_SIZE (IOM_END - IOM_BEGIN)
175 #endif /* !IOM_BEGIN */
178 * RAM Physical Address Space (ignoring the above mentioned "hole")
181 #define RAM_BEGIN 0x0000000 /* Start of RAM Memory */
182 #define RAM_END 0x1000000 /* End of RAM Memory */
183 #define RAM_SIZE (RAM_END - RAM_BEGIN)
184 #endif /* !RAM_BEGIN */
187 * Oddball Physical Memory Addresses
189 #ifndef COMPAQ_RAMRELOC
190 #define COMPAQ_RAMRELOC 0x80C00000 /* Compaq RAM relocation/diag */
191 #define COMPAQ_RAMSETUP 0x80C00002 /* Compaq RAM setup */
192 #define WEITEK_FPU 0xC0000000 /* WTL 2167 */
193 #define CYRIX_EMC 0xC0000000 /* Cyrix EMC */
194 #endif /* !COMPAQ_RAMRELOC */
196 #endif /* !_BUS_ISA_ARCH_ISA_H_ */