2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61 * does not support external SSRAM.
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
73 #include "opt_ifpoll.h"
75 #include <sys/param.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
80 #include <sys/interrupt.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
90 #include <netinet/ip.h>
91 #include <netinet/tcp.h>
94 #include <net/ethernet.h>
96 #include <net/if_arp.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
99 #include <net/if_poll.h>
100 #include <net/if_types.h>
101 #include <net/ifq_var.h>
102 #include <net/vlan/if_vlan_var.h>
103 #include <net/vlan/if_vlan_ether.h>
105 #include <dev/netif/mii_layer/mii.h>
106 #include <dev/netif/mii_layer/miivar.h>
107 #include <dev/netif/mii_layer/brgphyreg.h>
109 #include <bus/pci/pcidevs.h>
110 #include <bus/pci/pcireg.h>
111 #include <bus/pci/pcivar.h>
113 #include <dev/netif/bge/if_bgereg.h>
114 #include <dev/netif/bge/if_bgevar.h>
116 /* "device miibus" required. See GENERIC if you get errors here. */
117 #include "miibus_if.h"
119 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
121 static const struct bge_type {
126 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
127 "3COM 3C996 Gigabit Ethernet" },
129 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
130 "Alteon BCM5700 Gigabit Ethernet" },
131 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
132 "Alteon BCM5701 Gigabit Ethernet" },
134 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
135 "Altima AC1000 Gigabit Ethernet" },
136 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
137 "Altima AC1002 Gigabit Ethernet" },
138 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
139 "Altima AC9100 Gigabit Ethernet" },
141 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
142 "Apple BCM5701 Gigabit Ethernet" },
144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
145 "Broadcom BCM5700 Gigabit Ethernet" },
146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
147 "Broadcom BCM5701 Gigabit Ethernet" },
148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
149 "Broadcom BCM5702 Gigabit Ethernet" },
150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
151 "Broadcom BCM5702X Gigabit Ethernet" },
152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
153 "Broadcom BCM5702 Gigabit Ethernet" },
154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
155 "Broadcom BCM5703 Gigabit Ethernet" },
156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
157 "Broadcom BCM5703X Gigabit Ethernet" },
158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
159 "Broadcom BCM5703 Gigabit Ethernet" },
160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
161 "Broadcom BCM5704C Dual Gigabit Ethernet" },
162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
163 "Broadcom BCM5704S Dual Gigabit Ethernet" },
164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
165 "Broadcom BCM5704S Dual Gigabit Ethernet" },
166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
167 "Broadcom BCM5705 Gigabit Ethernet" },
168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
169 "Broadcom BCM5705F Gigabit Ethernet" },
170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
171 "Broadcom BCM5705K Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
173 "Broadcom BCM5705M Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
175 "Broadcom BCM5705M Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
177 "Broadcom BCM5714C Gigabit Ethernet" },
178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
179 "Broadcom BCM5714S Gigabit Ethernet" },
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
181 "Broadcom BCM5715 Gigabit Ethernet" },
182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
183 "Broadcom BCM5715S Gigabit Ethernet" },
184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
185 "Broadcom BCM5720 Gigabit Ethernet" },
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
187 "Broadcom BCM5721 Gigabit Ethernet" },
188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
189 "Broadcom BCM5722 Gigabit Ethernet" },
190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
191 "Broadcom BCM5723 Gigabit Ethernet" },
192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
193 "Broadcom BCM5750 Gigabit Ethernet" },
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
195 "Broadcom BCM5750M Gigabit Ethernet" },
196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
197 "Broadcom BCM5751 Gigabit Ethernet" },
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
199 "Broadcom BCM5751F Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
201 "Broadcom BCM5751M Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
203 "Broadcom BCM5752 Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
205 "Broadcom BCM5752M Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
207 "Broadcom BCM5753 Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
209 "Broadcom BCM5753F Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
211 "Broadcom BCM5753M Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
213 "Broadcom BCM5754 Gigabit Ethernet" },
214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
215 "Broadcom BCM5754M Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
217 "Broadcom BCM5755 Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
219 "Broadcom BCM5755M Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
221 "Broadcom BCM5756 Gigabit Ethernet" },
222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
223 "Broadcom BCM5761 Gigabit Ethernet" },
224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
225 "Broadcom BCM5761E Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
227 "Broadcom BCM5761S Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
229 "Broadcom BCM5761SE Gigabit Ethernet" },
230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
231 "Broadcom BCM5764 Gigabit Ethernet" },
232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
233 "Broadcom BCM5780 Gigabit Ethernet" },
234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
235 "Broadcom BCM5780S Gigabit Ethernet" },
236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
237 "Broadcom BCM5781 Gigabit Ethernet" },
238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
239 "Broadcom BCM5782 Gigabit Ethernet" },
240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
241 "Broadcom BCM5784 Gigabit Ethernet" },
242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
243 "Broadcom BCM5785F Gigabit Ethernet" },
244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
245 "Broadcom BCM5785G Gigabit Ethernet" },
246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
247 "Broadcom BCM5786 Gigabit Ethernet" },
248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
249 "Broadcom BCM5787 Gigabit Ethernet" },
250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
251 "Broadcom BCM5787F Gigabit Ethernet" },
252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
253 "Broadcom BCM5787M Gigabit Ethernet" },
254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
255 "Broadcom BCM5788 Gigabit Ethernet" },
256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
257 "Broadcom BCM5789 Gigabit Ethernet" },
258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
259 "Broadcom BCM5901 Fast Ethernet" },
260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
261 "Broadcom BCM5901A2 Fast Ethernet" },
262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
263 "Broadcom BCM5903M Fast Ethernet" },
264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
265 "Broadcom BCM5906 Fast Ethernet"},
266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
267 "Broadcom BCM5906M Fast Ethernet"},
268 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
269 "Broadcom BCM57760 Gigabit Ethernet"},
270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
271 "Broadcom BCM57780 Gigabit Ethernet"},
272 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
273 "Broadcom BCM57788 Gigabit Ethernet"},
274 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
275 "Broadcom BCM57790 Gigabit Ethernet"},
276 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
277 "SysKonnect Gigabit Ethernet" },
282 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
283 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
284 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
285 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
286 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
287 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
288 #define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788)
290 #define BGE_IS_CRIPPLED(sc) \
291 (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700)
293 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
295 static int bge_probe(device_t);
296 static int bge_attach(device_t);
297 static int bge_detach(device_t);
298 static void bge_txeof(struct bge_softc *, uint16_t);
299 static void bge_rxeof(struct bge_softc *, uint16_t, int);
301 static void bge_tick(void *);
302 static void bge_stats_update(struct bge_softc *);
303 static void bge_stats_update_regs(struct bge_softc *);
305 bge_defrag_shortdma(struct mbuf *);
306 static int bge_encap(struct bge_softc *, struct mbuf **,
308 static void bge_xmit(struct bge_softc *, uint32_t);
309 static int bge_setup_tso(struct bge_softc *, struct mbuf **,
310 uint16_t *, uint16_t *);
313 static void bge_npoll(struct ifnet *, struct ifpoll_info *);
314 static void bge_npoll_compat(struct ifnet *, void *, int );
316 static void bge_intr_crippled(void *);
317 static void bge_intr_legacy(void *);
318 static void bge_msi(void *);
319 static void bge_msi_oneshot(void *);
320 static void bge_intr(struct bge_softc *);
321 static void bge_enable_intr(struct bge_softc *);
322 static void bge_disable_intr(struct bge_softc *);
323 static void bge_start(struct ifnet *, struct ifaltq_subque *);
324 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
325 static void bge_init(void *);
326 static void bge_stop(struct bge_softc *);
327 static void bge_watchdog(struct ifnet *);
328 static void bge_shutdown(device_t);
329 static int bge_suspend(device_t);
330 static int bge_resume(device_t);
331 static int bge_ifmedia_upd(struct ifnet *);
332 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
334 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
335 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
337 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
338 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
340 static void bge_setmulti(struct bge_softc *);
341 static void bge_setpromisc(struct bge_softc *);
342 static void bge_enable_msi(struct bge_softc *sc);
344 static int bge_alloc_jumbo_mem(struct bge_softc *);
345 static void bge_free_jumbo_mem(struct bge_softc *);
346 static struct bge_jslot
347 *bge_jalloc(struct bge_softc *);
348 static void bge_jfree(void *);
349 static void bge_jref(void *);
350 static int bge_newbuf_std(struct bge_softc *, int, int);
351 static int bge_newbuf_jumbo(struct bge_softc *, int, int);
352 static void bge_setup_rxdesc_std(struct bge_softc *, int);
353 static void bge_setup_rxdesc_jumbo(struct bge_softc *, int);
354 static int bge_init_rx_ring_std(struct bge_softc *);
355 static void bge_free_rx_ring_std(struct bge_softc *);
356 static int bge_init_rx_ring_jumbo(struct bge_softc *);
357 static void bge_free_rx_ring_jumbo(struct bge_softc *);
358 static void bge_free_tx_ring(struct bge_softc *);
359 static int bge_init_tx_ring(struct bge_softc *);
361 static int bge_chipinit(struct bge_softc *);
362 static int bge_blockinit(struct bge_softc *);
363 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
365 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
366 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
368 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
370 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
371 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
372 static void bge_writembx(struct bge_softc *, int, int);
374 static int bge_miibus_readreg(device_t, int, int);
375 static int bge_miibus_writereg(device_t, int, int, int);
376 static void bge_miibus_statchg(device_t);
377 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
378 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
379 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
380 static void bge_autopoll_link_upd(struct bge_softc *, uint32_t);
381 static void bge_link_poll(struct bge_softc *);
383 static void bge_reset(struct bge_softc *);
385 static int bge_dma_alloc(struct bge_softc *);
386 static void bge_dma_free(struct bge_softc *);
387 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
388 bus_dma_tag_t *, bus_dmamap_t *,
389 void **, bus_addr_t *);
390 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
392 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
393 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
394 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
395 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
397 static void bge_coal_change(struct bge_softc *);
398 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
399 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
400 static int bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
401 static int bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
402 static int bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
403 static int bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
404 static int bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
405 static int bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
406 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
410 * Set following tunable to 1 for some IBM blade servers with the DNLK
411 * switch module. Auto negotiation is broken for those configurations.
413 static int bge_fake_autoneg = 0;
414 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
416 static int bge_msi_enable = 1;
417 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable);
419 #if !defined(KTR_IF_BGE)
420 #define KTR_IF_BGE KTR_ALL
422 KTR_INFO_MASTER(if_bge);
423 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
424 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
425 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
426 #define logif(name) KTR_LOG(if_bge_ ## name)
428 static device_method_t bge_methods[] = {
429 /* Device interface */
430 DEVMETHOD(device_probe, bge_probe),
431 DEVMETHOD(device_attach, bge_attach),
432 DEVMETHOD(device_detach, bge_detach),
433 DEVMETHOD(device_shutdown, bge_shutdown),
434 DEVMETHOD(device_suspend, bge_suspend),
435 DEVMETHOD(device_resume, bge_resume),
438 DEVMETHOD(bus_print_child, bus_generic_print_child),
439 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
442 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
443 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
444 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
449 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
450 static devclass_t bge_devclass;
452 DECLARE_DUMMY_MODULE(if_bge);
453 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
454 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
457 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
459 device_t dev = sc->bge_dev;
462 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
463 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
466 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
467 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
468 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
473 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
475 device_t dev = sc->bge_dev;
477 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
478 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
481 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
482 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
483 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
488 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
490 device_t dev = sc->bge_dev;
492 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
493 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
498 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
500 device_t dev = sc->bge_dev;
502 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
503 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
507 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
509 CSR_WRITE_4(sc, off, val);
513 bge_writembx(struct bge_softc *sc, int off, int val)
515 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
516 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
518 CSR_WRITE_4(sc, off, val);
519 if (sc->bge_mbox_reorder)
524 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
526 uint32_t access, byte = 0;
530 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
531 for (i = 0; i < 8000; i++) {
532 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
540 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
541 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
543 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
544 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
545 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
547 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
553 if (i == BGE_TIMEOUT * 10) {
554 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
559 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
561 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
563 /* Disable access. */
564 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
567 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
568 CSR_READ_4(sc, BGE_NVRAM_SWARB);
574 * Read a sequence of bytes from NVRAM.
577 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
582 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
585 for (i = 0; i < cnt; i++) {
586 err = bge_nvram_getbyte(sc, off + i, &byte);
592 return (err ? 1 : 0);
596 * Read a byte of data stored in the EEPROM at address 'addr.' The
597 * BCM570x supports both the traditional bitbang interface and an
598 * auto access interface for reading the EEPROM. We use the auto
602 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
608 * Enable use of auto EEPROM access so we can avoid
609 * having to use the bitbang method.
611 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
613 /* Reset the EEPROM, load the clock period. */
614 CSR_WRITE_4(sc, BGE_EE_ADDR,
615 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
618 /* Issue the read EEPROM command. */
619 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
621 /* Wait for completion */
622 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
624 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
628 if (i == BGE_TIMEOUT) {
629 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
634 byte = CSR_READ_4(sc, BGE_EE_DATA);
636 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
642 * Read a sequence of bytes from the EEPROM.
645 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
651 for (byte = 0, err = 0, i = 0; i < len; i++) {
652 err = bge_eeprom_getbyte(sc, off + i, &byte);
662 bge_miibus_readreg(device_t dev, int phy, int reg)
664 struct bge_softc *sc = device_get_softc(dev);
668 KASSERT(phy == sc->bge_phyno,
669 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
671 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
672 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
673 CSR_WRITE_4(sc, BGE_MI_MODE,
674 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
678 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
679 BGE_MIPHY(phy) | BGE_MIREG(reg));
681 /* Poll for the PHY register access to complete. */
682 for (i = 0; i < BGE_TIMEOUT; i++) {
684 val = CSR_READ_4(sc, BGE_MI_COMM);
685 if ((val & BGE_MICOMM_BUSY) == 0) {
687 val = CSR_READ_4(sc, BGE_MI_COMM);
691 if (i == BGE_TIMEOUT) {
692 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
693 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
697 /* Restore the autopoll bit if necessary. */
698 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
699 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
703 if (val & BGE_MICOMM_READFAIL)
706 return (val & 0xFFFF);
710 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
712 struct bge_softc *sc = device_get_softc(dev);
715 KASSERT(phy == sc->bge_phyno,
716 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
718 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
719 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
722 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
723 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
724 CSR_WRITE_4(sc, BGE_MI_MODE,
725 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
729 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
730 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
732 for (i = 0; i < BGE_TIMEOUT; i++) {
734 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
736 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
740 if (i == BGE_TIMEOUT) {
741 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
742 "(phy %d, reg %d, val %d)\n", phy, reg, val);
745 /* Restore the autopoll bit if necessary. */
746 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
747 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
755 bge_miibus_statchg(device_t dev)
757 struct bge_softc *sc;
758 struct mii_data *mii;
760 sc = device_get_softc(dev);
761 mii = device_get_softc(sc->bge_miibus);
763 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
764 (IFM_ACTIVE | IFM_AVALID)) {
765 switch (IFM_SUBTYPE(mii->mii_media_active)) {
773 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
785 if (sc->bge_link == 0)
788 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
789 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
790 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
791 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
793 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
796 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
797 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
799 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
804 * Memory management for jumbo frames.
807 bge_alloc_jumbo_mem(struct bge_softc *sc)
809 struct ifnet *ifp = &sc->arpcom.ac_if;
810 struct bge_jslot *entry;
816 * Create tag for jumbo mbufs.
817 * This is really a bit of a kludge. We allocate a special
818 * jumbo buffer pool which (thanks to the way our DMA
819 * memory allocation works) will consist of contiguous
820 * pages. This means that even though a jumbo buffer might
821 * be larger than a page size, we don't really need to
822 * map it into more than one DMA segment. However, the
823 * default mbuf tag will result in multi-segment mappings,
824 * so we have to create a special jumbo mbuf tag that
825 * lets us get away with mapping the jumbo buffers as
826 * a single segment. I think eventually the driver should
827 * be changed so that it uses ordinary mbufs and cluster
828 * buffers, i.e. jumbo frames can span multiple DMA
829 * descriptors. But that's a project for another day.
833 * Create DMA stuffs for jumbo RX ring.
835 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
836 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
837 &sc->bge_cdata.bge_rx_jumbo_ring_map,
838 (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
839 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
841 if_printf(ifp, "could not create jumbo RX ring\n");
846 * Create DMA stuffs for jumbo buffer block.
848 error = bge_dma_block_alloc(sc, BGE_JMEM,
849 &sc->bge_cdata.bge_jumbo_tag,
850 &sc->bge_cdata.bge_jumbo_map,
851 (void **)&sc->bge_ldata.bge_jumbo_buf,
854 if_printf(ifp, "could not create jumbo buffer\n");
858 SLIST_INIT(&sc->bge_jfree_listhead);
861 * Now divide it up into 9K pieces and save the addresses
862 * in an array. Note that we play an evil trick here by using
863 * the first few bytes in the buffer to hold the the address
864 * of the softc structure for this interface. This is because
865 * bge_jfree() needs it, but it is called by the mbuf management
866 * code which will not pass it to us explicitly.
868 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
869 entry = &sc->bge_cdata.bge_jslots[i];
871 entry->bge_buf = ptr;
872 entry->bge_paddr = paddr;
873 entry->bge_inuse = 0;
875 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
884 bge_free_jumbo_mem(struct bge_softc *sc)
886 /* Destroy jumbo RX ring. */
887 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
888 sc->bge_cdata.bge_rx_jumbo_ring_map,
889 sc->bge_ldata.bge_rx_jumbo_ring);
891 /* Destroy jumbo buffer block. */
892 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
893 sc->bge_cdata.bge_jumbo_map,
894 sc->bge_ldata.bge_jumbo_buf);
898 * Allocate a jumbo buffer.
900 static struct bge_jslot *
901 bge_jalloc(struct bge_softc *sc)
903 struct bge_jslot *entry;
905 lwkt_serialize_enter(&sc->bge_jslot_serializer);
906 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
908 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
909 entry->bge_inuse = 1;
911 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
913 lwkt_serialize_exit(&sc->bge_jslot_serializer);
918 * Adjust usage count on a jumbo buffer.
923 struct bge_jslot *entry = (struct bge_jslot *)arg;
924 struct bge_softc *sc = entry->bge_sc;
927 panic("bge_jref: can't find softc pointer!");
929 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
930 panic("bge_jref: asked to reference buffer "
931 "that we don't manage!");
932 } else if (entry->bge_inuse == 0) {
933 panic("bge_jref: buffer already free!");
935 atomic_add_int(&entry->bge_inuse, 1);
940 * Release a jumbo buffer.
945 struct bge_jslot *entry = (struct bge_jslot *)arg;
946 struct bge_softc *sc = entry->bge_sc;
949 panic("bge_jfree: can't find softc pointer!");
951 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
952 panic("bge_jfree: asked to free buffer that we don't manage!");
953 } else if (entry->bge_inuse == 0) {
954 panic("bge_jfree: buffer already free!");
957 * Possible MP race to 0, use the serializer. The atomic insn
958 * is still needed for races against bge_jref().
960 lwkt_serialize_enter(&sc->bge_jslot_serializer);
961 atomic_subtract_int(&entry->bge_inuse, 1);
962 if (entry->bge_inuse == 0) {
963 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
966 lwkt_serialize_exit(&sc->bge_jslot_serializer);
972 * Intialize a standard receive ring descriptor.
975 bge_newbuf_std(struct bge_softc *sc, int i, int init)
977 struct mbuf *m_new = NULL;
978 bus_dma_segment_t seg;
982 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
985 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
987 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
988 m_adj(m_new, ETHER_ALIGN);
990 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
991 sc->bge_cdata.bge_rx_tmpmap, m_new,
992 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
999 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1000 sc->bge_cdata.bge_rx_std_dmamap[i],
1001 BUS_DMASYNC_POSTREAD);
1002 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1003 sc->bge_cdata.bge_rx_std_dmamap[i]);
1006 map = sc->bge_cdata.bge_rx_tmpmap;
1007 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
1008 sc->bge_cdata.bge_rx_std_dmamap[i] = map;
1010 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
1011 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
1013 bge_setup_rxdesc_std(sc, i);
1018 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
1020 struct bge_rxchain *rc;
1021 struct bge_rx_bd *r;
1023 rc = &sc->bge_cdata.bge_rx_std_chain[i];
1024 r = &sc->bge_ldata.bge_rx_std_ring[i];
1026 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1027 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1028 r->bge_len = rc->bge_mbuf->m_len;
1030 r->bge_flags = BGE_RXBDFLAG_END;
1034 * Initialize a jumbo receive ring descriptor. This allocates
1035 * a jumbo buffer from the pool managed internally by the driver.
1038 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1040 struct mbuf *m_new = NULL;
1041 struct bge_jslot *buf;
1044 /* Allocate the mbuf. */
1045 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1049 /* Allocate the jumbo buffer */
1050 buf = bge_jalloc(sc);
1056 /* Attach the buffer to the mbuf. */
1057 m_new->m_ext.ext_arg = buf;
1058 m_new->m_ext.ext_buf = buf->bge_buf;
1059 m_new->m_ext.ext_free = bge_jfree;
1060 m_new->m_ext.ext_ref = bge_jref;
1061 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1063 m_new->m_flags |= M_EXT;
1065 m_new->m_data = m_new->m_ext.ext_buf;
1066 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1068 paddr = buf->bge_paddr;
1069 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1070 m_adj(m_new, ETHER_ALIGN);
1071 paddr += ETHER_ALIGN;
1074 /* Save necessary information */
1075 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1076 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1078 /* Set up the descriptor. */
1079 bge_setup_rxdesc_jumbo(sc, i);
1084 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1086 struct bge_rx_bd *r;
1087 struct bge_rxchain *rc;
1089 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1090 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1092 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1093 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1094 r->bge_len = rc->bge_mbuf->m_len;
1096 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1100 bge_init_rx_ring_std(struct bge_softc *sc)
1104 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1105 error = bge_newbuf_std(sc, i, 1);
1110 sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1111 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1117 bge_free_rx_ring_std(struct bge_softc *sc)
1121 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1122 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1124 if (rc->bge_mbuf != NULL) {
1125 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1126 sc->bge_cdata.bge_rx_std_dmamap[i]);
1127 m_freem(rc->bge_mbuf);
1128 rc->bge_mbuf = NULL;
1130 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1131 sizeof(struct bge_rx_bd));
1136 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1138 struct bge_rcb *rcb;
1141 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1142 error = bge_newbuf_jumbo(sc, i, 1);
1147 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1149 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1150 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1151 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1153 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1159 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1163 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1164 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1166 if (rc->bge_mbuf != NULL) {
1167 m_freem(rc->bge_mbuf);
1168 rc->bge_mbuf = NULL;
1170 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1171 sizeof(struct bge_rx_bd));
1176 bge_free_tx_ring(struct bge_softc *sc)
1180 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1181 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1182 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1183 sc->bge_cdata.bge_tx_dmamap[i]);
1184 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1185 sc->bge_cdata.bge_tx_chain[i] = NULL;
1187 bzero(&sc->bge_ldata.bge_tx_ring[i],
1188 sizeof(struct bge_tx_bd));
1193 bge_init_tx_ring(struct bge_softc *sc)
1196 sc->bge_tx_saved_considx = 0;
1197 sc->bge_tx_prodidx = 0;
1199 /* Initialize transmit producer index for host-memory send ring. */
1200 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1202 /* 5700 b2 errata */
1203 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1204 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1206 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1207 /* 5700 b2 errata */
1208 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1209 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1215 bge_setmulti(struct bge_softc *sc)
1218 struct ifmultiaddr *ifma;
1219 uint32_t hashes[4] = { 0, 0, 0, 0 };
1222 ifp = &sc->arpcom.ac_if;
1224 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1225 for (i = 0; i < 4; i++)
1226 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1230 /* First, zot all the existing filters. */
1231 for (i = 0; i < 4; i++)
1232 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1234 /* Now program new ones. */
1235 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1236 if (ifma->ifma_addr->sa_family != AF_LINK)
1239 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1240 ETHER_ADDR_LEN) & 0x7f;
1241 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1244 for (i = 0; i < 4; i++)
1245 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1249 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1250 * self-test results.
1253 bge_chipinit(struct bge_softc *sc)
1256 uint32_t dma_rw_ctl;
1259 /* Set endian type before we access any non-PCI registers. */
1260 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1261 BGE_INIT | sc->bge_pci_miscctl, 4);
1263 /* Clear the MAC control register */
1264 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1267 * Clear the MAC statistics block in the NIC's
1270 for (i = BGE_STATS_BLOCK;
1271 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1272 BGE_MEMWIN_WRITE(sc, i, 0);
1274 for (i = BGE_STATUS_BLOCK;
1275 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1276 BGE_MEMWIN_WRITE(sc, i, 0);
1278 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1280 * Fix data corruption caused by non-qword write with WB.
1281 * Fix master abort in PCI mode.
1282 * Fix PCI latency timer.
1284 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1285 val |= (1 << 10) | (1 << 12) | (1 << 13);
1286 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1289 /* Set up the PCI DMA control register. */
1290 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
1291 if (sc->bge_flags & BGE_FLAG_PCIE) {
1293 /* DMA read watermark not used on PCI-E */
1294 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1295 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1297 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1298 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1299 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1300 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1301 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) {
1302 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1303 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1304 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1305 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1306 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1307 uint32_t rd_wat = 0x7;
1310 clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1311 if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) &&
1312 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1314 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1315 } else if (clkctl == 0x6 || clkctl == 0x7) {
1317 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1319 if (sc->bge_asicrev == BGE_ASICREV_BCM5703)
1322 dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1323 (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1324 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1326 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1327 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1331 /* Conventional PCI bus */
1332 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1333 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1334 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1335 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1339 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1340 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1341 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1342 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1343 sc->bge_asicrev == BGE_ASICREV_BCM5701) {
1344 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1345 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1347 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1350 * Set up general mode register.
1352 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1353 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1354 BGE_MODECTL_TX_NO_PHDR_CSUM);
1357 * BCM5701 B5 have a bug causing data corruption when using
1358 * 64-bit DMA reads, which can be terminated early and then
1359 * completed later as 32-bit accesses, in combination with
1362 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1363 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1364 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1367 * Disable memory write invalidate. Apparently it is not supported
1368 * properly by these devices. Also ensure that INTx isn't disabled,
1369 * as these chips need it even when using MSI.
1371 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1372 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1374 /* Set the timer prescaler (always 66Mhz) */
1375 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1377 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1378 DELAY(40); /* XXX */
1380 /* Put PHY into ready state */
1381 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1382 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1390 bge_blockinit(struct bge_softc *sc)
1392 struct bge_rcb *rcb;
1399 * Initialize the memory window pointer register so that
1400 * we can access the first 32K of internal NIC RAM. This will
1401 * allow us to set up the TX send ring RCBs and the RX return
1402 * ring RCBs, plus other things which live in NIC memory.
1404 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1406 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1408 if (!BGE_IS_5705_PLUS(sc)) {
1409 /* Configure mbuf memory pool */
1410 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1411 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1412 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1414 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1416 /* Configure DMA resource pool */
1417 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1418 BGE_DMA_DESCRIPTORS);
1419 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1422 /* Configure mbuf pool watermarks */
1423 if (!BGE_IS_5705_PLUS(sc)) {
1424 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1425 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1426 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1427 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1428 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1429 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1430 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1432 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1433 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1434 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1437 /* Configure DMA resource watermarks */
1438 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1439 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1441 /* Enable buffer manager */
1442 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1443 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1445 /* Poll for buffer manager start indication */
1446 for (i = 0; i < BGE_TIMEOUT; i++) {
1447 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1452 if (i == BGE_TIMEOUT) {
1453 if_printf(&sc->arpcom.ac_if,
1454 "buffer manager failed to start\n");
1458 /* Enable flow-through queues */
1459 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1460 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1462 /* Wait until queue initialization is complete */
1463 for (i = 0; i < BGE_TIMEOUT; i++) {
1464 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1469 if (i == BGE_TIMEOUT) {
1470 if_printf(&sc->arpcom.ac_if,
1471 "flow-through queue init failed\n");
1476 * Summary of rings supported by the controller:
1478 * Standard Receive Producer Ring
1479 * - This ring is used to feed receive buffers for "standard"
1480 * sized frames (typically 1536 bytes) to the controller.
1482 * Jumbo Receive Producer Ring
1483 * - This ring is used to feed receive buffers for jumbo sized
1484 * frames (i.e. anything bigger than the "standard" frames)
1485 * to the controller.
1487 * Mini Receive Producer Ring
1488 * - This ring is used to feed receive buffers for "mini"
1489 * sized frames to the controller.
1490 * - This feature required external memory for the controller
1491 * but was never used in a production system. Should always
1494 * Receive Return Ring
1495 * - After the controller has placed an incoming frame into a
1496 * receive buffer that buffer is moved into a receive return
1497 * ring. The driver is then responsible to passing the
1498 * buffer up to the stack. Many versions of the controller
1499 * support multiple RR rings.
1502 * - This ring is used for outgoing frames. Many versions of
1503 * the controller support multiple send rings.
1506 /* Initialize the standard receive producer ring control block. */
1507 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1508 rcb->bge_hostaddr.bge_addr_lo =
1509 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1510 rcb->bge_hostaddr.bge_addr_hi =
1511 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1512 if (BGE_IS_5705_PLUS(sc)) {
1514 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1515 * Bits 15-2 : Reserved (should be 0)
1516 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1519 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1522 * Ring size is always XXX entries
1523 * Bits 31-16: Maximum RX frame size
1524 * Bits 15-2 : Reserved (should be 0)
1525 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1528 rcb->bge_maxlen_flags =
1529 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1531 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1532 /* Write the standard receive producer ring control block. */
1533 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1534 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1535 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1536 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1537 /* Reset the standard receive producer ring producer index. */
1538 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1541 * Initialize the jumbo RX producer ring control
1542 * block. We set the 'ring disabled' bit in the
1543 * flags field until we're actually ready to start
1544 * using this ring (i.e. once we set the MTU
1545 * high enough to require it).
1547 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1548 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1549 /* Get the jumbo receive producer ring RCB parameters. */
1550 rcb->bge_hostaddr.bge_addr_lo =
1551 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1552 rcb->bge_hostaddr.bge_addr_hi =
1553 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1554 rcb->bge_maxlen_flags =
1555 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1556 BGE_RCB_FLAG_RING_DISABLED);
1557 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1558 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1559 rcb->bge_hostaddr.bge_addr_hi);
1560 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1561 rcb->bge_hostaddr.bge_addr_lo);
1562 /* Program the jumbo receive producer ring RCB parameters. */
1563 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1564 rcb->bge_maxlen_flags);
1565 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1566 /* Reset the jumbo receive producer ring producer index. */
1567 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1570 /* Disable the mini receive producer ring RCB. */
1571 if (BGE_IS_5700_FAMILY(sc)) {
1572 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1573 rcb->bge_maxlen_flags =
1574 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1575 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1576 rcb->bge_maxlen_flags);
1577 /* Reset the mini receive producer ring producer index. */
1578 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1581 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1582 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1583 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1584 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1585 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1586 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1587 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1591 * The BD ring replenish thresholds control how often the
1592 * hardware fetches new BD's from the producer rings in host
1593 * memory. Setting the value too low on a busy system can
1594 * starve the hardware and recue the throughpout.
1596 * Set the BD ring replentish thresholds. The recommended
1597 * values are 1/8th the number of descriptors allocated to
1600 if (BGE_IS_5705_PLUS(sc))
1603 val = BGE_STD_RX_RING_CNT / 8;
1604 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1605 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1606 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1607 BGE_JUMBO_RX_RING_CNT/8);
1611 * Disable all send rings by setting the 'ring disabled' bit
1612 * in the flags field of all the TX send ring control blocks,
1613 * located in NIC memory.
1615 if (!BGE_IS_5705_PLUS(sc)) {
1616 /* 5700 to 5704 had 16 send rings. */
1617 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1621 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1622 for (i = 0; i < limit; i++) {
1623 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1624 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1625 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1626 vrcb += sizeof(struct bge_rcb);
1629 /* Configure send ring RCB 0 (we use only the first ring) */
1630 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1631 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1632 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1633 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1634 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1635 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1636 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1637 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1640 * Disable all receive return rings by setting the
1641 * 'ring diabled' bit in the flags field of all the receive
1642 * return ring control blocks, located in NIC memory.
1644 if (!BGE_IS_5705_PLUS(sc))
1645 limit = BGE_RX_RINGS_MAX;
1646 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1650 /* Disable all receive return rings. */
1651 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1652 for (i = 0; i < limit; i++) {
1653 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1654 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1655 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1656 BGE_RCB_FLAG_RING_DISABLED);
1657 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1658 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1659 (i * (sizeof(uint64_t))), 0);
1660 vrcb += sizeof(struct bge_rcb);
1664 * Set up receive return ring 0. Note that the NIC address
1665 * for RX return rings is 0x0. The return rings live entirely
1666 * within the host, so the nicaddr field in the RCB isn't used.
1668 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1669 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1670 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1671 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1672 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1673 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1674 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1676 /* Set random backoff seed for TX */
1677 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1678 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1679 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1680 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1681 BGE_TX_BACKOFF_SEED_MASK);
1683 /* Set inter-packet gap */
1684 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1687 * Specify which ring to use for packets that don't match
1690 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1693 * Configure number of RX lists. One interrupt distribution
1694 * list, sixteen active lists, one bad frames class.
1696 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1698 /* Inialize RX list placement stats mask. */
1699 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1700 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1702 /* Disable host coalescing until we get it set up */
1703 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1705 /* Poll to make sure it's shut down. */
1706 for (i = 0; i < BGE_TIMEOUT; i++) {
1707 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1712 if (i == BGE_TIMEOUT) {
1713 if_printf(&sc->arpcom.ac_if,
1714 "host coalescing engine failed to idle\n");
1718 /* Set up host coalescing defaults */
1719 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1720 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1721 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1722 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
1723 if (!BGE_IS_5705_PLUS(sc)) {
1724 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1725 sc->bge_rx_coal_ticks_int);
1726 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1727 sc->bge_tx_coal_ticks_int);
1731 * The datasheet (57XX-PG105-R) says BCM5705+ do not
1732 * have following two registers; obviously it is wrong.
1734 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1735 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
1737 /* Set up address of statistics block */
1738 if (!BGE_IS_5705_PLUS(sc)) {
1739 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1740 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1741 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1742 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1744 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1745 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1746 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1749 /* Set up address of status block */
1750 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1751 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1752 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1753 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1754 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1757 * Set up status block partail update size.
1759 * Because only single TX ring, RX produce ring and Rx return ring
1760 * are used, ask device to update only minimum part of status block
1761 * except for BCM5700 AX/BX, whose status block partial update size
1762 * can't be configured.
1764 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1765 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1766 /* XXX Actually reserved on BCM5700 AX/BX */
1767 val = BGE_STATBLKSZ_FULL;
1769 val = BGE_STATBLKSZ_32BYTE;
1773 * Does not seem to have visible effect in both
1774 * bulk data (1472B UDP datagram) and tiny data
1775 * (18B UDP datagram) TX tests.
1777 if (!BGE_IS_CRIPPLED(sc))
1778 val |= BGE_HCCMODE_CLRTICK_TX;
1781 /* Turn on host coalescing state machine */
1782 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1784 /* Turn on RX BD completion state machine and enable attentions */
1785 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1786 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1788 /* Turn on RX list placement state machine */
1789 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1791 /* Turn on RX list selector state machine. */
1792 if (!BGE_IS_5705_PLUS(sc))
1793 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1795 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1796 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1797 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1798 BGE_MACMODE_FRMHDR_DMA_ENB;
1800 if (sc->bge_flags & BGE_FLAG_TBI)
1801 val |= BGE_PORTMODE_TBI;
1802 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1803 val |= BGE_PORTMODE_GMII;
1805 val |= BGE_PORTMODE_MII;
1807 /* Turn on DMA, clear stats */
1808 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1810 /* Set misc. local control, enable interrupts on attentions */
1811 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1814 /* Assert GPIO pins for PHY reset */
1815 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1816 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1817 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1818 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1821 /* Turn on DMA completion state machine */
1822 if (!BGE_IS_5705_PLUS(sc))
1823 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1825 /* Turn on write DMA state machine */
1826 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1827 if (BGE_IS_5755_PLUS(sc)) {
1828 /* Enable host coalescing bug fix. */
1829 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1831 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1832 /* Request larger DMA burst size to get better performance. */
1833 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1835 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1838 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1839 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1840 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1841 sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1843 * Enable fix for read DMA FIFO overruns.
1844 * The fix is to limit the number of RX BDs
1845 * the hardware would fetch at a fime.
1847 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1848 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1849 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1852 /* Turn on read DMA state machine */
1853 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1854 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1855 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1856 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1857 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1858 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1859 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1860 if (sc->bge_flags & BGE_FLAG_PCIE)
1861 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1862 if (sc->bge_flags & BGE_FLAG_TSO)
1863 val |= BGE_RDMAMODE_TSO4_ENABLE;
1864 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1867 /* Turn on RX data completion state machine */
1868 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1870 /* Turn on RX BD initiator state machine */
1871 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1873 /* Turn on RX data and RX BD initiator state machine */
1874 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1876 /* Turn on Mbuf cluster free state machine */
1877 if (!BGE_IS_5705_PLUS(sc))
1878 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1880 /* Turn on send BD completion state machine */
1881 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1883 /* Turn on send data completion state machine */
1884 val = BGE_SDCMODE_ENABLE;
1885 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1886 val |= BGE_SDCMODE_CDELAY;
1887 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1889 /* Turn on send data initiator state machine */
1890 if (sc->bge_flags & BGE_FLAG_TSO)
1891 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1892 BGE_SDIMODE_HW_LSO_PRE_DMA);
1894 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1896 /* Turn on send BD initiator state machine */
1897 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1899 /* Turn on send BD selector state machine */
1900 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1902 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1903 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1904 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1906 /* ack/clear link change events */
1907 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1908 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1909 BGE_MACSTAT_LINK_CHANGED);
1910 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1913 * Enable attention when the link has changed state for
1914 * devices that use auto polling.
1916 if (sc->bge_flags & BGE_FLAG_TBI) {
1917 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1919 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1920 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1923 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1924 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1925 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1926 BGE_EVTENB_MI_INTERRUPT);
1931 * Clear any pending link state attention.
1932 * Otherwise some link state change events may be lost until attention
1933 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1934 * It's not necessary on newer BCM chips - perhaps enabling link
1935 * state change attentions implies clearing pending attention.
1937 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1938 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1939 BGE_MACSTAT_LINK_CHANGED);
1941 /* Enable link state change attentions. */
1942 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1948 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1949 * against our list and return its name if we find a match. Note
1950 * that since the Broadcom controller contains VPD support, we
1951 * can get the device name string from the controller itself instead
1952 * of the compiled-in string. This is a little slow, but it guarantees
1953 * we'll always announce the right product name.
1956 bge_probe(device_t dev)
1958 const struct bge_type *t;
1959 uint16_t product, vendor;
1961 product = pci_get_device(dev);
1962 vendor = pci_get_vendor(dev);
1964 for (t = bge_devs; t->bge_name != NULL; t++) {
1965 if (vendor == t->bge_vid && product == t->bge_did)
1968 if (t->bge_name == NULL)
1971 device_set_desc(dev, t->bge_name);
1976 bge_attach(device_t dev)
1979 struct bge_softc *sc;
1980 uint32_t hwcfg = 0, misccfg;
1981 int error = 0, rid, capmask;
1982 uint8_t ether_addr[ETHER_ADDR_LEN];
1983 uint16_t product, vendor;
1984 driver_intr_t *intr_func;
1985 uintptr_t mii_priv = 0;
1989 sc = device_get_softc(dev);
1991 callout_init_mp(&sc->bge_stat_timer);
1992 lwkt_serialize_init(&sc->bge_jslot_serializer);
1994 product = pci_get_device(dev);
1995 vendor = pci_get_vendor(dev);
1997 #ifndef BURN_BRIDGES
1998 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2001 irq = pci_read_config(dev, PCIR_INTLINE, 4);
2002 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
2004 device_printf(dev, "chip is in D%d power mode "
2005 "-- setting to D0\n", pci_get_powerstate(dev));
2007 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2009 pci_write_config(dev, PCIR_INTLINE, irq, 4);
2010 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
2012 #endif /* !BURN_BRIDGE */
2015 * Map control/status registers.
2017 pci_enable_busmaster(dev);
2020 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2023 if (sc->bge_res == NULL) {
2024 device_printf(dev, "couldn't map memory\n");
2028 sc->bge_btag = rman_get_bustag(sc->bge_res);
2029 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2031 /* Save various chip information */
2033 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2034 BGE_PCIMISCCTL_ASICREV_SHIFT;
2035 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2036 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */
2037 sc->bge_flags |= BGE_FLAG_CPMU;
2038 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2040 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2041 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2043 /* Save chipset family. */
2044 switch (sc->bge_asicrev) {
2045 case BGE_ASICREV_BCM5755:
2046 case BGE_ASICREV_BCM5761:
2047 case BGE_ASICREV_BCM5784:
2048 case BGE_ASICREV_BCM5785:
2049 case BGE_ASICREV_BCM5787:
2050 case BGE_ASICREV_BCM57780:
2051 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2055 case BGE_ASICREV_BCM5700:
2056 case BGE_ASICREV_BCM5701:
2057 case BGE_ASICREV_BCM5703:
2058 case BGE_ASICREV_BCM5704:
2059 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2062 case BGE_ASICREV_BCM5714_A0:
2063 case BGE_ASICREV_BCM5780:
2064 case BGE_ASICREV_BCM5714:
2065 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2068 case BGE_ASICREV_BCM5750:
2069 case BGE_ASICREV_BCM5752:
2070 case BGE_ASICREV_BCM5906:
2071 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2074 case BGE_ASICREV_BCM5705:
2075 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2079 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2080 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2082 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2083 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2084 (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2085 misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2086 sc->bge_flags |= BGE_FLAG_5788;
2088 /* BCM5755 or higher and BCM5906 have short DMA bug. */
2089 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2090 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2093 * Increase STD RX ring prod index by at most 8 for BCM5750,
2094 * BCM5752 and BCM5755 to workaround hardware errata.
2096 if (sc->bge_asicrev == BGE_ASICREV_BCM5750 ||
2097 sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2098 sc->bge_asicrev == BGE_ASICREV_BCM5755)
2099 sc->bge_rx_wreg = 8;
2102 * Check if this is a PCI-X or PCI Express device.
2104 if (BGE_IS_5705_PLUS(sc)) {
2105 if (pci_is_pcie(dev)) {
2106 sc->bge_flags |= BGE_FLAG_PCIE;
2107 sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2108 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2112 * Check if the device is in PCI-X Mode.
2113 * (This bit is not valid on PCI Express controllers.)
2115 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2116 BGE_PCISTATE_PCI_BUSMODE) == 0) {
2117 sc->bge_flags |= BGE_FLAG_PCIX;
2118 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2119 sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2123 device_printf(dev, "CHIP ID 0x%08x; "
2124 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2125 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2126 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2127 : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2131 * The 40bit DMA bug applies to the 5714/5715 controllers and is
2132 * not actually a MAC controller bug but an issue with the embedded
2133 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2135 if ((sc->bge_flags & BGE_FLAG_PCIX) &&
2136 (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0)))
2137 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2140 * When using the BCM5701 in PCI-X mode, data corruption has
2141 * been observed in the first few bytes of some received packets.
2142 * Aligning the packet buffer in memory eliminates the corruption.
2143 * Unfortunately, this misaligns the packet payloads. On platforms
2144 * which do not support unaligned accesses, we will realign the
2145 * payloads by copying the received packets.
2147 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2148 (sc->bge_flags & BGE_FLAG_PCIX))
2149 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2151 if (!BGE_IS_CRIPPLED(sc)) {
2152 if (device_getenv_int(dev, "status_tag", 1)) {
2153 sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2154 sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2156 device_printf(dev, "enable status tag\n");
2160 if (BGE_IS_5755_PLUS(sc)) {
2162 * BCM5754 and BCM5787 shares the same ASIC id so
2163 * explicit device id check is required.
2164 * Due to unknown reason TSO does not work on BCM5755M.
2166 if (product != PCI_PRODUCT_BROADCOM_BCM5754 &&
2167 product != PCI_PRODUCT_BROADCOM_BCM5754M &&
2168 product != PCI_PRODUCT_BROADCOM_BCM5755M)
2169 sc->bge_flags |= BGE_FLAG_TSO;
2173 * Set various PHY quirk flags.
2176 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2177 sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2178 pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2179 mii_priv |= BRGPHY_FLAG_NO_3LED;
2181 capmask = MII_CAPMASK_DEFAULT;
2182 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2183 (misccfg == 0x4000 || misccfg == 0x8000)) ||
2184 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2185 vendor == PCI_VENDOR_BROADCOM &&
2186 (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2187 product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2188 product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2189 (vendor == PCI_VENDOR_BROADCOM &&
2190 (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2191 product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2192 product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2193 product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2194 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2196 capmask &= ~BMSR_EXTSTAT;
2199 mii_priv |= BRGPHY_FLAG_WIRESPEED;
2200 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2201 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2202 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2203 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2204 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2205 mii_priv &= ~BRGPHY_FLAG_WIRESPEED;
2207 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2208 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2209 mii_priv |= BRGPHY_FLAG_CRC_BUG;
2211 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2212 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2213 mii_priv |= BRGPHY_FLAG_ADC_BUG;
2215 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2216 mii_priv |= BRGPHY_FLAG_5704_A0;
2218 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2219 mii_priv |= BRGPHY_FLAG_5906;
2221 if (BGE_IS_5705_PLUS(sc) &&
2222 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2223 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2224 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2225 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2226 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2227 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2228 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2229 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2230 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2231 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2232 product != PCI_PRODUCT_BROADCOM_BCM5756)
2233 mii_priv |= BRGPHY_FLAG_JITTER_BUG;
2234 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2235 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM;
2237 mii_priv |= BRGPHY_FLAG_BER_BUG;
2242 * Allocate interrupt
2244 msi_enable = bge_msi_enable;
2245 if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) {
2246 /* If "tagged status" is disabled, don't enable MSI */
2248 } else if (msi_enable) {
2249 msi_enable = 0; /* Disable by default */
2250 if (BGE_IS_575X_PLUS(sc)) {
2252 /* XXX we filter all 5714 chips */
2253 if (sc->bge_asicrev == BGE_ASICREV_BCM5714 ||
2254 (sc->bge_asicrev == BGE_ASICREV_BCM5750 &&
2255 (sc->bge_chiprev == BGE_CHIPREV_5750_AX ||
2256 sc->bge_chiprev == BGE_CHIPREV_5750_BX)))
2258 else if (BGE_IS_5755_PLUS(sc) ||
2259 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2260 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI;
2264 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) {
2265 device_printf(dev, "no MSI capability\n");
2270 sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid,
2273 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid,
2275 if (sc->bge_irq == NULL) {
2276 device_printf(dev, "couldn't map interrupt\n");
2281 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2284 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI;
2286 /* Initialize if_name earlier, so if_printf could be used */
2287 ifp = &sc->arpcom.ac_if;
2288 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2290 /* Try to reset the chip. */
2293 if (bge_chipinit(sc)) {
2294 device_printf(dev, "chip initialization failed\n");
2300 * Get station address
2302 error = bge_get_eaddr(sc, ether_addr);
2304 device_printf(dev, "failed to read station address\n");
2308 /* 5705/5750 limits RX return ring to 512 entries. */
2309 if (BGE_IS_5705_PLUS(sc))
2310 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2312 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2314 error = bge_dma_alloc(sc);
2318 /* Set default tuneable values. */
2319 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2320 sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2321 sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2322 sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2323 sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2324 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2325 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2326 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2327 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2328 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2330 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2331 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2332 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2333 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2335 sc->bge_tx_wreg = BGE_TX_WREG_NSEGS;
2337 /* Set up TX spare and reserved descriptor count */
2338 if (sc->bge_flags & BGE_FLAG_TSO) {
2339 sc->bge_txspare = BGE_NSEG_SPARE_TSO;
2340 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO;
2342 sc->bge_txspare = BGE_NSEG_SPARE;
2343 sc->bge_txrsvd = BGE_NSEG_RSVD;
2346 /* Set up ifnet structure */
2348 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2349 ifp->if_ioctl = bge_ioctl;
2350 ifp->if_start = bge_start;
2351 #ifdef IFPOLL_ENABLE
2352 ifp->if_npoll = bge_npoll;
2354 ifp->if_watchdog = bge_watchdog;
2355 ifp->if_init = bge_init;
2356 ifp->if_mtu = ETHERMTU;
2357 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2358 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2359 ifq_set_ready(&ifp->if_snd);
2362 * 5700 B0 chips do not support checksumming correctly due
2365 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2366 ifp->if_capabilities |= IFCAP_HWCSUM;
2367 ifp->if_hwassist |= BGE_CSUM_FEATURES;
2369 if (sc->bge_flags & BGE_FLAG_TSO) {
2370 ifp->if_capabilities |= IFCAP_TSO;
2371 ifp->if_hwassist |= CSUM_TSO;
2373 ifp->if_capenable = ifp->if_capabilities;
2376 * Figure out what sort of media we have by checking the
2377 * hardware config word in the first 32k of NIC internal memory,
2378 * or fall back to examining the EEPROM if necessary.
2379 * Note: on some BCM5700 cards, this value appears to be unset.
2380 * If that's the case, we have to rely on identifying the NIC
2381 * by its PCI subsystem ID, as we do below for the SysKonnect
2384 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2385 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2387 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2389 device_printf(dev, "failed to read EEPROM\n");
2393 hwcfg = ntohl(hwcfg);
2396 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2397 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2398 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2399 if (BGE_IS_5714_FAMILY(sc))
2400 sc->bge_flags |= BGE_FLAG_MII_SERDES;
2402 sc->bge_flags |= BGE_FLAG_TBI;
2406 if (sc->bge_flags & BGE_FLAG_CPMU)
2407 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2409 sc->bge_mi_mode = BGE_MIMODE_BASE;
2410 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2411 /* Enable auto polling for BCM570[0-5]. */
2412 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2415 /* Setup link status update stuffs */
2416 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2417 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2418 sc->bge_link_upd = bge_bcm5700_link_upd;
2419 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2420 } else if (sc->bge_flags & BGE_FLAG_TBI) {
2421 sc->bge_link_upd = bge_tbi_link_upd;
2422 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2423 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2424 sc->bge_link_upd = bge_autopoll_link_upd;
2425 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2427 sc->bge_link_upd = bge_copper_link_upd;
2428 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2432 * Broadcom's own driver always assumes the internal
2433 * PHY is at GMII address 1. On some chips, the PHY responds
2434 * to accesses at all addresses, which could cause us to
2435 * bogusly attach the PHY 32 times at probe type. Always
2436 * restricting the lookup to address 1 is simpler than
2437 * trying to figure out which chips revisions should be
2442 if (sc->bge_flags & BGE_FLAG_TBI) {
2443 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2444 bge_ifmedia_upd, bge_ifmedia_sts);
2445 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2446 ifmedia_add(&sc->bge_ifmedia,
2447 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2448 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2449 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2450 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2452 struct mii_probe_args mii_args;
2454 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2455 mii_args.mii_probemask = 1 << sc->bge_phyno;
2456 mii_args.mii_capmask = capmask;
2457 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2458 mii_args.mii_priv = mii_priv;
2460 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2462 device_printf(dev, "MII without any PHY!\n");
2468 * Create sysctl nodes.
2470 sysctl_ctx_init(&sc->bge_sysctl_ctx);
2471 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2472 SYSCTL_STATIC_CHILDREN(_hw),
2474 device_get_nameunit(dev),
2476 if (sc->bge_sysctl_tree == NULL) {
2477 device_printf(dev, "can't add sysctl node\n");
2482 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2483 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2484 OID_AUTO, "rx_coal_ticks",
2485 CTLTYPE_INT | CTLFLAG_RW,
2486 sc, 0, bge_sysctl_rx_coal_ticks, "I",
2487 "Receive coalescing ticks (usec).");
2488 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2489 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2490 OID_AUTO, "tx_coal_ticks",
2491 CTLTYPE_INT | CTLFLAG_RW,
2492 sc, 0, bge_sysctl_tx_coal_ticks, "I",
2493 "Transmit coalescing ticks (usec).");
2494 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2495 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2496 OID_AUTO, "rx_coal_bds",
2497 CTLTYPE_INT | CTLFLAG_RW,
2498 sc, 0, bge_sysctl_rx_coal_bds, "I",
2499 "Receive max coalesced BD count.");
2500 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2501 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2502 OID_AUTO, "tx_coal_bds",
2503 CTLTYPE_INT | CTLFLAG_RW,
2504 sc, 0, bge_sysctl_tx_coal_bds, "I",
2505 "Transmit max coalesced BD count.");
2507 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2508 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2509 OID_AUTO, "tx_wreg", CTLFLAG_RW,
2510 &sc->bge_tx_wreg, 0,
2511 "# of segments before writing to hardware register");
2513 if (sc->bge_flags & BGE_FLAG_PCIE) {
2515 * A common design characteristic for many Broadcom
2516 * client controllers is that they only support a
2517 * single outstanding DMA read operation on the PCIe
2518 * bus. This means that it will take twice as long to
2519 * fetch a TX frame that is split into header and
2520 * payload buffers as it does to fetch a single,
2521 * contiguous TX frame (2 reads vs. 1 read). For these
2522 * controllers, coalescing buffers to reduce the number
2523 * of memory reads is effective way to get maximum
2524 * performance(about 940Mbps). Without collapsing TX
2525 * buffers the maximum TCP bulk transfer performance
2526 * is about 850Mbps. However forcing coalescing mbufs
2527 * consumes a lot of CPU cycles, so leave it off by
2530 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2531 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2532 OID_AUTO, "force_defrag", CTLFLAG_RW,
2533 &sc->bge_force_defrag, 0,
2534 "Force defragment on TX path");
2536 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2537 if (!BGE_IS_5705_PLUS(sc)) {
2538 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2539 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2540 "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2541 sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2542 "Receive coalescing ticks "
2543 "during interrupt (usec).");
2544 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2545 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2546 "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2547 sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2548 "Transmit coalescing ticks "
2549 "during interrupt (usec).");
2551 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2552 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2553 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2554 sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2555 "Receive max coalesced BD count during interrupt.");
2556 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2557 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2558 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2559 sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2560 "Transmit max coalesced BD count during interrupt.");
2564 * Call MI attach routine.
2566 ether_ifattach(ifp, ether_addr, NULL);
2568 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
2570 #ifdef IFPOLL_ENABLE
2572 ifpoll_compat_setup(&sc->bge_npoll,
2573 &sc->bge_sysctl_ctx, sc->bge_sysctl_tree, device_get_unit(dev),
2574 ifp->if_serializer);
2577 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2578 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
2579 intr_func = bge_msi_oneshot;
2581 device_printf(dev, "oneshot MSI\n");
2583 intr_func = bge_msi;
2585 } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2586 intr_func = bge_intr_legacy;
2588 intr_func = bge_intr_crippled;
2590 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2591 &sc->bge_intrhand, ifp->if_serializer);
2593 ether_ifdetach(ifp);
2594 device_printf(dev, "couldn't set up irq\n");
2605 bge_detach(device_t dev)
2607 struct bge_softc *sc = device_get_softc(dev);
2609 if (device_is_attached(dev)) {
2610 struct ifnet *ifp = &sc->arpcom.ac_if;
2612 lwkt_serialize_enter(ifp->if_serializer);
2615 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2616 lwkt_serialize_exit(ifp->if_serializer);
2618 ether_ifdetach(ifp);
2621 if (sc->bge_flags & BGE_FLAG_TBI)
2622 ifmedia_removeall(&sc->bge_ifmedia);
2624 device_delete_child(dev, sc->bge_miibus);
2625 bus_generic_detach(dev);
2627 if (sc->bge_irq != NULL) {
2628 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid,
2631 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2632 pci_release_msi(dev);
2634 if (sc->bge_res != NULL) {
2635 bus_release_resource(dev, SYS_RES_MEMORY,
2636 BGE_PCI_BAR0, sc->bge_res);
2639 if (sc->bge_sysctl_tree != NULL)
2640 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2648 bge_reset(struct bge_softc *sc)
2651 uint32_t cachesize, command, pcistate, reset;
2652 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2657 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2658 sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2659 if (sc->bge_flags & BGE_FLAG_PCIE)
2660 write_op = bge_writemem_direct;
2662 write_op = bge_writemem_ind;
2664 write_op = bge_writereg_ind;
2667 /* Save some important PCI state. */
2668 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2669 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2670 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2672 pci_write_config(dev, BGE_PCI_MISC_CTL,
2673 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2674 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2675 sc->bge_pci_miscctl, 4);
2677 /* Disable fastboot on controllers that support it. */
2678 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2679 BGE_IS_5755_PLUS(sc)) {
2681 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2682 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2686 * Write the magic number to SRAM at offset 0xB50.
2687 * When firmware finishes its initialization it will
2688 * write ~BGE_MAGIC_NUMBER to the same location.
2690 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2692 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2694 /* XXX: Broadcom Linux driver. */
2695 if (sc->bge_flags & BGE_FLAG_PCIE) {
2696 /* Force PCI-E 1.0a mode */
2697 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2698 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2699 (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2700 BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2701 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2702 BGE_PCIE_PHY_TSTCTL_PSCRAM);
2704 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2705 /* Prevent PCIE link training during global reset */
2706 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2712 * Set GPHY Power Down Override to leave GPHY
2713 * powered up in D0 uninitialized.
2715 if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2716 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2718 /* Issue global reset */
2719 write_op(sc, BGE_MISC_CFG, reset);
2721 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2722 uint32_t status, ctrl;
2724 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2725 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2726 status | BGE_VCPU_STATUS_DRV_RESET);
2727 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2728 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2729 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2734 /* XXX: Broadcom Linux driver. */
2735 if (sc->bge_flags & BGE_FLAG_PCIE) {
2738 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2741 DELAY(500000); /* wait for link training to complete */
2742 v = pci_read_config(dev, 0xc4, 4);
2743 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2746 devctl = pci_read_config(dev,
2747 sc->bge_pciecap + PCIER_DEVCTRL, 2);
2749 /* Disable no snoop and disable relaxed ordering. */
2750 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2752 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2753 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) {
2754 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2755 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2758 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2761 /* Clear error status. */
2762 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2763 PCIEM_DEVSTS_CORR_ERR |
2764 PCIEM_DEVSTS_NFATAL_ERR |
2765 PCIEM_DEVSTS_FATAL_ERR |
2766 PCIEM_DEVSTS_UNSUPP_REQ, 2);
2769 /* Reset some of the PCI state that got zapped by reset */
2770 pci_write_config(dev, BGE_PCI_MISC_CTL,
2771 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2772 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2773 sc->bge_pci_miscctl, 4);
2774 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2775 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2776 write_op(sc, BGE_MISC_CFG, (65 << 1));
2779 * Disable PCI-X relaxed ordering to ensure status block update
2780 * comes first then packet buffer DMA. Otherwise driver may
2781 * read stale status block.
2783 if (sc->bge_flags & BGE_FLAG_PCIX) {
2786 devctl = pci_read_config(dev,
2787 sc->bge_pcixcap + PCIXR_COMMAND, 2);
2788 devctl &= ~PCIXM_COMMAND_ERO;
2789 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2790 devctl &= ~PCIXM_COMMAND_MAX_READ;
2791 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2792 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2793 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2794 PCIXM_COMMAND_MAX_READ);
2795 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2797 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2802 * Enable memory arbiter and re-enable MSI if necessary.
2804 if (BGE_IS_5714_FAMILY(sc)) {
2807 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2809 * Resetting BCM5714 family will clear MSI
2810 * enable bit; restore it after resetting.
2812 PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL,
2813 PCIM_MSICTRL_MSI_ENABLE, 2);
2814 BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE);
2816 val = CSR_READ_4(sc, BGE_MARB_MODE);
2817 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2819 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2822 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2823 for (i = 0; i < BGE_TIMEOUT; i++) {
2824 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2825 if (val & BGE_VCPU_STATUS_INIT_DONE)
2829 if (i == BGE_TIMEOUT) {
2830 if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2835 * Poll until we see the 1's complement of the magic number.
2836 * This indicates that the firmware initialization
2839 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2840 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2841 if (val == ~BGE_MAGIC_NUMBER)
2845 if (i == BGE_FIRMWARE_TIMEOUT) {
2846 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2847 "timed out, found 0x%08x\n", val);
2852 * XXX Wait for the value of the PCISTATE register to
2853 * return to its original pre-reset state. This is a
2854 * fairly good indicator of reset completion. If we don't
2855 * wait for the reset to fully complete, trying to read
2856 * from the device's non-PCI registers may yield garbage
2859 for (i = 0; i < BGE_TIMEOUT; i++) {
2860 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2865 /* Fix up byte swapping */
2866 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2867 BGE_MODECTL_BYTESWAP_DATA);
2869 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2872 * The 5704 in TBI mode apparently needs some special
2873 * adjustment to insure the SERDES drive level is set
2876 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2877 (sc->bge_flags & BGE_FLAG_TBI)) {
2880 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2881 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2882 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2885 /* XXX: Broadcom Linux driver. */
2886 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2887 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2888 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2891 /* Enable Data FIFO protection. */
2892 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2893 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2900 * Frame reception handling. This is called if there's a frame
2901 * on the receive return list.
2903 * Note: we have to be able to handle two possibilities here:
2904 * 1) the frame is from the jumbo recieve ring
2905 * 2) the frame is from the standard receive ring
2909 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int count)
2912 int stdcnt = 0, jumbocnt = 0;
2914 ifp = &sc->arpcom.ac_if;
2916 while (sc->bge_rx_saved_considx != rx_prod && count != 0) {
2917 struct bge_rx_bd *cur_rx;
2919 struct mbuf *m = NULL;
2920 uint16_t vlan_tag = 0;
2926 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2928 rxidx = cur_rx->bge_idx;
2929 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2932 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2934 vlan_tag = cur_rx->bge_vlan_tag;
2937 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2938 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2941 if (rxidx != sc->bge_jumbo) {
2942 IFNET_STAT_INC(ifp, ierrors, 1);
2943 if_printf(ifp, "sw jumbo index(%d) "
2944 "and hw jumbo index(%d) mismatch, drop!\n",
2945 sc->bge_jumbo, rxidx);
2946 bge_setup_rxdesc_jumbo(sc, rxidx);
2950 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2951 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2952 IFNET_STAT_INC(ifp, ierrors, 1);
2953 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2956 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2957 IFNET_STAT_INC(ifp, ierrors, 1);
2958 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2964 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2967 if (rxidx != sc->bge_std) {
2968 IFNET_STAT_INC(ifp, ierrors, 1);
2969 if_printf(ifp, "sw std index(%d) "
2970 "and hw std index(%d) mismatch, drop!\n",
2971 sc->bge_std, rxidx);
2972 bge_setup_rxdesc_std(sc, rxidx);
2977 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2978 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2979 IFNET_STAT_INC(ifp, ierrors, 1);
2980 bge_setup_rxdesc_std(sc, sc->bge_std);
2984 if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2985 IFNET_STAT_INC(ifp, ierrors, 1);
2986 bge_setup_rxdesc_std(sc, sc->bge_std);
2990 if (sc->bge_rx_wreg > 0 && stdcnt >= sc->bge_rx_wreg) {
2991 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO,
2999 IFNET_STAT_INC(ifp, ipackets, 1);
3000 #if !defined(__i386__) && !defined(__x86_64__)
3002 * The x86 allows unaligned accesses, but for other
3003 * platforms we must make sure the payload is aligned.
3005 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3006 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3008 m->m_data += ETHER_ALIGN;
3011 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3012 m->m_pkthdr.rcvif = ifp;
3014 if (ifp->if_capenable & IFCAP_RXCSUM) {
3015 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3016 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3017 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
3018 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3020 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
3021 m->m_pkthdr.len >= BGE_MIN_FRAMELEN) {
3022 m->m_pkthdr.csum_data =
3023 cur_rx->bge_tcp_udp_csum;
3024 m->m_pkthdr.csum_flags |=
3025 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3030 * If we received a packet with a vlan tag, pass it
3031 * to vlan_input() instead of ether_input().
3034 m->m_flags |= M_VLANTAG;
3035 m->m_pkthdr.ether_vlantag = vlan_tag;
3037 ifp->if_input(ifp, m);
3040 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3042 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3044 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3048 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3052 ifp = &sc->arpcom.ac_if;
3055 * Go through our tx ring and free mbufs for those
3056 * frames that have been sent.
3058 while (sc->bge_tx_saved_considx != tx_cons) {
3061 idx = sc->bge_tx_saved_considx;
3062 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3063 IFNET_STAT_INC(ifp, opackets, 1);
3064 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3065 sc->bge_cdata.bge_tx_dmamap[idx]);
3066 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3067 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3070 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3074 if ((BGE_TX_RING_CNT - sc->bge_txcnt) >=
3075 (sc->bge_txrsvd + sc->bge_txspare))
3076 ifq_clr_oactive(&ifp->if_snd);
3078 if (sc->bge_txcnt == 0)
3081 if (!ifq_is_empty(&ifp->if_snd))
3085 #ifdef IFPOLL_ENABLE
3088 bge_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycles)
3090 struct bge_softc *sc = ifp->if_softc;
3091 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3092 uint16_t rx_prod, tx_cons;
3094 ASSERT_SERIALIZED(ifp->if_serializer);
3096 if (sc->bge_npoll.ifpc_stcount-- == 0) {
3097 sc->bge_npoll.ifpc_stcount = sc->bge_npoll.ifpc_stfrac;
3099 * Process link state changes.
3104 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
3105 sc->bge_status_tag = sblk->bge_status_tag;
3107 * Use a load fence to ensure that status_tag
3108 * is saved before rx_prod and tx_cons.
3113 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3114 if (sc->bge_rx_saved_considx != rx_prod)
3115 bge_rxeof(sc, rx_prod, cycles);
3117 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3118 if (sc->bge_tx_saved_considx != tx_cons)
3119 bge_txeof(sc, tx_cons);
3121 if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
3122 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3124 if (sc->bge_coal_chg)
3125 bge_coal_change(sc);
3129 bge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3131 struct bge_softc *sc = ifp->if_softc;
3133 ASSERT_SERIALIZED(ifp->if_serializer);
3136 int cpuid = sc->bge_npoll.ifpc_cpuid;
3138 info->ifpi_rx[cpuid].poll_func = bge_npoll_compat;
3139 info->ifpi_rx[cpuid].arg = NULL;
3140 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
3142 if (ifp->if_flags & IFF_RUNNING)
3143 bge_disable_intr(sc);
3144 ifq_set_cpuid(&ifp->if_snd, cpuid);
3146 if (ifp->if_flags & IFF_RUNNING)
3147 bge_enable_intr(sc);
3148 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
3152 #endif /* IFPOLL_ENABLE */
3155 bge_intr_crippled(void *xsc)
3157 struct bge_softc *sc = xsc;
3158 struct ifnet *ifp = &sc->arpcom.ac_if;
3163 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3164 * disable interrupts by writing nonzero like we used to, since with
3165 * our current organization this just gives complications and
3166 * pessimizations for re-enabling interrupts. We used to have races
3167 * instead of the necessary complications. Disabling interrupts
3168 * would just reduce the chance of a status update while we are
3169 * running (by switching to the interrupt-mode coalescence
3170 * parameters), but this chance is already very low so it is more
3171 * efficient to get another interrupt than prevent it.
3173 * We do the ack first to ensure another interrupt if there is a
3174 * status update after the ack. We don't check for the status
3175 * changing later because it is more efficient to get another
3176 * interrupt than prevent it, not quite as above (not checking is
3177 * a smaller optimization than not toggling the interrupt enable,
3178 * since checking doesn't involve PCI accesses and toggling require
3179 * the status check). So toggling would probably be a pessimization
3180 * even with MSI. It would only be needed for using a task queue.
3182 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3185 * Process link state changes.
3189 if (ifp->if_flags & IFF_RUNNING) {
3190 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3191 uint16_t rx_prod, tx_cons;
3193 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3194 if (sc->bge_rx_saved_considx != rx_prod)
3195 bge_rxeof(sc, rx_prod, -1);
3197 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3198 if (sc->bge_tx_saved_considx != tx_cons)
3199 bge_txeof(sc, tx_cons);
3202 if (sc->bge_coal_chg)
3203 bge_coal_change(sc);
3207 bge_intr_legacy(void *xsc)
3209 struct bge_softc *sc = xsc;
3210 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3212 if (sc->bge_status_tag == sblk->bge_status_tag) {
3215 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3216 if (val & BGE_PCISTAT_INTR_NOTACT)
3222 * Interrupt will have to be disabled if tagged status
3223 * is used, else interrupt will always be asserted on
3224 * certain chips (at least on BCM5750 AX/BX).
3226 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3234 struct bge_softc *sc = xsc;
3236 /* Disable interrupt first */
3237 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3242 bge_msi_oneshot(void *xsc)
3248 bge_intr(struct bge_softc *sc)
3250 struct ifnet *ifp = &sc->arpcom.ac_if;
3251 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3252 uint16_t rx_prod, tx_cons;
3255 sc->bge_status_tag = sblk->bge_status_tag;
3257 * Use a load fence to ensure that status_tag is saved
3258 * before rx_prod, tx_cons and status.
3262 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3263 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3264 status = sblk->bge_status;
3266 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt)
3269 if (ifp->if_flags & IFF_RUNNING) {
3270 if (sc->bge_rx_saved_considx != rx_prod)
3271 bge_rxeof(sc, rx_prod, -1);
3273 if (sc->bge_tx_saved_considx != tx_cons)
3274 bge_txeof(sc, tx_cons);
3277 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3279 if (sc->bge_coal_chg)
3280 bge_coal_change(sc);
3286 struct bge_softc *sc = xsc;
3287 struct ifnet *ifp = &sc->arpcom.ac_if;
3289 lwkt_serialize_enter(ifp->if_serializer);
3291 if (BGE_IS_5705_PLUS(sc))
3292 bge_stats_update_regs(sc);
3294 bge_stats_update(sc);
3296 if (sc->bge_flags & BGE_FLAG_TBI) {
3298 * Since in TBI mode auto-polling can't be used we should poll
3299 * link status manually. Here we register pending link event
3300 * and trigger interrupt.
3303 if (BGE_IS_CRIPPLED(sc))
3304 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3306 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3307 } else if (!sc->bge_link) {
3308 mii_tick(device_get_softc(sc->bge_miibus));
3311 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3313 lwkt_serialize_exit(ifp->if_serializer);
3317 bge_stats_update_regs(struct bge_softc *sc)
3319 struct ifnet *ifp = &sc->arpcom.ac_if;
3320 struct bge_mac_stats_regs stats;
3324 s = (uint32_t *)&stats;
3325 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3326 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3330 IFNET_STAT_SET(ifp, collisions,
3331 (stats.dot3StatsSingleCollisionFrames +
3332 stats.dot3StatsMultipleCollisionFrames +
3333 stats.dot3StatsExcessiveCollisions +
3334 stats.dot3StatsLateCollisions));
3338 bge_stats_update(struct bge_softc *sc)
3340 struct ifnet *ifp = &sc->arpcom.ac_if;
3343 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3345 #define READ_STAT(sc, stats, stat) \
3346 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3348 IFNET_STAT_SET(ifp, collisions,
3349 (READ_STAT(sc, stats,
3350 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3351 READ_STAT(sc, stats,
3352 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3353 READ_STAT(sc, stats,
3354 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3355 READ_STAT(sc, stats,
3356 txstats.dot3StatsLateCollisions.bge_addr_lo)));
3361 IFNET_STAT_SET(ifp, collisions,
3362 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3363 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3364 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3365 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions));
3370 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3371 * pointers to descriptors.
3374 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
3377 struct bge_tx_bd *d = NULL, *last_d;
3378 uint16_t csum_flags = 0, mss = 0;
3379 bus_dma_segment_t segs[BGE_NSEG_NEW];
3381 int error, maxsegs, nsegs, idx, i;
3382 struct mbuf *m_head = *m_head0, *m_new;
3384 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3385 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags);
3389 } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) {
3390 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3391 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3392 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3393 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3394 if (m_head->m_flags & M_LASTFRAG)
3395 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3396 else if (m_head->m_flags & M_FRAG)
3397 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3401 map = sc->bge_cdata.bge_tx_dmamap[idx];
3403 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd;
3404 KASSERT(maxsegs >= sc->bge_txspare,
3405 ("not enough segments %d", maxsegs));
3407 if (maxsegs > BGE_NSEG_NEW)
3408 maxsegs = BGE_NSEG_NEW;
3411 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3412 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3413 * but when such padded frames employ the bge IP/TCP checksum
3414 * offload, the hardware checksum assist gives incorrect results
3415 * (possibly from incorporating its own padding into the UDP/TCP
3416 * checksum; who knows). If we pad such runts with zeros, the
3417 * onboard checksum comes out correct.
3419 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3420 m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) {
3421 error = m_devpad(m_head, BGE_MIN_FRAMELEN);
3426 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3427 m_new = bge_defrag_shortdma(m_head);
3428 if (m_new == NULL) {
3432 *m_head0 = m_head = m_new;
3434 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3435 sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3436 m_head->m_next != NULL) {
3438 * Forcefully defragment mbuf chain to overcome hardware
3439 * limitation which only support a single outstanding
3440 * DMA read operation. If it fails, keep moving on using
3441 * the original mbuf chain.
3443 m_new = m_defrag(m_head, MB_DONTWAIT);
3445 *m_head0 = m_head = m_new;
3448 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3449 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3452 *segs_used += nsegs;
3455 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3457 for (i = 0; ; i++) {
3458 d = &sc->bge_ldata.bge_tx_ring[idx];
3460 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3461 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3462 d->bge_len = segs[i].ds_len;
3463 d->bge_flags = csum_flags;
3468 BGE_INC(idx, BGE_TX_RING_CNT);
3472 /* Set vlan tag to the first segment of the packet. */
3473 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3474 if (m_head->m_flags & M_VLANTAG) {
3475 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3476 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3478 d->bge_vlan_tag = 0;
3481 /* Mark the last segment as end of packet... */
3482 last_d->bge_flags |= BGE_TXBDFLAG_END;
3485 * Insure that the map for this transmission is placed at
3486 * the array index of the last descriptor in this chain.
3488 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3489 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3490 sc->bge_cdata.bge_tx_chain[idx] = m_head;
3491 sc->bge_txcnt += nsegs;
3493 BGE_INC(idx, BGE_TX_RING_CNT);
3504 bge_xmit(struct bge_softc *sc, uint32_t prodidx)
3507 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3508 /* 5700 b2 errata */
3509 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3510 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3514 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3515 * to the mbuf data regions directly in the transmit descriptors.
3518 bge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3520 struct bge_softc *sc = ifp->if_softc;
3521 struct mbuf *m_head = NULL;
3525 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
3527 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
3530 prodidx = sc->bge_tx_prodidx;
3532 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3533 m_head = ifq_dequeue(&ifp->if_snd);
3539 * The code inside the if() block is never reached since we
3540 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3541 * requests to checksum TCP/UDP in a fragmented packet.
3544 * safety overkill. If this is a fragmented packet chain
3545 * with delayed TCP/UDP checksums, then only encapsulate
3546 * it if we have enough descriptors to handle the entire
3548 * (paranoia -- may not actually be needed)
3550 if ((m_head->m_flags & M_FIRSTFRAG) &&
3551 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3552 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3553 m_head->m_pkthdr.csum_data + sc->bge_txrsvd) {
3554 ifq_set_oactive(&ifp->if_snd);
3555 ifq_prepend(&ifp->if_snd, m_head);
3561 * Sanity check: avoid coming within bge_txrsvd
3562 * descriptors of the end of the ring. Also make
3563 * sure there are bge_txspare descriptors for
3564 * jumbo buffers' defragmentation.
3566 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3567 (sc->bge_txrsvd + sc->bge_txspare)) {
3568 ifq_set_oactive(&ifp->if_snd);
3569 ifq_prepend(&ifp->if_snd, m_head);
3574 * Pack the data into the transmit ring. If we
3575 * don't have room, set the OACTIVE flag and wait
3576 * for the NIC to drain the ring.
3578 if (bge_encap(sc, &m_head, &prodidx, &nsegs)) {
3579 ifq_set_oactive(&ifp->if_snd);
3580 IFNET_STAT_INC(ifp, oerrors, 1);
3584 if (nsegs >= sc->bge_tx_wreg) {
3585 bge_xmit(sc, prodidx);
3589 ETHER_BPF_MTAP(ifp, m_head);
3592 * Set a timeout in case the chip goes out to lunch.
3598 bge_xmit(sc, prodidx);
3599 sc->bge_tx_prodidx = prodidx;
3605 struct bge_softc *sc = xsc;
3606 struct ifnet *ifp = &sc->arpcom.ac_if;
3610 ASSERT_SERIALIZED(ifp->if_serializer);
3612 /* Cancel pending I/O and flush buffers. */
3618 * Init the various state machines, ring
3619 * control blocks and firmware.
3621 if (bge_blockinit(sc)) {
3622 if_printf(ifp, "initialization failure\n");
3628 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3629 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3631 /* Load our MAC address. */
3632 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3633 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3634 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3636 /* Enable or disable promiscuous mode as needed. */
3639 /* Program multicast filter. */
3643 if (bge_init_rx_ring_std(sc)) {
3644 if_printf(ifp, "RX ring initialization failed\n");
3650 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3651 * memory to insure that the chip has in fact read the first
3652 * entry of the ring.
3654 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3656 for (i = 0; i < 10; i++) {
3658 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3659 if (v == (MCLBYTES - ETHER_ALIGN))
3663 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3666 /* Init jumbo RX ring. */
3667 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3668 if (bge_init_rx_ring_jumbo(sc)) {
3669 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3675 /* Init our RX return ring index */
3676 sc->bge_rx_saved_considx = 0;
3679 bge_init_tx_ring(sc);
3681 /* Enable TX MAC state machine lockup fix. */
3682 mode = CSR_READ_4(sc, BGE_TX_MODE);
3683 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3684 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3685 /* Turn on transmitter */
3686 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3688 /* Turn on receiver */
3689 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3692 * Set the number of good frames to receive after RX MBUF
3693 * Low Watermark has been reached. After the RX MAC receives
3694 * this number of frames, it will drop subsequent incoming
3695 * frames until the MBUF High Watermark is reached.
3697 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3699 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
3701 if_printf(ifp, "MSI_MODE: %#x\n",
3702 CSR_READ_4(sc, BGE_MSI_MODE));
3707 * Linux driver turns it on for all chips supporting MSI?!
3709 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
3712 * According to 5722-PG101-R,
3713 * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to
3716 BGE_SETBIT(sc, BGE_PCIE_TRANSACT,
3717 BGE_PCIE_TRANSACT_ONESHOT_MSI);
3721 /* Tell firmware we're alive. */
3722 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3724 /* Enable host interrupts if polling(4) is not enabled. */
3725 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3726 #ifdef IFPOLL_ENABLE
3727 if (ifp->if_flags & IFF_NPOLLING)
3728 bge_disable_intr(sc);
3731 bge_enable_intr(sc);
3733 bge_ifmedia_upd(ifp);
3735 ifp->if_flags |= IFF_RUNNING;
3736 ifq_clr_oactive(&ifp->if_snd);
3738 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3742 * Set media options.
3745 bge_ifmedia_upd(struct ifnet *ifp)
3747 struct bge_softc *sc = ifp->if_softc;
3749 /* If this is a 1000baseX NIC, enable the TBI port. */
3750 if (sc->bge_flags & BGE_FLAG_TBI) {
3751 struct ifmedia *ifm = &sc->bge_ifmedia;
3753 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3756 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3759 * The BCM5704 ASIC appears to have a special
3760 * mechanism for programming the autoneg
3761 * advertisement registers in TBI mode.
3763 if (!bge_fake_autoneg &&
3764 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3767 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3768 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3769 sgdig |= BGE_SGDIGCFG_AUTO |
3770 BGE_SGDIGCFG_PAUSE_CAP |
3771 BGE_SGDIGCFG_ASYM_PAUSE;
3772 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3773 sgdig | BGE_SGDIGCFG_SEND);
3775 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3779 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3780 BGE_CLRBIT(sc, BGE_MAC_MODE,
3781 BGE_MACMODE_HALF_DUPLEX);
3783 BGE_SETBIT(sc, BGE_MAC_MODE,
3784 BGE_MACMODE_HALF_DUPLEX);
3791 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3795 if (mii->mii_instance) {
3796 struct mii_softc *miisc;
3798 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3799 mii_phy_reset(miisc);
3804 * Force an interrupt so that we will call bge_link_upd
3805 * if needed and clear any pending link state attention.
3806 * Without this we are not getting any further interrupts
3807 * for link state changes and thus will not UP the link and
3808 * not be able to send in bge_start. The only way to get
3809 * things working was to receive a packet and get an RX
3812 * bge_tick should help for fiber cards and we might not
3813 * need to do this here if BGE_FLAG_TBI is set but as
3814 * we poll for fiber anyway it should not harm.
3816 if (BGE_IS_CRIPPLED(sc))
3817 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3819 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3825 * Report current media status.
3828 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3830 struct bge_softc *sc = ifp->if_softc;
3832 if (sc->bge_flags & BGE_FLAG_TBI) {
3833 ifmr->ifm_status = IFM_AVALID;
3834 ifmr->ifm_active = IFM_ETHER;
3835 if (CSR_READ_4(sc, BGE_MAC_STS) &
3836 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3837 ifmr->ifm_status |= IFM_ACTIVE;
3839 ifmr->ifm_active |= IFM_NONE;
3843 ifmr->ifm_active |= IFM_1000_SX;
3844 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3845 ifmr->ifm_active |= IFM_HDX;
3847 ifmr->ifm_active |= IFM_FDX;
3849 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3852 ifmr->ifm_active = mii->mii_media_active;
3853 ifmr->ifm_status = mii->mii_media_status;
3858 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3860 struct bge_softc *sc = ifp->if_softc;
3861 struct ifreq *ifr = (struct ifreq *)data;
3862 int mask, error = 0;
3864 ASSERT_SERIALIZED(ifp->if_serializer);
3868 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3869 (BGE_IS_JUMBO_CAPABLE(sc) &&
3870 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3872 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3873 ifp->if_mtu = ifr->ifr_mtu;
3874 if (ifp->if_flags & IFF_RUNNING)
3879 if (ifp->if_flags & IFF_UP) {
3880 if (ifp->if_flags & IFF_RUNNING) {
3881 mask = ifp->if_flags ^ sc->bge_if_flags;
3884 * If only the state of the PROMISC flag
3885 * changed, then just use the 'set promisc
3886 * mode' command instead of reinitializing
3887 * the entire NIC. Doing a full re-init
3888 * means reloading the firmware and waiting
3889 * for it to start up, which may take a
3890 * second or two. Similarly for ALLMULTI.
3892 if (mask & IFF_PROMISC)
3894 if (mask & IFF_ALLMULTI)
3899 } else if (ifp->if_flags & IFF_RUNNING) {
3902 sc->bge_if_flags = ifp->if_flags;
3906 if (ifp->if_flags & IFF_RUNNING)
3911 if (sc->bge_flags & BGE_FLAG_TBI) {
3912 error = ifmedia_ioctl(ifp, ifr,
3913 &sc->bge_ifmedia, command);
3915 struct mii_data *mii;
3917 mii = device_get_softc(sc->bge_miibus);
3918 error = ifmedia_ioctl(ifp, ifr,
3919 &mii->mii_media, command);
3923 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3924 if (mask & IFCAP_HWCSUM) {
3925 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3926 if (ifp->if_capenable & IFCAP_TXCSUM)
3927 ifp->if_hwassist |= BGE_CSUM_FEATURES;
3929 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
3931 if (mask & IFCAP_TSO) {
3932 ifp->if_capenable ^= IFCAP_TSO;
3933 if (ifp->if_capenable & IFCAP_TSO)
3934 ifp->if_hwassist |= CSUM_TSO;
3936 ifp->if_hwassist &= ~CSUM_TSO;
3940 error = ether_ioctl(ifp, command, data);
3947 bge_watchdog(struct ifnet *ifp)
3949 struct bge_softc *sc = ifp->if_softc;
3951 if_printf(ifp, "watchdog timeout -- resetting\n");
3955 IFNET_STAT_INC(ifp, oerrors, 1);
3957 if (!ifq_is_empty(&ifp->if_snd))
3962 * Stop the adapter and free any mbufs allocated to the
3966 bge_stop(struct bge_softc *sc)
3968 struct ifnet *ifp = &sc->arpcom.ac_if;
3970 ASSERT_SERIALIZED(ifp->if_serializer);
3972 callout_stop(&sc->bge_stat_timer);
3975 * Disable all of the receiver blocks
3977 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3978 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3979 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3980 if (BGE_IS_5700_FAMILY(sc))
3981 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3982 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3983 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3984 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3987 * Disable all of the transmit blocks
3989 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3990 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3991 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3992 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3993 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3994 if (BGE_IS_5700_FAMILY(sc))
3995 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3996 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3999 * Shut down all of the memory managers and related
4002 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4003 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4004 if (BGE_IS_5700_FAMILY(sc))
4005 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4006 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4007 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4008 if (!BGE_IS_5705_PLUS(sc)) {
4009 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4010 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4013 /* Disable host interrupts. */
4014 bge_disable_intr(sc);
4017 * Tell firmware we're shutting down.
4019 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4021 /* Free the RX lists. */
4022 bge_free_rx_ring_std(sc);
4024 /* Free jumbo RX list. */
4025 if (BGE_IS_JUMBO_CAPABLE(sc))
4026 bge_free_rx_ring_jumbo(sc);
4028 /* Free TX buffers. */
4029 bge_free_tx_ring(sc);
4031 sc->bge_status_tag = 0;
4033 sc->bge_coal_chg = 0;
4035 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4037 ifp->if_flags &= ~IFF_RUNNING;
4038 ifq_clr_oactive(&ifp->if_snd);
4043 * Stop all chip I/O so that the kernel's probe routines don't
4044 * get confused by errant DMAs when rebooting.
4047 bge_shutdown(device_t dev)
4049 struct bge_softc *sc = device_get_softc(dev);
4050 struct ifnet *ifp = &sc->arpcom.ac_if;
4052 lwkt_serialize_enter(ifp->if_serializer);
4055 lwkt_serialize_exit(ifp->if_serializer);
4059 bge_suspend(device_t dev)
4061 struct bge_softc *sc = device_get_softc(dev);
4062 struct ifnet *ifp = &sc->arpcom.ac_if;
4064 lwkt_serialize_enter(ifp->if_serializer);
4066 lwkt_serialize_exit(ifp->if_serializer);
4072 bge_resume(device_t dev)
4074 struct bge_softc *sc = device_get_softc(dev);
4075 struct ifnet *ifp = &sc->arpcom.ac_if;
4077 lwkt_serialize_enter(ifp->if_serializer);
4079 if (ifp->if_flags & IFF_UP) {
4082 if (!ifq_is_empty(&ifp->if_snd))
4086 lwkt_serialize_exit(ifp->if_serializer);
4092 bge_setpromisc(struct bge_softc *sc)
4094 struct ifnet *ifp = &sc->arpcom.ac_if;
4096 if (ifp->if_flags & IFF_PROMISC)
4097 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
4099 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
4103 bge_dma_free(struct bge_softc *sc)
4107 /* Destroy RX mbuf DMA stuffs. */
4108 if (sc->bge_cdata.bge_rx_mtag != NULL) {
4109 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
4110 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4111 sc->bge_cdata.bge_rx_std_dmamap[i]);
4113 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4114 sc->bge_cdata.bge_rx_tmpmap);
4115 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4118 /* Destroy TX mbuf DMA stuffs. */
4119 if (sc->bge_cdata.bge_tx_mtag != NULL) {
4120 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4121 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4122 sc->bge_cdata.bge_tx_dmamap[i]);
4124 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4127 /* Destroy standard RX ring */
4128 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
4129 sc->bge_cdata.bge_rx_std_ring_map,
4130 sc->bge_ldata.bge_rx_std_ring);
4132 if (BGE_IS_JUMBO_CAPABLE(sc))
4133 bge_free_jumbo_mem(sc);
4135 /* Destroy RX return ring */
4136 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
4137 sc->bge_cdata.bge_rx_return_ring_map,
4138 sc->bge_ldata.bge_rx_return_ring);
4140 /* Destroy TX ring */
4141 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
4142 sc->bge_cdata.bge_tx_ring_map,
4143 sc->bge_ldata.bge_tx_ring);
4145 /* Destroy status block */
4146 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
4147 sc->bge_cdata.bge_status_map,
4148 sc->bge_ldata.bge_status_block);
4150 /* Destroy statistics block */
4151 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
4152 sc->bge_cdata.bge_stats_map,
4153 sc->bge_ldata.bge_stats);
4155 /* Destroy the parent tag */
4156 if (sc->bge_cdata.bge_parent_tag != NULL)
4157 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
4161 bge_dma_alloc(struct bge_softc *sc)
4163 struct ifnet *ifp = &sc->arpcom.ac_if;
4168 lowaddr = BUS_SPACE_MAXADDR;
4169 if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
4170 lowaddr = BGE_DMA_MAXADDR_40BIT;
4173 * Allocate the parent bus DMA tag appropriate for PCI.
4175 * All of the NetExtreme/NetLink controllers have 4GB boundary
4177 * Whenever an address crosses a multiple of the 4GB boundary
4178 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
4179 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
4180 * state machine will lockup and cause the device to hang.
4182 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
4183 lowaddr, BUS_SPACE_MAXADDR,
4185 BUS_SPACE_MAXSIZE_32BIT, 0,
4186 BUS_SPACE_MAXSIZE_32BIT,
4187 0, &sc->bge_cdata.bge_parent_tag);
4189 if_printf(ifp, "could not allocate parent dma tag\n");
4194 * Create DMA tag and maps for RX mbufs.
4196 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
4197 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4198 NULL, NULL, MCLBYTES, 1, MCLBYTES,
4199 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
4200 &sc->bge_cdata.bge_rx_mtag);
4202 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
4206 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
4207 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
4209 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4210 sc->bge_cdata.bge_rx_mtag = NULL;
4214 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
4215 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
4217 &sc->bge_cdata.bge_rx_std_dmamap[i]);
4221 for (j = 0; j < i; ++j) {
4222 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4223 sc->bge_cdata.bge_rx_std_dmamap[j]);
4225 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4226 sc->bge_cdata.bge_rx_mtag = NULL;
4228 if_printf(ifp, "could not create DMA map for RX\n");
4234 * Create DMA tag and maps for TX mbufs.
4236 if (sc->bge_flags & BGE_FLAG_TSO)
4237 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4239 txmaxsz = BGE_JUMBO_FRAMELEN;
4240 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
4241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4243 txmaxsz, BGE_NSEG_NEW, PAGE_SIZE,
4244 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
4246 &sc->bge_cdata.bge_tx_mtag);
4248 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
4252 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4253 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
4254 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4255 &sc->bge_cdata.bge_tx_dmamap[i]);
4259 for (j = 0; j < i; ++j) {
4260 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4261 sc->bge_cdata.bge_tx_dmamap[j]);
4263 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4264 sc->bge_cdata.bge_tx_mtag = NULL;
4266 if_printf(ifp, "could not create DMA map for TX\n");
4272 * Create DMA stuffs for standard RX ring.
4274 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4275 &sc->bge_cdata.bge_rx_std_ring_tag,
4276 &sc->bge_cdata.bge_rx_std_ring_map,
4277 (void *)&sc->bge_ldata.bge_rx_std_ring,
4278 &sc->bge_ldata.bge_rx_std_ring_paddr);
4280 if_printf(ifp, "could not create std RX ring\n");
4285 * Create jumbo buffer pool.
4287 if (BGE_IS_JUMBO_CAPABLE(sc)) {
4288 error = bge_alloc_jumbo_mem(sc);
4290 if_printf(ifp, "could not create jumbo buffer pool\n");
4296 * Create DMA stuffs for RX return ring.
4298 error = bge_dma_block_alloc(sc,
4299 BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt),
4300 &sc->bge_cdata.bge_rx_return_ring_tag,
4301 &sc->bge_cdata.bge_rx_return_ring_map,
4302 (void *)&sc->bge_ldata.bge_rx_return_ring,
4303 &sc->bge_ldata.bge_rx_return_ring_paddr);
4305 if_printf(ifp, "could not create RX ret ring\n");
4310 * Create DMA stuffs for TX ring.
4312 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
4313 &sc->bge_cdata.bge_tx_ring_tag,
4314 &sc->bge_cdata.bge_tx_ring_map,
4315 (void *)&sc->bge_ldata.bge_tx_ring,
4316 &sc->bge_ldata.bge_tx_ring_paddr);
4318 if_printf(ifp, "could not create TX ring\n");
4323 * Create DMA stuffs for status block.
4325 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
4326 &sc->bge_cdata.bge_status_tag,
4327 &sc->bge_cdata.bge_status_map,
4328 (void *)&sc->bge_ldata.bge_status_block,
4329 &sc->bge_ldata.bge_status_block_paddr);
4331 if_printf(ifp, "could not create status block\n");
4336 * Create DMA stuffs for statistics block.
4338 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
4339 &sc->bge_cdata.bge_stats_tag,
4340 &sc->bge_cdata.bge_stats_map,
4341 (void *)&sc->bge_ldata.bge_stats,
4342 &sc->bge_ldata.bge_stats_paddr);
4344 if_printf(ifp, "could not create stats block\n");
4351 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4352 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4357 error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
4358 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4359 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4363 *tag = dmem.dmem_tag;
4364 *map = dmem.dmem_map;
4365 *addr = dmem.dmem_addr;
4366 *paddr = dmem.dmem_busaddr;
4372 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4375 bus_dmamap_unload(tag, map);
4376 bus_dmamem_free(tag, addr, map);
4377 bus_dma_tag_destroy(tag);
4382 * Grrr. The link status word in the status block does
4383 * not work correctly on the BCM5700 rev AX and BX chips,
4384 * according to all available information. Hence, we have
4385 * to enable MII interrupts in order to properly obtain
4386 * async link changes. Unfortunately, this also means that
4387 * we have to read the MAC status register to detect link
4388 * changes, thereby adding an additional register access to
4389 * the interrupt handler.
4391 * XXX: perhaps link state detection procedure used for
4392 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4395 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
4397 struct ifnet *ifp = &sc->arpcom.ac_if;
4398 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4402 if (!sc->bge_link &&
4403 (mii->mii_media_status & IFM_ACTIVE) &&
4404 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4407 if_printf(ifp, "link UP\n");
4408 } else if (sc->bge_link &&
4409 (!(mii->mii_media_status & IFM_ACTIVE) ||
4410 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4413 if_printf(ifp, "link DOWN\n");
4416 /* Clear the interrupt. */
4417 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4418 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4419 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4423 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4425 struct ifnet *ifp = &sc->arpcom.ac_if;
4427 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4430 * Sometimes PCS encoding errors are detected in
4431 * TBI mode (on fiber NICs), and for some reason
4432 * the chip will signal them as link changes.
4433 * If we get a link change event, but the 'PCS
4434 * encoding error' bit in the MAC status register
4435 * is set, don't bother doing a link check.
4436 * This avoids spurious "gigabit link up" messages
4437 * that sometimes appear on fiber NICs during
4438 * periods of heavy traffic.
4440 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4441 if (!sc->bge_link) {
4443 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4444 BGE_CLRBIT(sc, BGE_MAC_MODE,
4445 BGE_MACMODE_TBI_SEND_CFGS);
4447 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4450 if_printf(ifp, "link UP\n");
4452 ifp->if_link_state = LINK_STATE_UP;
4453 if_link_state_change(ifp);
4455 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4460 if_printf(ifp, "link DOWN\n");
4462 ifp->if_link_state = LINK_STATE_DOWN;
4463 if_link_state_change(ifp);
4467 #undef PCS_ENCODE_ERR
4469 /* Clear the attention. */
4470 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4471 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4472 BGE_MACSTAT_LINK_CHANGED);
4476 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4478 struct ifnet *ifp = &sc->arpcom.ac_if;
4479 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4482 bge_miibus_statchg(sc->bge_dev);
4486 if_printf(ifp, "link UP\n");
4488 if_printf(ifp, "link DOWN\n");
4491 /* Clear the attention. */
4492 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4493 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4494 BGE_MACSTAT_LINK_CHANGED);
4498 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4500 struct ifnet *ifp = &sc->arpcom.ac_if;
4501 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4505 if (!sc->bge_link &&
4506 (mii->mii_media_status & IFM_ACTIVE) &&
4507 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4510 if_printf(ifp, "link UP\n");
4511 } else if (sc->bge_link &&
4512 (!(mii->mii_media_status & IFM_ACTIVE) ||
4513 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4516 if_printf(ifp, "link DOWN\n");
4519 /* Clear the attention. */
4520 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4521 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4522 BGE_MACSTAT_LINK_CHANGED);
4526 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4528 struct bge_softc *sc = arg1;
4530 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4531 &sc->bge_rx_coal_ticks,
4532 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4533 BGE_RX_COAL_TICKS_CHG);
4537 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4539 struct bge_softc *sc = arg1;
4541 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4542 &sc->bge_tx_coal_ticks,
4543 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4544 BGE_TX_COAL_TICKS_CHG);
4548 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4550 struct bge_softc *sc = arg1;
4552 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4553 &sc->bge_rx_coal_bds,
4554 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4555 BGE_RX_COAL_BDS_CHG);
4559 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4561 struct bge_softc *sc = arg1;
4563 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4564 &sc->bge_tx_coal_bds,
4565 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4566 BGE_TX_COAL_BDS_CHG);
4570 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4572 struct bge_softc *sc = arg1;
4574 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4575 &sc->bge_rx_coal_ticks_int,
4576 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4577 BGE_RX_COAL_TICKS_INT_CHG);
4581 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4583 struct bge_softc *sc = arg1;
4585 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4586 &sc->bge_tx_coal_ticks_int,
4587 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4588 BGE_TX_COAL_TICKS_INT_CHG);
4592 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4594 struct bge_softc *sc = arg1;
4596 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4597 &sc->bge_rx_coal_bds_int,
4598 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4599 BGE_RX_COAL_BDS_INT_CHG);
4603 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4605 struct bge_softc *sc = arg1;
4607 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4608 &sc->bge_tx_coal_bds_int,
4609 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4610 BGE_TX_COAL_BDS_INT_CHG);
4614 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4615 int coal_min, int coal_max, uint32_t coal_chg_mask)
4617 struct bge_softc *sc = arg1;
4618 struct ifnet *ifp = &sc->arpcom.ac_if;
4621 lwkt_serialize_enter(ifp->if_serializer);
4624 error = sysctl_handle_int(oidp, &v, 0, req);
4625 if (!error && req->newptr != NULL) {
4626 if (v < coal_min || v > coal_max) {
4630 sc->bge_coal_chg |= coal_chg_mask;
4634 lwkt_serialize_exit(ifp->if_serializer);
4639 bge_coal_change(struct bge_softc *sc)
4641 struct ifnet *ifp = &sc->arpcom.ac_if;
4643 ASSERT_SERIALIZED(ifp->if_serializer);
4645 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4646 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4647 sc->bge_rx_coal_ticks);
4649 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4652 if_printf(ifp, "rx_coal_ticks -> %u\n",
4653 sc->bge_rx_coal_ticks);
4657 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4658 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4659 sc->bge_tx_coal_ticks);
4661 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4664 if_printf(ifp, "tx_coal_ticks -> %u\n",
4665 sc->bge_tx_coal_ticks);
4669 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) {
4670 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4671 sc->bge_rx_coal_bds);
4673 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4676 if_printf(ifp, "rx_coal_bds -> %u\n",
4677 sc->bge_rx_coal_bds);
4681 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) {
4682 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4683 sc->bge_tx_coal_bds);
4685 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4688 if_printf(ifp, "tx_max_coal_bds -> %u\n",
4689 sc->bge_tx_coal_bds);
4693 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) {
4694 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
4695 sc->bge_rx_coal_ticks_int);
4697 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT);
4700 if_printf(ifp, "rx_coal_ticks_int -> %u\n",
4701 sc->bge_rx_coal_ticks_int);
4705 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) {
4706 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
4707 sc->bge_tx_coal_ticks_int);
4709 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT);
4712 if_printf(ifp, "tx_coal_ticks_int -> %u\n",
4713 sc->bge_tx_coal_ticks_int);
4717 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) {
4718 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4719 sc->bge_rx_coal_bds_int);
4721 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
4724 if_printf(ifp, "rx_coal_bds_int -> %u\n",
4725 sc->bge_rx_coal_bds_int);
4729 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) {
4730 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4731 sc->bge_tx_coal_bds_int);
4733 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4736 if_printf(ifp, "tx_coal_bds_int -> %u\n",
4737 sc->bge_tx_coal_bds_int);
4741 sc->bge_coal_chg = 0;
4745 bge_enable_intr(struct bge_softc *sc)
4747 struct ifnet *ifp = &sc->arpcom.ac_if;
4749 lwkt_serialize_handler_enable(ifp->if_serializer);
4754 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4755 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
4756 /* XXX Linux driver */
4757 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4761 * Unmask the interrupt when we stop polling.
4763 PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4764 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4767 * Trigger another interrupt, since above writing
4768 * to interrupt mailbox0 may acknowledge pending
4771 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4775 bge_disable_intr(struct bge_softc *sc)
4777 struct ifnet *ifp = &sc->arpcom.ac_if;
4780 * Mask the interrupt when we start polling.
4782 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4783 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4786 * Acknowledge possible asserted interrupt.
4788 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4790 sc->bge_npoll.ifpc_stcount = 0;
4792 lwkt_serialize_handler_disable(ifp->if_serializer);
4796 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4801 mac_addr = bge_readmem_ind(sc, 0x0c14);
4802 if ((mac_addr >> 16) == 0x484b) {
4803 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4804 ether_addr[1] = (uint8_t)mac_addr;
4805 mac_addr = bge_readmem_ind(sc, 0x0c18);
4806 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4807 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4808 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4809 ether_addr[5] = (uint8_t)mac_addr;
4816 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4818 int mac_offset = BGE_EE_MAC_OFFSET;
4820 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4821 mac_offset = BGE_EE_MAC_OFFSET_5906;
4823 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4827 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4829 if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4832 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4837 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4839 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4840 /* NOTE: Order is critical */
4842 bge_get_eaddr_nvram,
4843 bge_get_eaddr_eeprom,
4846 const bge_eaddr_fcn_t *func;
4848 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4849 if ((*func)(sc, eaddr) == 0)
4852 return (*func == NULL ? ENXIO : 0);
4856 * NOTE: 'm' is not freed upon failure
4859 bge_defrag_shortdma(struct mbuf *m)
4865 * If device receive two back-to-back send BDs with less than
4866 * or equal to 8 total bytes then the device may hang. The two
4867 * back-to-back send BDs must in the same frame for this failure
4868 * to occur. Scan mbuf chains and see whether two back-to-back
4869 * send BDs are there. If this is the case, allocate new mbuf
4870 * and copy the frame to workaround the silicon bug.
4872 for (n = m, found = 0; n != NULL; n = n->m_next) {
4883 n = m_defrag(m, MB_DONTWAIT);
4890 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
4894 BGE_CLRBIT(sc, reg, bit);
4895 for (i = 0; i < BGE_TIMEOUT; i++) {
4896 if ((CSR_READ_4(sc, reg) & bit) == 0)
4903 bge_link_poll(struct bge_softc *sc)
4907 status = CSR_READ_4(sc, BGE_MAC_STS);
4908 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
4909 sc->bge_link_evt = 0;
4910 sc->bge_link_upd(sc, status);
4915 bge_enable_msi(struct bge_softc *sc)
4919 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4920 msi_mode |= BGE_MSIMODE_ENABLE;
4921 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
4923 * According to all of the datasheets that are publicly
4924 * available, bit 5 of the MSI_MODE is defined to be
4925 * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on
4926 * which "oneshot MSI" is enabled. However, it is always
4927 * safe to clear it here.
4929 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4931 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4935 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp,
4936 uint16_t *mss0, uint16_t *flags0)
4941 int thoff, iphlen, hoff, hlen;
4942 uint16_t flags, mss;
4945 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4947 hoff = m->m_pkthdr.csum_lhlen;
4948 iphlen = m->m_pkthdr.csum_iphlen;
4949 thoff = m->m_pkthdr.csum_thlen;
4951 KASSERT(hoff > 0, ("invalid ether header len"));
4952 KASSERT(iphlen > 0, ("invalid ip header len"));
4953 KASSERT(thoff > 0, ("invalid tcp header len"));
4955 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4956 m = m_pullup(m, hoff + iphlen + thoff);
4963 ip = mtodoff(m, struct ip *, hoff);
4964 th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4966 mss = m->m_pkthdr.tso_segsz;
4967 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4969 ip->ip_len = htons(mss + iphlen + thoff);
4972 hlen = (iphlen + thoff) >> 2;
4973 mss |= (hlen << 11);