2 * Copyright 2005 Nicolai Haehnle et al.
3 * Copyright 2008 Advanced Micro Devices, Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Nicolai Haehnle
27 * $FreeBSD: head/sys/dev/drm2/radeon/r300_reg.h 254885 2013-08-25 19:37:15Z dumbbell $
32 #define R300_SURF_TILE_MACRO (1<<16)
33 #define R300_SURF_TILE_MICRO (2<<16)
34 #define R300_SURF_TILE_BOTH (3<<16)
37 #define R300_MC_INIT_MISC_LAT_TIMER 0x180
38 # define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0
39 # define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4
40 # define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8
41 # define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12
42 # define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16
43 # define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20
44 # define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24
45 # define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28
47 #define R300_MC_INIT_GFX_LAT_TIMER 0x154
48 # define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0
49 # define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4
50 # define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8
51 # define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12
52 # define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16
53 # define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20
54 # define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24
55 # define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28
58 * This file contains registers and constants for the R300. They have been
59 * found mostly by examining command buffers captured using glxtest, as well
60 * as by extrapolating some known registers and constants from the R200.
61 * I am fairly certain that they are correct unless stated otherwise
65 #define R300_SE_VPORT_XSCALE 0x1D98
66 #define R300_SE_VPORT_XOFFSET 0x1D9C
67 #define R300_SE_VPORT_YSCALE 0x1DA0
68 #define R300_SE_VPORT_YOFFSET 0x1DA4
69 #define R300_SE_VPORT_ZSCALE 0x1DA8
70 #define R300_SE_VPORT_ZOFFSET 0x1DAC
74 * Vertex Array Processing (VAP) Control
75 * Stolen from r200 code from Christoph Brill (It's a guess!)
77 #define R300_VAP_CNTL 0x2080
79 /* This register is written directly and also starts data section
80 * in many 3d CP_PACKET3's
82 #define R300_VAP_VF_CNTL 0x2084
83 # define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
84 # define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
85 # define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
86 # define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
87 # define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
88 # define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
89 # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
90 # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
91 # define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
92 # define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
93 # define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
94 # define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
96 # define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
97 /* State based - direct writes to registers trigger vertex
99 # define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
100 # define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
101 # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
102 # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
104 /* I don't think I saw these three used.. */
105 # define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
106 # define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
107 # define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
109 /* index size - when not set the indices are assumed to be 16 bit */
110 # define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
111 /* number of vertices */
112 # define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
114 /* BEGIN: Wild guesses */
115 #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
116 # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
117 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
118 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
119 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
120 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
121 # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
123 #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
124 /* each of the following is 3 bits wide, specifies number
126 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
127 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
128 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
129 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
130 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
131 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
132 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
133 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
134 /* END: Wild guesses */
136 #define R300_SE_VTE_CNTL 0x20b0
137 # define R300_VPORT_X_SCALE_ENA 0x00000001
138 # define R300_VPORT_X_OFFSET_ENA 0x00000002
139 # define R300_VPORT_Y_SCALE_ENA 0x00000004
140 # define R300_VPORT_Y_OFFSET_ENA 0x00000008
141 # define R300_VPORT_Z_SCALE_ENA 0x00000010
142 # define R300_VPORT_Z_OFFSET_ENA 0x00000020
143 # define R300_VTX_XY_FMT 0x00000100
144 # define R300_VTX_Z_FMT 0x00000200
145 # define R300_VTX_W0_FMT 0x00000400
146 # define R300_VTX_W0_NORMALIZE 0x00000800
147 # define R300_VTX_ST_DENORMALIZED 0x00001000
149 /* BEGIN: Vertex data assembly - lots of uncertainties */
153 #define R300_VAP_CNTL_STATUS 0x2140
154 # define R300_VC_NO_SWAP (0 << 0)
155 # define R300_VC_16BIT_SWAP (1 << 0)
156 # define R300_VC_32BIT_SWAP (2 << 0)
157 # define R300_VAP_TCL_BYPASS (1 << 8)
161 /* Where do we get our vertex data?
163 * Vertex data either comes either from immediate mode registers or from
165 * There appears to be no mixed mode (though we can force the pitch of
166 * vertex arrays to 0, effectively reusing the same element over and over
169 * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
170 * if these registers influence vertex array processing.
172 * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
174 * In both cases, vertex attributes are then passed through INPUT_ROUTE.
176 * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
177 * into the vertex processor's input registers.
178 * The first word routes the first input, the second word the second, etc.
179 * The corresponding input is routed into the register with the given index.
180 * The list is ended by a word with INPUT_ROUTE_END set.
182 * Always set COMPONENTS_4 in immediate mode.
185 #define R300_VAP_INPUT_ROUTE_0_0 0x2150
186 # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)
187 # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)
188 # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)
189 # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)
190 # define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */
191 # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8
192 # define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */
193 # define R300_VAP_INPUT_ROUTE_END (1 << 13)
194 # define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */
195 # define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */
196 # define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */
197 # define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */
198 #define R300_VAP_INPUT_ROUTE_0_1 0x2154
199 #define R300_VAP_INPUT_ROUTE_0_2 0x2158
200 #define R300_VAP_INPUT_ROUTE_0_3 0x215C
201 #define R300_VAP_INPUT_ROUTE_0_4 0x2160
202 #define R300_VAP_INPUT_ROUTE_0_5 0x2164
203 #define R300_VAP_INPUT_ROUTE_0_6 0x2168
204 #define R300_VAP_INPUT_ROUTE_0_7 0x216C
209 * - always set up to produce at least two attributes:
210 * if vertex program uses only position, fglrx will set normal, too
211 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
213 #define R300_VAP_INPUT_CNTL_0 0x2180
214 # define R300_INPUT_CNTL_0_COLOR 0x00000001
215 #define R300_VAP_INPUT_CNTL_1 0x2184
216 # define R300_INPUT_CNTL_POS 0x00000001
217 # define R300_INPUT_CNTL_NORMAL 0x00000002
218 # define R300_INPUT_CNTL_COLOR 0x00000004
219 # define R300_INPUT_CNTL_TC0 0x00000400
220 # define R300_INPUT_CNTL_TC1 0x00000800
221 # define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
222 # define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
223 # define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
224 # define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
225 # define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
226 # define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
230 /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
231 * are set to a swizzling bit pattern, other words are 0.
233 * In immediate mode, the pattern is always set to xyzw. In vertex array
234 * mode, the swizzling pattern is e.g. used to set zw components in texture
235 * coordinates with only tweo components.
237 #define R300_VAP_INPUT_ROUTE_1_0 0x21E0
238 # define R300_INPUT_ROUTE_SELECT_X 0
239 # define R300_INPUT_ROUTE_SELECT_Y 1
240 # define R300_INPUT_ROUTE_SELECT_Z 2
241 # define R300_INPUT_ROUTE_SELECT_W 3
242 # define R300_INPUT_ROUTE_SELECT_ZERO 4
243 # define R300_INPUT_ROUTE_SELECT_ONE 5
244 # define R300_INPUT_ROUTE_SELECT_MASK 7
245 # define R300_INPUT_ROUTE_X_SHIFT 0
246 # define R300_INPUT_ROUTE_Y_SHIFT 3
247 # define R300_INPUT_ROUTE_Z_SHIFT 6
248 # define R300_INPUT_ROUTE_W_SHIFT 9
249 # define R300_INPUT_ROUTE_ENABLE (15 << 12)
250 #define R300_VAP_INPUT_ROUTE_1_1 0x21E4
251 #define R300_VAP_INPUT_ROUTE_1_2 0x21E8
252 #define R300_VAP_INPUT_ROUTE_1_3 0x21EC
253 #define R300_VAP_INPUT_ROUTE_1_4 0x21F0
254 #define R300_VAP_INPUT_ROUTE_1_5 0x21F4
255 #define R300_VAP_INPUT_ROUTE_1_6 0x21F8
256 #define R300_VAP_INPUT_ROUTE_1_7 0x21FC
258 /* END: Vertex data assembly */
262 /* BEGIN: Upload vertex program and data */
265 * The programmable vertex shader unit has a memory bank of unknown size
266 * that can be written to in 16 byte units by writing the address into
267 * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
269 * Pointers into the memory bank are always in multiples of 16 bytes.
271 * The memory bank is divided into areas with fixed meaning.
273 * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
274 * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
275 * whereas the difference between known addresses suggests size 512.
277 * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
278 * Native reported limits and the VPI layout suggest size 256, whereas
279 * difference between known addresses suggests size 512.
281 * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
282 * floating point pointsize. The exact purpose of this state is uncertain,
283 * as there is also the R300_RE_POINTSIZE register.
285 * Multiple vertex programs and parameter sets can be loaded at once,
286 * which could explain the size discrepancy.
288 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
289 # define R300_PVS_UPLOAD_PROGRAM 0x00000000
290 # define R300_PVS_UPLOAD_PARAMETERS 0x00000200
291 # define R300_PVS_UPLOAD_POINTSIZE 0x00000406
295 #define R300_VAP_PVS_UPLOAD_DATA 0x2208
297 /* END: Upload vertex program and data */
301 /* I do not know the purpose of this register. However, I do know that
302 * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
303 * for normal rendering.
305 #define R300_VAP_UNKNOWN_221C 0x221C
306 # define R300_221C_NORMAL 0x00000000
307 # define R300_221C_CLEAR 0x0001C000
309 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
310 * plane is per-pixel and the second plane is per-vertex.
312 * This was determined by experimentation alone but I believe it is correct.
314 * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
316 #define R300_VAP_CLIP_X_0 0x2220
317 #define R300_VAP_CLIP_X_1 0x2224
318 #define R300_VAP_CLIP_Y_0 0x2228
319 #define R300_VAP_CLIP_Y_1 0x2230
323 /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
324 * rendering commands and overwriting vertex program parameters.
325 * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
326 * avoids bugs caused by still running shaders reading bad data from memory.
328 #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
330 /* Absolutely no clue what this register is about. */
331 #define R300_VAP_UNKNOWN_2288 0x2288
332 # define R300_2288_R300 0x00750000 /* -- nh */
333 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
337 /* Addresses are relative to the vertex program instruction area of the
338 * memory bank. PROGRAM_END points to the last instruction of the active
341 * The meaning of the two UNKNOWN fields is obviously not known. However,
342 * experiments so far have shown that both *must* point to an instruction
343 * inside the vertex program, otherwise the GPU locks up.
345 * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
346 * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
347 * position takes place.
349 * Most likely this is used to ignore rest of the program in cases
350 * where group of verts arent visible. For some reason this "section"
351 * is sometimes accepted other instruction that have no relationship with
352 * position calculations.
354 #define R300_VAP_PVS_CNTL_1 0x22D0
355 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
356 # define R300_PVS_CNTL_1_POS_END_SHIFT 10
357 # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20
358 /* Addresses are relative the the vertex program parameters area. */
359 #define R300_VAP_PVS_CNTL_2 0x22D4
360 # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
361 # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16
362 #define R300_VAP_PVS_CNTL_3 0x22D8
363 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10
364 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0
366 /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
369 #define R300_VAP_VTX_COLOR_R 0x2464
370 #define R300_VAP_VTX_COLOR_G 0x2468
371 #define R300_VAP_VTX_COLOR_B 0x246C
372 #define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
373 #define R300_VAP_VTX_POS_0_Y_1 0x2494
374 #define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
375 #define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
376 #define R300_VAP_VTX_POS_0_Y_2 0x24A4
377 #define R300_VAP_VTX_POS_0_Z_2 0x24A8
378 /* write 0 to indicate end of packet? */
379 #define R300_VAP_VTX_END_OF_PKT 0x24AC
383 /* These are values from r300_reg/r300_reg.h - they are known to be correct
384 * and are here so we can use one register file instead of several
387 #define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
388 # define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
389 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
390 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
391 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
392 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
393 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
394 # define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
396 #define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004
397 /* each of the following is 3 bits wide, specifies number
399 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
400 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
401 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
402 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
403 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
404 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
405 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
406 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
408 /* UNK30 seems to enables point to quad transformation on textures
409 * (or something closely related to that).
410 * This bit is rather fatal at the time being due to lackings at pixel
413 #define R300_GB_ENABLE 0x4008
414 # define R300_GB_POINT_STUFF_ENABLE (1<<0)
415 # define R300_GB_LINE_STUFF_ENABLE (1<<1)
416 # define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2)
417 # define R300_GB_STENCIL_AUTO_ENABLE (1<<4)
418 # define R300_GB_UNK31 (1<<31)
419 /* each of the following is 2 bits wide */
420 #define R300_GB_TEX_REPLICATE 0
421 #define R300_GB_TEX_ST 1
422 #define R300_GB_TEX_STR 2
423 # define R300_GB_TEX0_SOURCE_SHIFT 16
424 # define R300_GB_TEX1_SOURCE_SHIFT 18
425 # define R300_GB_TEX2_SOURCE_SHIFT 20
426 # define R300_GB_TEX3_SOURCE_SHIFT 22
427 # define R300_GB_TEX4_SOURCE_SHIFT 24
428 # define R300_GB_TEX5_SOURCE_SHIFT 26
429 # define R300_GB_TEX6_SOURCE_SHIFT 28
430 # define R300_GB_TEX7_SOURCE_SHIFT 30
432 /* MSPOS - positions for multisample antialiasing (?) */
433 #define R300_GB_MSPOS0 0x4010
434 /* shifts - each of the fields is 4 bits */
435 # define R300_GB_MSPOS0__MS_X0_SHIFT 0
436 # define R300_GB_MSPOS0__MS_Y0_SHIFT 4
437 # define R300_GB_MSPOS0__MS_X1_SHIFT 8
438 # define R300_GB_MSPOS0__MS_Y1_SHIFT 12
439 # define R300_GB_MSPOS0__MS_X2_SHIFT 16
440 # define R300_GB_MSPOS0__MS_Y2_SHIFT 20
441 # define R300_GB_MSPOS0__MSBD0_Y 24
442 # define R300_GB_MSPOS0__MSBD0_X 28
444 #define R300_GB_MSPOS1 0x4014
445 # define R300_GB_MSPOS1__MS_X3_SHIFT 0
446 # define R300_GB_MSPOS1__MS_Y3_SHIFT 4
447 # define R300_GB_MSPOS1__MS_X4_SHIFT 8
448 # define R300_GB_MSPOS1__MS_Y4_SHIFT 12
449 # define R300_GB_MSPOS1__MS_X5_SHIFT 16
450 # define R300_GB_MSPOS1__MS_Y5_SHIFT 20
451 # define R300_GB_MSPOS1__MSBD1 24
454 #define R300_GB_TILE_CONFIG 0x4018
455 # define R300_GB_TILE_ENABLE (1<<0)
456 # define R300_GB_TILE_PIPE_COUNT_RV300 0
457 # define R300_GB_TILE_PIPE_COUNT_R300 (3<<1)
458 # define R300_GB_TILE_PIPE_COUNT_R420 (7<<1)
459 # define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1)
460 # define R300_GB_TILE_SIZE_8 0
461 # define R300_GB_TILE_SIZE_16 (1<<4)
462 # define R300_GB_TILE_SIZE_32 (2<<4)
463 # define R300_GB_SUPER_SIZE_1 (0<<6)
464 # define R300_GB_SUPER_SIZE_2 (1<<6)
465 # define R300_GB_SUPER_SIZE_4 (2<<6)
466 # define R300_GB_SUPER_SIZE_8 (3<<6)
467 # define R300_GB_SUPER_SIZE_16 (4<<6)
468 # define R300_GB_SUPER_SIZE_32 (5<<6)
469 # define R300_GB_SUPER_SIZE_64 (6<<6)
470 # define R300_GB_SUPER_SIZE_128 (7<<6)
471 # define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */
472 # define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */
473 # define R300_GB_SUPER_TILE_A 0
474 # define R300_GB_SUPER_TILE_B (1<<15)
475 # define R300_GB_SUBPIXEL_1_12 0
476 # define R300_GB_SUBPIXEL_1_16 (1<<16)
478 #define R300_GB_FIFO_SIZE 0x4024
479 /* each of the following is 2 bits wide */
480 #define R300_GB_FIFO_SIZE_32 0
481 #define R300_GB_FIFO_SIZE_64 1
482 #define R300_GB_FIFO_SIZE_128 2
483 #define R300_GB_FIFO_SIZE_256 3
484 # define R300_SC_IFIFO_SIZE_SHIFT 0
485 # define R300_SC_TZFIFO_SIZE_SHIFT 2
486 # define R300_SC_BFIFO_SIZE_SHIFT 4
488 # define R300_US_OFIFO_SIZE_SHIFT 12
489 # define R300_US_WFIFO_SIZE_SHIFT 14
490 /* the following use the same constants as above, but meaning is
491 is times 2 (i.e. instead of 32 words it means 64 */
492 # define R300_RS_TFIFO_SIZE_SHIFT 6
493 # define R300_RS_CFIFO_SIZE_SHIFT 8
494 # define R300_US_RAM_SIZE_SHIFT 10
495 /* watermarks, 3 bits wide */
496 # define R300_RS_HIGHWATER_COL_SHIFT 16
497 # define R300_RS_HIGHWATER_TEX_SHIFT 19
498 # define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
499 # define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24
501 #define R300_GB_SELECT 0x401C
502 # define R300_GB_FOG_SELECT_C0A 0
503 # define R300_GB_FOG_SELECT_C1A 1
504 # define R300_GB_FOG_SELECT_C2A 2
505 # define R300_GB_FOG_SELECT_C3A 3
506 # define R300_GB_FOG_SELECT_1_1_W 4
507 # define R300_GB_FOG_SELECT_Z 5
508 # define R300_GB_DEPTH_SELECT_Z 0
509 # define R300_GB_DEPTH_SELECT_1_1_W (1<<3)
510 # define R300_GB_W_SELECT_1_W 0
511 # define R300_GB_W_SELECT_1 (1<<4)
513 #define R300_GB_AA_CONFIG 0x4020
514 # define R300_AA_DISABLE 0x00
515 # define R300_AA_ENABLE 0x01
516 # define R300_AA_SUBSAMPLES_2 0
517 # define R300_AA_SUBSAMPLES_3 (1<<1)
518 # define R300_AA_SUBSAMPLES_4 (2<<1)
519 # define R300_AA_SUBSAMPLES_6 (3<<1)
523 /* Zero to flush caches. */
524 #define R300_TX_INVALTAGS 0x4100
525 #define R300_TX_FLUSH 0x0
527 /* The upper enable bits are guessed, based on fglrx reported limits. */
528 #define R300_TX_ENABLE 0x4104
529 # define R300_TX_ENABLE_0 (1 << 0)
530 # define R300_TX_ENABLE_1 (1 << 1)
531 # define R300_TX_ENABLE_2 (1 << 2)
532 # define R300_TX_ENABLE_3 (1 << 3)
533 # define R300_TX_ENABLE_4 (1 << 4)
534 # define R300_TX_ENABLE_5 (1 << 5)
535 # define R300_TX_ENABLE_6 (1 << 6)
536 # define R300_TX_ENABLE_7 (1 << 7)
537 # define R300_TX_ENABLE_8 (1 << 8)
538 # define R300_TX_ENABLE_9 (1 << 9)
539 # define R300_TX_ENABLE_10 (1 << 10)
540 # define R300_TX_ENABLE_11 (1 << 11)
541 # define R300_TX_ENABLE_12 (1 << 12)
542 # define R300_TX_ENABLE_13 (1 << 13)
543 # define R300_TX_ENABLE_14 (1 << 14)
544 # define R300_TX_ENABLE_15 (1 << 15)
546 /* The pointsize is given in multiples of 6. The pointsize can be
547 * enormous: Clear() renders a single point that fills the entire
550 #define R300_RE_POINTSIZE 0x421C
551 # define R300_POINTSIZE_Y_SHIFT 0
552 # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */
553 # define R300_POINTSIZE_X_SHIFT 16
554 # define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */
555 # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
557 /* The line width is given in multiples of 6.
558 * In default mode lines are classified as vertical lines.
560 * VE: vertical or horizontal
561 * HO & VE: no classification
563 #define R300_RE_LINE_CNT 0x4234
564 # define R300_LINESIZE_SHIFT 0
565 # define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */
566 # define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6)
567 # define R300_LINE_CNT_HO (1 << 16)
568 # define R300_LINE_CNT_VE (1 << 17)
570 /* Some sort of scale or clamp value for texcoordless textures. */
571 #define R300_RE_UNK4238 0x4238
573 /* Something shade related */
574 #define R300_RE_SHADE 0x4274
576 #define R300_RE_SHADE_MODEL 0x4278
577 # define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa
578 # define R300_RE_SHADE_MODEL_FLAT 0x39595
581 #define R300_RE_POLYGON_MODE 0x4288
582 # define R300_PM_ENABLED (1 << 0)
583 # define R300_PM_FRONT_POINT (0 << 0)
584 # define R300_PM_BACK_POINT (0 << 0)
585 # define R300_PM_FRONT_LINE (1 << 4)
586 # define R300_PM_FRONT_FILL (1 << 5)
587 # define R300_PM_BACK_LINE (1 << 7)
588 # define R300_PM_BACK_FILL (1 << 8)
591 #define R300_RE_FOG_SCALE 0x4294
592 #define R300_RE_FOG_START 0x4298
594 /* Not sure why there are duplicate of factor and constant values.
595 * My best guess so far is that there are separate zbiases for test and write.
596 * Ordering might be wrong.
597 * Some of the tests indicate that fgl has a fallback implementation of zbias
600 #define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */
601 #define R300_RE_ZBIAS_T_FACTOR 0x42A4
602 #define R300_RE_ZBIAS_T_CONSTANT 0x42A8
603 #define R300_RE_ZBIAS_W_FACTOR 0x42AC
604 #define R300_RE_ZBIAS_W_CONSTANT 0x42B0
606 /* This register needs to be set to (1<<1) for RV350 to correctly
607 * perform depth test (see --vb-triangles in r300_demo)
608 * Don't know about other chips. - Vladimir
609 * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
610 * My guess is that there are two bits for each zbias primitive
611 * (FILL, LINE, POINT).
612 * One to enable depth test and one for depth write.
613 * Yet this doesn't explain why depth writes work ...
615 #define R300_RE_OCCLUSION_CNTL 0x42B4
616 # define R300_OCCLUSION_ON (1<<1)
618 #define R300_RE_CULL_CNTL 0x42B8
619 # define R300_CULL_FRONT (1 << 0)
620 # define R300_CULL_BACK (1 << 1)
621 # define R300_FRONT_FACE_CCW (0 << 2)
622 # define R300_FRONT_FACE_CW (1 << 2)
625 /* BEGIN: Rasterization / Interpolators - many guesses */
627 /* 0_UNKNOWN_18 has always been set except for clear operations.
628 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
629 * on the vertex program, *not* the fragment program)
631 #define R300_RS_CNTL_0 0x4300
632 # define R300_RS_CNTL_TC_CNT_SHIFT 2
633 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2)
634 /* number of color interpolators used */
635 # define R300_RS_CNTL_CI_CNT_SHIFT 7
636 # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)
637 /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n
639 #define R300_RS_CNTL_1 0x4304
643 /* Only used for texture coordinates.
644 * Use the source field to route texture coordinate input from the
645 * vertex program to the desired interpolator. Note that the source
646 * field is relative to the outputs the vertex program *actually*
647 * writes. If a vertex program only writes texcoord[1], this will
649 * Set INTERP_USED on all interpolators that produce data used by
650 * the fragment program. INTERP_USED looks like a swizzling mask,
651 * but I haven't seen it used that way.
653 * Note: The _UNKNOWN constants are always set in their respective
654 * register. I don't know if this is necessary.
656 #define R300_RS_INTERP_0 0x4310
657 #define R300_RS_INTERP_1 0x4314
658 # define R300_RS_INTERP_1_UNKNOWN 0x40
659 #define R300_RS_INTERP_2 0x4318
660 # define R300_RS_INTERP_2_UNKNOWN 0x80
661 #define R300_RS_INTERP_3 0x431C
662 # define R300_RS_INTERP_3_UNKNOWN 0xC0
663 #define R300_RS_INTERP_4 0x4320
664 #define R300_RS_INTERP_5 0x4324
665 #define R300_RS_INTERP_6 0x4328
666 #define R300_RS_INTERP_7 0x432C
667 # define R300_RS_INTERP_SRC_SHIFT 2
668 # define R300_RS_INTERP_SRC_MASK (7 << 2)
669 # define R300_RS_INTERP_USED 0x00D10000
671 /* These DWORDs control how vertex data is routed into fragment program
672 * registers, after interpolators.
674 #define R300_RS_ROUTE_0 0x4330
675 #define R300_RS_ROUTE_1 0x4334
676 #define R300_RS_ROUTE_2 0x4338
677 #define R300_RS_ROUTE_3 0x433C /* GUESS */
678 #define R300_RS_ROUTE_4 0x4340 /* GUESS */
679 #define R300_RS_ROUTE_5 0x4344 /* GUESS */
680 #define R300_RS_ROUTE_6 0x4348 /* GUESS */
681 #define R300_RS_ROUTE_7 0x434C /* GUESS */
682 # define R300_RS_ROUTE_SOURCE_INTERP_0 0
683 # define R300_RS_ROUTE_SOURCE_INTERP_1 1
684 # define R300_RS_ROUTE_SOURCE_INTERP_2 2
685 # define R300_RS_ROUTE_SOURCE_INTERP_3 3
686 # define R300_RS_ROUTE_SOURCE_INTERP_4 4
687 # define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */
688 # define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */
689 # define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */
690 # define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */
691 # define R300_RS_ROUTE_DEST_SHIFT 6
692 # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */
694 /* Special handling for color: When the fragment program uses color,
695 * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
696 * color register index.
698 * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any
699 * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.
700 * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly
701 * correct or not. - Oliver.
703 # define R300_RS_ROUTE_0_COLOR (1 << 14)
704 # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17
705 # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */
706 /* As above, but for secondary color */
707 # define R300_RS_ROUTE_1_COLOR1 (1 << 14)
708 # define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17
709 # define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17)
710 # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
711 /* END: Rasterization / Interpolators - many guesses */
713 /* Hierarchical Z Enable */
714 #define R300_SC_HYPERZ 0x43a4
715 # define R300_SC_HYPERZ_DISABLE (0 << 0)
716 # define R300_SC_HYPERZ_ENABLE (1 << 0)
717 # define R300_SC_HYPERZ_MIN (0 << 1)
718 # define R300_SC_HYPERZ_MAX (1 << 1)
719 # define R300_SC_HYPERZ_ADJ_256 (0 << 2)
720 # define R300_SC_HYPERZ_ADJ_128 (1 << 2)
721 # define R300_SC_HYPERZ_ADJ_64 (2 << 2)
722 # define R300_SC_HYPERZ_ADJ_32 (3 << 2)
723 # define R300_SC_HYPERZ_ADJ_16 (4 << 2)
724 # define R300_SC_HYPERZ_ADJ_8 (5 << 2)
725 # define R300_SC_HYPERZ_ADJ_4 (6 << 2)
726 # define R300_SC_HYPERZ_ADJ_2 (7 << 2)
727 # define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
728 # define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
729 # define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
730 # define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
732 #define R300_SC_EDGERULE 0x43a8
734 /* BEGIN: Scissors and cliprects */
736 /* There are four clipping rectangles. Their corner coordinates are inclusive.
737 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
738 * on whether the pixel is inside cliprects 0-3, respectively. For example,
739 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
740 * the number 3 (binary 0011).
741 * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
742 * the pixel is rasterized.
744 * In addition to this, there is a scissors rectangle. Only pixels inside the
745 * scissors rectangle are drawn. (coordinates are inclusive)
747 * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
748 * for the purpose of clipping and scissors.
750 #define R300_RE_CLIPRECT_TL_0 0x43B0
751 #define R300_RE_CLIPRECT_BR_0 0x43B4
752 #define R300_RE_CLIPRECT_TL_1 0x43B8
753 #define R300_RE_CLIPRECT_BR_1 0x43BC
754 #define R300_RE_CLIPRECT_TL_2 0x43C0
755 #define R300_RE_CLIPRECT_BR_2 0x43C4
756 #define R300_RE_CLIPRECT_TL_3 0x43C8
757 #define R300_RE_CLIPRECT_BR_3 0x43CC
758 # define R300_CLIPRECT_OFFSET 1440
759 # define R300_CLIPRECT_MASK 0x1FFF
760 # define R300_CLIPRECT_X_SHIFT 0
761 # define R300_CLIPRECT_X_MASK (0x1FFF << 0)
762 # define R300_CLIPRECT_Y_SHIFT 13
763 # define R300_CLIPRECT_Y_MASK (0x1FFF << 13)
764 #define R300_RE_CLIPRECT_CNTL 0x43D0
765 # define R300_CLIP_OUT (1 << 0)
766 # define R300_CLIP_0 (1 << 1)
767 # define R300_CLIP_1 (1 << 2)
768 # define R300_CLIP_10 (1 << 3)
769 # define R300_CLIP_2 (1 << 4)
770 # define R300_CLIP_20 (1 << 5)
771 # define R300_CLIP_21 (1 << 6)
772 # define R300_CLIP_210 (1 << 7)
773 # define R300_CLIP_3 (1 << 8)
774 # define R300_CLIP_30 (1 << 9)
775 # define R300_CLIP_31 (1 << 10)
776 # define R300_CLIP_310 (1 << 11)
777 # define R300_CLIP_32 (1 << 12)
778 # define R300_CLIP_320 (1 << 13)
779 # define R300_CLIP_321 (1 << 14)
780 # define R300_CLIP_3210 (1 << 15)
784 #define R300_RE_SCISSORS_TL 0x43E0
785 #define R300_RE_SCISSORS_BR 0x43E4
786 # define R300_SCISSORS_OFFSET 1440
787 # define R300_SCISSORS_X_SHIFT 0
788 # define R300_SCISSORS_X_MASK (0x1FFF << 0)
789 # define R300_SCISSORS_Y_SHIFT 13
790 # define R300_SCISSORS_Y_MASK (0x1FFF << 13)
791 /* END: Scissors and cliprects */
793 /* BEGIN: Texture specification */
796 * The texture specification dwords are grouped by meaning and not by texture
797 * unit. This means that e.g. the offset for texture image unit N is found in
798 * register TX_OFFSET_0 + (4*N)
800 #define R300_TX_FILTER_0 0x4400
801 # define R300_TX_REPEAT 0
802 # define R300_TX_MIRRORED 1
803 # define R300_TX_CLAMP 4
804 # define R300_TX_CLAMP_TO_EDGE 2
805 # define R300_TX_CLAMP_TO_BORDER 6
806 # define R300_TX_WRAP_S_SHIFT 0
807 # define R300_TX_WRAP_S_MASK (7 << 0)
808 # define R300_TX_WRAP_T_SHIFT 3
809 # define R300_TX_WRAP_T_MASK (7 << 3)
810 # define R300_TX_WRAP_Q_SHIFT 6
811 # define R300_TX_WRAP_Q_MASK (7 << 6)
812 # define R300_TX_MAG_FILTER_NEAREST (1 << 9)
813 # define R300_TX_MAG_FILTER_LINEAR (2 << 9)
814 # define R300_TX_MAG_FILTER_MASK (3 << 9)
815 # define R300_TX_MIN_FILTER_NEAREST (1 << 11)
816 # define R300_TX_MIN_FILTER_LINEAR (2 << 11)
817 # define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11)
818 # define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11)
819 # define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11)
820 # define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)
822 /* NOTE: NEAREST doesn't seem to exist.
823 * Im not seting MAG_FILTER_MASK and (3 << 11) on for all
824 * anisotropy modes because that would void selected mag filter
826 # define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13)
827 # define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13)
828 # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13)
829 # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13)
830 # define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) )
831 # define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)
832 # define R300_TX_MAX_ANISO_2_TO_1 (2 << 21)
833 # define R300_TX_MAX_ANISO_4_TO_1 (4 << 21)
834 # define R300_TX_MAX_ANISO_8_TO_1 (6 << 21)
835 # define R300_TX_MAX_ANISO_16_TO_1 (8 << 21)
836 # define R300_TX_MAX_ANISO_MASK (14 << 21)
838 #define R300_TX_FILTER1_0 0x4440
839 # define R300_CHROMA_KEY_MODE_DISABLE 0
840 # define R300_CHROMA_KEY_FORCE 1
841 # define R300_CHROMA_KEY_BLEND 2
842 # define R300_MC_ROUND_NORMAL (0<<2)
843 # define R300_MC_ROUND_MPEG4 (1<<2)
844 # define R300_LOD_BIAS_MASK 0x1fff
845 # define R300_EDGE_ANISO_EDGE_DIAG (0<<13)
846 # define R300_EDGE_ANISO_EDGE_ONLY (1<<13)
847 # define R300_MC_COORD_TRUNCATE_DISABLE (0<<14)
848 # define R300_MC_COORD_TRUNCATE_MPEG (1<<14)
849 # define R300_TX_TRI_PERF_0_8 (0<<15)
850 # define R300_TX_TRI_PERF_1_8 (1<<15)
851 # define R300_TX_TRI_PERF_1_4 (2<<15)
852 # define R300_TX_TRI_PERF_3_8 (3<<15)
853 # define R300_ANISO_THRESHOLD_MASK (7<<17)
855 #define R300_TX_SIZE_0 0x4480
856 # define R300_TX_WIDTHMASK_SHIFT 0
857 # define R300_TX_WIDTHMASK_MASK (2047 << 0)
858 # define R300_TX_HEIGHTMASK_SHIFT 11
859 # define R300_TX_HEIGHTMASK_MASK (2047 << 11)
860 # define R300_TX_UNK23 (1 << 23)
861 # define R300_TX_MAX_MIP_LEVEL_SHIFT 26
862 # define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26)
863 # define R300_TX_SIZE_PROJECTED (1<<30)
864 # define R300_TX_SIZE_TXPITCH_EN (1<<31)
865 #define R300_TX_FORMAT_0 0x44C0
866 /* The interpretation of the format word by Wladimir van der Laan */
867 /* The X, Y, Z and W refer to the layout of the components.
868 They are given meanings as R, G, B and Alpha by the swizzle
870 # define R300_TX_FORMAT_X8 0x0
871 # define R300_TX_FORMAT_X16 0x1
872 # define R300_TX_FORMAT_Y4X4 0x2
873 # define R300_TX_FORMAT_Y8X8 0x3
874 # define R300_TX_FORMAT_Y16X16 0x4
875 # define R300_TX_FORMAT_Z3Y3X2 0x5
876 # define R300_TX_FORMAT_Z5Y6X5 0x6
877 # define R300_TX_FORMAT_Z6Y5X5 0x7
878 # define R300_TX_FORMAT_Z11Y11X10 0x8
879 # define R300_TX_FORMAT_Z10Y11X11 0x9
880 # define R300_TX_FORMAT_W4Z4Y4X4 0xA
881 # define R300_TX_FORMAT_W1Z5Y5X5 0xB
882 # define R300_TX_FORMAT_W8Z8Y8X8 0xC
883 # define R300_TX_FORMAT_W2Z10Y10X10 0xD
884 # define R300_TX_FORMAT_W16Z16Y16X16 0xE
885 # define R300_TX_FORMAT_DXT1 0xF
886 # define R300_TX_FORMAT_DXT3 0x10
887 # define R300_TX_FORMAT_DXT5 0x11
888 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
889 # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
890 # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
891 # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
892 /* 0x16 - some 16 bit green format.. ?? */
893 # define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */
894 # define R300_TX_FORMAT_CUBIC_MAP (1 << 26)
897 /* Floating point formats */
898 /* Note - hardware supports both 16 and 32 bit floating point */
899 # define R300_TX_FORMAT_FL_I16 0x18
900 # define R300_TX_FORMAT_FL_I16A16 0x19
901 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
902 # define R300_TX_FORMAT_FL_I32 0x1B
903 # define R300_TX_FORMAT_FL_I32A32 0x1C
904 # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
905 # define R300_TX_FORMAT_ATI2N 0x1F
906 /* alpha modes, convenience mostly */
907 /* if you have alpha, pick constant appropriate to the
908 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
909 # define R300_TX_FORMAT_ALPHA_1CH 0x000
910 # define R300_TX_FORMAT_ALPHA_2CH 0x200
911 # define R300_TX_FORMAT_ALPHA_4CH 0x600
912 # define R300_TX_FORMAT_ALPHA_NONE 0xA00
915 # define R300_TX_FORMAT_X 0
916 # define R300_TX_FORMAT_Y 1
917 # define R300_TX_FORMAT_Z 2
918 # define R300_TX_FORMAT_W 3
919 # define R300_TX_FORMAT_ZERO 4
920 # define R300_TX_FORMAT_ONE 5
921 /* 2.0*Z, everything above 1.0 is set to 0.0 */
922 # define R300_TX_FORMAT_CUT_Z 6
923 /* 2.0*W, everything above 1.0 is set to 0.0 */
924 # define R300_TX_FORMAT_CUT_W 7
926 # define R300_TX_FORMAT_B_SHIFT 18
927 # define R300_TX_FORMAT_G_SHIFT 15
928 # define R300_TX_FORMAT_R_SHIFT 12
929 # define R300_TX_FORMAT_A_SHIFT 9
930 /* Convenience macro to take care of layout and swizzling */
931 # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
932 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
933 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
934 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
935 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
936 | (R300_TX_FORMAT_##FMT) \
938 /* These can be ORed with result of R300_EASY_TX_FORMAT()
939 We don't really know what they do. Take values from a
941 # define R300_TX_FORMAT_CONST_X (1<<5)
942 # define R300_TX_FORMAT_CONST_Y (2<<5)
943 # define R300_TX_FORMAT_CONST_Z (4<<5)
944 # define R300_TX_FORMAT_CONST_W (8<<5)
946 # define R300_TX_FORMAT_YUV_MODE 0x00800000
948 #define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */
949 #define R300_TX_OFFSET_0 0x4540
950 /* BEGIN: Guess from R200 */
951 # define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
952 # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
953 # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
954 # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
955 # define R300_TXO_MACRO_TILE (1 << 2)
956 # define R300_TXO_MICRO_TILE (1 << 3)
957 # define R300_TXO_MICRO_TILE_SQUARE (2 << 3)
958 # define R300_TXO_OFFSET_MASK 0xffffffe0
959 # define R300_TXO_OFFSET_SHIFT 5
960 /* END: Guess from R200 */
962 /* 32 bit chroma key */
963 #define R300_TX_CHROMA_KEY_0 0x4580
964 /* ff00ff00 == { 0, 1.0, 0, 1.0 } */
965 #define R300_TX_BORDER_COLOR_0 0x45C0
967 /* END: Texture specification */
969 /* BEGIN: Fragment program instruction set */
971 /* Fragment programs are written directly into register space.
972 * There are separate instruction streams for texture instructions and ALU
974 * In order to synchronize these streams, the program is divided into up
975 * to 4 nodes. Each node begins with a number of TEX operations, followed
976 * by a number of ALU operations.
977 * The first node can have zero TEX ops, all subsequent nodes must have at
980 * All nodes must have at least one ALU op.
982 * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
983 * 1 node, a value of 3 means 4 nodes.
984 * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
985 * offsets into the respective instruction streams, while *_END points to the
986 * last instruction relative to this offset.
988 #define R300_PFS_CNTL_0 0x4600
989 # define R300_PFS_CNTL_LAST_NODES_SHIFT 0
990 # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
991 # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
992 #define R300_PFS_CNTL_1 0x4604
993 /* There is an unshifted value here which has so far always been equal to the
994 * index of the highest used temporary register.
996 #define R300_PFS_CNTL_2 0x4608
997 # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
998 # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
999 # define R300_PFS_CNTL_ALU_END_SHIFT 6
1000 # define R300_PFS_CNTL_ALU_END_MASK (63 << 6)
1001 # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12
1002 # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */
1003 # define R300_PFS_CNTL_TEX_END_SHIFT 18
1004 # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */
1008 /* Nodes are stored backwards. The last active node is always stored in
1010 * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
1011 * first node is stored in NODE_2, the second node is stored in NODE_3.
1013 * Offsets are relative to the master offset from PFS_CNTL_2.
1015 #define R300_PFS_NODE_0 0x4610
1016 #define R300_PFS_NODE_1 0x4614
1017 #define R300_PFS_NODE_2 0x4618
1018 #define R300_PFS_NODE_3 0x461C
1019 # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0
1020 # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0)
1021 # define R300_PFS_NODE_ALU_END_SHIFT 6
1022 # define R300_PFS_NODE_ALU_END_MASK (63 << 6)
1023 # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12
1024 # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12)
1025 # define R300_PFS_NODE_TEX_END_SHIFT 17
1026 # define R300_PFS_NODE_TEX_END_MASK (31 << 17)
1027 # define R300_PFS_NODE_OUTPUT_COLOR (1 << 22)
1028 # define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23)
1031 * As far as I can tell, texture instructions cannot write into output
1032 * registers directly. A subsequent ALU instruction is always necessary,
1033 * even if it's just MAD o0, r0, 1, 0
1035 #define R300_PFS_TEXI_0 0x4620
1036 # define R300_FPITX_SRC_SHIFT 0
1037 # define R300_FPITX_SRC_MASK (31 << 0)
1039 # define R300_FPITX_SRC_CONST (1 << 5)
1040 # define R300_FPITX_DST_SHIFT 6
1041 # define R300_FPITX_DST_MASK (31 << 6)
1042 # define R300_FPITX_IMAGE_SHIFT 11
1043 /* GUESS based on layout and native limits */
1044 # define R300_FPITX_IMAGE_MASK (15 << 11)
1045 /* Unsure if these are opcodes, or some kind of bitfield, but this is how
1046 * they were set when I checked
1048 # define R300_FPITX_OPCODE_SHIFT 15
1049 # define R300_FPITX_OP_TEX 1
1050 # define R300_FPITX_OP_KIL 2
1051 # define R300_FPITX_OP_TXP 3
1052 # define R300_FPITX_OP_TXB 4
1053 # define R300_FPITX_OPCODE_MASK (7 << 15)
1056 * The ALU instructions register blocks are enumerated according to the order
1057 * in which fglrx. I assume there is space for 64 instructions, since
1058 * each block has space for a maximum of 64 DWORDs, and this matches reported
1061 * The basic functional block seems to be one MAD for each color and alpha,
1062 * and an adder that adds all components after the MUL.
1063 * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
1064 * - DP4: Use OUTC_DP4, OUTA_DP4
1065 * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
1066 * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
1067 * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
1068 * - CMP: If ARG2 < 0, return ARG1, else return ARG0
1069 * - FLR: use FRC+MAD
1070 * - XPD: use MAD+MAD
1071 * - SGE, SLT: use MAD+CMP
1072 * - RSQ: use ABS modifier for argument
1073 * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
1074 * (e.g. RCP) into color register
1075 * - apparently, there's no quick DST operation
1076 * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
1077 * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
1078 * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
1081 * First stage selects three sources from the available registers and
1082 * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
1083 * fglrx sorts the three source fields: Registers before constants,
1084 * lower indices before higher indices; I do not know whether this is
1087 * fglrx fills unused sources with "read constant 0"
1088 * According to specs, you cannot select more than two different constants.
1090 * Second stage selects the operands from the sources. This is defined in
1091 * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
1093 * Swizzling and negation happens in this stage, as well.
1095 * Important: Color and alpha seem to be mostly separate, i.e. their sources
1096 * selection appears to be fully independent (the register storage is probably
1097 * physically split into a color and an alpha section).
1098 * However (because of the apparent physical split), there is some interaction
1099 * WRT swizzling. If, for example, you want to load an R component into an
1100 * Alpha operand, this R component is taken from a *color* source, not from
1101 * an alpha source. The corresponding register doesn't even have to appear in
1102 * the alpha sources list. (I hope this all makes sense to you)
1104 * Destination selection
1105 * The destination register index is in FPI1 (color) and FPI3 (alpha)
1106 * together with enable bits.
1107 * There are separate enable bits for writing into temporary registers
1108 * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
1109 * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
1110 * same index must be used for both).
1112 * Note: There is a special form for LRP
1113 * - Argument order is the same as in ARB_fragment_program.
1114 * - Operation is MAD
1115 * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
1116 * - Set FPI0/FPI2_SPECIAL_LRP
1117 * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
1119 #define R300_PFS_INSTR1_0 0x46C0
1120 # define R300_FPI1_SRC0C_SHIFT 0
1121 # define R300_FPI1_SRC0C_MASK (31 << 0)
1122 # define R300_FPI1_SRC0C_CONST (1 << 5)
1123 # define R300_FPI1_SRC1C_SHIFT 6
1124 # define R300_FPI1_SRC1C_MASK (31 << 6)
1125 # define R300_FPI1_SRC1C_CONST (1 << 11)
1126 # define R300_FPI1_SRC2C_SHIFT 12
1127 # define R300_FPI1_SRC2C_MASK (31 << 12)
1128 # define R300_FPI1_SRC2C_CONST (1 << 17)
1129 # define R300_FPI1_SRC_MASK 0x0003ffff
1130 # define R300_FPI1_DSTC_SHIFT 18
1131 # define R300_FPI1_DSTC_MASK (31 << 18)
1132 # define R300_FPI1_DSTC_REG_MASK_SHIFT 23
1133 # define R300_FPI1_DSTC_REG_X (1 << 23)
1134 # define R300_FPI1_DSTC_REG_Y (1 << 24)
1135 # define R300_FPI1_DSTC_REG_Z (1 << 25)
1136 # define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 26
1137 # define R300_FPI1_DSTC_OUTPUT_X (1 << 26)
1138 # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27)
1139 # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28)
1141 #define R300_PFS_INSTR3_0 0x47C0
1142 # define R300_FPI3_SRC0A_SHIFT 0
1143 # define R300_FPI3_SRC0A_MASK (31 << 0)
1144 # define R300_FPI3_SRC0A_CONST (1 << 5)
1145 # define R300_FPI3_SRC1A_SHIFT 6
1146 # define R300_FPI3_SRC1A_MASK (31 << 6)
1147 # define R300_FPI3_SRC1A_CONST (1 << 11)
1148 # define R300_FPI3_SRC2A_SHIFT 12
1149 # define R300_FPI3_SRC2A_MASK (31 << 12)
1150 # define R300_FPI3_SRC2A_CONST (1 << 17)
1151 # define R300_FPI3_SRC_MASK 0x0003ffff
1152 # define R300_FPI3_DSTA_SHIFT 18
1153 # define R300_FPI3_DSTA_MASK (31 << 18)
1154 # define R300_FPI3_DSTA_REG (1 << 23)
1155 # define R300_FPI3_DSTA_OUTPUT (1 << 24)
1156 # define R300_FPI3_DSTA_DEPTH (1 << 27)
1158 #define R300_PFS_INSTR0_0 0x48C0
1159 # define R300_FPI0_ARGC_SRC0C_XYZ 0
1160 # define R300_FPI0_ARGC_SRC0C_XXX 1
1161 # define R300_FPI0_ARGC_SRC0C_YYY 2
1162 # define R300_FPI0_ARGC_SRC0C_ZZZ 3
1163 # define R300_FPI0_ARGC_SRC1C_XYZ 4
1164 # define R300_FPI0_ARGC_SRC1C_XXX 5
1165 # define R300_FPI0_ARGC_SRC1C_YYY 6
1166 # define R300_FPI0_ARGC_SRC1C_ZZZ 7
1167 # define R300_FPI0_ARGC_SRC2C_XYZ 8
1168 # define R300_FPI0_ARGC_SRC2C_XXX 9
1169 # define R300_FPI0_ARGC_SRC2C_YYY 10
1170 # define R300_FPI0_ARGC_SRC2C_ZZZ 11
1171 # define R300_FPI0_ARGC_SRC0A 12
1172 # define R300_FPI0_ARGC_SRC1A 13
1173 # define R300_FPI0_ARGC_SRC2A 14
1174 # define R300_FPI0_ARGC_SRC1C_LRP 15
1175 # define R300_FPI0_ARGC_ZERO 20
1176 # define R300_FPI0_ARGC_ONE 21
1178 # define R300_FPI0_ARGC_HALF 22
1179 # define R300_FPI0_ARGC_SRC0C_YZX 23
1180 # define R300_FPI0_ARGC_SRC1C_YZX 24
1181 # define R300_FPI0_ARGC_SRC2C_YZX 25
1182 # define R300_FPI0_ARGC_SRC0C_ZXY 26
1183 # define R300_FPI0_ARGC_SRC1C_ZXY 27
1184 # define R300_FPI0_ARGC_SRC2C_ZXY 28
1185 # define R300_FPI0_ARGC_SRC0CA_WZY 29
1186 # define R300_FPI0_ARGC_SRC1CA_WZY 30
1187 # define R300_FPI0_ARGC_SRC2CA_WZY 31
1189 # define R300_FPI0_ARG0C_SHIFT 0
1190 # define R300_FPI0_ARG0C_MASK (31 << 0)
1191 # define R300_FPI0_ARG0C_NEG (1 << 5)
1192 # define R300_FPI0_ARG0C_ABS (1 << 6)
1193 # define R300_FPI0_ARG1C_SHIFT 7
1194 # define R300_FPI0_ARG1C_MASK (31 << 7)
1195 # define R300_FPI0_ARG1C_NEG (1 << 12)
1196 # define R300_FPI0_ARG1C_ABS (1 << 13)
1197 # define R300_FPI0_ARG2C_SHIFT 14
1198 # define R300_FPI0_ARG2C_MASK (31 << 14)
1199 # define R300_FPI0_ARG2C_NEG (1 << 19)
1200 # define R300_FPI0_ARG2C_ABS (1 << 20)
1201 # define R300_FPI0_SPECIAL_LRP (1 << 21)
1202 # define R300_FPI0_OUTC_MAD (0 << 23)
1203 # define R300_FPI0_OUTC_DP3 (1 << 23)
1204 # define R300_FPI0_OUTC_DP4 (2 << 23)
1205 # define R300_FPI0_OUTC_MIN (4 << 23)
1206 # define R300_FPI0_OUTC_MAX (5 << 23)
1207 # define R300_FPI0_OUTC_CMPH (7 << 23)
1208 # define R300_FPI0_OUTC_CMP (8 << 23)
1209 # define R300_FPI0_OUTC_FRC (9 << 23)
1210 # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
1211 # define R300_FPI0_OUTC_SAT (1 << 30)
1212 # define R300_FPI0_INSERT_NOP (1 << 31)
1214 #define R300_PFS_INSTR2_0 0x49C0
1215 # define R300_FPI2_ARGA_SRC0C_X 0
1216 # define R300_FPI2_ARGA_SRC0C_Y 1
1217 # define R300_FPI2_ARGA_SRC0C_Z 2
1218 # define R300_FPI2_ARGA_SRC1C_X 3
1219 # define R300_FPI2_ARGA_SRC1C_Y 4
1220 # define R300_FPI2_ARGA_SRC1C_Z 5
1221 # define R300_FPI2_ARGA_SRC2C_X 6
1222 # define R300_FPI2_ARGA_SRC2C_Y 7
1223 # define R300_FPI2_ARGA_SRC2C_Z 8
1224 # define R300_FPI2_ARGA_SRC0A 9
1225 # define R300_FPI2_ARGA_SRC1A 10
1226 # define R300_FPI2_ARGA_SRC2A 11
1227 # define R300_FPI2_ARGA_SRC1A_LRP 15
1228 # define R300_FPI2_ARGA_ZERO 16
1229 # define R300_FPI2_ARGA_ONE 17
1231 # define R300_FPI2_ARGA_HALF 18
1232 # define R300_FPI2_ARG0A_SHIFT 0
1233 # define R300_FPI2_ARG0A_MASK (31 << 0)
1234 # define R300_FPI2_ARG0A_NEG (1 << 5)
1236 # define R300_FPI2_ARG0A_ABS (1 << 6)
1237 # define R300_FPI2_ARG1A_SHIFT 7
1238 # define R300_FPI2_ARG1A_MASK (31 << 7)
1239 # define R300_FPI2_ARG1A_NEG (1 << 12)
1241 # define R300_FPI2_ARG1A_ABS (1 << 13)
1242 # define R300_FPI2_ARG2A_SHIFT 14
1243 # define R300_FPI2_ARG2A_MASK (31 << 14)
1244 # define R300_FPI2_ARG2A_NEG (1 << 19)
1246 # define R300_FPI2_ARG2A_ABS (1 << 20)
1247 # define R300_FPI2_SPECIAL_LRP (1 << 21)
1248 # define R300_FPI2_OUTA_MAD (0 << 23)
1249 # define R300_FPI2_OUTA_DP4 (1 << 23)
1250 # define R300_FPI2_OUTA_MIN (2 << 23)
1251 # define R300_FPI2_OUTA_MAX (3 << 23)
1252 # define R300_FPI2_OUTA_CMP (6 << 23)
1253 # define R300_FPI2_OUTA_FRC (7 << 23)
1254 # define R300_FPI2_OUTA_EX2 (8 << 23)
1255 # define R300_FPI2_OUTA_LG2 (9 << 23)
1256 # define R300_FPI2_OUTA_RCP (10 << 23)
1257 # define R300_FPI2_OUTA_RSQ (11 << 23)
1258 # define R300_FPI2_OUTA_SAT (1 << 30)
1259 # define R300_FPI2_UNKNOWN_31 (1 << 31)
1260 /* END: Fragment program instruction set */
1262 /* Fog state and color */
1263 #define R300_RE_FOG_STATE 0x4BC0
1264 # define R300_FOG_ENABLE (1 << 0)
1265 # define R300_FOG_MODE_LINEAR (0 << 1)
1266 # define R300_FOG_MODE_EXP (1 << 1)
1267 # define R300_FOG_MODE_EXP2 (2 << 1)
1268 # define R300_FOG_MODE_MASK (3 << 1)
1269 #define R300_FOG_COLOR_R 0x4BC8
1270 #define R300_FOG_COLOR_G 0x4BCC
1271 #define R300_FOG_COLOR_B 0x4BD0
1273 #define R300_PP_ALPHA_TEST 0x4BD4
1274 # define R300_REF_ALPHA_MASK 0x000000ff
1275 # define R300_ALPHA_TEST_FAIL (0 << 8)
1276 # define R300_ALPHA_TEST_LESS (1 << 8)
1277 # define R300_ALPHA_TEST_LEQUAL (3 << 8)
1278 # define R300_ALPHA_TEST_EQUAL (2 << 8)
1279 # define R300_ALPHA_TEST_GEQUAL (6 << 8)
1280 # define R300_ALPHA_TEST_GREATER (4 << 8)
1281 # define R300_ALPHA_TEST_NEQUAL (5 << 8)
1282 # define R300_ALPHA_TEST_PASS (7 << 8)
1283 # define R300_ALPHA_TEST_OP_MASK (7 << 8)
1284 # define R300_ALPHA_TEST_ENABLE (1 << 11)
1288 /* Fragment program parameters in 7.16 floating point */
1289 #define R300_PFS_PARAM_0_X 0x4C00
1290 #define R300_PFS_PARAM_0_Y 0x4C04
1291 #define R300_PFS_PARAM_0_Z 0x4C08
1292 #define R300_PFS_PARAM_0_W 0x4C0C
1293 /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */
1294 #define R300_PFS_PARAM_31_X 0x4DF0
1295 #define R300_PFS_PARAM_31_Y 0x4DF4
1296 #define R300_PFS_PARAM_31_Z 0x4DF8
1297 #define R300_PFS_PARAM_31_W 0x4DFC
1300 * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
1302 * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
1303 * are set to the same
1304 * function (both registers are always set up completely in any case)
1305 * - Most blend flags are simply copied from R200 and not tested yet
1307 #define R300_RB3D_CBLEND 0x4E04
1308 #define R300_RB3D_ABLEND 0x4E08
1309 /* the following only appear in CBLEND */
1310 # define R300_BLEND_ENABLE (1 << 0)
1311 # define R300_BLEND_UNKNOWN (3 << 1)
1312 # define R300_BLEND_NO_SEPARATE (1 << 3)
1313 /* the following are shared between CBLEND and ABLEND */
1314 # define R300_FCN_MASK (3 << 12)
1315 # define R300_COMB_FCN_ADD_CLAMP (0 << 12)
1316 # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
1317 # define R300_COMB_FCN_SUB_CLAMP (2 << 12)
1318 # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
1319 # define R300_COMB_FCN_MIN (4 << 12)
1320 # define R300_COMB_FCN_MAX (5 << 12)
1321 # define R300_COMB_FCN_RSUB_CLAMP (6 << 12)
1322 # define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12)
1323 # define R300_BLEND_GL_ZERO (32)
1324 # define R300_BLEND_GL_ONE (33)
1325 # define R300_BLEND_GL_SRC_COLOR (34)
1326 # define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35)
1327 # define R300_BLEND_GL_DST_COLOR (36)
1328 # define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37)
1329 # define R300_BLEND_GL_SRC_ALPHA (38)
1330 # define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)
1331 # define R300_BLEND_GL_DST_ALPHA (40)
1332 # define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41)
1333 # define R300_BLEND_GL_SRC_ALPHA_SATURATE (42)
1334 # define R300_BLEND_GL_CONST_COLOR (43)
1335 # define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44)
1336 # define R300_BLEND_GL_CONST_ALPHA (45)
1337 # define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)
1338 # define R300_BLEND_MASK (63)
1339 # define R300_SRC_BLEND_SHIFT (16)
1340 # define R300_DST_BLEND_SHIFT (24)
1341 #define R300_RB3D_BLEND_COLOR 0x4E10
1342 #define R300_RB3D_COLORMASK 0x4E0C
1343 # define R300_COLORMASK0_B (1<<0)
1344 # define R300_COLORMASK0_G (1<<1)
1345 # define R300_COLORMASK0_R (1<<2)
1346 # define R300_COLORMASK0_A (1<<3)
1350 #define R300_RB3D_COLOROFFSET0 0x4E28
1351 # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */
1352 #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */
1353 #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */
1354 #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */
1358 /* Bit 16: Larger tiles
1360 * Bit 18: Extremely weird tile like, but some pixels duplicated?
1362 #define R300_RB3D_COLORPITCH0 0x4E38
1363 # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
1364 # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
1365 # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */
1366 # define R300_COLOR_MICROTILE_SQUARE_ENABLE (2 << 17)
1367 # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
1368 # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
1369 # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
1370 # define R300_COLOR_FORMAT_RGB565 (2 << 22)
1371 # define R300_COLOR_FORMAT_ARGB8888 (3 << 22)
1372 #define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */
1373 #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */
1374 #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
1376 #define R300_RB3D_AARESOLVE_OFFSET 0x4E80
1377 #define R300_RB3D_AARESOLVE_PITCH 0x4E84
1378 #define R300_RB3D_AARESOLVE_CTL 0x4E88
1381 /* Guess by Vladimir.
1382 * Set to 0A before 3D operations, set to 02 afterwards.
1384 /*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/
1385 # define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
1386 # define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
1389 /* There seems to be no "write only" setting, so use Z-test = ALWAYS
1391 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
1393 #define R300_ZB_CNTL 0x4F00
1394 # define R300_STENCIL_ENABLE (1 << 0)
1395 # define R300_Z_ENABLE (1 << 1)
1396 # define R300_Z_WRITE_ENABLE (1 << 2)
1397 # define R300_Z_SIGNED_COMPARE (1 << 3)
1398 # define R300_STENCIL_FRONT_BACK (1 << 4)
1400 #define R300_ZB_ZSTENCILCNTL 0x4f04
1402 # define R300_ZS_NEVER 0
1403 # define R300_ZS_LESS 1
1404 # define R300_ZS_LEQUAL 2
1405 # define R300_ZS_EQUAL 3
1406 # define R300_ZS_GEQUAL 4
1407 # define R300_ZS_GREATER 5
1408 # define R300_ZS_NOTEQUAL 6
1409 # define R300_ZS_ALWAYS 7
1410 # define R300_ZS_MASK 7
1412 # define R300_ZS_KEEP 0
1413 # define R300_ZS_ZERO 1
1414 # define R300_ZS_REPLACE 2
1415 # define R300_ZS_INCR 3
1416 # define R300_ZS_DECR 4
1417 # define R300_ZS_INVERT 5
1418 # define R300_ZS_INCR_WRAP 6
1419 # define R300_ZS_DECR_WRAP 7
1420 # define R300_Z_FUNC_SHIFT 0
1421 /* front and back refer to operations done for front
1422 and back faces, i.e. separate stencil function support */
1423 # define R300_S_FRONT_FUNC_SHIFT 3
1424 # define R300_S_FRONT_SFAIL_OP_SHIFT 6
1425 # define R300_S_FRONT_ZPASS_OP_SHIFT 9
1426 # define R300_S_FRONT_ZFAIL_OP_SHIFT 12
1427 # define R300_S_BACK_FUNC_SHIFT 15
1428 # define R300_S_BACK_SFAIL_OP_SHIFT 18
1429 # define R300_S_BACK_ZPASS_OP_SHIFT 21
1430 # define R300_S_BACK_ZFAIL_OP_SHIFT 24
1432 #define R300_ZB_STENCILREFMASK 0x4f08
1433 # define R300_STENCILREF_SHIFT 0
1434 # define R300_STENCILREF_MASK 0x000000ff
1435 # define R300_STENCILMASK_SHIFT 8
1436 # define R300_STENCILMASK_MASK 0x0000ff00
1437 # define R300_STENCILWRITEMASK_SHIFT 16
1438 # define R300_STENCILWRITEMASK_MASK 0x00ff0000
1442 #define R300_ZB_FORMAT 0x4f10
1443 # define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
1444 # define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
1445 # define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
1446 /* reserved up to (15 << 0) */
1447 # define R300_INVERT_13E3_LEADING_ONES (0 << 4)
1448 # define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
1450 #define R300_ZB_ZTOP 0x4F14
1451 # define R300_ZTOP_DISABLE (0 << 0)
1452 # define R300_ZTOP_ENABLE (1 << 0)
1456 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
1457 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
1458 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
1459 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
1460 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
1461 # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
1462 # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
1464 #define R300_ZB_BW_CNTL 0x4f1c
1465 # define R300_HIZ_DISABLE (0 << 0)
1466 # define R300_HIZ_ENABLE (1 << 0)
1467 # define R300_HIZ_MIN (0 << 1)
1468 # define R300_HIZ_MAX (1 << 1)
1469 # define R300_FAST_FILL_DISABLE (0 << 2)
1470 # define R300_FAST_FILL_ENABLE (1 << 2)
1471 # define R300_RD_COMP_DISABLE (0 << 3)
1472 # define R300_RD_COMP_ENABLE (1 << 3)
1473 # define R300_WR_COMP_DISABLE (0 << 4)
1474 # define R300_WR_COMP_ENABLE (1 << 4)
1475 # define R300_ZB_CB_CLEAR_RMW (0 << 5)
1476 # define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
1477 # define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
1478 # define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
1480 # define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
1481 # define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
1482 # define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
1483 # define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
1485 # define R500_BMASK_ENABLE (0 << 10)
1486 # define R500_BMASK_DISABLE (1 << 10)
1487 # define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
1488 # define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
1489 # define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
1490 # define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
1491 # define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
1492 # define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
1493 # define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
1494 # define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
1495 # define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
1496 # define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
1497 # define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
1498 # define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
1499 # define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
1500 # define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
1501 # define R500_PEQ_PACKING_DISABLE (0 << 18)
1502 # define R500_PEQ_PACKING_ENABLE (1 << 18)
1503 # define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
1504 # define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
1509 /* Z Buffer Address Offset.
1510 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
1512 #define R300_ZB_DEPTHOFFSET 0x4f20
1514 /* Z Buffer Pitch and Endian Control */
1515 #define R300_ZB_DEPTHPITCH 0x4f24
1516 # define R300_DEPTHPITCH_MASK 0x00003FFC
1517 # define R300_DEPTHMACROTILE_DISABLE (0 << 16)
1518 # define R300_DEPTHMACROTILE_ENABLE (1 << 16)
1519 # define R300_DEPTHMICROTILE_LINEAR (0 << 17)
1520 # define R300_DEPTHMICROTILE_TILED (1 << 17)
1521 # define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
1522 # define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
1523 # define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
1524 # define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
1525 # define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
1527 /* Z Buffer Clear Value */
1528 #define R300_ZB_DEPTHCLEARVALUE 0x4f28
1530 #define R300_ZB_ZMASK_OFFSET 0x4f30
1531 #define R300_ZB_ZMASK_PITCH 0x4f34
1532 #define R300_ZB_ZMASK_WRINDEX 0x4f38
1533 #define R300_ZB_ZMASK_DWORD 0x4f3c
1534 #define R300_ZB_ZMASK_RDINDEX 0x4f40
1536 /* Hierarchical Z Memory Offset */
1537 #define R300_ZB_HIZ_OFFSET 0x4f44
1539 /* Hierarchical Z Write Index */
1540 #define R300_ZB_HIZ_WRINDEX 0x4f48
1542 /* Hierarchical Z Data */
1543 #define R300_ZB_HIZ_DWORD 0x4f4c
1545 /* Hierarchical Z Read Index */
1546 #define R300_ZB_HIZ_RDINDEX 0x4f50
1548 /* Hierarchical Z Pitch */
1549 #define R300_ZB_HIZ_PITCH 0x4f54
1551 /* Z Buffer Z Pass Counter Data */
1552 #define R300_ZB_ZPASS_DATA 0x4f58
1554 /* Z Buffer Z Pass Counter Address */
1555 #define R300_ZB_ZPASS_ADDR 0x4f5c
1557 /* Depth buffer X and Y coordinate offset */
1558 #define R300_ZB_DEPTHXY_OFFSET 0x4f60
1559 # define R300_DEPTHX_OFFSET_SHIFT 1
1560 # define R300_DEPTHX_OFFSET_MASK 0x000007FE
1561 # define R300_DEPTHY_OFFSET_SHIFT 17
1562 # define R300_DEPTHY_OFFSET_MASK 0x07FE0000
1564 /* Sets the fifo sizes */
1565 #define R500_ZB_FIFO_SIZE 0x4fd0
1566 # define R500_OP_FIFO_SIZE_FULL (0 << 0)
1567 # define R500_OP_FIFO_SIZE_HALF (1 << 0)
1568 # define R500_OP_FIFO_SIZE_QUATER (2 << 0)
1569 # define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
1571 /* Stencil Reference Value and Mask for backfacing quads */
1572 /* R300_ZB_STENCILREFMASK handles front face */
1573 #define R500_ZB_STENCILREFMASK_BF 0x4fd4
1574 # define R500_STENCILREF_SHIFT 0
1575 # define R500_STENCILREF_MASK 0x000000ff
1576 # define R500_STENCILMASK_SHIFT 8
1577 # define R500_STENCILMASK_MASK 0x0000ff00
1578 # define R500_STENCILWRITEMASK_SHIFT 16
1579 # define R500_STENCILWRITEMASK_MASK 0x00ff0000
1581 /* BEGIN: Vertex program instruction set */
1583 /* Every instruction is four dwords long:
1584 * DWORD 0: output and opcode
1585 * DWORD 1: first argument
1586 * DWORD 2: second argument
1587 * DWORD 3: third argument
1590 * - ABS r, a is implemented as MAX r, a, -a
1591 * - MOV is implemented as ADD to zero
1592 * - XPD is implemented as MUL + MAD
1593 * - FLR is implemented as FRC + ADD
1594 * - apparently, fglrx tries to schedule instructions so that there is at
1595 * least one instruction between the write to a temporary and the first
1596 * read from said temporary; however, violations of this scheduling are
1598 * - register indices seem to be unrelated with OpenGL aliasing to
1599 * conventional state
1600 * - only one attribute and one parameter can be loaded at a time; however,
1601 * the same attribute/parameter can be used for more than one argument
1602 * - the second software argument for POW is the third hardware argument
1604 * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
1606 * There is some magic surrounding LIT:
1607 * The single argument is replicated across all three inputs, but swizzled:
1608 * First argument: xyzy
1609 * Second argument: xyzx
1610 * Third argument: xyzw
1611 * Whenever the result is used later in the fragment program, fglrx forces
1612 * x and w to be 1.0 in the input selection; I don't know whether this is
1613 * strictly necessary
1615 #define R300_VPI_OUT_OP_DOT (1 << 0)
1616 #define R300_VPI_OUT_OP_MUL (2 << 0)
1617 #define R300_VPI_OUT_OP_ADD (3 << 0)
1618 #define R300_VPI_OUT_OP_MAD (4 << 0)
1619 #define R300_VPI_OUT_OP_DST (5 << 0)
1620 #define R300_VPI_OUT_OP_FRC (6 << 0)
1621 #define R300_VPI_OUT_OP_MAX (7 << 0)
1622 #define R300_VPI_OUT_OP_MIN (8 << 0)
1623 #define R300_VPI_OUT_OP_SGE (9 << 0)
1624 #define R300_VPI_OUT_OP_SLT (10 << 0)
1625 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
1626 #define R300_VPI_OUT_OP_UNK12 (12 << 0)
1627 #define R300_VPI_OUT_OP_ARL (13 << 0)
1628 #define R300_VPI_OUT_OP_EXP (65 << 0)
1629 #define R300_VPI_OUT_OP_LOG (66 << 0)
1630 /* Used in fog computations, scalar(scalar) */
1631 #define R300_VPI_OUT_OP_UNK67 (67 << 0)
1632 #define R300_VPI_OUT_OP_LIT (68 << 0)
1633 #define R300_VPI_OUT_OP_POW (69 << 0)
1634 #define R300_VPI_OUT_OP_RCP (70 << 0)
1635 #define R300_VPI_OUT_OP_RSQ (72 << 0)
1636 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
1637 #define R300_VPI_OUT_OP_UNK73 (73 << 0)
1638 #define R300_VPI_OUT_OP_EX2 (75 << 0)
1639 #define R300_VPI_OUT_OP_LG2 (76 << 0)
1640 #define R300_VPI_OUT_OP_MAD_2 (128 << 0)
1641 /* all temps, vector(scalar, vector, vector) */
1642 #define R300_VPI_OUT_OP_UNK129 (129 << 0)
1644 #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
1645 #define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8)
1646 #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
1647 #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
1649 #define R300_VPI_OUT_REG_INDEX_SHIFT 13
1650 /* GUESS based on fglrx native limits */
1651 #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13)
1653 #define R300_VPI_OUT_WRITE_X (1 << 20)
1654 #define R300_VPI_OUT_WRITE_Y (1 << 21)
1655 #define R300_VPI_OUT_WRITE_Z (1 << 22)
1656 #define R300_VPI_OUT_WRITE_W (1 << 23)
1658 #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0)
1659 #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
1660 #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
1661 #define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
1662 #define R300_VPI_IN_REG_CLASS_MASK (31 << 0)
1664 #define R300_VPI_IN_REG_INDEX_SHIFT 5
1665 /* GUESS based on fglrx native limits */
1666 #define R300_VPI_IN_REG_INDEX_MASK (255 << 5)
1668 /* The R300 can select components from the input register arbitrarily.
1669 * Use the following constants, shifted by the component shift you
1672 #define R300_VPI_IN_SELECT_X 0
1673 #define R300_VPI_IN_SELECT_Y 1
1674 #define R300_VPI_IN_SELECT_Z 2
1675 #define R300_VPI_IN_SELECT_W 3
1676 #define R300_VPI_IN_SELECT_ZERO 4
1677 #define R300_VPI_IN_SELECT_ONE 5
1678 #define R300_VPI_IN_SELECT_MASK 7
1680 #define R300_VPI_IN_X_SHIFT 13
1681 #define R300_VPI_IN_Y_SHIFT 16
1682 #define R300_VPI_IN_Z_SHIFT 19
1683 #define R300_VPI_IN_W_SHIFT 22
1685 #define R300_VPI_IN_NEG_X (1 << 25)
1686 #define R300_VPI_IN_NEG_Y (1 << 26)
1687 #define R300_VPI_IN_NEG_Z (1 << 27)
1688 #define R300_VPI_IN_NEG_W (1 << 28)
1689 /* END: Vertex program instruction set */
1691 /* BEGIN: Packet 3 commands */
1693 /* A primitive emission dword. */
1694 #define R300_PRIM_TYPE_NONE (0 << 0)
1695 #define R300_PRIM_TYPE_POINT (1 << 0)
1696 #define R300_PRIM_TYPE_LINE (2 << 0)
1697 #define R300_PRIM_TYPE_LINE_STRIP (3 << 0)
1698 #define R300_PRIM_TYPE_TRI_LIST (4 << 0)
1699 #define R300_PRIM_TYPE_TRI_FAN (5 << 0)
1700 #define R300_PRIM_TYPE_TRI_STRIP (6 << 0)
1701 #define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1702 #define R300_PRIM_TYPE_RECT_LIST (8 << 0)
1703 #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1704 #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1705 /* GUESS (based on r200) */
1706 #define R300_PRIM_TYPE_POINT_SPRITES (11 << 0)
1707 #define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
1708 #define R300_PRIM_TYPE_QUADS (13 << 0)
1709 #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
1710 #define R300_PRIM_TYPE_POLYGON (15 << 0)
1711 #define R300_PRIM_TYPE_MASK 0xF
1712 #define R300_PRIM_WALK_IND (1 << 4)
1713 #define R300_PRIM_WALK_LIST (2 << 4)
1714 #define R300_PRIM_WALK_RING (3 << 4)
1715 #define R300_PRIM_WALK_MASK (3 << 4)
1716 /* GUESS (based on r200) */
1717 #define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)
1718 #define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)
1719 #define R300_PRIM_NUM_VERTICES_SHIFT 16
1720 #define R300_PRIM_NUM_VERTICES_MASK 0xffff
1722 /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
1723 * Two parameter dwords:
1724 * 0. The first parameter appears to be always 0
1725 * 1. The second parameter is a standard primitive emission dword.
1727 #define R300_PACKET3_3D_DRAW_VBUF 0x00002800
1729 /* Specify the full set of vertex arrays as (address, stride).
1730 * The first parameter is the number of vertex arrays specified.
1731 * The rest of the command is a variable length list of blocks, where
1732 * each block is three dwords long and specifies two arrays.
1733 * The first dword of a block is split into two words, the lower significant
1734 * word refers to the first array, the more significant word to the second
1735 * array in the block.
1736 * The low byte of each word contains the size of an array entry in dwords,
1737 * the high byte contains the stride of the array.
1738 * The second dword of a block contains the pointer to the first array,
1739 * the third dword of a block contains the pointer to the second array.
1740 * Note that if the total number of arrays is odd, the third dword of
1741 * the last block is omitted.
1743 #define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00
1745 #define R300_PACKET3_INDX_BUFFER 0x00003300
1746 # define R300_EB_UNK1_SHIFT 24
1747 # define R300_EB_UNK1 (0x80<<24)
1748 # define R300_EB_UNK2 0x0810
1749 #define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400
1750 #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600
1752 /* END: Packet 3 commands */
1755 /* Color formats for 2d packets
1757 #define R300_CP_COLOR_FORMAT_CI8 2
1758 #define R300_CP_COLOR_FORMAT_ARGB1555 3
1759 #define R300_CP_COLOR_FORMAT_RGB565 4
1760 #define R300_CP_COLOR_FORMAT_ARGB8888 6
1761 #define R300_CP_COLOR_FORMAT_RGB332 7
1762 #define R300_CP_COLOR_FORMAT_RGB8 9
1763 #define R300_CP_COLOR_FORMAT_ARGB4444 15
1768 #define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
1770 #define R500_VAP_INDEX_OFFSET 0x208c
1772 #define R500_GA_US_VECTOR_INDEX 0x4250
1773 #define R500_GA_US_VECTOR_DATA 0x4254
1775 #define R500_RS_IP_0 0x4074
1776 #define R500_RS_INST_0 0x4320
1778 #define R500_US_CONFIG 0x4600
1780 #define R500_US_FC_CTRL 0x4624
1781 #define R500_US_CODE_ADDR 0x4630
1783 #define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0
1784 #define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
1786 #define R300_SU_REG_DEST 0x42c8
1787 #define RV530_FG_ZBREG_DEST 0x4be8
1788 #define R300_ZB_ZPASS_DATA 0x4f58
1789 #define R300_ZB_ZPASS_ADDR 0x4f5c
1791 #endif /* _R300_REG_H */
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