2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.6 2006/10/12 04:19:37 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.2 2007/01/06 08:34:52 dillon Exp $
32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
33 * that this driver still in its early stage, and possible of rewrite are
34 * pretty much guaranteed. There are supposedly several distinct parent/child
35 * busses to make this "perfect", but as for now and for the sake of
36 * simplicity, everything is gobble up within single source.
39 * 1) HDA Controller support
40 * 2) HDA Codecs support, which may include
44 * 3) Widget parser - the real magic of why this driver works on so
45 * many hardwares with minimal vendor specific quirk. The original
46 * parser was written using Ruby and can be found at
47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
48 * ruby parser take the verbose dmesg dump as its input. Refer to
49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
50 * interesting documents, especiall UAA (Universal Audio Architecture).
51 * 4) Possible vendor specific support.
52 * (snd_hda_intel, snd_hda_ati, etc..)
54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
55 * Compaq V3000 with Conexant HDA.
57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
59 * * This driver is a collaborative effort made by: *
61 * * Stephane E. Potvin <sepotvin@videotron.ca> *
62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
63 * * Wesley Morgan <morganw@chemikals.org> *
64 * * Daniel Eischen <deischen@FreeBSD.org> *
65 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
66 * * Ariff Abdullah <ariff@FreeBSD.org> *
68 * * ....and various people from freebsd-multimedia@FreeBSD.org *
70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
73 #include <sys/ctype.h>
75 #include <dev/sound/pcm/sound.h>
76 #include <bus/pci/pcireg.h>
77 #include <bus/pci/pcivar.h>
79 #include <dev/sound/pci/hda/hdac_private.h>
80 #include <dev/sound/pci/hda/hdac_reg.h>
81 #include <dev/sound/pci/hda/hda_reg.h>
82 #include <dev/sound/pci/hda/hdac.h>
86 #define HDA_DRV_TEST_REV "20061009_0031"
87 #define HDA_WIDGET_PARSER_REV 1
89 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.2 2007/01/06 08:34:52 dillon Exp $");
91 #undef HDA_DEBUG_ENABLED
92 #define HDA_DEBUG_ENABLED 1
94 #ifdef HDA_DEBUG_ENABLED
95 #define HDA_DEBUG(stmt) do { \
99 #define HDA_DEBUG(stmt)
102 #define HDA_BOOTVERBOSE(stmt) do { \
109 #undef HDAC_INTR_EXTRA
110 #define HDAC_INTR_EXTRA 1
113 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
114 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
115 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
116 #define hdac_lockowned(sc) (1)/*mtx_owned((sc)->lock)*/
118 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
119 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
120 (fl) == 0xffffffff || \
121 (((fl) & 0xffff0000) == 0xffff0000 && \
122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
123 (((fl) & 0x0000ffff) == 0x0000ffff && \
124 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
125 #define HDA_MATCH_ALL 0xffffffff
126 #define HDAC_INVALID 0xffffffff
128 #define HDA_MODEL_CONSTRUCT(vendor, model) \
129 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
131 /* Controller models */
134 #define INTEL_VENDORID 0x8086
135 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
136 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
137 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
138 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
139 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
142 #define NVIDIA_VENDORID 0x10de
143 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
144 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
145 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
146 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
147 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
148 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
149 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
152 #define ATI_VENDORID 0x1002
153 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
154 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
155 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
158 #define VIA_VENDORID 0x1106
159 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
160 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
163 #define SIS_VENDORID 0x1039
164 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
165 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
170 #define HP_VENDORID 0x103c
171 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
172 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
173 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
174 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
177 #define DELL_VENDORID 0x1028
178 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
179 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
180 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
183 #define CLEVO_VENDORID 0x1558
184 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
185 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
188 #define ACER_VENDORID 0x1025
189 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
192 #define ASUS_VENDORID 0x1043
193 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
194 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
197 #define IBM_VENDORID 0x1014
198 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
199 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
202 /* Misc constants.. */
203 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
204 #define HDA_AMP_MUTE_NONE (0)
205 #define HDA_AMP_MUTE_LEFT (1 << 0)
206 #define HDA_AMP_MUTE_RIGHT (1 << 1)
207 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
209 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
210 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
212 #define HDA_DAC_PATH (1 << 0)
213 #define HDA_ADC_PATH (1 << 1)
214 #define HDA_ADC_RECSEL (1 << 2)
216 #define HDA_CTL_OUT (1 << 0)
217 #define HDA_CTL_IN (1 << 1)
218 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT)
220 #define HDA_GPIO_MAX 15
222 #define HDA_QUIRK_GPIO0 (1 << 0)
223 #define HDA_QUIRK_GPIO1 (1 << 1)
224 #define HDA_QUIRK_GPIO2 (1 << 2)
225 #define HDA_QUIRK_SOFTPCMVOL (1 << 15)
226 #define HDA_QUIRK_FIXEDRATE (1 << 16)
227 #define HDA_QUIRK_FORCESTEREO (1 << 17)
229 static const struct {
232 } hdac_quirks_tab[] = {
233 { "gpio0", HDA_QUIRK_GPIO0 },
234 { "gpio1", HDA_QUIRK_GPIO1 },
235 { "gpio2", HDA_QUIRK_GPIO2 },
236 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
237 { "fixedrate", HDA_QUIRK_FIXEDRATE },
238 { "forcestereo", HDA_QUIRK_FORCESTEREO },
240 #define HDAC_QUIRKS_TAB_LEN \
241 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
243 #define HDA_BDL_MIN 2
244 #define HDA_BDL_MAX 256
245 #define HDA_BDL_DEFAULT HDA_BDL_MIN
247 #define HDA_BUFSZ_MIN 4096
248 #define HDA_BUFSZ_MAX 65536
249 #define HDA_BUFSZ_DEFAULT 16384
251 #define HDA_PARSE_MAXDEPTH 10
253 #define HDAC_UNSOLTAG_EVENT_HP 0x00
255 static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
263 static uint32_t hdac_fmt[] = {
264 AFMT_STEREO | AFMT_S16_LE,
268 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
270 static const struct {
274 { HDA_INTEL_82801F, "Intel 82801F" },
275 { HDA_INTEL_82801G, "Intel 82801G" },
276 { HDA_INTEL_82801H, "Intel 82801H" },
277 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
278 { HDA_NVIDIA_MCP51, "NVidia MCP51" },
279 { HDA_NVIDIA_MCP55, "NVidia MCP55" },
280 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" },
281 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" },
282 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" },
283 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" },
284 { HDA_ATI_SB450, "ATI SB450" },
285 { HDA_ATI_SB600, "ATI SB600" },
286 { HDA_VIA_VT82XX, "VIA VT8251/8237A" },
287 { HDA_SIS_966, "SiS 966" },
289 { HDA_INTEL_ALL, "Intel (Unknown)" },
290 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
291 { HDA_ATI_ALL, "ATI (Unknown)" },
292 { HDA_VIA_ALL, "VIA (Unknown)" },
293 { HDA_SIS_ALL, "SiS (Unknown)" },
295 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
297 static const struct {
304 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
305 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
306 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
307 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
308 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
309 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
310 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
311 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
312 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
313 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
314 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
315 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
316 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
317 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
318 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
319 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
320 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
321 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
322 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
323 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
324 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
325 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
326 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
327 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
328 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
329 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
330 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
331 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
332 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
333 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
334 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
335 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
336 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
337 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
338 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
340 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
342 /* All codecs you can eat... */
343 #define HDA_CODEC_CONSTRUCT(vendor, id) \
344 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
347 #define REALTEK_VENDORID 0x10ec
348 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
349 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
350 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
351 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
352 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
353 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
356 #define ANALOGDEVICE_VENDORID 0x11d4
357 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981)
358 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983)
359 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986)
360 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff)
363 #define CMEDIA_VENDORID 0x434d
364 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
365 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
368 #define SIGMATEL_VENDORID 0x8384
369 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
370 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
371 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
372 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
373 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
378 * Ok, the truth is, I don't have any idea at all whether
379 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
380 * place that tell me it is "Venice" is from its Windows driver INF.
383 * Waikiki - CX20551-22
385 #define CONEXANT_VENDORID 0x14f1
386 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
387 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
388 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
392 static const struct {
396 { HDA_CODEC_ALC260, "Realtek ALC260" },
397 { HDA_CODEC_ALC861, "Realtek ALC861" },
398 { HDA_CODEC_ALC880, "Realtek ALC880" },
399 { HDA_CODEC_ALC882, "Realtek ALC882" },
400 { HDA_CODEC_ALC883, "Realtek ALC883" },
401 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" },
402 { HDA_CODEC_AD1983, "Analog Device AD1983" },
403 { HDA_CODEC_AD1986A, "Analog Device AD1986A" },
404 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
405 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
406 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
407 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
408 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
409 { HDA_CODEC_CXVENICE, "Conexant Venice" },
410 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
412 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
413 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" },
414 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
415 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
416 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
418 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
425 static const struct {
432 } hdac_hp_switch[] = {
433 /* Specific OEM models */
434 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
435 17, { 16, -1 }, 16 },
436 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
438 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
440 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
441 13, { 14, -1 }, -1 },
442 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
443 13, { 14, -1 }, -1 },
445 * All models that at least come from the same vendor with
448 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
449 17, { 16, -1 }, 16 },
450 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
452 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
453 13, { 14, -1 }, -1 },
455 #define HDAC_HP_SWITCH_LEN \
456 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
458 static const struct {
463 } hdac_eapd_switch[] = {
464 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
465 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
466 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
468 #define HDAC_EAPD_SWITCH_LEN \
469 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
471 /****************************************************************************
472 * Function prototypes
473 ****************************************************************************/
474 static void hdac_intr_handler(void *);
475 static int hdac_reset(struct hdac_softc *);
476 static int hdac_get_capabilities(struct hdac_softc *);
477 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
478 static int hdac_dma_alloc(struct hdac_softc *,
479 struct hdac_dma *, bus_size_t);
480 static void hdac_dma_free(struct hdac_dma *);
481 static int hdac_mem_alloc(struct hdac_softc *);
482 static void hdac_mem_free(struct hdac_softc *);
483 static int hdac_irq_alloc(struct hdac_softc *);
484 static void hdac_irq_free(struct hdac_softc *);
485 static void hdac_corb_init(struct hdac_softc *);
486 static void hdac_rirb_init(struct hdac_softc *);
487 static void hdac_corb_start(struct hdac_softc *);
488 static void hdac_rirb_start(struct hdac_softc *);
489 static void hdac_scan_codecs(struct hdac_softc *);
490 static int hdac_probe_codec(struct hdac_codec *);
491 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
492 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
494 static void hdac_attach2(void *);
496 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
498 static void hdac_command_send_internal(struct hdac_softc *,
499 struct hdac_command_list *, int);
501 static int hdac_probe(device_t);
502 static int hdac_attach(device_t);
503 static int hdac_detach(device_t);
504 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
505 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
507 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
509 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
510 nid_t, nid_t, int, int, int, int, int, int);
511 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
512 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
514 #define hdac_command(a1, a2, a3) \
515 hdac_command_sendone_internal(a1, a2, a3)
517 #define hdac_codec_id(d) \
518 ((uint32_t)((d == NULL) ? 0x00000000 : \
519 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \
520 ((uint32_t)(d)->device_id & 0x0000ffff))))
523 hdac_codec_name(struct hdac_devinfo *devinfo)
528 id = hdac_codec_id(devinfo);
530 for (i = 0; i < HDAC_CODECS_LEN; i++) {
531 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
532 return (hdac_codecs[i].name);
535 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
539 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
541 static char *ossname[] = SOUND_DEVICE_NAMES;
542 static char *unknown = "???";
545 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
546 if (devmask & (1 << i))
553 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
555 static char *ossname[] = SOUND_DEVICE_NAMES;
559 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
560 if (mask & (1 << i)) {
562 strlcat(buf, ", ", len);
563 strlcat(buf, ossname[i], len);
569 static struct hdac_audio_ctl *
570 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
572 if (devinfo == NULL ||
573 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
574 index == NULL || devinfo->function.audio.ctl == NULL ||
575 devinfo->function.audio.ctlcnt < 1 ||
576 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
578 return (&devinfo->function.audio.ctl[(*index)++]);
581 static struct hdac_audio_ctl *
582 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
585 struct hdac_audio_ctl *ctl, *retctl = NULL;
586 int i, at, atindex, found = 0;
588 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
601 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
602 if (ctl->enable == 0 || ctl->widget == NULL)
604 if (!(ctl->widget->nid == nid && (atindex == -1 ||
605 ctl->index == atindex)))
613 return ((at == -1) ? retctl : NULL);
617 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
619 struct hdac_softc *sc;
620 struct hdac_widget *w;
621 struct hdac_audio_ctl *ctl;
623 int i = 0, j, forcemute;
626 if (devinfo == NULL || devinfo->codec == NULL ||
627 devinfo->codec->sc == NULL)
630 sc = devinfo->codec->sc;
631 cad = devinfo->codec->cad;
632 id = hdac_codec_id(devinfo);
633 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
634 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
635 sc->pci_subvendor) &&
636 hdac_hp_switch[i].id == id)
640 if (i >= HDAC_HP_SWITCH_LEN)
644 if (hdac_hp_switch[i].eapdnid != -1) {
645 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
646 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
647 forcemute = (w->param.eapdbtl &
648 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
651 res = hdac_command(sc,
652 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
654 device_printf(sc->dev,
655 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
656 hdac_hp_switch[i].hpnid, res);
660 switch (hdac_hp_switch[i].type) {
661 case HDAC_HP_SWITCH_CTL:
662 ctl = hdac_audio_ctl_amp_get(devinfo,
663 hdac_hp_switch[i].hpnid, 0, 1);
665 ctl->muted = (res != 0 && forcemute == 0) ?
666 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
667 hdac_audio_ctl_amp_set(ctl,
668 HDA_AMP_MUTE_DEFAULT, ctl->left,
671 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
672 ctl = hdac_audio_ctl_amp_get(devinfo,
673 hdac_hp_switch[i].spkrnid[j], 0, 1);
675 ctl->muted = (res != 0 || forcemute == 1) ?
676 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
677 hdac_audio_ctl_amp_set(ctl,
678 HDA_AMP_MUTE_DEFAULT, ctl->left,
683 case HDAC_HP_SWITCH_CTRL:
686 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
687 if (w != NULL && w->type ==
688 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
690 w->wclass.pin.ctrl |=
691 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
693 w->wclass.pin.ctrl &=
694 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
696 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
697 w->wclass.pin.ctrl), cad);
699 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
700 w = hdac_widget_get(devinfo,
701 hdac_hp_switch[i].spkrnid[j]);
702 if (w != NULL && w->type ==
703 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
704 w->wclass.pin.ctrl &=
705 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
707 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
709 w->wclass.pin.ctrl), cad);
714 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
715 if (w != NULL && w->type ==
716 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
717 w->wclass.pin.ctrl &=
718 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
720 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
721 w->wclass.pin.ctrl), cad);
723 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
724 w = hdac_widget_get(devinfo,
725 hdac_hp_switch[i].spkrnid[j]);
726 if (w != NULL && w->type ==
727 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
729 w->wclass.pin.ctrl |=
730 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
732 w->wclass.pin.ctrl &=
733 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
735 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
737 w->wclass.pin.ctrl), cad);
748 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
750 struct hdac_softc *sc;
751 struct hdac_devinfo *devinfo = NULL;
752 device_t *devlist = NULL;
755 if (codec == NULL || codec->sc == NULL)
761 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
764 device_get_children(sc->dev, &devlist, &devcount);
765 for (i = 0; devlist != NULL && i < devcount; i++) {
766 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
767 if (devinfo != NULL && devinfo->node_type ==
768 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
769 devinfo->codec != NULL &&
770 devinfo->codec->cad == codec->cad) {
776 kfree(devlist, M_TEMP);
782 case HDAC_UNSOLTAG_EVENT_HP:
783 hdac_hp_switch_handler(devinfo);
791 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
793 /* XXX to be removed */
794 #ifdef HDAC_INTR_EXTRA
801 /* XXX to be removed */
802 #ifdef HDAC_INTR_EXTRA
803 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
806 /* XXX to be removed */
807 #ifdef HDAC_INTR_EXTRA
809 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
810 device_printf(sc->dev,
811 "PCMDIR_%s intr triggered beyond stream boundary:"
813 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
817 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
818 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
820 /* XXX to be removed */
821 #ifdef HDAC_INTR_EXTRA
822 if (res & HDAC_SDSTS_BCIS) {
824 ch->prevptr = ch->ptr;
825 ch->ptr += sndbuf_getblksz(ch->b);
826 ch->ptr %= sndbuf_getsize(ch->b);
830 /* XXX to be removed */
831 #ifdef HDAC_INTR_EXTRA
836 /****************************************************************************
837 * void hdac_intr_handler(void *)
839 * Interrupt handler. Processes interrupts received from the hdac.
840 ****************************************************************************/
842 hdac_intr_handler(void *context)
844 struct hdac_softc *sc;
848 struct hdac_rirb *rirb_base, *rirb;
852 sc = (struct hdac_softc *)context;
855 /* Do we have anything to do? */
856 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
857 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
862 /* Was this a controller interrupt? */
863 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
864 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
865 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
866 /* Get as many responses that we can */
867 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
868 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
869 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
870 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
871 BUS_DMASYNC_POSTREAD);
872 while (sc->rirb_rp != rirbwp) {
874 sc->rirb_rp %= sc->rirb_size;
875 rirb = &rirb_base[sc->rirb_rp];
876 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
877 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
878 utag = rirb->response >> 26;
879 if (ucad > -1 && ucad < HDAC_CODEC_MAX &&
880 sc->codecs[ucad] != NULL) {
881 sc->unsolq[sc->unsolq_wp++] =
884 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
888 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
890 /* XXX to be removed */
891 /* Clear interrupt and exit */
892 #ifdef HDAC_INTR_EXTRA
893 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
896 if (intsts & HDAC_INTSTS_SIS_MASK) {
897 if (intsts & (1 << sc->num_iss))
898 hdac_stream_intr(sc, &sc->play);
899 if (intsts & (1 << 0))
900 hdac_stream_intr(sc, &sc->rec);
901 /* XXX to be removed */
902 #ifdef HDAC_INTR_EXTRA
903 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & HDAC_INTSTS_SIS_MASK);
907 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
908 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
909 while (sc->unsolq_rp != sc->unsolq_wp) {
910 ucad = sc->unsolq[sc->unsolq_rp] >> 16;
911 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
912 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
913 hdac_unsolicited_handler(sc->codecs[ucad], utag);
915 sc->unsolq_st = HDAC_UNSOLQ_READY;
921 /****************************************************************************
922 * int hdac_reset(hdac_softc *)
924 * Reset the hdac to a quiescent and known state.
925 ****************************************************************************/
927 hdac_reset(struct hdac_softc *sc)
933 * Stop all Streams DMA engine
935 for (i = 0; i < sc->num_iss; i++)
936 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
937 for (i = 0; i < sc->num_oss; i++)
938 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
939 for (i = 0; i < sc->num_bss; i++)
940 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
943 * Stop Control DMA engines
945 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
946 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
949 * Reset the controller. The reset must remain asserted for
950 * a minimum of 100us.
952 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
953 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
956 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
957 if (!(gctl & HDAC_GCTL_CRST))
961 if (gctl & HDAC_GCTL_CRST) {
962 device_printf(sc->dev, "Unable to put hdac in reset\n");
966 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
967 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
970 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
971 if (gctl & HDAC_GCTL_CRST)
975 if (!(gctl & HDAC_GCTL_CRST)) {
976 device_printf(sc->dev, "Device stuck in reset\n");
981 * Wait for codecs to finish their own reset sequence. The delay here
982 * should be of 250us but for some reasons, on it's not enough on my
983 * computer. Let's use twice as much as necessary to make sure that
984 * it's reset properly.
992 /****************************************************************************
993 * int hdac_get_capabilities(struct hdac_softc *);
995 * Retreive the general capabilities of the hdac;
996 * Number of Input Streams
997 * Number of Output Streams
998 * Number of bidirectional Streams
1000 * CORB and RIRB sizes
1001 ****************************************************************************/
1003 hdac_get_capabilities(struct hdac_softc *sc)
1006 uint8_t corbsize, rirbsize;
1008 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1009 sc->num_iss = HDAC_GCAP_ISS(gcap);
1010 sc->num_oss = HDAC_GCAP_OSS(gcap);
1011 sc->num_bss = HDAC_GCAP_BSS(gcap);
1013 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1015 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1016 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1017 HDAC_CORBSIZE_CORBSZCAP_256)
1018 sc->corb_size = 256;
1019 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1020 HDAC_CORBSIZE_CORBSZCAP_16)
1022 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1023 HDAC_CORBSIZE_CORBSZCAP_2)
1026 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1027 __func__, corbsize);
1031 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1032 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1033 HDAC_RIRBSIZE_RIRBSZCAP_256)
1034 sc->rirb_size = 256;
1035 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1036 HDAC_RIRBSIZE_RIRBSZCAP_16)
1038 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1039 HDAC_RIRBSIZE_RIRBSZCAP_2)
1042 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1043 __func__, rirbsize);
1051 /****************************************************************************
1054 * This function is called by bus_dmamap_load when the mapping has been
1055 * established. We just record the physical address of the mapping into
1056 * the struct hdac_dma passed in.
1057 ****************************************************************************/
1059 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1061 struct hdac_dma *dma;
1064 dma = (struct hdac_dma *)callback_arg;
1065 dma->dma_paddr = segs[0].ds_addr;
1070 hdac_dma_nocache(void *ptr)
1072 #if defined(__i386__) || defined(__amd64__)
1075 va = (vm_offset_t)ptr;
1076 pmap_kmodify_nc(va);
1080 /****************************************************************************
1081 * int hdac_dma_alloc
1083 * This function allocate and setup a dma region (struct hdac_dma).
1084 * It must be freed by a corresponding hdac_dma_free.
1085 ****************************************************************************/
1087 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1092 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1093 BUS_SPACE_MAXADDR_32BIT;
1094 bzero(dma, sizeof(*dma));
1099 result = bus_dma_tag_create(NULL, /* parent */
1100 HDAC_DMA_ALIGNMENT, /* alignment */
1102 lowaddr, /* lowaddr */
1103 BUS_SPACE_MAXADDR, /* highaddr */
1104 NULL, /* filtfunc */
1105 NULL, /* fistfuncarg */
1108 size, /* maxsegsz */
1110 &dma->dma_tag); /* dmat */
1112 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1118 * Allocate DMA memory
1120 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1121 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
1123 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1131 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1132 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma,
1134 if (result != 0 || dma->dma_paddr == 0) {
1135 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1139 bzero((void *)dma->dma_vaddr, size);
1140 hdac_dma_nocache(dma->dma_vaddr);
1144 if (dma->dma_map != NULL)
1145 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1146 if (dma->dma_tag != NULL)
1147 bus_dma_tag_destroy(dma->dma_tag);
1152 /****************************************************************************
1153 * void hdac_dma_free(struct hdac_dma *)
1155 * Free a struct dhac_dma that has been previously allocated via the
1156 * hdac_dma_alloc function.
1157 ****************************************************************************/
1159 hdac_dma_free(struct hdac_dma *dma)
1161 if (dma->dma_tag != NULL) {
1163 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1164 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1165 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1166 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1167 bus_dma_tag_destroy(dma->dma_tag);
1171 /****************************************************************************
1172 * int hdac_mem_alloc(struct hdac_softc *)
1174 * Allocate all the bus resources necessary to speak with the physical
1176 ****************************************************************************/
1178 hdac_mem_alloc(struct hdac_softc *sc)
1180 struct hdac_mem *mem;
1183 mem->mem_rid = PCIR_BAR(0);
1184 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1185 &mem->mem_rid, RF_ACTIVE);
1186 if (mem->mem_res == NULL) {
1187 device_printf(sc->dev,
1188 "%s: Unable to allocate memory resource\n", __func__);
1191 mem->mem_tag = rman_get_bustag(mem->mem_res);
1192 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1197 /****************************************************************************
1198 * void hdac_mem_free(struct hdac_softc *)
1200 * Free up resources previously allocated by hdac_mem_alloc.
1201 ****************************************************************************/
1203 hdac_mem_free(struct hdac_softc *sc)
1205 struct hdac_mem *mem;
1208 if (mem->mem_res != NULL)
1209 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1213 /****************************************************************************
1214 * int hdac_irq_alloc(struct hdac_softc *)
1216 * Allocate and setup the resources necessary for interrupt handling.
1217 ****************************************************************************/
1219 hdac_irq_alloc(struct hdac_softc *sc)
1221 struct hdac_irq *irq;
1226 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1227 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1228 if (irq->irq_res == NULL) {
1229 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1233 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1234 hdac_intr_handler, sc, &irq->irq_handle);
1236 device_printf(sc->dev,
1237 "%s: Unable to setup interrupt handler (%x)\n",
1245 if (irq->irq_res != NULL)
1246 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1251 /****************************************************************************
1252 * void hdac_irq_free(struct hdac_softc *)
1254 * Free up resources previously allocated by hdac_irq_alloc.
1255 ****************************************************************************/
1257 hdac_irq_free(struct hdac_softc *sc)
1259 struct hdac_irq *irq;
1262 if (irq->irq_handle != NULL)
1263 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1264 if (irq->irq_res != NULL)
1265 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1269 /****************************************************************************
1270 * void hdac_corb_init(struct hdac_softc *)
1272 * Initialize the corb registers for operations but do not start it up yet.
1273 * The CORB engine must not be running when this function is called.
1274 ****************************************************************************/
1276 hdac_corb_init(struct hdac_softc *sc)
1281 /* Setup the CORB size. */
1282 switch (sc->corb_size) {
1284 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1287 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1290 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1293 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1295 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1297 /* Setup the CORB Address in the hdac */
1298 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1299 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1300 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1302 /* Set the WP and RP */
1304 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1305 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1307 * The HDA specification indicates that the CORBRPRST bit will always
1308 * read as zero. Unfortunately, it seems that at least the 82801G
1309 * doesn't reset the bit to zero, which stalls the corb engine.
1310 * manually reset the bit to zero before continuing.
1312 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1314 /* Enable CORB error reporting */
1316 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1320 /****************************************************************************
1321 * void hdac_rirb_init(struct hdac_softc *)
1323 * Initialize the rirb registers for operations but do not start it up yet.
1324 * The RIRB engine must not be running when this function is called.
1325 ****************************************************************************/
1327 hdac_rirb_init(struct hdac_softc *sc)
1332 /* Setup the RIRB size. */
1333 switch (sc->rirb_size) {
1335 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1338 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1341 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1344 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1346 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1348 /* Setup the RIRB Address in the hdac */
1349 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1350 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1351 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1353 /* Setup the WP and RP */
1355 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1357 /* Setup the interrupt threshold */
1358 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1360 /* Enable Overrun and response received reporting */
1362 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1363 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1365 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1369 * Make sure that the Host CPU cache doesn't contain any dirty
1370 * cache lines that falls in the rirb. If I understood correctly, it
1371 * should be sufficient to do this only once as the rirb is purely
1372 * read-only from now on.
1374 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1375 BUS_DMASYNC_PREREAD);
1378 /****************************************************************************
1379 * void hdac_corb_start(hdac_softc *)
1381 * Startup the corb DMA engine
1382 ****************************************************************************/
1384 hdac_corb_start(struct hdac_softc *sc)
1388 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1389 corbctl |= HDAC_CORBCTL_CORBRUN;
1390 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1393 /****************************************************************************
1394 * void hdac_rirb_start(hdac_softc *)
1396 * Startup the rirb DMA engine
1397 ****************************************************************************/
1399 hdac_rirb_start(struct hdac_softc *sc)
1403 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1404 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1405 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1409 /****************************************************************************
1410 * void hdac_scan_codecs(struct hdac_softc *)
1412 * Scan the bus for available codecs.
1413 ****************************************************************************/
1415 hdac_scan_codecs(struct hdac_softc *sc)
1417 struct hdac_codec *codec;
1421 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1422 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1423 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1424 /* We have found a codec. */
1426 codec = (struct hdac_codec *)kmalloc(sizeof(*codec),
1427 M_HDAC, M_ZERO | M_NOWAIT);
1429 if (codec == NULL) {
1430 device_printf(sc->dev,
1431 "Unable to allocate memory for codec\n");
1434 codec->verbs_sent = 0;
1437 sc->codecs[i] = codec;
1438 if (hdac_probe_codec(codec) != 0)
1442 /* All codecs have been probed, now try to attach drivers to them */
1443 /* bus_generic_attach(sc->dev); */
1446 /****************************************************************************
1447 * void hdac_probe_codec(struct hdac_softc *, int)
1449 * Probe a the given codec_id for available function groups.
1450 ****************************************************************************/
1452 hdac_probe_codec(struct hdac_codec *codec)
1454 struct hdac_softc *sc = codec->sc;
1455 struct hdac_devinfo *devinfo;
1456 uint32_t vendorid, revisionid, subnode;
1460 nid_t cad = codec->cad;
1463 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1465 vendorid = hdac_command(sc,
1466 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1468 revisionid = hdac_command(sc,
1469 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1471 subnode = hdac_command(sc,
1472 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1474 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1475 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1477 if (vendorid == HDAC_INVALID ||
1478 revisionid == HDAC_INVALID ||
1479 subnode == HDAC_INVALID) {
1480 device_printf(sc->dev, "invalid response\n");
1485 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1486 startnode, endnode);
1488 for (i = startnode; i < endnode; i++) {
1489 devinfo = hdac_probe_function(codec, i);
1490 if (devinfo != NULL) {
1491 /* XXX Ignore other FG. */
1492 devinfo->vendor_id =
1493 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1494 devinfo->device_id =
1495 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1496 devinfo->revision_id =
1497 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1498 devinfo->stepping_id =
1499 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1501 device_printf(sc->dev,
1502 "HDA_DEBUG: \tFound AFG nid=%d "
1503 "[startnode=%d endnode=%d]\n",
1504 devinfo->nid, startnode, endnode);
1511 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1516 static struct hdac_devinfo *
1517 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1519 struct hdac_softc *sc = codec->sc;
1520 struct hdac_devinfo *devinfo;
1521 uint32_t fctgrptype;
1522 nid_t cad = codec->cad;
1524 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1525 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1527 /* XXX For now, ignore other FG. */
1528 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1532 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC,
1535 if (devinfo == NULL) {
1536 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1542 devinfo->node_type = fctgrptype;
1543 devinfo->codec = codec;
1545 hdac_add_child(sc, devinfo);
1551 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1553 devinfo->dev = device_add_child(sc->dev, NULL, -1);
1554 device_set_ivars(devinfo->dev, (void *)devinfo);
1555 /* XXX - Print more information when booting verbose??? */
1559 hdac_widget_connection_parse(struct hdac_widget *w)
1561 struct hdac_softc *sc = w->devinfo->codec->sc;
1563 int i, j, max, found, entnum, cnid;
1564 nid_t cad = w->devinfo->codec->cad;
1567 res = hdac_command(sc,
1568 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1570 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1575 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1579 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
1581 while (i < w->nconns) {
1582 res = hdac_command(sc,
1583 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1584 for (j = 0; j < entnum; j++) {
1586 cnid >>= (32 / entnum) * j;
1587 cnid &= (1 << (32 / entnum)) - 1;
1591 device_printf(sc->dev,
1592 "node %d: Adding %d: "
1593 "Max connection reached!\n",
1597 w->conns[found++] = cnid;
1603 if (w->nconns != found) {
1604 device_printf(sc->dev,
1605 "HDA_DEBUG: nid=%d WARNING!!! Connection "
1606 "length=%d != found=%d\n",
1607 nid, w->nconns, found);
1613 hdac_widget_pin_getconfig(struct hdac_widget *w)
1615 struct hdac_softc *sc;
1616 uint32_t config, id;
1619 sc = w->devinfo->codec->sc;
1620 cad = w->devinfo->codec->cad;
1622 id = hdac_codec_id(w->devinfo);
1624 config = hdac_command(sc,
1625 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
1628 * XXX REWRITE!!!! Don't argue!
1630 if (id == HDA_CODEC_ALC880 &&
1631 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
1632 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
1646 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1647 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1649 case 25: /* XXX MIC2 */
1650 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1651 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1653 case 26: /* LINE1 */
1654 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1655 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1657 case 27: /* XXX LINE2 */
1658 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1659 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1662 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1663 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
1678 hdac_widget_pin_parse(struct hdac_widget *w)
1680 struct hdac_softc *sc = w->devinfo->codec->sc;
1681 uint32_t config, pincap;
1682 char *devstr, *connstr;
1683 nid_t cad = w->devinfo->codec->cad;
1686 config = hdac_widget_pin_getconfig(w);
1687 w->wclass.pin.config = config;
1689 pincap = hdac_command(sc,
1690 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
1691 w->wclass.pin.cap = pincap;
1693 w->wclass.pin.ctrl = hdac_command(sc,
1694 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
1695 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
1696 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
1697 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE);
1699 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
1700 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
1701 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
1702 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1703 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
1704 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
1705 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
1706 w->param.eapdbtl = hdac_command(sc,
1707 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
1708 w->param.eapdbtl &= 0x7;
1709 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
1711 w->param.eapdbtl = HDAC_INVALID;
1713 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
1714 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
1715 devstr = "line out";
1717 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
1720 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
1721 devstr = "headphones out";
1723 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
1726 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
1727 devstr = "SPDIF out";
1729 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
1730 devstr = "digital (other) out";
1732 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
1733 devstr = "modem, line side";
1735 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
1736 devstr = "modem, handset side";
1738 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
1741 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
1744 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
1747 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
1748 devstr = "telephony";
1750 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
1751 devstr = "SPDIF in";
1753 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
1754 devstr = "digital (other) in";
1756 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
1764 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
1765 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
1768 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
1771 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
1774 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
1775 connstr = "jack / fixed";
1778 connstr = "unknown";
1782 strlcat(w->name, ": ", sizeof(w->name));
1783 strlcat(w->name, devstr, sizeof(w->name));
1784 strlcat(w->name, " (", sizeof(w->name));
1785 strlcat(w->name, connstr, sizeof(w->name));
1786 strlcat(w->name, ")", sizeof(w->name));
1790 hdac_widget_parse(struct hdac_widget *w)
1792 struct hdac_softc *sc = w->devinfo->codec->sc;
1795 nid_t cad = w->devinfo->codec->cad;
1798 wcap = hdac_command(sc,
1799 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
1801 w->param.widget_cap = wcap;
1802 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
1805 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
1806 typestr = "audio output";
1808 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
1809 typestr = "audio input";
1811 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
1812 typestr = "audio mixer";
1814 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
1815 typestr = "audio selector";
1817 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
1820 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
1821 typestr = "power widget";
1823 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
1824 typestr = "volume widget";
1826 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
1827 typestr = "beep widget";
1829 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
1830 typestr = "vendor widget";
1833 typestr = "unknown type";
1837 strlcpy(w->name, typestr, sizeof(w->name));
1839 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
1841 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
1846 hdac_widget_connection_parse(w);
1848 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
1849 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
1850 w->param.outamp_cap =
1852 HDA_CMD_GET_PARAMETER(cad, nid,
1853 HDA_PARAM_OUTPUT_AMP_CAP), cad);
1855 w->param.outamp_cap =
1856 w->devinfo->function.audio.outamp_cap;
1858 w->param.outamp_cap = 0;
1860 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
1861 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
1862 w->param.inamp_cap =
1864 HDA_CMD_GET_PARAMETER(cad, nid,
1865 HDA_PARAM_INPUT_AMP_CAP), cad);
1867 w->param.inamp_cap =
1868 w->devinfo->function.audio.inamp_cap;
1870 w->param.inamp_cap = 0;
1872 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
1873 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
1874 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
1875 cap = hdac_command(sc,
1876 HDA_CMD_GET_PARAMETER(cad, nid,
1877 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
1878 w->param.supp_stream_formats = (cap != 0) ? cap :
1879 w->devinfo->function.audio.supp_stream_formats;
1880 cap = hdac_command(sc,
1881 HDA_CMD_GET_PARAMETER(cad, nid,
1882 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
1883 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
1884 w->devinfo->function.audio.supp_pcm_size_rate;
1886 w->param.supp_stream_formats =
1887 w->devinfo->function.audio.supp_stream_formats;
1888 w->param.supp_pcm_size_rate =
1889 w->devinfo->function.audio.supp_pcm_size_rate;
1892 w->param.supp_stream_formats = 0;
1893 w->param.supp_pcm_size_rate = 0;
1896 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1897 hdac_widget_pin_parse(w);
1900 static struct hdac_widget *
1901 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
1903 if (devinfo == NULL || devinfo->widget == NULL ||
1904 nid < devinfo->startnode || nid >= devinfo->endnode)
1906 return (&devinfo->widget[nid - devinfo->startnode]);
1910 hdac_stream_stop(struct hdac_chan *ch)
1912 struct hdac_softc *sc = ch->devinfo->codec->sc;
1915 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
1916 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1918 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
1920 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1921 ctl &= ~(1 << (ch->off >> 5));
1922 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1926 hdac_stream_start(struct hdac_chan *ch)
1928 struct hdac_softc *sc = ch->devinfo->codec->sc;
1931 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1932 ctl |= 1 << (ch->off >> 5);
1933 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1935 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
1936 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1938 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
1942 hdac_stream_reset(struct hdac_chan *ch)
1944 struct hdac_softc *sc = ch->devinfo->codec->sc;
1949 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
1950 ctl |= HDAC_SDCTL_SRST;
1951 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
1953 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
1954 if (ctl & HDAC_SDCTL_SRST)
1958 if (!(ctl & HDAC_SDCTL_SRST)) {
1959 device_printf(sc->dev, "timeout in reset\n");
1961 ctl &= ~HDAC_SDCTL_SRST;
1962 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
1965 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
1966 if (!(ctl & HDAC_SDCTL_SRST))
1970 if (ctl & HDAC_SDCTL_SRST)
1971 device_printf(sc->dev, "can't reset!\n");
1975 hdac_stream_setid(struct hdac_chan *ch)
1977 struct hdac_softc *sc = ch->devinfo->codec->sc;
1980 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
1981 ctl &= ~HDAC_SDCTL2_STRM_MASK;
1982 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
1983 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
1987 hdac_bdl_setup(struct hdac_chan *ch)
1989 struct hdac_softc *sc = ch->devinfo->codec->sc;
1991 int blks, size, blocksize;
1992 struct hdac_bdle *bdle;
1995 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
1996 size = sndbuf_getsize(ch->b);
1997 blocksize = sndbuf_getblksz(ch->b);
1998 blks = size / blocksize;
1999 bdle = (struct hdac_bdle*)ch->bdl_dma.dma_vaddr;
2001 for (i = 0; i < blks; i++, bdle++) {
2002 bdle->addrl = (uint32_t)addr;
2003 bdle->addrh = (uint32_t)(addr >> 32);
2004 bdle->len = blocksize;
2010 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, size);
2011 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blks - 1);
2012 addr = ch->bdl_dma.dma_paddr;
2013 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2014 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2018 hdac_bdl_alloc(struct hdac_chan *ch)
2020 struct hdac_softc *sc = ch->devinfo->codec->sc;
2023 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2024 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2026 device_printf(sc->dev, "can't alloc bdl\n");
2029 hdac_dma_nocache(ch->bdl_dma.dma_vaddr);
2035 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2036 int index, int lmute, int rmute,
2037 int left, int right, int dir)
2044 if (left != right || lmute != rmute) {
2045 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2046 (lmute << 7) | left;
2048 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2049 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2050 (rmute << 7) | right;
2052 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2053 (lmute << 7) | left;
2056 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2060 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2061 int left, int right)
2063 struct hdac_softc *sc;
2067 if (ctl == NULL || ctl->widget == NULL ||
2068 ctl->widget->devinfo == NULL ||
2069 ctl->widget->devinfo->codec == NULL ||
2070 ctl->widget->devinfo->codec->sc == NULL)
2073 sc = ctl->widget->devinfo->codec->sc;
2074 cad = ctl->widget->devinfo->codec->cad;
2075 nid = ctl->widget->nid;
2077 if (mute == HDA_AMP_MUTE_DEFAULT) {
2078 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2079 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2081 lmute = HDA_AMP_LEFT_MUTED(mute);
2082 rmute = HDA_AMP_RIGHT_MUTED(mute);
2085 if (ctl->dir & HDA_CTL_OUT)
2086 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2087 lmute, rmute, left, right, 0);
2088 if (ctl->dir & HDA_CTL_IN)
2089 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2090 lmute, rmute, left, right, 1);
2096 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2098 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2100 hdac_command(w->devinfo->codec->sc,
2101 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2102 w->nid, index), w->devinfo->codec->cad);
2107 /****************************************************************************
2108 * uint32_t hdac_command_sendone_internal
2110 * Wrapper function that sends only one command to a given codec
2111 ****************************************************************************/
2113 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2115 struct hdac_command_list cl;
2116 uint32_t response = HDAC_INVALID;
2118 if (!hdac_lockowned(sc))
2119 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2120 cl.num_commands = 1;
2122 cl.responses = &response;
2124 hdac_command_send_internal(sc, &cl, cad);
2129 /****************************************************************************
2130 * hdac_command_send_internal
2132 * Send a command list to the codec via the corb. We queue as much verbs as
2133 * we can and msleep on the codec. When the interrupt get the responses
2134 * back from the rirb, it will wake us up so we can queue the remaining verbs
2136 ****************************************************************************/
2138 hdac_command_send_internal(struct hdac_softc *sc,
2139 struct hdac_command_list *commands, nid_t cad)
2141 struct hdac_codec *codec;
2147 struct hdac_rirb *rirb_base, *rirb;
2151 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL)
2154 codec = sc->codecs[cad];
2155 codec->commands = commands;
2156 codec->responses_received = 0;
2157 codec->verbs_sent = 0;
2158 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2159 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2162 if (codec->verbs_sent != commands->num_commands) {
2163 /* Queue as many verbs as possible */
2164 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2165 bus_dmamap_sync(sc->corb_dma.dma_tag,
2166 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2167 while (codec->verbs_sent != commands->num_commands &&
2168 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2170 sc->corb_wp %= sc->corb_size;
2172 commands->verbs[codec->verbs_sent++];
2175 /* Send the verbs to the codecs */
2176 bus_dmamap_sync(sc->corb_dma.dma_tag,
2177 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2178 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2183 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2184 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2185 BUS_DMASYNC_POSTREAD);
2186 if (sc->rirb_rp != rirbwp) {
2189 sc->rirb_rp %= sc->rirb_size;
2190 rirb = &rirb_base[sc->rirb_rp];
2191 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2192 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2193 utag = rirb->response >> 26;
2194 if (ucad > -1 && ucad < HDAC_CODEC_MAX &&
2195 sc->codecs[ucad] != NULL) {
2196 sc->unsolq[sc->unsolq_wp++] =
2199 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2201 } else if (codec->responses_received < commands->num_commands)
2202 codec->commands->responses[codec->responses_received++] =
2204 } while (sc->rirb_rp != rirbwp);
2208 } while (--timeout);
2209 } while ((codec->verbs_sent != commands->num_commands ||
2210 codec->responses_received != commands->num_commands) &&
2214 device_printf(sc->dev,
2215 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2216 __func__, commands->num_commands,
2217 codec->verbs_sent, codec->responses_received);
2219 codec->verbs_sent = 0;
2221 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2222 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2223 while (sc->unsolq_rp != sc->unsolq_wp) {
2224 ucad = sc->unsolq[sc->unsolq_rp] >> 16;
2225 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2226 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2227 hdac_unsolicited_handler(sc->codecs[ucad], utag);
2229 sc->unsolq_st = HDAC_UNSOLQ_READY;
2234 /****************************************************************************
2236 ****************************************************************************/
2238 /****************************************************************************
2239 * int hdac_probe(device_t)
2241 * Probe for the presence of an hdac. If none is found, check for a generic
2242 * match using the subclass of the device.
2243 ****************************************************************************/
2245 hdac_probe(device_t dev)
2249 uint16_t class, subclass;
2252 model = (uint32_t)pci_get_device(dev) << 16;
2253 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2254 class = pci_get_class(dev);
2255 subclass = pci_get_subclass(dev);
2257 bzero(desc, sizeof(desc));
2259 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
2260 if (hdac_devices[i].model == model) {
2261 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2265 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
2266 class == PCIC_MULTIMEDIA &&
2267 subclass == PCIS_MULTIMEDIA_HDA) {
2268 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2273 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
2274 subclass == PCIS_MULTIMEDIA_HDA) {
2275 strlcpy(desc, "Generic", sizeof(desc));
2278 if (result != ENXIO) {
2279 strlcat(desc, " High Definition Audio Controller",
2281 device_set_desc_copy(dev, desc);
2288 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
2289 struct pcm_channel *c, int dir)
2291 struct hdac_devinfo *devinfo = data;
2292 struct hdac_softc *sc = devinfo->codec->sc;
2293 struct hdac_chan *ch;
2296 if (dir == PCMDIR_PLAY) {
2298 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
2299 ch->dir = PCMDIR_PLAY;
2300 ch->sid = ++sc->streamcnt;
2301 devinfo->function.audio.playcnt++;
2304 ch->off = devinfo->function.audio.reccnt << 5;
2305 ch->dir = PCMDIR_REC;
2306 ch->sid = ++sc->streamcnt;
2307 devinfo->function.audio.reccnt++;
2309 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
2310 ch->caps.minspeed = ch->caps.maxspeed = 48000;
2311 ch->pcmrates[0] = 48000;
2312 ch->pcmrates[1] = 0;
2316 ch->devinfo = devinfo;
2317 ch->blksz = sc->chan_size / sc->chan_blkcnt;
2318 ch->blkcnt = sc->chan_blkcnt;
2321 if (hdac_bdl_alloc(ch) != 0) {
2326 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
2329 hdac_dma_nocache(sndbuf_getbuf(ch->b));
2335 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
2337 struct hdac_chan *ch = data;
2340 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
2341 if (format == ch->caps.fmtlist[i]) {
2351 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
2353 struct hdac_chan *ch = data;
2357 for (i = 0; ch->pcmrates[i] != 0; i++) {
2358 spd = ch->pcmrates[i];
2372 hdac_stream_setup(struct hdac_chan *ch)
2374 struct hdac_softc *sc = ch->devinfo->codec->sc;
2376 nid_t cad = ch->devinfo->codec->cad;
2380 if (ch->fmt & AFMT_S16_LE)
2381 fmt |= ch->bit16 << 4;
2382 else if (ch->fmt & AFMT_S32_LE)
2383 fmt |= ch->bit32 << 4;
2387 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
2388 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
2389 fmt |= hda_rate_tab[i].base;
2390 fmt |= hda_rate_tab[i].mul;
2391 fmt |= hda_rate_tab[i].div;
2396 if (ch->fmt & AFMT_STEREO)
2399 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
2401 for (i = 0; ch->io[i] != -1; i++) {
2403 device_printf(sc->dev,
2404 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
2406 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
2410 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
2412 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
2413 ch->sid << 4), cad);
2418 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
2420 struct hdac_chan *ch = data;
2422 sndbuf_resize(ch->b, ch->blkcnt, ch->blksz);
2428 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
2430 struct hdac_devinfo *devinfo = ch->devinfo;
2431 nid_t cad = devinfo->codec->cad;
2434 hdac_stream_stop(ch);
2436 for (i = 0; ch->io[i] != -1; i++) {
2438 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
2444 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
2448 hdac_stream_stop(ch);
2449 hdac_stream_reset(ch);
2451 hdac_stream_setid(ch);
2452 hdac_stream_setup(ch);
2453 hdac_stream_start(ch);
2457 hdac_channel_trigger(kobj_t obj, void *data, int go)
2459 struct hdac_chan *ch = data;
2460 struct hdac_softc *sc = ch->devinfo->codec->sc;
2465 hdac_channel_start(sc, ch);
2469 hdac_channel_stop(sc, ch);
2478 hdac_channel_getptr(kobj_t obj, void *data)
2480 struct hdac_chan *ch = data;
2481 struct hdac_softc *sc = ch->devinfo->codec->sc;
2486 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
2489 sz = sndbuf_getsize(ch->b);
2492 if (ch->dir == PCMDIR_REC) {
2493 delta = ptr % sndbuf_getblksz(ch->b);
2506 static struct pcmchan_caps *
2507 hdac_channel_getcaps(kobj_t obj, void *data)
2509 return (&((struct hdac_chan *)data)->caps);
2512 static kobj_method_t hdac_channel_methods[] = {
2513 KOBJMETHOD(channel_init, hdac_channel_init),
2514 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
2515 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
2516 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
2517 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
2518 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
2519 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
2522 CHANNEL_DECLARE(hdac_channel);
2525 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
2527 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
2528 struct hdac_softc *sc = devinfo->codec->sc;
2529 struct hdac_widget *w, *cw;
2530 struct hdac_audio_ctl *ctl;
2531 uint32_t mask, recmask, id;
2532 int i, j, softpcmvol;
2540 id = hdac_codec_id(devinfo);
2541 cad = devinfo->codec->cad;
2542 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
2543 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
2544 sc->pci_subvendor) &&
2545 hdac_hp_switch[i].id == id))
2547 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
2548 if (w != NULL && w->enable != 0
2550 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
2551 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) {
2553 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad,
2555 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE|
2556 HDAC_UNSOLTAG_EVENT_HP), cad);
2557 hdac_hp_switch_handler(devinfo);
2559 device_printf(sc->dev,
2560 "HDA_DEBUG: Enabling headphone/speaker "
2561 "audio routing switching:\n");
2562 device_printf(sc->dev,
2563 "HDA_DEBUG: \tindex=%d nid=%d "
2564 "pci_subvendor=0x%08x "
2566 i, w->nid, sc->pci_subvendor, id);
2571 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
2572 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
2573 sc->pci_subvendor) &&
2574 hdac_eapd_switch[i].id == id))
2576 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
2577 if (w == NULL || w->enable == 0)
2579 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
2580 w->param.eapdbtl == HDAC_INVALID)
2582 mask |= SOUND_MASK_OGAIN;
2586 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
2587 w = hdac_widget_get(devinfo, i);
2588 if (w == NULL || w->enable == 0)
2590 mask |= w->ctlflags;
2591 if (!(w->pflags & HDA_ADC_RECSEL))
2593 for (j = 0; j < w->nconns; j++) {
2594 cw = hdac_widget_get(devinfo, w->conns[j]);
2595 if (cw == NULL || cw->enable == 0)
2597 recmask |= cw->ctlflags;
2601 if (!(mask & SOUND_MASK_PCM)) {
2603 mask |= SOUND_MASK_PCM;
2605 softpcmvol = (devinfo->function.audio.quirks &
2606 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
2610 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
2611 if (ctl->widget == NULL || ctl->enable == 0)
2613 if (!(ctl->ossmask & SOUND_MASK_PCM))
2619 if (softpcmvol == 1 || ctl == NULL) {
2620 device_printf(sc->dev, "no softpcm support available\n");
2622 struct snddev_info *d = NULL;
2623 d = device_get_softc(sc->dev);
2625 d->flags |= SD_F_SOFTPCMVOL;
2627 device_printf(sc->dev,
2628 "HDA_DEBUG: %s Soft PCM volume\n",
2630 "Forcing" : "Enabling");
2635 * XXX Temporary quirk for STAC9220, until the parser
2638 if (id == HDA_CODEC_STAC9220) {
2639 mask |= SOUND_MASK_VOLUME;
2640 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
2642 if (ctl->widget == NULL || ctl->enable == 0)
2644 if (ctl->widget->nid == 11 && ctl->index == 0) {
2645 ctl->ossmask = SOUND_MASK_VOLUME;
2646 ctl->ossval = 100 | (100 << 8);
2648 ctl->ossmask &= ~SOUND_MASK_VOLUME;
2651 mix_setparentchild(m, SOUND_MIXER_VOLUME,
2653 if (!(mask & SOUND_MASK_VOLUME))
2654 mix_setrealdev(m, SOUND_MIXER_VOLUME,
2656 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
2658 if (ctl->widget == NULL || ctl->enable == 0)
2660 if (!HDA_FLAG_MATCH(ctl->ossmask,
2661 SOUND_MASK_VOLUME | SOUND_MASK_PCM))
2663 if (!(ctl->mute == 1 && ctl->step == 0))
2670 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER);
2672 mix_setrecdevs(m, recmask);
2673 mix_setdevs(m, mask);
2681 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
2682 unsigned left, unsigned right)
2684 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
2685 struct hdac_softc *sc = devinfo->codec->sc;
2686 struct hdac_widget *w;
2687 struct hdac_audio_ctl *ctl;
2689 int lvol, rvol, mlvol, mrvol;
2693 if (dev == SOUND_MIXER_OGAIN) {
2695 /*if (left != right || !(left == 0 || left == 1)) {
2699 id = hdac_codec_id(devinfo);
2700 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
2701 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
2702 sc->pci_subvendor) &&
2703 hdac_eapd_switch[i].id == id)
2706 if (i >= HDAC_EAPD_SWITCH_LEN) {
2710 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
2712 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
2713 w->param.eapdbtl == HDAC_INVALID) {
2717 orig = w->param.eapdbtl;
2719 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2721 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2722 if (orig != w->param.eapdbtl) {
2723 if (hdac_eapd_switch[i].hp_switch != 0)
2724 hdac_hp_switch_handler(devinfo);
2726 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
2727 w->nid, w->param.eapdbtl), devinfo->codec->cad);
2730 return (left | (left << 8));
2732 if (dev == SOUND_MIXER_VOLUME)
2733 devinfo->function.audio.mvol = left | (right << 8);
2735 mlvol = devinfo->function.audio.mvol & 0x7f;
2736 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
2741 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
2742 if (ctl->widget == NULL || ctl->enable == 0 ||
2743 !(ctl->ossmask & (1 << dev)))
2746 case SOUND_MIXER_VOLUME:
2747 lvol = ((ctl->ossval & 0x7f) * left) / 100;
2748 lvol = (lvol * ctl->step) / 100;
2749 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
2750 rvol = (rvol * ctl->step) / 100;
2753 if (ctl->ossmask & SOUND_MASK_VOLUME) {
2754 lvol = (left * mlvol) / 100;
2755 lvol = (lvol * ctl->step) / 100;
2756 rvol = (right * mrvol) / 100;
2757 rvol = (rvol * ctl->step) / 100;
2759 lvol = (left * ctl->step) / 100;
2760 rvol = (right * ctl->step) / 100;
2762 ctl->ossval = left | (right << 8);
2766 if (ctl->step < 1) {
2767 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
2768 (ctl->muted & HDA_AMP_MUTE_LEFT);
2769 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
2770 (ctl->muted & HDA_AMP_MUTE_RIGHT);
2772 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
2773 (ctl->muted & HDA_AMP_MUTE_LEFT);
2774 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
2775 (ctl->muted & HDA_AMP_MUTE_RIGHT);
2777 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
2781 return (left | (right << 8));
2785 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
2787 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
2788 struct hdac_widget *w, *cw;
2789 struct hdac_softc *sc = devinfo->codec->sc;
2790 uint32_t ret = src, target;
2794 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
2795 if (src & (1 << i)) {
2803 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
2804 w = hdac_widget_get(devinfo, i);
2805 if (w == NULL || w->enable == 0)
2807 if (!(w->pflags & HDA_ADC_RECSEL))
2809 for (j = 0; j < w->nconns; j++) {
2810 cw = hdac_widget_get(devinfo, w->conns[j]);
2811 if (cw == NULL || cw->enable == 0)
2813 if ((target == SOUND_MASK_VOLUME &&
2815 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
2816 (target != SOUND_MASK_VOLUME &&
2818 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
2820 if (cw->ctlflags & target) {
2821 hdac_widget_connection_select(w, j);
2833 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
2834 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
2835 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
2836 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
2839 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
2841 /****************************************************************************
2842 * int hdac_attach(device_t)
2844 * Attach the device into the kernel. Interrupts usually won't be enabled
2845 * when this function is called. Setup everything that doesn't require
2846 * interrupts and defer probing of codecs until interrupts are enabled.
2847 ****************************************************************************/
2849 hdac_attach(device_t dev)
2851 struct hdac_softc *sc;
2855 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO);
2857 device_printf(dev, "cannot allocate softc\n");
2861 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
2862 if (sc->lock == NULL) {
2863 device_printf(dev, "mutex creation failed\n");
2864 kfree(sc, M_DEVBUF);
2869 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
2870 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
2872 sc->chan_size = pcm_getbuffersize(dev,
2873 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_DEFAULT);
2874 if (resource_int_value(device_get_name(sc->dev),
2875 device_get_unit(sc->dev), "blocksize", &i) == 0 &&
2877 sc->chan_blkcnt = sc->chan_size / i;
2879 while (sc->chan_blkcnt >> i)
2881 sc->chan_blkcnt = 1 << (i - 1);
2882 if (sc->chan_blkcnt < HDA_BDL_MIN)
2883 sc->chan_blkcnt = HDA_BDL_MIN;
2884 else if (sc->chan_blkcnt > HDA_BDL_MAX)
2885 sc->chan_blkcnt = HDA_BDL_MAX;
2887 sc->chan_blkcnt = HDA_BDL_DEFAULT;
2889 result = bus_dma_tag_create(NULL, /* parent */
2890 HDAC_DMA_ALIGNMENT, /* alignment */
2892 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2893 BUS_SPACE_MAXADDR, /* highaddr */
2894 NULL, /* filtfunc */
2895 NULL, /* fistfuncarg */
2896 sc->chan_size, /* maxsize */
2898 sc->chan_size, /* maxsegsz */
2900 &sc->chan_dmat); /* dmat */
2902 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
2904 snd_mtxfree(sc->lock);
2905 kfree(sc, M_DEVBUF);
2911 for (i = 0; i < HDAC_CODEC_MAX; i++)
2912 sc->codecs[i] = NULL;
2914 pci_enable_busmaster(dev);
2916 /* Allocate resources */
2917 result = hdac_mem_alloc(sc);
2919 goto hdac_attach_fail;
2920 result = hdac_irq_alloc(sc);
2922 goto hdac_attach_fail;
2924 /* Get Capabilities */
2925 result = hdac_get_capabilities(sc);
2927 goto hdac_attach_fail;
2929 /* Allocate CORB and RIRB dma memory */
2930 result = hdac_dma_alloc(sc, &sc->corb_dma,
2931 sc->corb_size * sizeof(uint32_t));
2933 goto hdac_attach_fail;
2934 result = hdac_dma_alloc(sc, &sc->rirb_dma,
2935 sc->rirb_size * sizeof(struct hdac_rirb));
2937 goto hdac_attach_fail;
2939 /* Quiesce everything */
2942 /* Disable PCI-Express QOS */
2943 pci_write_config(sc->dev, 0x44,
2944 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1);
2946 /* Initialize the CORB and RIRB */
2950 /* Defer remaining of initialization until interrupts are enabled */
2951 sc->intrhook.ich_func = hdac_attach2;
2952 sc->intrhook.ich_arg = (void *)sc;
2953 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
2954 sc->intrhook.ich_func = NULL;
2955 hdac_attach2((void *)sc);
2961 hdac_dma_free(&sc->rirb_dma);
2962 hdac_dma_free(&sc->corb_dma);
2965 snd_mtxfree(sc->lock);
2966 kfree(sc, M_DEVBUF);
2972 hdac_audio_parse(struct hdac_devinfo *devinfo)
2974 struct hdac_softc *sc = devinfo->codec->sc;
2975 struct hdac_widget *w;
2980 cad = devinfo->codec->cad;
2984 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad);
2988 res = hdac_command(sc,
2989 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
2991 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
2992 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
2993 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
2996 device_printf(sc->dev, " Vendor: 0x%08x\n",
2997 devinfo->vendor_id);
2998 device_printf(sc->dev, " Device: 0x%08x\n",
2999 devinfo->device_id);
3000 device_printf(sc->dev, " Revision: 0x%08x\n",
3001 devinfo->revision_id);
3002 device_printf(sc->dev, " Stepping: 0x%08x\n",
3003 devinfo->stepping_id);
3004 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
3006 device_printf(sc->dev, " Nodes: start=%d "
3007 "endnode=%d total=%d\n",
3008 devinfo->startnode, devinfo->endnode, devinfo->nodecnt);
3011 res = hdac_command(sc,
3012 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
3014 devinfo->function.audio.supp_stream_formats = res;
3016 res = hdac_command(sc,
3017 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
3019 devinfo->function.audio.supp_pcm_size_rate = res;
3021 res = hdac_command(sc,
3022 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
3024 devinfo->function.audio.outamp_cap = res;
3026 res = hdac_command(sc,
3027 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
3029 devinfo->function.audio.inamp_cap = res;
3031 if (devinfo->nodecnt > 0) {
3033 devinfo->widget = (struct hdac_widget *)kmalloc(
3034 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
3038 devinfo->widget = NULL;
3040 if (devinfo->widget == NULL) {
3041 device_printf(sc->dev, "unable to allocate widgets!\n");
3042 devinfo->endnode = devinfo->startnode;
3043 devinfo->nodecnt = 0;
3047 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3048 w = hdac_widget_get(devinfo, i);
3050 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
3052 w->devinfo = devinfo;
3058 w->param.eapdbtl = HDAC_INVALID;
3059 hdac_widget_parse(w);
3065 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
3067 struct hdac_softc *sc = devinfo->codec->sc;
3068 struct hdac_audio_ctl *ctls;
3069 struct hdac_widget *w, *cw;
3070 int i, j, cnt, max, ocap, icap;
3071 int mute, offset, step, size;
3073 /* XXX This is redundant */
3075 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3076 w = hdac_widget_get(devinfo, i);
3077 if (w == NULL || w->enable == 0)
3079 if (w->param.outamp_cap != 0)
3081 if (w->param.inamp_cap != 0) {
3083 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3084 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3085 for (j = 0; j < w->nconns; j++) {
3086 cw = hdac_widget_get(devinfo,
3088 if (cw == NULL || cw->enable == 0)
3100 devinfo->function.audio.ctlcnt = max;
3106 ctls = (struct hdac_audio_ctl *)kmalloc(
3107 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
3112 device_printf(sc->dev, "unable to allocate ctls!\n");
3113 devinfo->function.audio.ctlcnt = 0;
3118 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
3120 device_printf(sc->dev, "%s: Ctl overflow!\n",
3124 w = hdac_widget_get(devinfo, i);
3125 if (w == NULL || w->enable == 0)
3127 ocap = w->param.outamp_cap;
3128 icap = w->param.inamp_cap;
3130 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
3131 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
3132 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
3133 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
3134 /*if (offset > step) {
3136 device_printf(sc->dev,
3137 "HDA_DEBUG: BUGGY outamp: nid=%d "
3138 "[offset=%d > step=%d]\n",
3139 w->nid, offset, step);
3143 ctls[cnt].enable = 1;
3144 ctls[cnt].widget = w;
3145 ctls[cnt].mute = mute;
3146 ctls[cnt].step = step;
3147 ctls[cnt].size = size;
3148 ctls[cnt].offset = offset;
3149 ctls[cnt].left = offset;
3150 ctls[cnt].right = offset;
3151 ctls[cnt++].dir = HDA_CTL_OUT;
3155 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
3156 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
3157 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
3158 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
3159 /*if (offset > step) {
3161 device_printf(sc->dev,
3162 "HDA_DEBUG: BUGGY inamp: nid=%d "
3163 "[offset=%d > step=%d]\n",
3164 w->nid, offset, step);
3169 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3170 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3171 for (j = 0; j < w->nconns; j++) {
3173 device_printf(sc->dev,
3174 "%s: Ctl overflow!\n",
3178 cw = hdac_widget_get(devinfo,
3180 if (cw == NULL || cw->enable == 0)
3182 ctls[cnt].enable = 1;
3183 ctls[cnt].widget = w;
3184 ctls[cnt].childwidget = cw;
3185 ctls[cnt].index = j;
3186 ctls[cnt].mute = mute;
3187 ctls[cnt].step = step;
3188 ctls[cnt].size = size;
3189 ctls[cnt].offset = offset;
3190 ctls[cnt].left = offset;
3191 ctls[cnt].right = offset;
3192 ctls[cnt++].dir = HDA_CTL_IN;
3197 device_printf(sc->dev,
3198 "%s: Ctl overflow!\n",
3202 ctls[cnt].enable = 1;
3203 ctls[cnt].widget = w;
3204 ctls[cnt].mute = mute;
3205 ctls[cnt].step = step;
3206 ctls[cnt].size = size;
3207 ctls[cnt].offset = offset;
3208 ctls[cnt].left = offset;
3209 ctls[cnt].right = offset;
3210 ctls[cnt++].dir = HDA_CTL_IN;
3216 devinfo->function.audio.ctl = ctls;
3219 static const struct {
3222 uint32_t set, unset;
3225 * XXX Fixed rate quirk. Other than 48000
3226 * sounds pretty much like train wreck.
3228 * XXX Force stereo quirk. Monoural recording / playback
3229 * on few codecs (especially ALC880) seems broken or
3230 * perhaps unsupported.
3232 { HDA_MATCH_ALL, HDA_MATCH_ALL,
3233 HDA_QUIRK_FIXEDRATE | HDA_QUIRK_FORCESTEREO, 0 },
3234 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
3235 HDA_QUIRK_GPIO1, 0 },
3236 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
3237 HDA_QUIRK_GPIO1, 0 },
3238 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE,
3239 0, HDA_QUIRK_FORCESTEREO },
3240 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX,
3241 HDA_QUIRK_SOFTPCMVOL, 0 }
3243 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
3246 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
3248 struct hdac_widget *w;
3249 uint32_t id, subvendor;
3252 id = hdac_codec_id(devinfo);
3253 subvendor = devinfo->codec->sc->pci_subvendor;
3258 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
3259 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
3260 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
3262 if (hdac_quirks[i].set != 0)
3263 devinfo->function.audio.quirks |=
3265 if (hdac_quirks[i].unset != 0)
3266 devinfo->function.audio.quirks &=
3267 ~(hdac_quirks[i].unset);
3271 case HDA_CODEC_ALC260:
3272 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3273 w = hdac_widget_get(devinfo, i);
3274 if (w == NULL || w->enable == 0)
3277 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
3283 case HDA_CODEC_ALC880:
3284 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3285 w = hdac_widget_get(devinfo, i);
3286 if (w == NULL || w->enable == 0)
3289 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
3290 w->nid != 9 && w->nid != 29) {
3292 } else if (w->type !=
3293 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET &&
3296 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
3297 w->param.widget_cap &=
3298 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
3299 w->param.widget_cap |=
3300 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
3301 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
3302 strlcpy(w->name, "beep widget", sizeof(w->name));
3306 case HDA_CODEC_AD1981HD:
3307 w = hdac_widget_get(devinfo, 11);
3308 if (w != NULL && w->enable != 0 && w->nconns > 3)
3310 if (subvendor == IBM_M52_SUBVENDOR) {
3311 struct hdac_audio_ctl *ctl;
3313 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1);
3315 ctl->ossmask = SOUND_MASK_SPEAKER;
3318 case HDA_CODEC_AD1986A:
3319 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3320 w = hdac_widget_get(devinfo, i);
3321 if (w == NULL || w->enable == 0)
3324 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
3330 case HDA_CODEC_STAC9221:
3331 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3332 w = hdac_widget_get(devinfo, i);
3333 if (w == NULL || w->enable == 0)
3336 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
3342 case HDA_CODEC_STAC9221D:
3343 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3344 w = hdac_widget_get(devinfo, i);
3345 if (w == NULL || w->enable == 0)
3348 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
3360 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo)
3362 int *dev = &devinfo->function.audio.ossidx;
3364 while (*dev < SOUND_MIXER_NRDEVICES) {
3366 case SOUND_MIXER_VOLUME:
3367 case SOUND_MIXER_BASS:
3368 case SOUND_MIXER_TREBLE:
3369 case SOUND_MIXER_PCM:
3370 case SOUND_MIXER_SPEAKER:
3371 case SOUND_MIXER_LINE:
3372 case SOUND_MIXER_MIC:
3373 case SOUND_MIXER_CD:
3374 case SOUND_MIXER_RECLEV:
3375 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */
3388 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
3390 struct hdac_widget *w;
3393 if (depth > HDA_PARSE_MAXDEPTH)
3395 w = hdac_widget_get(devinfo, nid);
3396 if (w == NULL || w->enable == 0)
3399 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
3400 w->pflags |= HDA_DAC_PATH;
3403 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3404 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3405 for (i = 0; i < w->nconns; i++) {
3406 if (hdac_widget_find_dac_path(devinfo,
3407 w->conns[i], depth + 1) != 0) {
3408 if (w->selconn == -1)
3411 w->pflags |= HDA_DAC_PATH;
3422 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
3424 struct hdac_widget *w;
3425 int i, conndev, ret = 0;
3427 if (depth > HDA_PARSE_MAXDEPTH)
3429 w = hdac_widget_get(devinfo, nid);
3430 if (w == NULL || w->enable == 0)
3433 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
3434 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3435 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3436 for (i = 0; i < w->nconns; i++) {
3437 if (hdac_widget_find_adc_path(devinfo, w->conns[i],
3439 if (w->selconn == -1)
3441 w->pflags |= HDA_ADC_PATH;
3446 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
3447 conndev = w->wclass.pin.config &
3448 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
3449 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
3450 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD ||
3451 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN ||
3452 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) {
3453 w->pflags |= HDA_ADC_PATH;
3457 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3458 if (w->pflags & HDA_DAC_PATH) {
3459 w->pflags |= HDA_ADC_PATH;
3470 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo,
3471 nid_t nid, nid_t pnid, int index, int depth)
3473 struct hdac_widget *w, *pw;
3474 struct hdac_audio_ctl *ctl;
3476 int i, ossdev, conndev, strategy;
3478 if (depth > HDA_PARSE_MAXDEPTH)
3481 w = hdac_widget_get(devinfo, nid);
3482 if (w == NULL || w->enable == 0)
3485 pw = hdac_widget_get(devinfo, pnid);
3486 strategy = devinfo->function.audio.parsing_strategy;
3488 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER
3489 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) {
3490 for (i = 0; i < w->nconns; i++) {
3491 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i],
3492 w->nid, i, depth + 1);
3496 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3497 (w->pflags & HDA_DAC_PATH)) {
3499 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3500 if (ctl->enable == 0 || ctl->widget == NULL)
3502 /* XXX This should be compressed! */
3503 if ((ctl->widget->nid == w->nid) ||
3504 (ctl->widget->nid == pnid && ctl->index == index &&
3505 (ctl->dir & HDA_CTL_IN)) ||
3506 (ctl->widget->nid == pnid && pw != NULL &&
3508 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
3509 (pw->nconns < 2 || pw->selconn == index ||
3510 pw->selconn == -1) &&
3511 (ctl->dir & HDA_CTL_OUT)) ||
3512 (strategy == HDA_PARSE_DIRECT &&
3513 ctl->widget->nid == w->nid)) {
3514 /*if (pw != NULL && pw->selconn == -1)
3515 pw->selconn = index;
3516 fl |= SOUND_MASK_VOLUME;
3517 fl |= SOUND_MASK_PCM;
3518 ctl->ossmask |= SOUND_MASK_VOLUME;
3519 ctl->ossmask |= SOUND_MASK_PCM;
3520 ctl->ossdev = SOUND_MIXER_PCM;*/
3521 if (!(w->ctlflags & SOUND_MASK_PCM) ||
3523 !(pw->ctlflags & SOUND_MASK_PCM))) {
3524 fl |= SOUND_MASK_VOLUME;
3525 fl |= SOUND_MASK_PCM;
3526 ctl->ossmask |= SOUND_MASK_VOLUME;
3527 ctl->ossmask |= SOUND_MASK_PCM;
3528 ctl->ossdev = SOUND_MIXER_PCM;
3529 w->ctlflags |= SOUND_MASK_VOLUME;
3530 w->ctlflags |= SOUND_MASK_PCM;
3532 if (pw->selconn == -1)
3533 pw->selconn = index;
3544 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX
3545 && HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
3546 (w->pflags & HDA_ADC_PATH)) {
3547 conndev = w->wclass.pin.config &
3548 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
3550 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3551 if (ctl->enable == 0 || ctl->widget == NULL)
3553 /* XXX This should be compressed! */
3554 if (((ctl->widget->nid == pnid && ctl->index == index &&
3555 (ctl->dir & HDA_CTL_IN)) ||
3556 (ctl->widget->nid == pnid && pw != NULL &&
3558 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
3559 (pw->nconns < 2 || pw->selconn == index ||
3560 pw->selconn == -1) &&
3561 (ctl->dir & HDA_CTL_OUT)) ||
3562 (strategy == HDA_PARSE_DIRECT &&
3563 ctl->widget->nid == w->nid)) &&
3564 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
3565 if (pw != NULL && pw->selconn == -1)
3566 pw->selconn = index;
3569 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
3570 ossdev = SOUND_MIXER_MIC;
3572 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
3573 ossdev = SOUND_MIXER_LINE;
3575 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
3576 ossdev = SOUND_MIXER_CD;
3580 hdac_audio_ctl_ossmixer_getnextdev(
3586 if (strategy == HDA_PARSE_MIXER) {
3587 fl |= SOUND_MASK_VOLUME;
3588 ctl->ossmask |= SOUND_MASK_VOLUME;
3591 ctl->ossmask |= 1 << ossdev;
3592 ctl->ossdev = ossdev;
3597 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
3599 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3600 if (ctl->enable == 0 || ctl->widget == NULL)
3602 /* XXX This should be compressed! */
3603 if (((ctl->widget->nid == pnid && ctl->index == index &&
3604 (ctl->dir & HDA_CTL_IN)) ||
3605 (ctl->widget->nid == pnid && pw != NULL &&
3607 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
3608 (pw->nconns < 2 || pw->selconn == index ||
3609 pw->selconn == -1) &&
3610 (ctl->dir & HDA_CTL_OUT)) ||
3611 (strategy == HDA_PARSE_DIRECT &&
3612 ctl->widget->nid == w->nid)) &&
3613 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
3614 if (pw != NULL && pw->selconn == -1)
3615 pw->selconn = index;
3616 fl |= SOUND_MASK_VOLUME;
3617 fl |= SOUND_MASK_SPEAKER;
3618 ctl->ossmask |= SOUND_MASK_VOLUME;
3619 ctl->ossmask |= SOUND_MASK_SPEAKER;
3620 ctl->ossdev = SOUND_MIXER_SPEAKER;
3630 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
3632 struct hdac_widget *w, *cw;
3633 struct hdac_audio_ctl *ctl;
3637 if (depth > HDA_PARSE_MAXDEPTH)
3640 w = hdac_widget_get(devinfo, nid);
3641 if (w == NULL || w->enable == 0)
3643 /*if (!(w->pflags & HDA_ADC_PATH))
3645 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
3646 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
3649 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3650 if (ctl->enable == 0 || ctl->widget == NULL)
3652 if (ctl->widget->nid == nid) {
3653 ctl->ossmask |= SOUND_MASK_RECLEV;
3654 w->ctlflags |= SOUND_MASK_RECLEV;
3655 return (SOUND_MASK_RECLEV);
3658 for (i = 0; i < w->nconns; i++) {
3659 cw = hdac_widget_get(devinfo, w->conns[i]);
3660 if (cw == NULL || cw->enable == 0)
3662 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
3664 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1);
3675 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
3677 struct hdac_widget *w, *cw;
3680 if (depth > HDA_PARSE_MAXDEPTH)
3683 w = hdac_widget_get(devinfo, nid);
3684 if (w == NULL || w->enable == 0)
3686 /*if (!(w->pflags & HDA_ADC_PATH))
3688 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
3689 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
3692 for (i = 0; i < w->nconns; i++) {
3693 cw = hdac_widget_get(devinfo, w->conns[i]);
3697 w->pflags |= HDA_ADC_RECSEL;
3701 for (i = 0; i < w->nconns; i++) {
3702 if (hdac_audio_ctl_recsel_build(devinfo,
3703 w->conns[i], depth + 1) != 0)
3710 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo)
3712 struct hdac_widget *w, *cw;
3713 int i, j, conndev, found_dac = 0;
3716 strategy = devinfo->function.audio.parsing_strategy;
3718 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3719 w = hdac_widget_get(devinfo, i);
3720 if (w == NULL || w->enable == 0)
3722 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3724 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap))
3726 conndev = w->wclass.pin.config &
3727 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
3728 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
3729 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
3730 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT))
3732 for (j = 0; j < w->nconns; j++) {
3733 cw = hdac_widget_get(devinfo, w->conns[j]);
3734 if (cw == NULL || cw->enable == 0)
3736 if (strategy == HDA_PARSE_MIXER && !(cw->type ==
3737 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
3739 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
3741 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0)
3743 if (w->selconn == -1)
3745 w->pflags |= HDA_DAC_PATH;
3755 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
3757 struct hdac_widget *w;
3758 struct hdac_audio_ctl *ctl;
3759 int i, j, dacs, strategy;
3761 /* Construct DAC path */
3762 strategy = HDA_PARSE_MIXER;
3763 devinfo->function.audio.parsing_strategy = strategy;
3765 device_printf(devinfo->codec->sc->dev,
3766 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n",
3767 HDA_WIDGET_PARSER_REV);
3769 dacs = hdac_audio_build_tree_strategy(devinfo);
3772 device_printf(devinfo->codec->sc->dev,
3773 "HDA_DEBUG: HWiP: 0 DAC path found! "
3775 "using HDA_PARSE_DIRECT strategy.\n");
3777 strategy = HDA_PARSE_DIRECT;
3778 devinfo->function.audio.parsing_strategy = strategy;
3779 dacs = hdac_audio_build_tree_strategy(devinfo);
3783 device_printf(devinfo->codec->sc->dev,
3784 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s "
3786 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT");
3789 /* Construct ADC path */
3790 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3791 w = hdac_widget_get(devinfo, i);
3792 if (w == NULL || w->enable == 0)
3794 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
3796 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0);
3800 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3801 w = hdac_widget_get(devinfo, i);
3802 if (w == NULL || w->enable == 0)
3804 if ((strategy == HDA_PARSE_MIXER &&
3805 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
3806 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
3807 && (w->pflags & HDA_DAC_PATH)) ||
3808 (strategy == HDA_PARSE_DIRECT && (w->pflags &
3809 (HDA_DAC_PATH | HDA_ADC_PATH)))) {
3810 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo,
3811 w->nid, devinfo->startnode - 1, 0, 0);
3812 } else if (w->type ==
3813 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
3815 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) !=
3817 if (ctl->enable == 0 || ctl->widget == NULL)
3819 if (ctl->widget->nid != w->nid)
3821 ctl->ossmask |= SOUND_MASK_VOLUME;
3822 ctl->ossmask |= SOUND_MASK_SPEAKER;
3823 ctl->ossdev = SOUND_MIXER_SPEAKER;
3824 w->ctlflags |= SOUND_MASK_VOLUME;
3825 w->ctlflags |= SOUND_MASK_SPEAKER;
3830 /* Input mixers (rec) */
3831 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3832 w = hdac_widget_get(devinfo, i);
3833 if (w == NULL || w->enable == 0)
3835 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
3836 w->pflags & HDA_ADC_PATH))
3838 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0);
3839 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0);
3843 #define HDA_COMMIT_CONN (1 << 0)
3844 #define HDA_COMMIT_CTRL (1 << 1)
3845 #define HDA_COMMIT_EAPD (1 << 2)
3846 #define HDA_COMMIT_GPIO (1 << 3)
3847 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \
3848 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO)
3851 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl)
3853 struct hdac_softc *sc = devinfo->codec->sc;
3854 struct hdac_widget *w;
3858 if (!(cfl & HDA_COMMIT_ALL))
3861 cad = devinfo->codec->cad;
3863 if (cfl & HDA_COMMIT_GPIO) {
3865 for (i = 0; i < HDA_GPIO_MAX; i++) {
3866 if (!(devinfo->function.audio.quirks & (1 << i)))
3868 gpioval = (1 << i) - 1;
3870 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, gpioval),
3873 HDA_CMD_SET_GPIO_DIRECTION(cad, nid, gpioval),
3876 HDA_CMD_SET_GPIO_DATA(cad, nid, gpioval),
3881 for (i = 0; i < devinfo->nodecnt; i++) {
3882 w = &devinfo->widget[i];
3883 if (w == NULL || w->enable == 0)
3885 if (cfl & HDA_COMMIT_CONN) {
3886 if (w->selconn == -1)
3889 hdac_widget_connection_select(w, w->selconn);
3891 if ((cfl & HDA_COMMIT_CTRL) &&
3892 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
3893 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) ==
3894 (HDA_DAC_PATH | HDA_ADC_PATH))
3895 device_printf(sc->dev, "WARNING: node %d "
3896 "participate both for DAC/ADC!\n", w->nid);
3897 if (w->pflags & HDA_DAC_PATH) {
3898 w->wclass.pin.ctrl &=
3899 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
3900 if ((w->wclass.pin.config &
3901 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) !=
3902 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
3903 w->wclass.pin.ctrl &=
3904 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
3905 } else if (w->pflags & HDA_ADC_PATH) {
3906 w->wclass.pin.ctrl &=
3907 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
3908 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE);
3910 w->wclass.pin.ctrl &= ~(
3911 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
3912 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
3913 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE);
3915 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
3916 w->wclass.pin.ctrl), cad);
3918 if ((cfl & HDA_COMMIT_EAPD) &&
3919 w->param.eapdbtl != HDAC_INVALID)
3921 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
3922 w->param.eapdbtl), cad);
3929 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
3931 struct hdac_softc *sc = devinfo->codec->sc;
3932 struct hdac_audio_ctl *ctl;
3935 devinfo->function.audio.mvol = 100 | (100 << 8);
3937 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3938 if (ctl->enable == 0 || ctl->widget == NULL) {
3940 device_printf(sc->dev, "[%2d] Ctl nid=%d",
3941 i, (ctl->widget != NULL) ?
3942 ctl->widget->nid : -1);
3943 if (ctl->childwidget != NULL)
3944 kprintf(" childnid=%d",
3945 ctl->childwidget->nid);
3946 if (ctl->widget == NULL)
3947 kprintf(" NULL WIDGET!");
3948 kprintf(" DISABLED\n");
3953 if (ctl->ossmask == 0) {
3954 device_printf(sc->dev, "[%2d] Ctl nid=%d",
3955 i, ctl->widget->nid);
3956 if (ctl->childwidget != NULL)
3957 kprintf(" childnid=%d",
3958 ctl->childwidget->nid);
3959 kprintf(" Bind to NONE\n");
3962 if (ctl->step > 0) {
3963 ctl->ossval = (ctl->left * 100) / ctl->step;
3964 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8;
3967 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
3968 ctl->left, ctl->right);
3973 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir)
3975 struct hdac_chan *ch;
3976 struct hdac_widget *w;
3977 uint32_t cap, fmtcap, pcmcap, path;
3978 int i, type, ret, max;
3980 if (dir == PCMDIR_PLAY) {
3981 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT;
3982 ch = &devinfo->codec->sc->play;
3983 path = HDA_DAC_PATH;
3985 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT;
3986 ch = &devinfo->codec->sc->rec;
3987 path = HDA_ADC_PATH;
3990 ch->caps = hdac_caps;
3991 ch->caps.fmtlist = ch->fmtlist;
3994 ch->pcmrates[0] = 48000;
3995 ch->pcmrates[1] = 0;
3998 fmtcap = devinfo->function.audio.supp_stream_formats;
3999 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
4000 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
4002 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) {
4003 w = hdac_widget_get(devinfo, i);
4004 if (w == NULL || w->enable == 0 || w->type != type ||
4005 !(w->pflags & path))
4007 cap = w->param.widget_cap;
4008 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap))
4010 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap))
4012 cap = w->param.supp_stream_formats;
4013 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) {
4015 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
4017 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
4020 fmtcap &= w->param.supp_stream_formats;
4021 pcmcap &= w->param.supp_pcm_size_rate;
4025 ch->supp_stream_formats = fmtcap;
4026 ch->supp_pcm_size_rate = pcmcap;
4037 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
4039 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
4041 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
4043 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
4045 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
4048 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
4049 ch->fmtlist[i++] = AFMT_S16_LE;
4050 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO;
4051 if (ch->bit32 > 0) {
4052 if (!(devinfo->function.audio.quirks &
4053 HDA_QUIRK_FORCESTEREO))
4054 ch->fmtlist[i++] = AFMT_S32_LE;
4055 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO;
4059 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
4060 ch->pcmrates[i++] = 8000;
4061 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
4062 ch->pcmrates[i++] = 11025;
4063 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
4064 ch->pcmrates[i++] = 16000;
4065 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
4066 ch->pcmrates[i++] = 22050;
4067 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
4068 ch->pcmrates[i++] = 32000;
4069 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
4070 ch->pcmrates[i++] = 44100;
4071 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */
4072 ch->pcmrates[i++] = 48000;
4073 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
4074 ch->pcmrates[i++] = 88200;
4075 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
4076 ch->pcmrates[i++] = 96000;
4077 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
4078 ch->pcmrates[i++] = 176400;
4079 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
4080 ch->pcmrates[i++] = 192000;
4081 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */
4082 ch->pcmrates[i] = 0;
4084 ch->caps.minspeed = ch->pcmrates[0];
4085 ch->caps.maxspeed = ch->pcmrates[i - 1];
4093 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag)
4095 struct hdac_audio_ctl *ctl;
4096 struct hdac_softc *sc = devinfo->codec->sc;
4102 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM |
4103 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
4104 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN;
4108 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4109 if (ctl->enable == 0 || ctl->widget == NULL ||
4110 ctl->widget->enable == 0)
4112 if ((flag == 0 && (ctl->ossmask & ~fl)) ||
4113 (flag != 0 && (ctl->ossmask & flag))) {
4114 if (banner != NULL) {
4115 device_printf(sc->dev, "\n");
4116 device_printf(sc->dev, "%s\n", banner);
4118 goto hdac_ctl_dump_it_all;
4124 hdac_ctl_dump_it_all:
4126 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4127 if (ctl->enable == 0 || ctl->widget == NULL ||
4128 ctl->widget->enable == 0)
4130 if (!((flag == 0 && (ctl->ossmask & ~fl)) ||
4131 (flag != 0 && (ctl->ossmask & flag))))
4134 device_printf(sc->dev, "\n");
4135 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n",
4136 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask));
4138 device_printf(sc->dev, " |\n");
4139 device_printf(sc->dev, " +- nid: %2d index: %2d ",
4140 ctl->widget->nid, ctl->index);
4141 if (ctl->childwidget != NULL)
4142 kprintf("(nid: %2d) ", ctl->childwidget->nid);
4145 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n",
4146 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir,
4152 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap)
4158 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap);
4159 device_printf(sc->dev, " Format:");
4160 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
4162 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
4163 kprintf(" FLOAT32");
4164 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
4170 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap);
4171 device_printf(sc->dev, " PCM size:");
4172 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
4174 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
4176 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
4178 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
4180 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
4183 device_printf(sc->dev, " PCM rate:");
4184 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
4186 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
4188 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
4190 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
4192 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
4194 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
4197 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
4199 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
4201 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
4203 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
4210 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
4212 uint32_t pincap, wcap;
4214 pincap = w->wclass.pin.cap;
4215 wcap = w->param.widget_cap;
4217 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
4218 device_printf(sc->dev, " ");
4219 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
4221 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
4223 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
4225 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
4227 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
4229 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
4231 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
4233 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
4235 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap))
4236 kprintf(" : UNSOL");
4238 device_printf(sc->dev, " Pin config: 0x%08x\n",
4239 w->wclass.pin.config);
4240 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
4241 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
4243 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
4245 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
4251 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
4253 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
4254 device_printf(sc->dev, " "
4255 "mute=%d step=%d size=%d offset=%d\n",
4256 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
4257 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
4258 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
4259 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
4263 hdac_dump_nodes(struct hdac_devinfo *devinfo)
4265 struct hdac_softc *sc = devinfo->codec->sc;
4266 struct hdac_widget *w, *cw;
4269 device_printf(sc->dev, "\n");
4270 device_printf(sc->dev, "Default Parameter\n");
4271 device_printf(sc->dev, "-----------------\n");
4272 hdac_dump_audio_formats(sc,
4273 devinfo->function.audio.supp_stream_formats,
4274 devinfo->function.audio.supp_pcm_size_rate);
4275 device_printf(sc->dev, " IN amp: 0x%08x\n",
4276 devinfo->function.audio.inamp_cap);
4277 device_printf(sc->dev, " OUT amp: 0x%08x\n",
4278 devinfo->function.audio.outamp_cap);
4279 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4280 w = hdac_widget_get(devinfo, i);
4282 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
4285 device_printf(sc->dev, "\n");
4286 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid,
4287 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ?
4288 "DIGITAL" : "ANALOG",
4289 (w->enable == 0) ? " [DISABLED]" : "");
4290 device_printf(sc->dev, " name: %s\n", w->name);
4291 device_printf(sc->dev, " widget_cap: 0x%08x\n",
4292 w->param.widget_cap);
4293 device_printf(sc->dev, " Parse flags: 0x%08x\n",
4295 device_printf(sc->dev, " Ctl flags: 0x%08x\n",
4297 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
4298 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
4299 hdac_dump_audio_formats(sc,
4300 w->param.supp_stream_formats,
4301 w->param.supp_pcm_size_rate);
4302 } else if (w->type ==
4303 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4304 hdac_dump_pin(sc, w);
4305 if (w->param.eapdbtl != HDAC_INVALID)
4306 device_printf(sc->dev, " EAPD: 0x%08x\n",
4308 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
4309 w->param.outamp_cap != 0)
4310 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
4311 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
4312 w->param.inamp_cap != 0)
4313 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
4314 device_printf(sc->dev, " connections: %d\n", w->nconns);
4315 for (j = 0; j < w->nconns; j++) {
4316 cw = hdac_widget_get(devinfo, w->conns[j]);
4317 device_printf(sc->dev, " |\n");
4318 device_printf(sc->dev, " + <- nid=%d [%s]",
4319 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
4321 kprintf(" [UNKNOWN]");
4322 else if (cw->enable == 0)
4323 kprintf(" [DISABLED]");
4324 if (w->nconns > 1 && w->selconn == j && w->type !=
4325 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
4326 kprintf(" (selected)");
4334 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4336 struct hdac_widget *w, *cw;
4337 struct hdac_softc *sc = devinfo->codec->sc;
4340 if (depth > HDA_PARSE_MAXDEPTH)
4343 w = hdac_widget_get(devinfo, nid);
4344 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH))
4347 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
4348 device_printf(sc->dev, "\n");
4349 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
4350 device_printf(sc->dev, " ^\n");
4351 device_printf(sc->dev, " |\n");
4352 device_printf(sc->dev, " +-----<------+\n");
4354 device_printf(sc->dev, " ^\n");
4355 device_printf(sc->dev, " |\n");
4356 device_printf(sc->dev, " ");
4357 kprintf(" nid=%d [%s]\n", w->nid, w->name);
4360 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) {
4362 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
4363 for (i = 0; i < w->nconns; i++) {
4364 cw = hdac_widget_get(devinfo, w->conns[i]);
4365 if (cw == NULL || cw->enable == 0 || cw->type ==
4366 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4368 if (hdac_dump_dac_internal(devinfo, cw->nid,
4372 } else if ((w->type ==
4373 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR ||
4374 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
4375 w->selconn > -1 && w->selconn < w->nconns) {
4376 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn],
4385 hdac_dump_dac(struct hdac_devinfo *devinfo)
4387 struct hdac_widget *w;
4388 struct hdac_softc *sc = devinfo->codec->sc;
4391 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4392 w = hdac_widget_get(devinfo, i);
4393 if (w == NULL || w->enable == 0)
4395 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
4396 !(w->pflags & HDA_DAC_PATH))
4400 device_printf(sc->dev, "\n");
4401 device_printf(sc->dev, "Playback path:\n");
4403 hdac_dump_dac_internal(devinfo, w->nid, 0);
4408 hdac_dump_adc(struct hdac_devinfo *devinfo)
4410 struct hdac_widget *w, *cw;
4411 struct hdac_softc *sc = devinfo->codec->sc;
4416 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4417 w = hdac_widget_get(devinfo, i);
4418 if (w == NULL || w->enable == 0)
4420 if (!(w->pflags & HDA_ADC_RECSEL))
4424 device_printf(sc->dev, "\n");
4425 device_printf(sc->dev, "Recording sources:\n");
4427 device_printf(sc->dev, "\n");
4428 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
4429 for (j = 0; j < w->nconns; j++) {
4430 cw = hdac_widget_get(devinfo, w->conns[j]);
4431 if (cw == NULL || cw->enable == 0)
4433 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags,
4434 ossdevs, sizeof(ossdevs));
4435 device_printf(sc->dev, " |\n");
4436 device_printf(sc->dev, " + <- nid=%d [%s]",
4438 if (strlen(ossdevs) > 0) {
4439 kprintf(" [recsrc: %s]", ossdevs);
4447 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt)
4452 device_printf(sc->dev, "\n");
4453 device_printf(sc->dev, " PCM Playback: %d\n", pcnt);
4454 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
4455 sc->play.supp_pcm_size_rate);
4456 device_printf(sc->dev, " DAC:");
4457 for (nids = sc->play.io; *nids != -1; nids++)
4458 kprintf(" %d", *nids);
4463 device_printf(sc->dev, "\n");
4464 device_printf(sc->dev, " PCM Record: %d\n", rcnt);
4465 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
4466 sc->rec.supp_pcm_size_rate);
4467 device_printf(sc->dev, " ADC:");
4468 for (nids = sc->rec.io; *nids != -1; nids++)
4469 kprintf(" %d", *nids);
4475 hdac_release_resources(struct hdac_softc *sc)
4477 struct hdac_devinfo *devinfo = NULL;
4478 device_t *devlist = NULL;
4487 snd_mtxfree(sc->lock);
4489 device_get_children(sc->dev, &devlist, &devcount);
4490 for (i = 0; devlist != NULL && i < devcount; i++) {
4491 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
4492 if (devinfo == NULL)
4494 if (devinfo->widget != NULL)
4495 kfree(devinfo->widget, M_HDAC);
4496 if (devinfo->node_type ==
4497 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
4498 devinfo->function.audio.ctl != NULL)
4499 kfree(devinfo->function.audio.ctl, M_HDAC);
4500 kfree(devinfo, M_HDAC);
4501 device_delete_child(sc->dev, devlist[i]);
4503 if (devlist != NULL)
4504 kfree(devlist, M_TEMP);
4506 for (i = 0; i < HDAC_CODEC_MAX; i++) {
4507 if (sc->codecs[i] != NULL)
4508 kfree(sc->codecs[i], M_HDAC);
4509 sc->codecs[i] = NULL;
4512 hdac_dma_free(&sc->rirb_dma);
4513 hdac_dma_free(&sc->corb_dma);
4514 if (sc->play.blkcnt > 0)
4515 hdac_dma_free(&sc->play.bdl_dma);
4516 if (sc->rec.blkcnt > 0)
4517 hdac_dma_free(&sc->rec.bdl_dma);
4520 kfree(sc, M_DEVBUF);
4524 /* This function surely going to make its way into upper level someday. */
4526 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
4529 int i = 0, j, k, len, inv;
4537 if (resource_string_value(device_get_name(sc->dev),
4538 device_get_unit(sc->dev), "config", &res) != 0)
4540 if (!(res != NULL && strlen(res) > 0))
4543 device_printf(sc->dev, "HDA_DEBUG: HDA Config:");
4546 while (res[i] != '\0' &&
4547 (res[i] == ',' || isspace(res[i]) != 0))
4549 if (res[i] == '\0') {
4556 while (res[j] != '\0' &&
4557 !(res[j] == ',' || isspace(res[j]) != 0))
4560 if (len > 2 && strncmp(res + i, "no", 2) == 0)
4564 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
4565 if (strncmp(res + i + inv,
4566 hdac_quirks_tab[k].key, len - inv) != 0)
4568 if (len - inv != strlen(hdac_quirks_tab[k].key))
4571 kprintf(" %s%s", (inv != 0) ? "no" : "",
4572 hdac_quirks_tab[k].key);
4574 if (inv == 0 && on != NULL)
4575 *on |= hdac_quirks_tab[k].value;
4576 else if (inv != 0 && off != NULL)
4577 *off |= hdac_quirks_tab[k].value;
4585 hdac_attach2(void *arg)
4587 struct hdac_softc *sc;
4588 struct hdac_widget *w;
4589 struct hdac_audio_ctl *ctl;
4590 uint32_t quirks_on, quirks_off;
4593 char status[SND_STATUSLEN];
4594 device_t *devlist = NULL;
4596 struct hdac_devinfo *devinfo = NULL;
4598 sc = (struct hdac_softc *)arg;
4600 hdac_config_fetch(sc, &quirks_on, &quirks_off);
4603 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n",
4604 quirks_on, quirks_off);
4609 /* Remove ourselves from the config hooks */
4610 if (sc->intrhook.ich_func != NULL) {
4611 config_intrhook_disestablish(&sc->intrhook);
4612 sc->intrhook.ich_func = NULL;
4615 /* Start the corb and rirb engines */
4617 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n");
4619 hdac_corb_start(sc);
4621 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n");
4623 hdac_rirb_start(sc);
4626 device_printf(sc->dev,
4627 "HDA_DEBUG: Enabling controller interrupt...\n");
4629 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
4630 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
4636 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n");
4638 hdac_scan_codecs(sc);
4640 device_get_children(sc->dev, &devlist, &devcount);
4641 for (i = 0; devlist != NULL && i < devcount; i++) {
4642 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
4643 if (devinfo != NULL && devinfo->node_type ==
4644 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
4649 if (devlist != NULL)
4650 kfree(devlist, M_TEMP);
4652 if (devinfo == NULL) {
4654 device_printf(sc->dev, "Audio Function Group not found!\n");
4655 hdac_release_resources(sc);
4660 device_printf(sc->dev,
4661 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n",
4662 devinfo->nid, devinfo->codec->cad);
4664 hdac_audio_parse(devinfo);
4666 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n");
4668 hdac_audio_ctl_parse(devinfo);
4670 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n");
4672 hdac_vendor_patch_parse(devinfo);
4674 devinfo->function.audio.quirks |= quirks_on;
4675 if (quirks_off != 0)
4676 devinfo->function.audio.quirks &= ~quirks_off;
4678 /* XXX Disable all DIGITAL path. */
4679 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4680 w = hdac_widget_get(devinfo, i);
4683 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
4687 /* XXX Disable useless pin ? */
4688 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4689 (w->wclass.pin.config &
4690 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4691 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
4695 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4696 if (ctl->widget == NULL)
4701 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
4703 w = ctl->childwidget;
4706 if (w->enable == 0 ||
4707 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
4712 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n");
4714 hdac_audio_build_tree(devinfo);
4717 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n");
4719 hdac_audio_commit(devinfo, HDA_COMMIT_ALL);
4721 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n");
4723 hdac_audio_ctl_commit(devinfo);
4726 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n");
4728 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY);
4730 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n");
4732 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC);
4736 device_printf(sc->dev,
4737 "HDA_DEBUG: OSS mixer initialization...\n");
4741 * There is no point of return after this. If the driver failed,
4742 * so be it. Let the detach procedure do all the cleanup.
4744 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0)
4745 device_printf(sc->dev, "Can't register mixer\n");
4753 device_printf(sc->dev,
4754 "HDA_DEBUG: Registering PCM channels...\n");
4756 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0)
4757 device_printf(sc->dev, "Can't register PCM\n");
4761 for (i = 0; i < pcnt; i++)
4762 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo);
4763 for (i = 0; i < rcnt; i++)
4764 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo);
4766 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]",
4767 rman_get_start(sc->mem.mem_res),
4768 rman_get_start(sc->irq.irq_res),
4769 "snd_hda", HDA_DRV_TEST_REV);
4770 pcm_setstatus(sc->dev, status);
4771 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo));
4773 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n",
4774 hdac_codec_id(devinfo));
4776 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV);
4779 if (devinfo->function.audio.quirks != 0) {
4780 device_printf(sc->dev, "\n");
4781 device_printf(sc->dev, "HDA config/quirks:");
4782 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
4783 if (devinfo->function.audio.quirks &
4784 hdac_quirks_tab[i].value)
4785 kprintf(" %s", hdac_quirks_tab[i].key);
4789 device_printf(sc->dev, "\n");
4790 device_printf(sc->dev, "+-------------------+\n");
4791 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
4792 device_printf(sc->dev, "+-------------------+\n");
4793 hdac_dump_nodes(devinfo);
4794 device_printf(sc->dev, "\n");
4795 device_printf(sc->dev, "+------------------------+\n");
4796 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
4797 device_printf(sc->dev, "+------------------------+\n");
4798 device_printf(sc->dev, "\n");
4800 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4801 device_printf(sc->dev, "%3d: nid=%d", i,
4802 (ctl->widget != NULL) ? ctl->widget->nid : -1);
4803 if (ctl->childwidget != NULL)
4804 kprintf(" cnid=%d", ctl->childwidget->nid);
4805 kprintf(" dir=0x%x index=%d "
4806 "ossmask=0x%08x ossdev=%d%s\n",
4807 ctl->dir, ctl->index,
4808 ctl->ossmask, ctl->ossdev,
4809 (ctl->enable == 0) ? " [DISABLED]" : "");
4811 device_printf(sc->dev, "\n");
4812 device_printf(sc->dev, "+-----------------------------------+\n");
4813 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n");
4814 device_printf(sc->dev, "+-----------------------------------+\n");
4815 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME);
4816 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM);
4817 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD);
4818 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC);
4819 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE);
4820 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV);
4821 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER);
4822 hdac_dump_ctls(devinfo, NULL, 0);
4823 hdac_dump_dac(devinfo);
4824 hdac_dump_adc(devinfo);
4825 device_printf(sc->dev, "\n");
4826 device_printf(sc->dev, "+--------------------------------------+\n");
4827 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n");
4828 device_printf(sc->dev, "+--------------------------------------+\n");
4829 hdac_dump_pcmchannels(sc, pcnt, rcnt);
4833 /****************************************************************************
4834 * int hdac_detach(device_t)
4836 * Detach and free up resources utilized by the hdac device.
4837 ****************************************************************************/
4839 hdac_detach(device_t dev)
4841 struct hdac_softc *sc = NULL;
4842 struct hdac_devinfo *devinfo = NULL;
4845 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev);
4846 if (devinfo != NULL && devinfo->codec != NULL)
4847 sc = devinfo->codec->sc;
4851 if (sc->registered > 0) {
4852 err = pcm_unregister(dev);
4857 hdac_release_resources(sc);
4862 static device_method_t hdac_methods[] = {
4863 /* device interface */
4864 DEVMETHOD(device_probe, hdac_probe),
4865 DEVMETHOD(device_attach, hdac_attach),
4866 DEVMETHOD(device_detach, hdac_detach),
4870 static driver_t hdac_driver = {
4876 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0);
4877 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
4878 MODULE_VERSION(snd_hda, 1);