sys/dev/netif/gx/if_gx.c

   1 /*-
   2  * Copyright (c) 1999,2000,2001 Jonathan Lemon
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of the author nor the names of any co-contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * $FreeBSD: src/sys/dev/gx/if_gx.c,v 1.2.2.3 2001/12/14 19:51:39 jlemon Exp $
  30  * $DragonFly: src/sys/dev/netif/gx/Attic/if_gx.c,v 1.10 2004/07/23 07:16:26 joerg Exp $
  31  */
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/sockio.h>
  36 #include <sys/mbuf.h>
  37 #include <sys/malloc.h>
  38 #include <sys/kernel.h>
  39 #include <sys/socket.h>
  40 #include <sys/queue.h>
  41
  42 #include <net/if.h>
  43 #include <net/if_arp.h>
  44 #include <net/ethernet.h>
  45 #include <net/if_dl.h>
  46 #include <net/if_media.h>
  47
  48 #include <net/bpf.h>
  49 #include <net/if_types.h>
  50 #include <net/vlan/if_vlan_var.h>
  51
  52 #include <netinet/in_systm.h>
  53 #include <netinet/in.h>
  54 #include <netinet/ip.h>
  55 #include <netinet/tcp.h>
  56 #include <netinet/udp.h>
  57
  58 #include <vm/vm.h>              /* for vtophys */
  59 #include <vm/pmap.h>            /* for vtophys */
  60 #include <machine/clock.h>      /* for DELAY */
  61 #include <machine/bus_memio.h>
  62 #include <machine/bus.h>
  63 #include <machine/resource.h>
  64 #include <sys/bus.h>
  65 #include <sys/rman.h>
  66
  67 #include <bus/pci/pcireg.h>
  68 #include <bus/pci/pcivar.h>
  69
  70 #include "../mii_layer/mii.h"
  71 #include "../mii_layer/miivar.h"
  72
  73 #include "if_gxreg.h"
  74 #include "if_gxvar.h"
  75
  76 #include "miibus_if.h"
  77
  78 #define TUNABLE_TX_INTR_DELAY   100
  79 #define TUNABLE_RX_INTR_DELAY   100
  80
  81 #define GX_CSUM_FEATURES        (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
  82
  83 /*
  84  * Various supported device vendors/types and their names.
  85  */
  86 struct gx_device {
  87         u_int16_t       vendor;
  88         u_int16_t       device;
  89         int             version_flags;
  90         u_int32_t       version_ipg;
  91         char            *name;
  92 };
  93
  94 static struct gx_device gx_devs[] = {
  95         { INTEL_VENDORID, DEVICEID_WISEMAN,
  96             GXF_FORCE_TBI | GXF_OLD_REGS,
  97             10 | 2 << 10 | 10 << 20,
  98             "Intel Gigabit Ethernet (82542)" },
  99         { INTEL_VENDORID, DEVICEID_LIVINGOOD_FIBER,
 100             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 101             6 | 8 << 10 | 6 << 20,
 102             "Intel Gigabit Ethernet (82543GC-F)" },
 103         { INTEL_VENDORID, DEVICEID_LIVINGOOD_COPPER,
 104             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 105             8 | 8 << 10 | 6 << 20,
 106             "Intel Gigabit Ethernet (82543GC-T)" },
 107 #if 0
 108 /* notyet.. */
 109         { INTEL_VENDORID, DEVICEID_CORDOVA_FIBER,
 110             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 111             6 | 8 << 10 | 6 << 20,
 112             "Intel Gigabit Ethernet (82544EI-F)" },
 113         { INTEL_VENDORID, DEVICEID_CORDOVA_COPPER,
 114             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 115             8 | 8 << 10 | 6 << 20,
 116             "Intel Gigabit Ethernet (82544EI-T)" },
 117         { INTEL_VENDORID, DEVICEID_CORDOVA2_COPPER,
 118             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
 119             8 | 8 << 10 | 6 << 20,
 120             "Intel Gigabit Ethernet (82544GC-T)" },
 121 #endif
 122         { 0, 0, 0, NULL }
 123 };
 124
 125 static struct gx_regs new_regs = {
 126         GX_RX_RING_BASE, GX_RX_RING_LEN,
 127         GX_RX_RING_HEAD, GX_RX_RING_TAIL,
 128         GX_RX_INTR_DELAY, GX_RX_DMA_CTRL,
 129
 130         GX_TX_RING_BASE, GX_TX_RING_LEN,
 131         GX_TX_RING_HEAD, GX_TX_RING_TAIL,
 132         GX_TX_INTR_DELAY, GX_TX_DMA_CTRL,
 133 };
 134 static struct gx_regs old_regs = {
 135         GX_RX_OLD_RING_BASE, GX_RX_OLD_RING_LEN,
 136         GX_RX_OLD_RING_HEAD, GX_RX_OLD_RING_TAIL,
 137         GX_RX_OLD_INTR_DELAY, GX_RX_OLD_DMA_CTRL,
 138
 139         GX_TX_OLD_RING_BASE, GX_TX_OLD_RING_LEN,
 140         GX_TX_OLD_RING_HEAD, GX_TX_OLD_RING_TAIL,
 141         GX_TX_OLD_INTR_DELAY, GX_TX_OLD_DMA_CTRL,
 142 };
 143
 144 static int      gx_probe(device_t dev);
 145 static int      gx_attach(device_t dev);
 146 static int      gx_detach(device_t dev);
 147 static void     gx_shutdown(device_t dev);
 148
 149 static void     gx_intr(void *xsc);
 150 static void     gx_init(void *xsc);
 151
 152 static struct   gx_device *gx_match(device_t dev);
 153 static void     gx_eeprom_getword(struct gx_softc *gx, int addr,
 154                     u_int16_t *dest);
 155 static int      gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off,
 156                     int cnt);
 157 static int      gx_ifmedia_upd(struct ifnet *ifp);
 158 static void     gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
 159 static int      gx_miibus_readreg(device_t dev, int phy, int reg);
 160 static void     gx_miibus_writereg(device_t dev, int phy, int reg, int value);
 161 static void     gx_miibus_statchg(device_t dev);
 162 static int      gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
 163                     struct ucred *);
 164 static void     gx_setmulti(struct gx_softc *gx);
 165 static void     gx_reset(struct gx_softc *gx);
 166 static void     gx_phy_reset(struct gx_softc *gx);
 167 static void     gx_release(struct gx_softc *gx);
 168 static void     gx_stop(struct gx_softc *gx);
 169 static void     gx_watchdog(struct ifnet *ifp);
 170 static void     gx_start(struct ifnet *ifp);
 171
 172 static int      gx_init_rx_ring(struct gx_softc *gx);
 173 static void     gx_free_rx_ring(struct gx_softc *gx);
 174 static int      gx_init_tx_ring(struct gx_softc *gx);
 175 static void     gx_free_tx_ring(struct gx_softc *gx);
 176
 177 static device_method_t gx_methods[] = {
 178         /* Device interface */
 179         DEVMETHOD(device_probe,         gx_probe),
 180         DEVMETHOD(device_attach,        gx_attach),
 181         DEVMETHOD(device_detach,        gx_detach),
 182         DEVMETHOD(device_shutdown,      gx_shutdown),
 183
 184         /* MII interface */
 185         DEVMETHOD(miibus_readreg,       gx_miibus_readreg),
 186         DEVMETHOD(miibus_writereg,      gx_miibus_writereg),
 187         DEVMETHOD(miibus_statchg,       gx_miibus_statchg),
 188
 189         { 0, 0 }
 190 };
 191
 192 static driver_t gx_driver = {
 193         "gx",
 194         gx_methods,
 195         sizeof(struct gx_softc)
 196 };
 197
 198 static devclass_t gx_devclass;
 199
 200 DECLARE_DUMMY_MODULE(if_gx);
 201 MODULE_DEPEND(if_gx, miibus, 1, 1, 1);
 202 DRIVER_MODULE(if_gx, pci, gx_driver, gx_devclass, 0, 0);
 203 DRIVER_MODULE(miibus, gx, miibus_driver, miibus_devclass, 0, 0);
 204
 205 static struct gx_device *
 206 gx_match(device_t dev)
 207 {
 208         int i;
 209
 210         for (i = 0; gx_devs[i].name != NULL; i++) {
 211                 if ((pci_get_vendor(dev) == gx_devs[i].vendor) &&
 212                     (pci_get_device(dev) == gx_devs[i].device))
 213                         return (&gx_devs[i]);
 214         }
 215         return (NULL);
 216 }
 217
 218 static int
 219 gx_probe(device_t dev)
 220 {
 221         struct gx_device *gx_dev;
 222
 223         gx_dev = gx_match(dev);
 224         if (gx_dev == NULL)
 225                 return (ENXIO);
 226
 227         device_set_desc(dev, gx_dev->name);
 228         return (0);
 229 }
 230
 231 static int
 232 gx_attach(device_t dev)
 233 {
 234         struct gx_softc *gx;
 235         struct gx_device *gx_dev;
 236         struct ifnet *ifp;
 237         u_int32_t command;
 238         int rid, s;
 239         int error = 0;
 240
 241         s = splimp();
 242
 243         gx = device_get_softc(dev);
 244         bzero(gx, sizeof(struct gx_softc));
 245         gx->gx_dev = dev;
 246
 247         gx_dev = gx_match(dev);
 248         gx->gx_vflags = gx_dev->version_flags;
 249         gx->gx_ipg = gx_dev->version_ipg;
 250
 251         mtx_init(&gx->gx_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
 252
 253         GX_LOCK(gx);
 254
 255         /*
 256          * Map control/status registers.
 257          */
 258         command = pci_read_config(dev, PCIR_COMMAND, 4);
 259         command |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
 260         if (gx->gx_vflags & GXF_ENABLE_MWI)
 261                 command |= PCIM_CMD_MWIEN;
 262         pci_write_config(dev, PCIR_COMMAND, command, 4);
 263         command = pci_read_config(dev, PCIR_COMMAND, 4);
 264
 265 /* XXX check cache line size? */
 266
 267         if ((command & PCIM_CMD_MEMEN) == 0) {
 268                 device_printf(dev, "failed to enable memory mapping!\n");
 269                 error = ENXIO;
 270                 goto fail;
 271         }
 272
 273         rid = GX_PCI_LOMEM;
 274         gx->gx_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
 275             0, ~0, 1, RF_ACTIVE);
 276 #if 0
 277 /* support PIO mode */
 278         rid = PCI_LOIO;
 279         gx->gx_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
 280             0, ~0, 1, RF_ACTIVE);
 281 #endif
 282
 283         if (gx->gx_res == NULL) {
 284                 device_printf(dev, "couldn't map memory\n");
 285                 error = ENXIO;
 286                 goto fail;
 287         }
 288
 289         gx->gx_btag = rman_get_bustag(gx->gx_res);
 290         gx->gx_bhandle = rman_get_bushandle(gx->gx_res);
 291
 292         /* Allocate interrupt */
 293         rid = 0;
 294         gx->gx_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
 295             RF_SHAREABLE | RF_ACTIVE);
 296
 297         if (gx->gx_irq == NULL) {
 298                 device_printf(dev, "couldn't map interrupt\n");
 299                 error = ENXIO;
 300                 goto fail;
 301         }
 302
 303         error = bus_setup_intr(dev, gx->gx_irq, INTR_TYPE_NET,
 304            gx_intr, gx, &gx->gx_intrhand);
 305         if (error) {
 306                 device_printf(dev, "couldn't setup irq\n");
 307                 goto fail;
 308         }
 309
 310         /* compensate for different register mappings */
 311         if (gx->gx_vflags & GXF_OLD_REGS)
 312                 gx->gx_reg = old_regs;
 313         else
 314                 gx->gx_reg = new_regs;
 315
 316         if (gx_read_eeprom(gx, (caddr_t)&gx->arpcom.ac_enaddr,
 317             GX_EEMAP_MAC, 3)) {
 318                 device_printf(dev, "failed to read station address\n");
 319                 error = ENXIO;
 320                 goto fail;
 321         }
 322
 323         /* Allocate the ring buffers. */
 324         gx->gx_rdata = contigmalloc(sizeof(struct gx_ring_data), M_DEVBUF,
 325             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 326
 327         if (gx->gx_rdata == NULL) {
 328                 device_printf(dev, "no memory for list buffers!\n");
 329                 error = ENXIO;
 330                 goto fail;
 331         }
 332         bzero(gx->gx_rdata, sizeof(struct gx_ring_data));
 333
 334         /* Set default tuneable values. */
 335         gx->gx_tx_intr_delay = TUNABLE_TX_INTR_DELAY;
 336         gx->gx_rx_intr_delay = TUNABLE_RX_INTR_DELAY;
 337
 338         /* Set up ifnet structure */
 339         ifp = &gx->arpcom.ac_if;
 340         ifp->if_softc = gx;
 341         if_initname(ifp, "gx", device_get_unit(dev));
 342         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 343         ifp->if_ioctl = gx_ioctl;
 344         ifp->if_start = gx_start;
 345         ifp->if_watchdog = gx_watchdog;
 346         ifp->if_init = gx_init;
 347         ifp->if_mtu = ETHERMTU;
 348         ifp->if_snd.ifq_maxlen = GX_TX_RING_CNT - 1;
 349
 350         /* see if we can enable hardware checksumming */
 351         if (gx->gx_vflags & GXF_CSUM) {
 352                 ifp->if_capabilities = IFCAP_HWCSUM;
 353                 ifp->if_capenable = ifp->if_capabilities;
 354         }
 355
 356         /* figure out transciever type */
 357         if (gx->gx_vflags & GXF_FORCE_TBI ||
 358             CSR_READ_4(gx, GX_STATUS) & GX_STAT_TBIMODE)
 359                 gx->gx_tbimode = 1;
 360
 361         if (gx->gx_tbimode) {
 362                 /* SERDES transceiver */
 363                 ifmedia_init(&gx->gx_media, IFM_IMASK, gx_ifmedia_upd,
 364                     gx_ifmedia_sts);
 365                 ifmedia_add(&gx->gx_media,
 366                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 367                 ifmedia_add(&gx->gx_media, IFM_ETHER|IFM_AUTO, 0, NULL);
 368                 ifmedia_set(&gx->gx_media, IFM_ETHER|IFM_AUTO);
 369         } else {
 370                 /* GMII/MII transceiver */
 371                 gx_phy_reset(gx);
 372                 if (mii_phy_probe(dev, &gx->gx_miibus, gx_ifmedia_upd,
 373                     gx_ifmedia_sts)) {
 374                         device_printf(dev, "GMII/MII, PHY not detected\n");
 375                         error = ENXIO;
 376                         goto fail;
 377                 }
 378         }
 379
 380         /*
 381          * Call MI attach routines.
 382          */
 383         ether_ifattach(ifp, gx->arpcom.ac_enaddr);
 384
 385         GX_UNLOCK(gx);
 386         splx(s);
 387         return (0);
 388
 389 fail:
 390         GX_UNLOCK(gx);
 391         gx_release(gx);
 392         splx(s);
 393         return (error);
 394 }
 395
 396 static void
 397 gx_release(struct gx_softc *gx)
 398 {
 399
 400         bus_generic_detach(gx->gx_dev);
 401         if (gx->gx_miibus)
 402                 device_delete_child(gx->gx_dev, gx->gx_miibus);
 403
 404         if (gx->gx_intrhand)
 405                 bus_teardown_intr(gx->gx_dev, gx->gx_irq, gx->gx_intrhand);
 406         if (gx->gx_irq)
 407                 bus_release_resource(gx->gx_dev, SYS_RES_IRQ, 0, gx->gx_irq);
 408         if (gx->gx_res)
 409                 bus_release_resource(gx->gx_dev, SYS_RES_MEMORY,
 410                     GX_PCI_LOMEM, gx->gx_res);
 411 }
 412
 413 static void
 414 gx_init(void *xsc)
 415 {
 416         struct gx_softc *gx = (struct gx_softc *)xsc;
 417         struct ifmedia *ifm;
 418         struct ifnet *ifp;
 419         device_t dev;
 420         u_int16_t *m;
 421         u_int32_t ctrl;
 422         int s, i, tmp;
 423
 424         dev = gx->gx_dev;
 425         ifp = &gx->arpcom.ac_if;
 426
 427         s = splimp();
 428         GX_LOCK(gx);
 429
 430         /* Disable host interrupts, halt chip. */
 431         gx_reset(gx);
 432
 433         /* disable I/O, flush RX/TX FIFOs, and free RX/TX buffers */
 434         gx_stop(gx);
 435
 436         /* Load our MAC address, invalidate other 15 RX addresses. */
 437         m = (u_int16_t *)&gx->arpcom.ac_enaddr[0];
 438         CSR_WRITE_4(gx, GX_RX_ADDR_BASE, (m[1] << 16) | m[0]);
 439         CSR_WRITE_4(gx, GX_RX_ADDR_BASE + 4, m[2] | GX_RA_VALID);
 440         for (i = 1; i < 16; i++)
 441                 CSR_WRITE_8(gx, GX_RX_ADDR_BASE + i * 8, (u_quad_t)0);
 442
 443         /* Program multicast filter. */
 444         gx_setmulti(gx);
 445
 446         /* Init RX ring. */
 447         gx_init_rx_ring(gx);
 448
 449         /* Init TX ring. */
 450         gx_init_tx_ring(gx);
 451
 452         if (gx->gx_vflags & GXF_DMA) {
 453                 /* set up DMA control */
 454                 CSR_WRITE_4(gx, gx->gx_reg.r_rx_dma_ctrl, 0x00010000);
 455                 CSR_WRITE_4(gx, gx->gx_reg.r_tx_dma_ctrl, 0x00000000);
 456         }
 457
 458         /* enable receiver */
 459         ctrl = GX_RXC_ENABLE | GX_RXC_RX_THOLD_EIGHTH | GX_RXC_RX_BSIZE_2K;
 460         ctrl |= GX_RXC_BCAST_ACCEPT;
 461
 462         /* Enable or disable promiscuous mode as needed. */
 463         if (ifp->if_flags & IFF_PROMISC)
 464                 ctrl |= GX_RXC_UNI_PROMISC;
 465
 466         /* This is required if we want to accept jumbo frames */
 467         if (ifp->if_mtu > ETHERMTU)
 468                 ctrl |= GX_RXC_LONG_PKT_ENABLE;
 469
 470         /* setup receive checksum control */
 471         if (ifp->if_capenable & IFCAP_RXCSUM)
 472                 CSR_WRITE_4(gx, GX_RX_CSUM_CONTROL,
 473                     GX_CSUM_TCP/* | GX_CSUM_IP*/);
 474
 475         /* setup transmit checksum control */
 476         if (ifp->if_capenable & IFCAP_TXCSUM)
 477                 ifp->if_hwassist = GX_CSUM_FEATURES;
 478
 479         ctrl |= GX_RXC_STRIP_ETHERCRC;          /* not on 82542? */
 480         CSR_WRITE_4(gx, GX_RX_CONTROL, ctrl);
 481
 482         /* enable transmitter */
 483         ctrl = GX_TXC_ENABLE | GX_TXC_PAD_SHORT_PKTS | GX_TXC_COLL_RETRY_16;
 484
 485         /* XXX we should support half-duplex here too... */
 486         ctrl |= GX_TXC_COLL_TIME_FDX;
 487
 488         CSR_WRITE_4(gx, GX_TX_CONTROL, ctrl);
 489
 490         /*
 491          * set up recommended IPG times, which vary depending on chip type:
 492          *      IPG transmit time:  80ns
 493          *      IPG receive time 1: 20ns
 494          *      IPG receive time 2: 80ns
 495          */
 496         CSR_WRITE_4(gx, GX_TX_IPG, gx->gx_ipg);
 497
 498         /* set up 802.3x MAC flow control address -- 01:80:c2:00:00:01 */
 499         CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE, 0x00C28001);
 500         CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE+4, 0x00000100);
 501
 502         /* set up 802.3x MAC flow control type -- 88:08 */
 503         CSR_WRITE_4(gx, GX_FLOW_CTRL_TYPE, 0x8808);
 504
 505         /* Set up tuneables */
 506         CSR_WRITE_4(gx, gx->gx_reg.r_rx_delay, gx->gx_rx_intr_delay);
 507         CSR_WRITE_4(gx, gx->gx_reg.r_tx_delay, gx->gx_tx_intr_delay);
 508
 509         /*
 510          * Configure chip for correct operation.
 511          */
 512         ctrl = GX_CTRL_DUPLEX;
 513 #if BYTE_ORDER == BIG_ENDIAN
 514         ctrl |= GX_CTRL_BIGENDIAN;
 515 #endif
 516         ctrl |= GX_CTRL_VLAN_ENABLE;
 517
 518         if (gx->gx_tbimode) {
 519                 /*
 520                  * It seems that TXCW must be initialized from the EEPROM
 521                  * manually.
 522                  *
 523                  * XXX
 524                  * should probably read the eeprom and re-insert the
 525                  * values here.
 526                  */
 527 #define TXCONFIG_WORD   0x000001A0
 528                 CSR_WRITE_4(gx, GX_TX_CONFIG, TXCONFIG_WORD);
 529
 530                 /* turn on hardware autonegotiate */
 531                 GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
 532         } else {
 533                 /*
 534                  * Auto-detect speed from PHY, instead of using direct
 535                  * indication.  The SLU bit doesn't force the link, but
 536                  * must be present for ASDE to work.
 537                  */
 538                 gx_phy_reset(gx);
 539                 ctrl |= GX_CTRL_SET_LINK_UP | GX_CTRL_AUTOSPEED;
 540         }
 541
 542         /*
 543          * Take chip out of reset and start it running.
 544          */
 545         CSR_WRITE_4(gx, GX_CTRL, ctrl);
 546
 547         /* Turn interrupts on. */
 548         CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
 549
 550         ifp->if_flags |= IFF_RUNNING;
 551         ifp->if_flags &= ~IFF_OACTIVE;
 552
 553         /*
 554          * Set the current media.
 555          */
 556         if (gx->gx_miibus != NULL) {
 557                 mii_mediachg(device_get_softc(gx->gx_miibus));
 558         } else {
 559                 ifm = &gx->gx_media;
 560                 tmp = ifm->ifm_media;
 561                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
 562                 gx_ifmedia_upd(ifp);
 563                 ifm->ifm_media = tmp;
 564         }
 565
 566         /*
 567          * XXX
 568          * Have the LINK0 flag force the link in TBI mode.
 569          */
 570         if (gx->gx_tbimode && ifp->if_flags & IFF_LINK0) {
 571                 GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
 572                 GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
 573         }
 574
 575 #if 0
 576 printf("66mhz: %s  64bit: %s\n",
 577         CSR_READ_4(gx, GX_STATUS) & GX_STAT_PCI66 ? "yes" : "no",
 578         CSR_READ_4(gx, GX_STATUS) & GX_STAT_BUS64 ? "yes" : "no");
 579 #endif
 580
 581         GX_UNLOCK(gx);
 582         splx(s);
 583 }
 584
 585 /*
 586  * Stop all chip I/O so that the kernel's probe routines don't
 587  * get confused by errant DMAs when rebooting.
 588  */
 589 static void
 590 gx_shutdown(device_t dev)
 591 {
 592         struct gx_softc *gx;
 593
 594         gx = device_get_softc(dev);
 595         gx_reset(gx);
 596         gx_stop(gx);
 597 }
 598
 599 static int
 600 gx_detach(device_t dev)
 601 {
 602         struct gx_softc *gx;
 603         struct ifnet *ifp;
 604         int s;
 605
 606         s = splimp();
 607
 608         gx = device_get_softc(dev);
 609         ifp = &gx->arpcom.ac_if;
 610         GX_LOCK(gx);
 611
 612         ether_ifdetach(ifp);
 613         gx_reset(gx);
 614         gx_stop(gx);
 615         ifmedia_removeall(&gx->gx_media);
 616         gx_release(gx);
 617
 618         contigfree(gx->gx_rdata, sizeof(struct gx_ring_data), M_DEVBUF);
 619
 620         GX_UNLOCK(gx);
 621         mtx_destroy(&gx->gx_mtx);
 622         splx(s);
 623
 624         return (0);
 625 }
 626
 627 static void
 628 gx_eeprom_getword(struct gx_softc *gx, int addr, u_int16_t *dest)
 629 {
 630         u_int16_t word = 0;
 631         u_int32_t base, reg;
 632         int x;
 633
 634         addr = (GX_EE_OPC_READ << GX_EE_ADDR_SIZE) |
 635             (addr & ((1 << GX_EE_ADDR_SIZE) - 1));
 636
 637         base = CSR_READ_4(gx, GX_EEPROM_CTRL);
 638         base &= ~(GX_EE_DATA_OUT | GX_EE_DATA_IN | GX_EE_CLOCK);
 639         base |= GX_EE_SELECT;
 640
 641         CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
 642
 643         for (x = 1 << ((GX_EE_OPC_SIZE + GX_EE_ADDR_SIZE) - 1); x; x >>= 1) {
 644                 reg = base | (addr & x ? GX_EE_DATA_IN : 0);
 645                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
 646                 DELAY(10);
 647                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg | GX_EE_CLOCK);
 648                 DELAY(10);
 649                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
 650                 DELAY(10);
 651         }
 652
 653         for (x = 1 << 15; x; x >>= 1) {
 654                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base | GX_EE_CLOCK);
 655                 DELAY(10);
 656                 reg = CSR_READ_4(gx, GX_EEPROM_CTRL);
 657                 if (reg & GX_EE_DATA_OUT)
 658                         word |= x;
 659                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
 660                 DELAY(10);
 661         }
 662
 663         CSR_WRITE_4(gx, GX_EEPROM_CTRL, base & ~GX_EE_SELECT);
 664         DELAY(10);
 665
 666         *dest = word;
 667 }
 668
 669 static int
 670 gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off, int cnt)
 671 {
 672         u_int16_t *word;
 673         int i;
 674
 675         word = (u_int16_t *)dest;
 676         for (i = 0; i < cnt; i ++) {
 677                 gx_eeprom_getword(gx, off + i, word);
 678                 word++;
 679         }
 680         return (0);
 681 }
 682
 683 /*
 684  * Set media options.
 685  */
 686 static int
 687 gx_ifmedia_upd(struct ifnet *ifp)
 688 {
 689         struct gx_softc *gx;
 690         struct ifmedia *ifm;
 691         struct mii_data *mii;
 692
 693         gx = ifp->if_softc;
 694
 695         if (gx->gx_tbimode) {
 696                 ifm = &gx->gx_media;
 697                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 698                         return (EINVAL);
 699                 switch (IFM_SUBTYPE(ifm->ifm_media)) {
 700                 case IFM_AUTO:
 701                         GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
 702                         GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
 703                         GX_CLRBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
 704                         break;
 705                 case IFM_1000_SX:
 706                         device_printf(gx->gx_dev,
 707                             "manual config not supported yet.\n");
 708 #if 0
 709                         GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
 710                         config = /* bit symbols for 802.3z */0;
 711                         ctrl |= GX_CTRL_SET_LINK_UP;
 712                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
 713                                 ctrl |= GX_CTRL_DUPLEX;
 714 #endif
 715                         break;
 716                 default:
 717                         return (EINVAL);
 718                 }
 719         } else {
 720                 ifm = &gx->gx_media;
 721
 722                 /*
 723                  * 1000TX half duplex does not work.
 724                  */
 725                 if (IFM_TYPE(ifm->ifm_media) == IFM_ETHER &&
 726                     IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_TX &&
 727                     (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) == 0)
 728                         return (EINVAL);
 729                 mii = device_get_softc(gx->gx_miibus);
 730                 mii_mediachg(mii);
 731         }
 732         return (0);
 733 }
 734
 735 /*
 736  * Report current media status.
 737  */
 738 static void
 739 gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 740 {
 741         struct gx_softc *gx;
 742         struct mii_data *mii;
 743         u_int32_t status;
 744
 745         gx = ifp->if_softc;
 746
 747         if (gx->gx_tbimode) {
 748                 ifmr->ifm_status = IFM_AVALID;
 749                 ifmr->ifm_active = IFM_ETHER;
 750
 751                 status = CSR_READ_4(gx, GX_STATUS);
 752                 if ((status & GX_STAT_LINKUP) == 0)
 753                         return;
 754
 755                 ifmr->ifm_status |= IFM_ACTIVE;
 756                 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
 757         } else {
 758                 mii = device_get_softc(gx->gx_miibus);
 759                 mii_pollstat(mii);
 760                 if ((mii->mii_media_active & (IFM_1000_TX | IFM_HDX)) ==
 761                     (IFM_1000_TX | IFM_HDX))
 762                         mii->mii_media_active = IFM_ETHER | IFM_NONE;
 763                 ifmr->ifm_active = mii->mii_media_active;
 764                 ifmr->ifm_status = mii->mii_media_status;
 765         }
 766 }
 767
 768 static void
 769 gx_mii_shiftin(struct gx_softc *gx, int data, int length)
 770 {
 771         u_int32_t reg, x;
 772
 773         /*
 774          * Set up default GPIO direction + PHY data out.
 775          */
 776         reg = CSR_READ_4(gx, GX_CTRL);
 777         reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
 778         reg |= GX_CTRL_GPIO_DIR | GX_CTRL_PHY_IO_DIR;
 779
 780         /*
 781          * Shift in data to PHY.
 782          */
 783         for (x = 1 << (length - 1); x; x >>= 1) {
 784                 if (data & x)
 785                         reg |= GX_CTRL_PHY_IO;
 786                 else
 787                         reg &= ~GX_CTRL_PHY_IO;
 788                 CSR_WRITE_4(gx, GX_CTRL, reg);
 789                 DELAY(10);
 790                 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
 791                 DELAY(10);
 792                 CSR_WRITE_4(gx, GX_CTRL, reg);
 793                 DELAY(10);
 794         }
 795 }
 796
 797 static u_int16_t
 798 gx_mii_shiftout(struct gx_softc *gx)
 799 {
 800         u_int32_t reg;
 801         u_int16_t data;
 802         int x;
 803
 804         /*
 805          * Set up default GPIO direction + PHY data in.
 806          */
 807         reg = CSR_READ_4(gx, GX_CTRL);
 808         reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
 809         reg |= GX_CTRL_GPIO_DIR;
 810
 811         CSR_WRITE_4(gx, GX_CTRL, reg);
 812         DELAY(10);
 813         CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
 814         DELAY(10);
 815         CSR_WRITE_4(gx, GX_CTRL, reg);
 816         DELAY(10);
 817         /*
 818          * Shift out data from PHY.
 819          */
 820         data = 0;
 821         for (x = 1 << 15; x; x >>= 1) {
 822                 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
 823                 DELAY(10);
 824                 if (CSR_READ_4(gx, GX_CTRL) & GX_CTRL_PHY_IO)
 825                         data |= x;
 826                 CSR_WRITE_4(gx, GX_CTRL, reg);
 827                 DELAY(10);
 828         }
 829         CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
 830         DELAY(10);
 831         CSR_WRITE_4(gx, GX_CTRL, reg);
 832         DELAY(10);
 833
 834         return (data);
 835 }
 836
 837 static int
 838 gx_miibus_readreg(device_t dev, int phy, int reg)
 839 {
 840         struct gx_softc *gx;
 841
 842         gx = device_get_softc(dev);
 843         if (gx->gx_tbimode)
 844                 return (0);
 845
 846         /*
 847          * XXX
 848          * Note: Cordova has a MDIC register. livingood and < have mii bits
 849          */
 850
 851         gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
 852         gx_mii_shiftin(gx, (GX_PHY_SOF << 12) | (GX_PHY_OP_READ << 10) |
 853             (phy << 5) | reg, GX_PHY_READ_LEN);
 854         return (gx_mii_shiftout(gx));
 855 }
 856
 857 static void
 858 gx_miibus_writereg(device_t dev, int phy, int reg, int value)
 859 {
 860         struct gx_softc *gx;
 861
 862         gx = device_get_softc(dev);
 863         if (gx->gx_tbimode)
 864                 return;
 865
 866         gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
 867         gx_mii_shiftin(gx, (GX_PHY_SOF << 30) | (GX_PHY_OP_WRITE << 28) |
 868             (phy << 23) | (reg << 18) | (GX_PHY_TURNAROUND << 16) |
 869             (value & 0xffff), GX_PHY_WRITE_LEN);
 870 }
 871
 872 static void
 873 gx_miibus_statchg(device_t dev)
 874 {
 875         struct gx_softc *gx;
 876         struct mii_data *mii;
 877         int reg, s;
 878
 879         gx = device_get_softc(dev);
 880         if (gx->gx_tbimode)
 881                 return;
 882
 883         /*
 884          * Set flow control behavior to mirror what PHY negotiated.
 885          */
 886         mii = device_get_softc(gx->gx_miibus);
 887
 888         s = splimp();
 889         GX_LOCK(gx);
 890
 891         reg = CSR_READ_4(gx, GX_CTRL);
 892         if (mii->mii_media_active & IFM_FLAG0)
 893                 reg |= GX_CTRL_RX_FLOWCTRL;
 894         else
 895                 reg &= ~GX_CTRL_RX_FLOWCTRL;
 896         if (mii->mii_media_active & IFM_FLAG1)
 897                 reg |= GX_CTRL_TX_FLOWCTRL;
 898         else
 899                 reg &= ~GX_CTRL_TX_FLOWCTRL;
 900         CSR_WRITE_4(gx, GX_CTRL, reg);
 901
 902         GX_UNLOCK(gx);
 903         splx(s);
 904 }
 905
 906 static int
 907 gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 908 {
 909         struct gx_softc *gx = ifp->if_softc;
 910         struct ifreq *ifr = (struct ifreq *)data;
 911         struct mii_data *mii;
 912         int s, mask, error = 0;
 913
 914         s = splimp();
 915         GX_LOCK(gx);
 916
 917         switch (command) {
 918         case SIOCSIFADDR:
 919         case SIOCGIFADDR:
 920                 error = ether_ioctl(ifp, command, data);
 921                 break;
 922         case SIOCSIFMTU:
 923                 if (ifr->ifr_mtu > GX_MAX_MTU) {
 924                         error = EINVAL;
 925                 } else {
 926                         ifp->if_mtu = ifr->ifr_mtu;
 927                         gx_init(gx);
 928                 }
 929                 break;
 930         case SIOCSIFFLAGS:
 931                 if ((ifp->if_flags & IFF_UP) == 0) {
 932                         gx_stop(gx);
 933                 } else if (ifp->if_flags & IFF_RUNNING &&
 934                     ((ifp->if_flags & IFF_PROMISC) !=
 935                     (gx->gx_if_flags & IFF_PROMISC))) {
 936                         if (ifp->if_flags & IFF_PROMISC)
 937                                 GX_SETBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
 938                         else
 939                                 GX_CLRBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
 940                 } else {
 941                         gx_init(gx);
 942                 }
 943                 gx->gx_if_flags = ifp->if_flags;
 944                 break;
 945         case SIOCADDMULTI:
 946         case SIOCDELMULTI:
 947                 if (ifp->if_flags & IFF_RUNNING)
 948                         gx_setmulti(gx);
 949                 break;
 950         case SIOCSIFMEDIA:
 951         case SIOCGIFMEDIA:
 952                 if (gx->gx_miibus != NULL) {
 953                         mii = device_get_softc(gx->gx_miibus);
 954                         error = ifmedia_ioctl(ifp, ifr,
 955                             &mii->mii_media, command);
 956                 } else {
 957                         error = ifmedia_ioctl(ifp, ifr, &gx->gx_media, command);
 958                 }
 959                 break;
 960         case SIOCSIFCAP:
 961                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 962                 if (mask & IFCAP_HWCSUM) {
 963                         if (IFCAP_HWCSUM & ifp->if_capenable)
 964                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
 965                         else
 966                                 ifp->if_capenable |= IFCAP_HWCSUM;
 967                         if (ifp->if_flags & IFF_RUNNING)
 968                                 gx_init(gx);
 969                 }
 970                 break;
 971         default:
 972                 error = EINVAL;
 973                 break;
 974         }
 975
 976         GX_UNLOCK(gx);
 977         splx(s);
 978         return (error);
 979 }
 980
 981 static void
 982 gx_phy_reset(struct gx_softc *gx)
 983 {
 984         int reg;
 985
 986         GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
 987
 988         /*
 989          * PHY reset is active low.
 990          */
 991         reg = CSR_READ_4(gx, GX_CTRL_EXT);
 992         reg &= ~(GX_CTRLX_GPIO_DIR_MASK | GX_CTRLX_PHY_RESET);
 993         reg |= GX_CTRLX_GPIO_DIR;
 994
 995         CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
 996         DELAY(10);
 997         CSR_WRITE_4(gx, GX_CTRL_EXT, reg);
 998         DELAY(10);
 999         CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
1000         DELAY(10);
1001
1002 #if 0
1003         /* post-livingood (cordova) only */
1004                 GX_SETBIT(gx, GX_CTRL, 0x80000000);
1005                 DELAY(1000);
1006                 GX_CLRBIT(gx, GX_CTRL, 0x80000000);
1007 #endif
1008 }
1009
1010 static void
1011 gx_reset(struct gx_softc *gx)
1012 {
1013
1014         /* Disable host interrupts. */
1015         CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
1016
1017         /* reset chip (THWAP!) */
1018         GX_SETBIT(gx, GX_CTRL, GX_CTRL_DEVICE_RESET);
1019         DELAY(10);
1020 }
1021
1022 static void
1023 gx_stop(struct gx_softc *gx)
1024 {
1025         struct ifnet *ifp;
1026
1027         ifp = &gx->arpcom.ac_if;
1028
1029         /* reset and flush transmitter */
1030         CSR_WRITE_4(gx, GX_TX_CONTROL, GX_TXC_RESET);
1031
1032         /* reset and flush receiver */
1033         CSR_WRITE_4(gx, GX_RX_CONTROL, GX_RXC_RESET);
1034
1035         /* reset link */
1036         if (gx->gx_tbimode)
1037                 GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
1038
1039         /* Free the RX lists. */
1040         gx_free_rx_ring(gx);
1041
1042         /* Free TX buffers. */
1043         gx_free_tx_ring(gx);
1044
1045         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1046 }
1047
1048 static void
1049 gx_watchdog(struct ifnet *ifp)
1050 {
1051         struct gx_softc *gx;
1052
1053         gx = ifp->if_softc;
1054
1055         device_printf(gx->gx_dev, "watchdog timeout -- resetting\n");
1056         gx_reset(gx);
1057         gx_init(gx);
1058
1059         ifp->if_oerrors++;
1060 }
1061
1062 /*
1063  * Intialize a receive ring descriptor.
1064  */
1065 static int
1066 gx_newbuf(struct gx_softc *gx, int idx, struct mbuf *m)
1067 {
1068         struct mbuf *m_new = NULL;
1069         struct gx_rx_desc *r;
1070
1071         if (m == NULL) {
1072                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1073                 if (m_new == NULL) {
1074                         device_printf(gx->gx_dev,
1075                             "mbuf allocation failed -- packet dropped\n");
1076                         return (ENOBUFS);
1077                 }
1078                 MCLGET(m_new, MB_DONTWAIT);
1079                 if ((m_new->m_flags & M_EXT) == 0) {
1080                         device_printf(gx->gx_dev,
1081                             "cluster allocation failed -- packet dropped\n");
1082                         m_freem(m_new);
1083                         return (ENOBUFS);
1084                 }
1085                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1086         } else {
1087                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1088                 m->m_data = m->m_ext.ext_buf;
1089                 m->m_next = NULL;
1090                 m_new = m;
1091         }
1092
1093         /*
1094          * XXX
1095          * this will _NOT_ work for large MTU's; it will overwrite
1096          * the end of the buffer.  E.g.: take this out for jumbograms,
1097          * but then that breaks alignment.
1098          */
1099         if (gx->arpcom.ac_if.if_mtu <= ETHERMTU)
1100                 m_adj(m_new, ETHER_ALIGN);
1101
1102         gx->gx_cdata.gx_rx_chain[idx] = m_new;
1103         r = &gx->gx_rdata->gx_rx_ring[idx];
1104         r->rx_addr = vtophys(mtod(m_new, caddr_t));
1105         r->rx_staterr = 0;
1106
1107         return (0);
1108 }
1109
1110 /*
1111  * The receive ring can have up to 64K descriptors, which at 2K per mbuf
1112  * cluster, could add up to 128M of memory.  Due to alignment constraints,
1113  * the number of descriptors must be a multiple of 8.  For now, we
1114  * allocate 256 entries and hope that our CPU is fast enough to keep up
1115  * with the NIC.
1116  */
1117 static int
1118 gx_init_rx_ring(struct gx_softc *gx)
1119 {
1120         int i, error;
1121
1122         for (i = 0; i < GX_RX_RING_CNT; i++) {
1123                 error = gx_newbuf(gx, i, NULL);
1124                 if (error)
1125                         return (error);
1126         }
1127
1128         /* bring receiver out of reset state, leave disabled */
1129         CSR_WRITE_4(gx, GX_RX_CONTROL, 0);
1130
1131         /* set up ring registers */
1132         CSR_WRITE_8(gx, gx->gx_reg.r_rx_base,
1133             (u_quad_t)vtophys(gx->gx_rdata->gx_rx_ring));
1134
1135         CSR_WRITE_4(gx, gx->gx_reg.r_rx_length,
1136             GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1137         CSR_WRITE_4(gx, gx->gx_reg.r_rx_head, 0);
1138         CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, GX_RX_RING_CNT - 1);
1139         gx->gx_rx_tail_idx = 0;
1140
1141         return (0);
1142 }
1143
1144 static void
1145 gx_free_rx_ring(struct gx_softc *gx)
1146 {
1147         struct mbuf **mp;
1148         int i;
1149
1150         mp = gx->gx_cdata.gx_rx_chain;
1151         for (i = 0; i < GX_RX_RING_CNT; i++, mp++) {
1152                 if (*mp != NULL) {
1153                         m_freem(*mp);
1154                         *mp = NULL;
1155                 }
1156         }
1157         bzero((void *)gx->gx_rdata->gx_rx_ring,
1158             GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1159
1160         /* release any partially-received packet chain */
1161         if (gx->gx_pkthdr != NULL) {
1162                 m_freem(gx->gx_pkthdr);
1163                 gx->gx_pkthdr = NULL;
1164         }
1165 }
1166
1167 static int
1168 gx_init_tx_ring(struct gx_softc *gx)
1169 {
1170
1171         /* bring transmitter out of reset state, leave disabled */
1172         CSR_WRITE_4(gx, GX_TX_CONTROL, 0);
1173
1174         /* set up ring registers */
1175         CSR_WRITE_8(gx, gx->gx_reg.r_tx_base,
1176             (u_quad_t)vtophys(gx->gx_rdata->gx_tx_ring));
1177         CSR_WRITE_4(gx, gx->gx_reg.r_tx_length,
1178             GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1179         CSR_WRITE_4(gx, gx->gx_reg.r_tx_head, 0);
1180         CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, 0);
1181         gx->gx_tx_head_idx = 0;
1182         gx->gx_tx_tail_idx = 0;
1183         gx->gx_txcnt = 0;
1184
1185         /* set up initial TX context */
1186         gx->gx_txcontext = GX_TXCONTEXT_NONE;
1187
1188         return (0);
1189 }
1190
1191 static void
1192 gx_free_tx_ring(struct gx_softc *gx)
1193 {
1194         struct mbuf **mp;
1195         int i;
1196
1197         mp = gx->gx_cdata.gx_tx_chain;
1198         for (i = 0; i < GX_TX_RING_CNT; i++, mp++) {
1199                 if (*mp != NULL) {
1200                         m_freem(*mp);
1201                         *mp = NULL;
1202                 }
1203         }
1204         bzero((void *)&gx->gx_rdata->gx_tx_ring,
1205             GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1206 }
1207
1208 static void
1209 gx_setmulti(struct gx_softc *gx)
1210 {
1211         int i;
1212
1213         /* wipe out the multicast table */
1214         for (i = 1; i < 128; i++)
1215                 CSR_WRITE_4(gx, GX_MULTICAST_BASE + i * 4, 0);
1216 }
1217
1218 static void
1219 gx_rxeof(struct gx_softc *gx)
1220 {
1221         struct gx_rx_desc *rx;
1222         struct ifnet *ifp;
1223         int idx, staterr, len;
1224         struct mbuf *m;
1225
1226         gx->gx_rx_interrupts++;
1227
1228         ifp = &gx->arpcom.ac_if;
1229         idx = gx->gx_rx_tail_idx;
1230
1231         while (gx->gx_rdata->gx_rx_ring[idx].rx_staterr & GX_RXSTAT_COMPLETED) {
1232
1233                 rx = &gx->gx_rdata->gx_rx_ring[idx];
1234                 m = gx->gx_cdata.gx_rx_chain[idx];
1235                 /*
1236                  * gx_newbuf overwrites status and length bits, so we
1237                  * make a copy of them here.
1238                  */
1239                 len = rx->rx_len;
1240                 staterr = rx->rx_staterr;
1241
1242                 if (staterr & GX_INPUT_ERROR)
1243                         goto ierror;
1244
1245                 if (gx_newbuf(gx, idx, NULL) == ENOBUFS)
1246                         goto ierror;
1247
1248                 GX_INC(idx, GX_RX_RING_CNT);
1249
1250                 if (staterr & GX_RXSTAT_INEXACT_MATCH) {
1251                         /*
1252                          * multicast packet, must verify against
1253                          * multicast address.
1254                          */
1255                 }
1256
1257                 if ((staterr & GX_RXSTAT_END_OF_PACKET) == 0) {
1258                         if (gx->gx_pkthdr == NULL) {
1259                                 m->m_len = len;
1260                                 m->m_pkthdr.len = len;
1261                                 gx->gx_pkthdr = m;
1262                                 gx->gx_pktnextp = &m->m_next;
1263                         } else {
1264                                 m->m_len = len;
1265                                 m->m_flags &= ~M_PKTHDR;
1266                                 gx->gx_pkthdr->m_pkthdr.len += len;
1267                                 *(gx->gx_pktnextp) = m;
1268                                 gx->gx_pktnextp = &m->m_next;
1269                         }
1270                         continue;
1271                 }
1272
1273                 if (gx->gx_pkthdr == NULL) {
1274                         m->m_len = len;
1275                         m->m_pkthdr.len = len;
1276                 } else {
1277                         m->m_len = len;
1278                         m->m_flags &= ~M_PKTHDR;
1279                         gx->gx_pkthdr->m_pkthdr.len += len;
1280                         *(gx->gx_pktnextp) = m;
1281                         m = gx->gx_pkthdr;
1282                         gx->gx_pkthdr = NULL;
1283                 }
1284
1285                 ifp->if_ipackets++;
1286                 m->m_pkthdr.rcvif = ifp;
1287
1288 #define IP_CSMASK       (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_IP_CSUM)
1289 #define TCP_CSMASK \
1290     (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_TCP_CSUM | GX_RXERR_TCP_CSUM)
1291                 if (ifp->if_capenable & IFCAP_RXCSUM) {
1292 #if 0
1293                         /*
1294                          * Intel Erratum #23 indicates that the Receive IP
1295                          * Checksum offload feature has been completely
1296                          * disabled.
1297                          */
1298                         if ((staterr & IP_CSUM_MASK) == GX_RXSTAT_HAS_IP_CSUM) {
1299                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1300                                 if ((staterr & GX_RXERR_IP_CSUM) == 0)
1301                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1302                         }
1303 #endif
1304                         if ((staterr & TCP_CSMASK) == GX_RXSTAT_HAS_TCP_CSUM) {
1305                                 m->m_pkthdr.csum_flags |=
1306                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1307                                 m->m_pkthdr.csum_data = 0xffff;
1308                         }
1309                 }
1310                 /*
1311                  * If we received a packet with a vlan tag, pass it
1312                  * to vlan_input() instead of ether_input().
1313                  */
1314                 if (staterr & GX_RXSTAT_VLAN_PKT)
1315                         VLAN_INPUT_TAG(m, rx->rx_special);
1316                 else
1317                         (*ifp->if_input)(ifp, m);
1318                 continue;
1319
1320   ierror:
1321                 ifp->if_ierrors++;
1322                 gx_newbuf(gx, idx, m);
1323
1324                 /*
1325                  * XXX
1326                  * this isn't quite right.  Suppose we have a packet that
1327                  * spans 5 descriptors (9K split into 2K buffers).  If
1328                  * the 3rd descriptor sets an error, we need to ignore
1329                  * the last two.  The way things stand now, the last two
1330                  * will be accepted as a single packet.
1331                  *
1332                  * we don't worry about this -- the chip may not set an
1333                  * error in this case, and the checksum of the upper layers
1334                  * will catch the error.
1335                  */
1336                 if (gx->gx_pkthdr != NULL) {
1337                         m_freem(gx->gx_pkthdr);
1338                         gx->gx_pkthdr = NULL;
1339                 }
1340                 GX_INC(idx, GX_RX_RING_CNT);
1341         }
1342
1343         gx->gx_rx_tail_idx = idx;
1344         if (--idx < 0)
1345                 idx = GX_RX_RING_CNT - 1;
1346         CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, idx);
1347 }
1348
1349 static void
1350 gx_txeof(struct gx_softc *gx)
1351 {
1352         struct ifnet *ifp;
1353         int idx, cnt;
1354
1355         gx->gx_tx_interrupts++;
1356
1357         ifp = &gx->arpcom.ac_if;
1358         idx = gx->gx_tx_head_idx;
1359         cnt = gx->gx_txcnt;
1360
1361         /*
1362          * If the system chipset performs I/O write buffering, it is
1363          * possible for the PIO read of the head descriptor to bypass the
1364          * memory write of the descriptor, resulting in reading a descriptor
1365          * which has not been updated yet.
1366          */
1367         while (cnt) {
1368                 struct gx_tx_desc_old *tx;
1369
1370                 tx = (struct gx_tx_desc_old *)&gx->gx_rdata->gx_tx_ring[idx];
1371                 cnt--;
1372
1373                 if ((tx->tx_command & GX_TXOLD_END_OF_PKT) == 0) {
1374                         GX_INC(idx, GX_TX_RING_CNT);
1375                         continue;
1376                 }
1377
1378                 if ((tx->tx_status & GX_TXSTAT_DONE) == 0)
1379                         break;
1380
1381                 ifp->if_opackets++;
1382
1383                 m_freem(gx->gx_cdata.gx_tx_chain[idx]);
1384                 gx->gx_cdata.gx_tx_chain[idx] = NULL;
1385                 gx->gx_txcnt = cnt;
1386                 ifp->if_timer = 0;
1387
1388                 GX_INC(idx, GX_TX_RING_CNT);
1389                 gx->gx_tx_head_idx = idx;
1390         }
1391
1392         if (gx->gx_txcnt == 0)
1393                 ifp->if_flags &= ~IFF_OACTIVE;
1394 }
1395
1396 static void
1397 gx_intr(void *xsc)
1398 {
1399         struct gx_softc *gx;
1400         struct ifnet *ifp;
1401         u_int32_t intr;
1402         int s;
1403
1404         gx = xsc;
1405         ifp = &gx->arpcom.ac_if;
1406
1407         s = splimp();
1408
1409         gx->gx_interrupts++;
1410
1411         /* Disable host interrupts. */
1412         CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
1413
1414         /*
1415          * find out why we're being bothered.
1416          * reading this register automatically clears all bits.
1417          */
1418         intr = CSR_READ_4(gx, GX_INT_READ);
1419
1420         /* Check RX return ring producer/consumer */
1421         if (intr & (GX_INT_RCV_TIMER | GX_INT_RCV_THOLD | GX_INT_RCV_OVERRUN))
1422                 gx_rxeof(gx);
1423
1424         /* Check TX ring producer/consumer */
1425         if (intr & (GX_INT_XMIT_DONE | GX_INT_XMIT_EMPTY))
1426                 gx_txeof(gx);
1427
1428         /*
1429          * handle other interrupts here.
1430          */
1431
1432         /*
1433          * Link change interrupts are not reliable; the interrupt may
1434          * not be generated if the link is lost.  However, the register
1435          * read is reliable, so check that.  Use SEQ errors to possibly
1436          * indicate that the link has changed.
1437          */
1438         if (intr & GX_INT_LINK_CHANGE) {
1439                 if ((CSR_READ_4(gx, GX_STATUS) & GX_STAT_LINKUP) == 0) {
1440                         device_printf(gx->gx_dev, "link down\n");
1441                 } else {
1442                         device_printf(gx->gx_dev, "link up\n");
1443                 }
1444         }
1445
1446         /* Turn interrupts on. */
1447         CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
1448
1449         if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1450                 gx_start(ifp);
1451
1452         splx(s);
1453 }
1454
1455 /*
1456  * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1457  * pointers to descriptors.
1458  */
1459 static int
1460 gx_encap(struct gx_softc *gx, struct mbuf *m_head)
1461 {
1462         struct gx_tx_desc_data *tx = NULL;
1463         struct gx_tx_desc_ctx *tctx;
1464         struct mbuf *m;
1465         int idx, cnt, csumopts, txcontext;
1466         struct ifvlan *ifv = NULL;
1467
1468         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1469             m_head->m_pkthdr.rcvif != NULL &&
1470             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1471                 ifv = m_head->m_pkthdr.rcvif->if_softc;
1472
1473         cnt = gx->gx_txcnt;
1474         idx = gx->gx_tx_tail_idx;
1475         txcontext = gx->gx_txcontext;
1476
1477         /*
1478          * Insure we have at least 4 descriptors pre-allocated.
1479          */
1480         if (cnt >= GX_TX_RING_CNT - 4)
1481                 return (ENOBUFS);
1482
1483         /*
1484          * Set up the appropriate offload context if necessary.
1485          */
1486         csumopts = 0;
1487         if (m_head->m_pkthdr.csum_flags) {
1488                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1489                         csumopts |= GX_TXTCP_OPT_IP_CSUM;
1490                 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) {
1491                         csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1492                         txcontext = GX_TXCONTEXT_TCPIP;
1493                 } else if (m_head->m_pkthdr.csum_flags & CSUM_UDP) {
1494                         csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1495                         txcontext = GX_TXCONTEXT_UDPIP;
1496                 } else if (txcontext == GX_TXCONTEXT_NONE)
1497                         txcontext = GX_TXCONTEXT_TCPIP;
1498                 if (txcontext == gx->gx_txcontext)
1499                         goto context_done;
1500
1501                 tctx = (struct gx_tx_desc_ctx *)&gx->gx_rdata->gx_tx_ring[idx];
1502                 tctx->tx_ip_csum_start = ETHER_HDR_LEN;
1503                 tctx->tx_ip_csum_end = ETHER_HDR_LEN + sizeof(struct ip) - 1;
1504                 tctx->tx_ip_csum_offset =
1505                     ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
1506                 tctx->tx_tcp_csum_start = ETHER_HDR_LEN + sizeof(struct ip);
1507                 tctx->tx_tcp_csum_end = 0;
1508                 if (txcontext == GX_TXCONTEXT_TCPIP)
1509                         tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1510                             sizeof(struct ip) + offsetof(struct tcphdr, th_sum);
1511                 else
1512                         tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1513                             sizeof(struct ip) + offsetof(struct udphdr, uh_sum);
1514                 tctx->tx_command = GX_TXCTX_EXTENSION | GX_TXCTX_INT_DELAY;
1515                 tctx->tx_type = 0;
1516                 tctx->tx_status = 0;
1517                 GX_INC(idx, GX_TX_RING_CNT);
1518                 cnt++;
1519         }
1520 context_done:
1521
1522         /*
1523          * Start packing the mbufs in this chain into the transmit
1524          * descriptors.  Stop when we run out of descriptors or hit
1525          * the end of the mbuf chain.
1526          */
1527         for (m = m_head; m != NULL; m = m->m_next) {
1528                 if (m->m_len == 0)
1529                         continue;
1530
1531                 if (cnt == GX_TX_RING_CNT) {
1532 printf("overflow(2): %d, %d\n", cnt, GX_TX_RING_CNT);
1533                         return (ENOBUFS);
1534 }
1535
1536                 tx = (struct gx_tx_desc_data *)&gx->gx_rdata->gx_tx_ring[idx];
1537                 tx->tx_addr = vtophys(mtod(m, vm_offset_t));
1538                 tx->tx_status = 0;
1539                 tx->tx_len = m->m_len;
1540                 if (gx->arpcom.ac_if.if_hwassist) {
1541                         tx->tx_type = 1;
1542                         tx->tx_command = GX_TXTCP_EXTENSION;
1543                         tx->tx_options = csumopts;
1544                 } else {
1545                         /*
1546                          * This is really a struct gx_tx_desc_old.
1547                          */
1548                         tx->tx_command = 0;
1549                 }
1550                 GX_INC(idx, GX_TX_RING_CNT);
1551                 cnt++;
1552         }
1553
1554         if (tx != NULL) {
1555                 tx->tx_command |= GX_TXTCP_REPORT_STATUS | GX_TXTCP_INT_DELAY |
1556                     GX_TXTCP_ETHER_CRC | GX_TXTCP_END_OF_PKT;
1557                 if (ifv != NULL) {
1558                         tx->tx_command |= GX_TXTCP_VLAN_ENABLE;
1559                         tx->tx_vlan = ifv->ifv_tag;
1560                 }
1561                 gx->gx_txcnt = cnt;
1562                 gx->gx_tx_tail_idx = idx;
1563                 gx->gx_txcontext = txcontext;
1564                 idx = GX_PREV(idx, GX_TX_RING_CNT);
1565                 gx->gx_cdata.gx_tx_chain[idx] = m_head;
1566
1567                 CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, gx->gx_tx_tail_idx);
1568         }
1569
1570         return (0);
1571 }
1572
1573 /*
1574  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1575  * to the mbuf data regions directly in the transmit descriptors.
1576  */
1577 static void
1578 gx_start(struct ifnet *ifp)
1579 {
1580         struct gx_softc *gx;
1581         struct mbuf *m_head;
1582         int s;
1583
1584         s = splimp();
1585
1586         gx = ifp->if_softc;
1587
1588         for (;;) {
1589                 IF_DEQUEUE(&ifp->if_snd, m_head);
1590                 if (m_head == NULL)
1591                         break;
1592
1593                 /*
1594                  * Pack the data into the transmit ring. If we
1595                  * don't have room, set the OACTIVE flag and wait
1596                  * for the NIC to drain the ring.
1597                  */
1598                 if (gx_encap(gx, m_head) != 0) {
1599                         IF_PREPEND(&ifp->if_snd, m_head);
1600                         ifp->if_flags |= IFF_OACTIVE;
1601                         break;
1602                 }
1603
1604                 /*
1605                  * If there's a BPF listener, bounce a copy of this frame
1606                  * to him.
1607                  */
1608                 if (ifp->if_bpf)
1609                         bpf_mtap(ifp, m_head);
1610
1611                 /*
1612                  * Set a timeout in case the chip goes out to lunch.
1613                  */
1614                 ifp->if_timer = 5;
1615         }
1616
1617         splx(s);
1618 }