2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
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14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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27 * THE POSSIBILITY OF SUCH DAMAGES.
29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 203683 2010-02-08 20:23:20Z rpaulo $
33 * Defintions for the Atheros Wireless LAN controller driver.
35 #ifndef _DEV_ATH_ATHVAR_H
36 #define _DEV_ATH_ATHVAR_H
38 #include <dev/netif/ath/hal/ath_hal/ah.h>
39 #include <dev/netif/ath/hal/ath_hal/ah_desc.h>
40 #include <netproto/802_11/ieee80211_radiotap.h>
41 #include <dev/netif/ath/ath/if_athioctl.h>
42 #include <dev/netif/ath/ath/if_athrate.h>
44 #define ATH_TIMEOUT 1000
47 #define ATH_RXBUF 40 /* number of RX buffers */
50 #define ATH_TXBUF 200 /* number of TX buffers */
52 #define ATH_BCBUF 4 /* number of beacon buffers */
54 #define ATH_TXDESC 10 /* number of descriptors per buffer */
55 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */
56 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */
57 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
59 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */
60 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
61 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
64 * The key cache is used for h/w cipher state and also for
65 * tracking station state such as the current tx antenna.
66 * We also setup a mapping table between key cache slot indices
67 * and station state to short-circuit node lookups on rx.
68 * Different parts have different size key caches. We handle
69 * up to ATH_KEYMAX entries (could dynamically allocate state).
71 #define ATH_KEYMAX 128 /* max key cache size we handle */
72 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
78 /* driver-specific node state */
80 struct ieee80211_node an_node; /* base class */
81 u_int8_t an_mgmtrix; /* min h/w rate index */
82 u_int8_t an_mcastrix; /* mcast h/w rate index */
83 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */
84 /* variable-length rate control state follows */
86 #define ATH_NODE(ni) ((struct ath_node *)(ni))
87 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
89 #define ATH_RSSI_LPF_LEN 10
90 #define ATH_RSSI_DUMMY_MARKER 0x127
91 #define ATH_EP_MUL(x, mul) ((x) * (mul))
92 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
93 #define ATH_LPF_RSSI(x, y, len) \
94 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
95 #define ATH_RSSI_LPF(x, y) do { \
97 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
99 #define ATH_EP_RND(x,mul) \
100 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
101 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
104 STAILQ_ENTRY(ath_buf) bf_list;
106 uint16_t bf_txflags; /* tx descriptor flags */
107 uint16_t bf_flags; /* status flags (below) */
108 struct ath_desc *bf_desc; /* virtual addr of desc */
109 struct ath_desc_status bf_status; /* tx/rx status */
110 bus_addr_t bf_daddr; /* physical addr of desc */
111 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
112 struct mbuf *bf_m; /* mbuf for buf */
113 struct ieee80211_node *bf_node; /* pointer to the node */
114 bus_size_t bf_mapsize;
115 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
116 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
118 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
120 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */
123 * DMA state for tx/rx descriptors.
127 struct ath_desc *dd_desc; /* descriptors */
128 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
129 bus_size_t dd_desc_len; /* size of dd_desc */
130 bus_dma_segment_t dd_dseg;
131 bus_dma_tag_t dd_dmat; /* bus DMA tag */
132 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
133 struct ath_buf *dd_bufptr; /* associated buffers */
137 * Data transmit queue state. One of these exists for each
138 * hardware transmit queue. Packets sent to us from above
139 * are assigned to queues based on their priority. Not all
140 * devices support a complete set of hardware transmit queues.
141 * For those devices the array sc_ac2q will map multiple
142 * priorities to fewer hardware queues (typically all to one
146 u_int axq_qnum; /* hardware q number */
147 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */
148 u_int axq_ac; /* WME AC */
150 #define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */
151 u_int axq_depth; /* queue depth (stat only) */
152 u_int axq_intrcnt; /* interrupt count */
153 u_int32_t *axq_link; /* link ptr in last TX desc */
154 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
155 struct lock axq_lock; /* lock on q and link */
156 char axq_name[12]; /* e.g. "ath0_txq4" */
159 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
160 ksnprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
161 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
162 lockinit(&(_tq)->axq_lock, (_tq)->axq_name, 0, 0); \
164 #define ATH_TXQ_LOCK_DESTROY(_tq) lockuninit(&(_tq)->axq_lock)
165 #define ATH_TXQ_LOCK(_tq) lockmgr(&(_tq)->axq_lock, LK_EXCLUSIVE)
166 #define ATH_TXQ_UNLOCK(_tq) lockmgr(&(_tq)->axq_lock, LK_RELEASE)
167 #define ATH_TXQ_LOCK_ASSERT(_tq) \
168 KKASSERT(lockstatus(&(_tq)->axq_lock, curthread) == LK_EXCLUSIVE)
170 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
171 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
172 (_tq)->axq_depth++; \
174 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
175 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
176 (_tq)->axq_depth--; \
178 /* NB: this does not do the "head empty check" that STAILQ_LAST does */
179 #define ATH_TXQ_LAST(_tq) \
180 ((struct ath_buf *)(void *) \
181 ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list)))
184 struct ieee80211vap av_vap; /* base class */
185 int av_bslot; /* beacon slot index */
186 struct ath_buf *av_bcbuf; /* beacon buffer */
187 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */
188 struct ath_txq av_mcastq; /* buffered mcast s/w queue */
190 void (*av_recv_mgmt)(struct ieee80211_node *,
191 struct mbuf *, int, int, int);
192 int (*av_newstate)(struct ieee80211vap *,
193 enum ieee80211_state, int);
194 void (*av_bmiss)(struct ieee80211vap *);
196 #define ATH_VAP(vap) ((struct ath_vap *)(vap))
202 struct arpcom arpcom;
203 struct ifnet *sc_ifp; /* interface common */
204 struct ath_stats sc_stats; /* interface statistics */
206 int sc_nvaps; /* # vaps */
207 int sc_nstavaps; /* # station vaps */
208 int sc_nmeshvaps; /* # mbss vaps */
209 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN];
210 u_int8_t sc_nbssid0; /* # vap's using base mac */
211 uint32_t sc_bssidmask; /* bssid mask */
213 void (*sc_node_free)(struct ieee80211_node *);
215 HAL_BUS_TAG sc_st; /* bus space tag */
216 HAL_BUS_HANDLE sc_sh; /* bus space handle */
217 bus_dma_tag_t sc_dmat; /* bus DMA tag */
218 struct lock sc_lock; /* master lock (recursive) */
219 struct taskqueue *sc_tq; /* private task queue */
220 struct ath_hal *sc_ah; /* Atheros HAL */
221 struct ath_ratectrl *sc_rc; /* tx rate control support */
222 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */
223 void (*sc_setdefantenna)(struct ath_softc *, u_int);
224 unsigned int sc_invalid : 1,/* disable hardware accesses */
225 sc_mrretry : 1,/* multi-rate retry support */
226 sc_softled : 1,/* enable LED gpio status */
227 sc_splitmic : 1,/* split TKIP MIC keys */
228 sc_needmib : 1,/* enable MIB stats intr */
229 sc_diversity: 1,/* enable rx diversity */
230 sc_hasveol : 1,/* tx VEOL support */
231 sc_ledstate : 1,/* LED on/off state */
232 sc_blinking : 1,/* LED blink operation active */
233 sc_mcastkey : 1,/* mcast key cache search */
234 sc_scanning : 1,/* scanning active */
235 sc_syncbeacon:1,/* sync/resync beacon timers */
236 sc_hasclrkey: 1,/* CLR key supported */
237 sc_xchanmode: 1,/* extended channel mode */
238 sc_outdoor : 1,/* outdoor operation */
239 sc_dturbo : 1,/* dynamic turbo in use */
240 sc_hasbmask : 1,/* bssid mask support */
241 sc_hasbmatch: 1,/* bssid match disable support*/
242 sc_hastsfadd: 1,/* tsf adjust support */
243 sc_beacons : 1,/* beacons running */
244 sc_swbmiss : 1,/* sta mode using sw bmiss */
245 sc_stagbeacons:1,/* use staggered beacons */
246 sc_wmetkipmic:1,/* can do WME+TKIP MIC */
247 sc_resume_up: 1,/* on resume, start all vaps */
248 sc_tdma : 1,/* TDMA in use */
249 sc_setcca : 1,/* set/clr CCA with TDMA */
250 sc_resetcal : 1;/* reset cal state next trip */
251 uint32_t sc_eerd; /* regdomain from EEPROM */
252 uint32_t sc_eecc; /* country code from EEPROM */
254 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
255 const HAL_RATE_TABLE *sc_currates; /* current rate table */
256 enum ieee80211_phymode sc_curmode; /* current phy mode */
257 HAL_OPMODE sc_opmode; /* current operating mode */
258 u_int16_t sc_curtxpow; /* current tx power limit */
259 u_int16_t sc_curaid; /* current association id */
260 struct ieee80211_channel *sc_curchan; /* current installed channel */
261 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
262 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
264 u_int8_t ieeerate; /* IEEE rate */
265 u_int8_t rxflags; /* radiotap rx flags */
266 u_int8_t txflags; /* radiotap tx flags */
267 u_int16_t ledon; /* softled on time */
268 u_int16_t ledoff; /* softled off time */
269 } sc_hwmap[32]; /* h/w rate ix mappings */
270 u_int8_t sc_protrix; /* protection rate index */
271 u_int8_t sc_lastdatarix; /* last data frame rate index */
272 u_int sc_mcastrate; /* ieee rate for mcastrateix */
273 u_int sc_fftxqmin; /* min frames before staging */
274 u_int sc_fftxqmax; /* max frames before drop */
275 u_int sc_txantenna; /* tx antenna (fixed or auto) */
276 HAL_INT sc_imask; /* interrupt mask copy */
277 u_int sc_keymax; /* size of key cache */
278 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
280 u_int sc_ledpin; /* GPIO pin for driving LED */
281 u_int sc_ledon; /* pin setting for LED on */
282 u_int sc_ledidle; /* idle polling interval */
283 int sc_ledevent; /* time of last LED event */
284 u_int8_t sc_txrix; /* current tx rate for LED */
285 u_int16_t sc_ledoff; /* off time for current blink */
286 struct callout sc_ledtimer; /* led off timer */
288 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */
289 u_int sc_rfsilentpol; /* pin setting for rfkill on */
291 struct ath_descdma sc_rxdma; /* RX descriptors */
292 ath_bufhead sc_rxbuf; /* receive buffer */
293 struct mbuf *sc_rxpending; /* pending receive data */
294 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
295 struct task sc_rxtask; /* rx int processing */
296 u_int8_t sc_defant; /* current default antenna */
297 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
298 u_int64_t sc_lastrx; /* tsf at last rx'd frame */
299 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */
300 struct ath_rx_radiotap_header sc_rx_th;
302 u_int sc_monpass; /* frames to pass in mon.mode */
304 struct ath_descdma sc_txdma; /* TX descriptors */
305 ath_bufhead sc_txbuf; /* transmit buffer */
306 struct lock sc_txbuflock; /* txbuf lock */
307 char sc_txname[12]; /* e.g. "ath0_buf" */
308 u_int sc_txqsetup; /* h/w queues setup */
309 u_int sc_txintrperiod;/* tx interrupt batching */
310 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
311 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
312 struct task sc_txtask; /* tx int processing */
313 int sc_wd_timer; /* count down for wd timer */
314 struct callout sc_wd_ch; /* tx watchdog timer */
315 struct ath_tx_radiotap_header sc_tx_th;
318 struct ath_descdma sc_bdma; /* beacon descriptors */
319 ath_bufhead sc_bbuf; /* beacon buffers */
320 u_int sc_bhalq; /* HAL q for outgoing beacons */
321 u_int sc_bmisscount; /* missed beacon transmits */
322 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
323 struct ath_txq *sc_cabq; /* tx q for cab frames */
324 struct task sc_bmisstask; /* bmiss int processing */
325 struct task sc_bstucktask; /* stuck beacon processing */
327 OK, /* no change needed */
328 UPDATE, /* update pending */
329 COMMIT /* beacon sent, commit change */
330 } sc_updateslot; /* slot time update fsm */
331 int sc_slotupdate; /* slot to advance fsm */
332 struct ieee80211vap *sc_bslot[ATH_BCBUF];
333 int sc_nbcnvaps; /* # vaps with beacons */
335 struct callout sc_cal_ch; /* callout handle for cals */
336 int sc_lastlongcal; /* last long cal completed */
337 int sc_lastcalreset;/* last cal reset done */
338 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
339 u_int sc_tdmadbaprep; /* TDMA DBA prep time */
340 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */
341 u_int sc_tdmaswba; /* TDMA SWBA counter */
342 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */
343 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */
344 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */
345 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */
346 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */
347 struct sysctl_ctx_list sc_sysctl_ctx;
350 #define ATH_LOCK_INIT(_sc) \
351 lockinit(&(_sc)->sc_lock, \
352 __DECONST(char *, device_get_nameunit((_sc)->sc_dev)), \
354 #define ATH_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_lock)
355 #define ATH_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE)
356 #define ATH_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE)
357 #define ATH_LOCK_ASSERT(_sc) \
358 KKASSERT(lockstatus(&(_sc)->sc_lock, curthread) == LK_EXCLUSIVE)
360 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
362 #define ATH_TXBUF_LOCK_INIT(_sc) do { \
363 ksnprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
364 device_get_nameunit((_sc)->sc_dev)); \
365 lockinit(&(_sc)->sc_txbuflock, (_sc)->sc_txname, 0, 0); \
367 #define ATH_TXBUF_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_txbuflock)
368 #define ATH_TXBUF_LOCK(_sc) \
369 lockmgr(&(_sc)->sc_txbuflock, LK_EXCLUSIVE)
370 #define ATH_TXBUF_UNLOCK(_sc) \
371 lockmgr(&(_sc)->sc_txbuflock, LK_RELEASE)
372 #define ATH_TXBUF_LOCK_ASSERT(_sc) \
373 KKASSERT(lockstatus(&(_sc)->sc_txbuflock, curthread) == LK_EXCLUSIVE)
375 int ath_attach(u_int16_t, struct ath_softc *);
376 int ath_detach(struct ath_softc *);
377 void ath_resume(struct ath_softc *);
378 void ath_suspend(struct ath_softc *);
379 void ath_shutdown(struct ath_softc *);
380 void ath_intr(void *);
383 * HAL definitions to comply with local coding convention.
385 #define ath_hal_detach(_ah) \
386 ((*(_ah)->ah_detach)((_ah)))
387 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
388 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
389 #define ath_hal_macversion(_ah) \
390 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
391 #define ath_hal_getratetable(_ah, _mode) \
392 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
393 #define ath_hal_getmac(_ah, _mac) \
394 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
395 #define ath_hal_setmac(_ah, _mac) \
396 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
397 #define ath_hal_getbssidmask(_ah, _mask) \
398 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
399 #define ath_hal_setbssidmask(_ah, _mask) \
400 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
401 #define ath_hal_intrset(_ah, _mask) \
402 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
403 #define ath_hal_intrget(_ah) \
404 ((*(_ah)->ah_getInterrupts)((_ah)))
405 #define ath_hal_intrpend(_ah) \
406 ((*(_ah)->ah_isInterruptPending)((_ah)))
407 #define ath_hal_getisr(_ah, _pmask) \
408 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
409 #define ath_hal_updatetxtriglevel(_ah, _inc) \
410 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
411 #define ath_hal_setpower(_ah, _mode) \
412 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
413 #define ath_hal_keycachesize(_ah) \
414 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
415 #define ath_hal_keyreset(_ah, _ix) \
416 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
417 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
418 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
419 #define ath_hal_keyisvalid(_ah, _ix) \
420 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
421 #define ath_hal_keysetmac(_ah, _ix, _mac) \
422 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
423 #define ath_hal_getrxfilter(_ah) \
424 ((*(_ah)->ah_getRxFilter)((_ah)))
425 #define ath_hal_setrxfilter(_ah, _filter) \
426 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
427 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
428 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
429 #define ath_hal_waitforbeacon(_ah, _bf) \
430 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
431 #define ath_hal_putrxbuf(_ah, _bufaddr) \
432 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
433 /* NB: common across all chips */
434 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */
435 #define ath_hal_gettsf32(_ah) \
436 OS_REG_READ(_ah, AR_TSF_L32)
437 #define ath_hal_gettsf64(_ah) \
438 ((*(_ah)->ah_getTsf64)((_ah)))
439 #define ath_hal_resettsf(_ah) \
440 ((*(_ah)->ah_resetTsf)((_ah)))
441 #define ath_hal_rxena(_ah) \
442 ((*(_ah)->ah_enableReceive)((_ah)))
443 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
444 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
445 #define ath_hal_gettxbuf(_ah, _q) \
446 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
447 #define ath_hal_numtxpending(_ah, _q) \
448 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
449 #define ath_hal_getrxbuf(_ah) \
450 ((*(_ah)->ah_getRxDP)((_ah)))
451 #define ath_hal_txstart(_ah, _q) \
452 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
453 #define ath_hal_setchannel(_ah, _chan) \
454 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
455 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
456 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
457 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
458 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
459 #define ath_hal_calreset(_ah, _chan) \
460 ((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
461 #define ath_hal_setledstate(_ah, _state) \
462 ((*(_ah)->ah_setLedState)((_ah), (_state)))
463 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
464 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
465 #define ath_hal_beaconreset(_ah) \
466 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
467 #define ath_hal_beaconsettimers(_ah, _bt) \
468 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
469 #define ath_hal_beacontimers(_ah, _bs) \
470 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
471 #define ath_hal_setassocid(_ah, _bss, _associd) \
472 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
473 #define ath_hal_phydisable(_ah) \
474 ((*(_ah)->ah_phyDisable)((_ah)))
475 #define ath_hal_setopmode(_ah) \
476 ((*(_ah)->ah_setPCUConfig)((_ah)))
477 #define ath_hal_stoptxdma(_ah, _qnum) \
478 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
479 #define ath_hal_stoppcurecv(_ah) \
480 ((*(_ah)->ah_stopPcuReceive)((_ah)))
481 #define ath_hal_startpcurecv(_ah) \
482 ((*(_ah)->ah_startPcuReceive)((_ah)))
483 #define ath_hal_stopdmarecv(_ah) \
484 ((*(_ah)->ah_stopDmaReceive)((_ah)))
485 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
486 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
487 (_indata), (_insize), (_outdata), (_outsize)))
488 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \
489 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
490 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
491 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
492 #define ath_hal_resettxqueue(_ah, _q) \
493 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
494 #define ath_hal_releasetxqueue(_ah, _q) \
495 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
496 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
497 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
498 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
499 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
500 /* NB: common across all chips */
501 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */
502 #define ath_hal_txqenabled(_ah, _qnum) \
503 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
504 #define ath_hal_getrfgain(_ah) \
505 ((*(_ah)->ah_getRfGain)((_ah)))
506 #define ath_hal_getdefantenna(_ah) \
507 ((*(_ah)->ah_getDefAntenna)((_ah)))
508 #define ath_hal_setdefantenna(_ah, _ant) \
509 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
510 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
511 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
512 #define ath_hal_mibevent(_ah, _stats) \
513 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
514 #define ath_hal_setslottime(_ah, _us) \
515 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
516 #define ath_hal_getslottime(_ah) \
517 ((*(_ah)->ah_getSlotTime)((_ah)))
518 #define ath_hal_setacktimeout(_ah, _us) \
519 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
520 #define ath_hal_getacktimeout(_ah) \
521 ((*(_ah)->ah_getAckTimeout)((_ah)))
522 #define ath_hal_setctstimeout(_ah, _us) \
523 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
524 #define ath_hal_getctstimeout(_ah) \
525 ((*(_ah)->ah_getCTSTimeout)((_ah)))
526 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
527 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
528 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
529 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
530 #define ath_hal_ciphersupported(_ah, _cipher) \
531 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
532 #define ath_hal_getregdomain(_ah, _prd) \
533 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
534 #define ath_hal_setregdomain(_ah, _rd) \
535 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
536 #define ath_hal_getcountrycode(_ah, _pcc) \
537 (*(_pcc) = (_ah)->ah_countryCode)
538 #define ath_hal_gettkipmic(_ah) \
539 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
540 #define ath_hal_settkipmic(_ah, _v) \
541 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
542 #define ath_hal_hastkipsplit(_ah) \
543 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
544 #define ath_hal_gettkipsplit(_ah) \
545 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
546 #define ath_hal_settkipsplit(_ah, _v) \
547 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
548 #define ath_hal_haswmetkipmic(_ah) \
549 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
550 #define ath_hal_hwphycounters(_ah) \
551 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
552 #define ath_hal_hasdiversity(_ah) \
553 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
554 #define ath_hal_getdiversity(_ah) \
555 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
556 #define ath_hal_setdiversity(_ah, _v) \
557 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
558 #define ath_hal_getantennaswitch(_ah) \
559 ((*(_ah)->ah_getAntennaSwitch)((_ah)))
560 #define ath_hal_setantennaswitch(_ah, _v) \
561 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
562 #define ath_hal_getdiag(_ah, _pv) \
563 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
564 #define ath_hal_setdiag(_ah, _v) \
565 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
566 #define ath_hal_getnumtxqueues(_ah, _pv) \
567 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
568 #define ath_hal_hasveol(_ah) \
569 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
570 #define ath_hal_hastxpowlimit(_ah) \
571 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
572 #define ath_hal_settxpowlimit(_ah, _pow) \
573 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
574 #define ath_hal_gettxpowlimit(_ah, _ppow) \
575 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
576 #define ath_hal_getmaxtxpow(_ah, _ppow) \
577 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
578 #define ath_hal_gettpscale(_ah, _scale) \
579 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
580 #define ath_hal_settpscale(_ah, _v) \
581 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
582 #define ath_hal_hastpc(_ah) \
583 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
584 #define ath_hal_gettpc(_ah) \
585 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
586 #define ath_hal_settpc(_ah, _v) \
587 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
588 #define ath_hal_hasbursting(_ah) \
589 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
590 #define ath_hal_setmcastkeysearch(_ah, _v) \
591 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
592 #define ath_hal_hasmcastkeysearch(_ah) \
593 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
594 #define ath_hal_getmcastkeysearch(_ah) \
595 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
596 #define ath_hal_hasfastframes(_ah) \
597 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
598 #define ath_hal_hasbssidmask(_ah) \
599 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
600 #define ath_hal_hasbssidmatch(_ah) \
601 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK)
602 #define ath_hal_hastsfadjust(_ah) \
603 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
604 #define ath_hal_gettsfadjust(_ah) \
605 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
606 #define ath_hal_settsfadjust(_ah, _onoff) \
607 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
608 #define ath_hal_hasrfsilent(_ah) \
609 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
610 #define ath_hal_getrfkill(_ah) \
611 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
612 #define ath_hal_setrfkill(_ah, _onoff) \
613 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
614 #define ath_hal_getrfsilent(_ah, _prfsilent) \
615 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
616 #define ath_hal_setrfsilent(_ah, _rfsilent) \
617 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
618 #define ath_hal_gettpack(_ah, _ptpack) \
619 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
620 #define ath_hal_settpack(_ah, _tpack) \
621 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
622 #define ath_hal_gettpcts(_ah, _ptpcts) \
623 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
624 #define ath_hal_settpcts(_ah, _tpcts) \
625 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
626 #define ath_hal_hasintmit(_ah) \
627 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 0, NULL) == HAL_OK)
628 #define ath_hal_getintmit(_ah) \
629 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 1, NULL) == HAL_OK)
630 #define ath_hal_setintmit(_ah, _v) \
631 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, 1, _v, NULL)
632 #define ath_hal_getchannoise(_ah, _c) \
633 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
635 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
636 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
637 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
638 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
639 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
640 _txr0, _txtr0, _keyix, _ant, _flags, \
641 _rtsrate, _rtsdura) \
642 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
643 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
644 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
645 #define ath_hal_setupxtxdesc(_ah, _ds, \
646 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
647 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
648 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
649 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
650 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
651 #define ath_hal_txprocdesc(_ah, _ds, _ts) \
652 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
653 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
654 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
656 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
657 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
658 #define ath_hal_gpioset(_ah, _gpio, _b) \
659 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
660 #define ath_hal_gpioget(_ah, _gpio) \
661 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
662 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \
663 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
665 #define ath_hal_radar_wait(_ah, _chan) \
666 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
668 #endif /* _DEV_ATH_ATHVAR_H */