2 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Takuya SHIOZAKI <AoiMoe@imou.to> .
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: head/sys/dev/sound/pci/cmireg.h 139749 2005-01-06 01:43:34Z imp $
32 /* C-Media CMI8x38 Audio Chip Support */
34 #ifndef _DEV_PCI_CMPCIREG_H_
35 #define _DEV_PCI_CMPCIREG_H_ (1)
38 * PCI Configuration Registers
41 #define CMPCI_PCI_IOBASEREG (PCI_MAPREG_START)
47 #define CMPCI_REG_FUNC_0 0x00
48 # define CMPCI_REG_CH0_DIR 0x00000001
49 # define CMPCI_REG_CH1_DIR 0x00000002
50 # define CMPCI_REG_CH0_PAUSE 0x00000004
51 # define CMPCI_REG_CH1_PAUSE 0x00000008
52 # define CMPCI_REG_CH0_ENABLE 0x00010000
53 # define CMPCI_REG_CH1_ENABLE 0x00020000
54 # define CMPCI_REG_CH0_RESET 0x00040000
55 # define CMPCI_REG_CH1_RESET 0x00080000
57 #define CMPCI_REG_FUNC_1 0x04
58 # define CMPCI_REG_JOY_ENABLE 0x00000002
59 # define CMPCI_REG_UART_ENABLE 0x00000004
60 # define CMPCI_REG_LEGACY_ENABLE 0x00000008
61 # define CMPCI_REG_BREQ 0x00000010
62 # define CMPCI_REG_MCBINTR_ENABLE 0x00000020
63 # define CMPCI_REG_SPDIFOUT_DAC 0x00000040
64 # define CMPCI_REG_SPDIF_LOOP 0x00000080
65 # define CMPCI_REG_SPDIF0_ENABLE 0x00000100
66 # define CMPCI_REG_SPDIF1_ENABLE 0x00000200
67 # define CMPCI_REG_DAC_FS_SHIFT 10
68 # define CMPCI_REG_DAC_FS_MASK 0x00000007
69 # define CMPCI_REG_ADC_FS_SHIFT 13
70 # define CMPCI_REG_ADC_FS_MASK 0x00000007
72 #define CMPCI_REG_CHANNEL_FORMAT 0x08
73 # define CMPCI_REG_CH0_FORMAT_SHIFT 0
74 # define CMPCI_REG_CH0_FORMAT_MASK 0x00000003
75 # define CMPCI_REG_CH1_FORMAT_SHIFT 2
76 # define CMPCI_REG_CH1_FORMAT_MASK 0x00000003
77 # define CMPCI_REG_FORMAT_MONO 0x00000000
78 # define CMPCI_REG_FORMAT_STEREO 0x00000001
79 # define CMPCI_REG_FORMAT_8BIT 0x00000000
80 # define CMPCI_REG_FORMAT_16BIT 0x00000002
82 #define CMPCI_REG_INTR_CTRL 0x0c
83 # define CMPCI_REG_CH0_INTR_ENABLE 0x00010000
84 # define CMPCI_REG_CH1_INTR_ENABLE 0x00020000
85 # define CMPCI_REG_TDMA_INTR_ENABLE 0x00040000
87 #define CMPCI_REG_INTR_STATUS 0x10
88 # define CMPCI_REG_CH0_INTR 0x00000001
89 # define CMPCI_REG_CH1_INTR 0x00000002
90 # define CMPCI_REG_CH0_BUSY 0x00000004
91 # define CMPCI_REG_CH1_BUSY 0x00000008
92 # define CMPCI_REG_LEGACY_STEREO 0x00000010
93 # define CMPCI_REG_LEGACY_HDMA 0x00000020
94 # define CMPCI_REG_DMASTAT 0x00000040
95 # define CMPCI_REG_XDO46 0x00000080
96 # define CMPCI_REG_HTDMA_INTR 0x00004000
97 # define CMPCI_REG_LTDMA_INTR 0x00008000
98 # define CMPCI_REG_UART_INTR 0x00010000
99 # define CMPCI_REG_MCB_INTR 0x04000000
100 # define CMPCI_REG_VCO 0x08000000
101 # define CMPCI_REG_ANY_INTR 0x80000000
103 #define CMPCI_REG_LEGACY_CTRL 0x14
104 # define CMPCI_REG_LEGACY_SPDIF_ENABLE 0x00200000
105 # define CMPCI_REG_SPDIF_COPYRIGHT 0x00400000
106 # define CMPCI_REG_XSPDIF_ENABLE 0x00800000
107 # define CMPCI_REG_FMSEL_SHIFT 24
108 # define CMPCI_REG_FMSEL_MASK 0x00000003
109 # define CMPCI_REG_VSBSEL_SHIFT 26
110 # define CMPCI_REG_VSBSEL_MASK 0x00000003
111 # define CMPCI_REG_VMPUSEL_SHIFT 29
112 # define CMPCI_REG_VMPUSEL_MASK 0x00000003
114 #define CMPCI_REG_MISC 0x18
115 # define CMPCI_REG_POWER_DOWN 0x80000000
116 # define CMPCI_REG_BUS_AND_DSP_RESET 0x40000000
117 # define CMPCI_REG_N4SPK3D 0x04000000
118 # define CMPCI_REG_W_SPDIF_48L 0x01000000
119 # define CMPCI_REG_XCHGDAC 0x00400000
120 # define CMPCI_REG_FM_ENABLE 0x00080000
121 # define CMPCI_REG_SPDIF_48K 0x00008000
123 #define CMPCI_REG_SBDATA 0x22
124 #define CMPCI_REG_SBADDR 0x23
125 # define CMPCI_SB16_MIXER_RESET 0x00
126 # define CMPCI_SB16_MIXER_MASTER_L 0x30
127 # define CMPCI_SB16_MIXER_MASTER_R 0x31
128 # define CMPCI_SB16_MIXER_VOICE_L 0x32
129 # define CMPCI_SB16_MIXER_VOICE_R 0x33
130 # define CMPCI_SB16_MIXER_FM_L 0x34
131 # define CMPCI_SB16_MIXER_FM_R 0x35
132 # define CMPCI_SB16_MIXER_CDDA_L 0x36
133 # define CMPCI_SB16_MIXER_CDDA_R 0x37
134 # define CMPCI_SB16_MIXER_LINE_L 0x38
135 # define CMPCI_SB16_MIXER_LINE_R 0x39
136 # define CMPCI_SB16_MIXER_MIC 0x3A
137 # define CMPCI_SB16_MIXER_SPEAKER 0x3B
138 # define CMPCI_SB16_MIXER_OUTMIX 0x3C
139 # define CMPCI_SB16_SW_MIC 0x01
140 # define CMPCI_SB16_SW_CD_R 0x02
141 # define CMPCI_SB16_SW_CD_L 0x04
142 # define CMPCI_SB16_SW_CD (CMPCI_SB16_SW_CD_L|CMPCI_SB16_SW_CD_R)
143 # define CMPCI_SB16_SW_LINE_R 0x08
144 # define CMPCI_SB16_SW_LINE_L 0x10
145 # define CMPCI_SB16_SW_LINE (CMPCI_SB16_SW_LINE_L|CMPCI_SB16_SW_LINE_R)
146 # define CMPCI_SB16_SW_FM_R 0x20
147 # define CMPCI_SB16_SW_FM_L 0x40
148 # define CMPCI_SB16_SW_FM (CMPCI_SB16_SW_FM_L|CMPCI_SB16_SW_FM_R)
149 # define CMPCI_SB16_MIXER_ADCMIX_L 0x3D
150 # define CMPCI_SB16_MIXER_ADCMIX_R 0x3E
151 # define CMPCI_SB16_MIXER_FM_SRC_R 0x20
152 # define CMPCI_SB16_MIXER_LINE_SRC_R 0x08
153 # define CMPCI_SB16_MIXER_CD_SRC_R 0x02
154 # define CMPCI_SB16_MIXER_MIC_SRC 0x01
155 # define CMPCI_SB16_MIXER_SRC_R_TO_L(v) ((v) << 1)
157 # define CMPCI_SB16_MIXER_INGAIN_L 0x3F
158 # define CMPCI_SB16_MIXER_INGAIN_R 0x40
159 # define CMPCI_SB16_MIXER_OUTGAIN_L 0x41
160 # define CMPCI_SB16_MIXER_OUTGAIN_R 0x42
161 # define CMPCI_SB16_MIXER_AGC 0x43
162 # define CMPCI_SB16_MIXER_TREBLE_L 0x44
163 # define CMPCI_SB16_MIXER_TREBLE_R 0x45
164 # define CMPCI_SB16_MIXER_BASS_L 0x46
165 # define CMPCI_SB16_MIXER_BASS_R 0x47
166 # define CMPCI_SB16_MIXER_L_TO_R(addr) ((addr)+1)
168 # define CMPCI_ADJUST_MIC_GAIN(sc, x) cmpci_adjust((x), 0xf8)
169 # define CMPCI_ADJUST_GAIN(sc, x) cmpci_adjust((x), 0xf8)
170 # define CMPCI_ADJUST_2_GAIN(sc, x) cmpci_adjust((x), 0xc0)
172 #define CMPCI_REG_MIXER1 0x24
173 # define CMPCI_SPK4 0x20
174 # define CMPCI_REAR2FRONT 0x10
175 # define CMPCI_X3DEN 0x02
177 #define CMPCI_REG_MPU_BASE 0x40
178 #define CMPCI_REG_MPU_SIZE 0x10
179 #define CMPCI_REG_FM_BASE 0x50
180 #define CMPCI_REG_FM_SIZE 0x10
182 #define CMPCI_REG_AUX_MIC 0x25
183 # define CMPCI_AUX_SELECT_R 0x80
184 # define CMPCI_AUX_SELECT_L 0x40
185 # define CMPCI_AUX_MUTE_R 0x20
186 # define CMPCI_AUX_MUTE_L 0x10
187 # define CMPCI_VAD_MIC 0x0e
188 # define CMPCI_MIC_QUIET 0x01
190 #define CMPCI_REG_DMA0_BASE 0x80
191 #define CMPCI_REG_DMA0_BYTES 0x84
192 #define CMPCI_REG_DMA0_SAMPLES 0x86
193 #define CMPCI_REG_DMA1_BASE 0x88
194 #define CMPCI_REG_DMA1_BYTES 0x8C
195 #define CMPCI_REG_DMA1_SAMPLES 0x8E
198 #define CMPCI_REG_RATE_5512 0
199 #define CMPCI_REG_RATE_11025 1
200 #define CMPCI_REG_RATE_22050 2
201 #define CMPCI_REG_RATE_44100 3
202 #define CMPCI_REG_RATE_8000 4
203 #define CMPCI_REG_RATE_16000 5
204 #define CMPCI_REG_RATE_32000 6
205 #define CMPCI_REG_RATE_48000 7
206 #define CMPCI_REG_NUMRATE 8
208 #endif /* _DEV_PCI_CMPCIREG_H_ */