2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.24 2005/05/31 12:29:05 joerg Exp $
37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
38 * Manuals, sample driver and firmware source kits are available
39 * from http://www.alteon.com/support/openkits.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Electrical Engineering Department
43 * Columbia University, New York City
47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
51 * filtering and jumbo (9014 byte) frames. The hardware is largely
52 * controlled by firmware, which must be loaded into the NIC during
55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
56 * revision, which supports new features such as extended commands,
57 * extended jumbo receive ring desciptors and a mini receive ring.
59 * Alteon Networks is to be commended for releasing such a vast amount
60 * of development material for the Tigon NIC without requiring an NDA
61 * (although they really should have done it a long time ago). With
62 * any luck, the other vendors will finally wise up and follow Alteon's
65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
66 * this driver by #including it as a C header file. This bloats the
67 * driver somewhat, but it's the easiest method considering that the
68 * driver code and firmware code need to be kept in sync. The source
69 * for the firmware is not provided with the FreeBSD distribution since
70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
72 * The following people deserve special thanks:
73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
75 * - Raymond Lee of Netgear, for providing a pair of Netgear
76 * GA620 Tigon 2 boards for testing
77 * - Ulf Zimmermann, for bringing the GA260 to my attention and
78 * convincing me to write this driver.
79 * - Andrew Gallatin for providing FreeBSD/Alpha support.
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/sockio.h>
86 #include <sys/malloc.h>
87 #include <sys/kernel.h>
88 #include <sys/socket.h>
89 #include <sys/queue.h>
92 #include <net/ifq_var.h>
93 #include <net/if_arp.h>
94 #include <net/ethernet.h>
95 #include <net/if_dl.h>
96 #include <net/if_media.h>
97 #include <net/if_types.h>
98 #include <net/vlan/if_vlan_var.h>
102 #include <netinet/in_systm.h>
103 #include <netinet/in.h>
104 #include <netinet/ip.h>
106 #include <vm/vm.h> /* for vtophys */
107 #include <vm/pmap.h> /* for vtophys */
108 #include <machine/bus.h>
109 #include <machine/resource.h>
111 #include <sys/rman.h>
113 #include <bus/pci/pcireg.h>
114 #include <bus/pci/pcivar.h>
116 #include "if_tireg.h"
121 * Temporarily disable the checksum offload support for now.
122 * Tests with ftp.freesoftware.com show that after about 12 hours,
123 * the firmware will begin calculating completely bogus TX checksums
124 * and refuse to stop until the interface is reset. Unfortunately,
125 * there isn't enough time to fully debug this before the 4.1
126 * release, so this will need to stay off for now.
129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
131 #define TI_CSUM_FEATURES 0
135 * Various supported device vendors/types and their names.
138 static struct ti_type ti_devs[] = {
139 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
140 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
141 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
142 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
143 { TC_VENDORID, TC_DEVICEID_3C985,
144 "3Com 3c985-SX Gigabit Ethernet" },
145 { NG_VENDORID, NG_DEVICEID_GA620,
146 "Netgear GA620 1000baseSX Gigabit Ethernet" },
147 { NG_VENDORID, NG_DEVICEID_GA620T,
148 "Netgear GA620 1000baseT Gigabit Ethernet" },
149 { SGI_VENDORID, SGI_DEVICEID_TIGON,
150 "Silicon Graphics Gigabit Ethernet" },
151 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
152 "Farallon PN9000SX Gigabit Ethernet" },
156 static int ti_probe(device_t);
157 static int ti_attach(device_t);
158 static int ti_detach(device_t);
159 static void ti_txeof(struct ti_softc *);
160 static void ti_rxeof(struct ti_softc *);
162 static void ti_stats_update(struct ti_softc *);
163 static int ti_encap(struct ti_softc *, struct mbuf *, uint32_t *);
165 static void ti_intr(void *);
166 static void ti_start(struct ifnet *);
167 static int ti_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
168 static void ti_init(void *);
169 static void ti_init2(struct ti_softc *);
170 static void ti_stop(struct ti_softc *);
171 static void ti_watchdog(struct ifnet *);
172 static void ti_shutdown(device_t);
173 static int ti_ifmedia_upd(struct ifnet *);
174 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
176 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
177 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
178 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
180 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
181 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
182 static void ti_setmulti(struct ti_softc *);
184 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t);
185 static void ti_loadfw(struct ti_softc *);
186 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
187 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *,
189 static void ti_handle_events(struct ti_softc *);
190 static int ti_alloc_jumbo_mem(struct ti_softc *);
191 static struct ti_jslot *
192 ti_jalloc(struct ti_softc *);
193 static void ti_jfree(void *);
194 static void ti_jref(void *);
195 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
196 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
197 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
198 static int ti_init_rx_ring_std(struct ti_softc *);
199 static void ti_free_rx_ring_std(struct ti_softc *);
200 static int ti_init_rx_ring_jumbo(struct ti_softc *);
201 static void ti_free_rx_ring_jumbo(struct ti_softc *);
202 static int ti_init_rx_ring_mini(struct ti_softc *);
203 static void ti_free_rx_ring_mini(struct ti_softc *);
204 static void ti_free_tx_ring(struct ti_softc *);
205 static int ti_init_tx_ring(struct ti_softc *);
207 static int ti_64bitslot_war(struct ti_softc *);
208 static int ti_chipinit(struct ti_softc *);
209 static int ti_gibinit(struct ti_softc *);
211 static device_method_t ti_methods[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe, ti_probe),
214 DEVMETHOD(device_attach, ti_attach),
215 DEVMETHOD(device_detach, ti_detach),
216 DEVMETHOD(device_shutdown, ti_shutdown),
221 static DEFINE_CLASS_0(ti, ti_driver, ti_methods, sizeof(struct ti_softc));
222 static devclass_t ti_devclass;
224 DECLARE_DUMMY_MODULE(if_ti);
225 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
228 * Send an instruction or address to the EEPROM, check for ACK.
231 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
236 * Make sure we're in TX mode.
238 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
241 * Feed in each bit and stobe the clock.
243 for (i = 0x80; i; i >>= 1) {
245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
249 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
251 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
257 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
262 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
263 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
264 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
270 * Read a byte of data stored in the EEPROM at address 'addr.'
271 * We have to send two address bytes since the EEPROM can hold
272 * more than 256 bytes of data.
275 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
283 * Send write control code to EEPROM.
285 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
286 printf("ti%d: failed to send write command, status: %x\n",
287 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
292 * Send first byte of address of byte we want to read.
294 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
295 printf("ti%d: failed to send address, status: %x\n",
296 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
300 * Send second byte address of byte we want to read.
302 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
303 printf("ti%d: failed to send address, status: %x\n",
304 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
311 * Send read control code to EEPROM.
313 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
314 printf("ti%d: failed to send read command, status: %x\n",
315 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
320 * Start reading bits from EEPROM.
322 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
323 for (i = 0x80; i; i >>= 1) {
324 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
326 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
335 * No ACK generated for read, so just return byte.
344 * Read a sequence of bytes from the EEPROM.
347 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
352 for (i = 0; i < cnt; i++) {
353 err = ti_eeprom_getbyte(sc, off + i, &byte);
363 * NIC memory access function. Can be used to either clear a section
364 * of NIC local memory or (if buf is non-NULL) copy data into it.
367 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, caddr_t buf)
369 int cnt, segptr, segsize;
370 caddr_t ti_winbase, ptr;
374 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
381 segsize = TI_WINLEN - (segptr % TI_WINLEN);
382 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
384 bzero((char *)ti_winbase + (segptr &
385 (TI_WINLEN - 1)), segsize);
387 bcopy((char *)ptr, (char *)ti_winbase +
388 (segptr & (TI_WINLEN - 1)), segsize);
397 * Load firmware image into the NIC. Check that the firmware revision
398 * is acceptable and see if we want the firmware for the Tigon 1 or
402 ti_loadfw(struct ti_softc *sc)
404 switch(sc->ti_hwrev) {
406 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
407 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
408 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
409 printf("ti%d: firmware revision mismatch; want "
410 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
411 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
412 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
413 tigonFwReleaseMinor, tigonFwReleaseFix);
416 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
417 (caddr_t)tigonFwText);
418 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
419 (caddr_t)tigonFwData);
420 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
421 (caddr_t)tigonFwRodata);
422 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
423 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
424 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
426 case TI_HWREV_TIGON_II:
427 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
428 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
429 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
430 printf("ti%d: firmware revision mismatch; want "
431 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
432 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
433 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
434 tigon2FwReleaseMinor, tigon2FwReleaseFix);
437 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
438 (caddr_t)tigon2FwText);
439 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
440 (caddr_t)tigon2FwData);
441 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
442 (caddr_t)tigon2FwRodata);
443 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
444 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
445 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
448 printf("ti%d: can't load firmware: unknown hardware rev\n",
455 * Send the NIC a command via the command ring.
458 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
462 if (sc->ti_rdata->ti_cmd_ring == NULL)
465 index = sc->ti_cmd_saved_prodidx;
466 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
467 TI_INC(index, TI_CMD_RING_CNT);
468 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
469 sc->ti_cmd_saved_prodidx = index;
473 * Send the NIC an extended command. The 'len' parameter specifies the
474 * number of command slots to include after the initial command.
477 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
482 if (sc->ti_rdata->ti_cmd_ring == NULL)
485 index = sc->ti_cmd_saved_prodidx;
486 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
487 TI_INC(index, TI_CMD_RING_CNT);
488 for (i = 0; i < len; i++) {
489 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
490 *(uint32_t *)(&arg[i * 4]));
491 TI_INC(index, TI_CMD_RING_CNT);
493 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
494 sc->ti_cmd_saved_prodidx = index;
498 * Handle events that have triggered interrupts.
501 ti_handle_events(struct ti_softc *sc)
503 struct ti_event_desc *e;
505 if (sc->ti_rdata->ti_event_ring == NULL)
508 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
509 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
510 switch(e->ti_event) {
511 case TI_EV_LINKSTAT_CHANGED:
512 sc->ti_linkstat = e->ti_code;
513 if (e->ti_code == TI_EV_CODE_LINK_UP)
514 printf("ti%d: 10/100 link up\n", sc->ti_unit);
515 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
516 printf("ti%d: gigabit link up\n", sc->ti_unit);
517 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
518 printf("ti%d: link down\n", sc->ti_unit);
521 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
522 printf("ti%d: invalid command\n", sc->ti_unit);
523 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
524 printf("ti%d: unknown command\n", sc->ti_unit);
525 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
526 printf("ti%d: bad config data\n", sc->ti_unit);
528 case TI_EV_FIRMWARE_UP:
531 case TI_EV_STATS_UPDATED:
534 case TI_EV_RESET_JUMBO_RING:
535 case TI_EV_MCAST_UPDATED:
539 printf("ti%d: unknown event: %d\n",
540 sc->ti_unit, e->ti_event);
543 /* Advance the consumer index. */
544 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
545 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
550 * Memory management for the jumbo receive ring is a pain in the
551 * butt. We need to allocate at least 9018 bytes of space per frame,
552 * _and_ it has to be contiguous (unless you use the extended
553 * jumbo descriptor format). Using malloc() all the time won't
554 * work: malloc() allocates memory in powers of two, which means we
555 * would end up wasting a considerable amount of space by allocating
556 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
557 * to do our own memory management.
559 * The driver needs to allocate a contiguous chunk of memory at boot
560 * time. We then chop this up ourselves into 9K pieces and use them
561 * as external mbuf storage.
563 * One issue here is how much memory to allocate. The jumbo ring has
564 * 256 slots in it, but at 9K per slot than can consume over 2MB of
565 * RAM. This is a bit much, especially considering we also need
566 * RAM for the standard ring and mini ring (on the Tigon 2). To
567 * save space, we only actually allocate enough memory for 64 slots
568 * by default, which works out to between 500 and 600K. This can
569 * be tuned by changing a #define in if_tireg.h.
573 ti_alloc_jumbo_mem(struct ti_softc *sc)
575 struct ti_jslot *entry;
579 /* Grab a big chunk o' storage. */
580 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
581 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
583 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
584 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
588 SLIST_INIT(&sc->ti_jfree_listhead);
591 * Now divide it up into 9K pieces and save the addresses
592 * in an array. Note that we play an evil trick here by using
593 * the first few bytes in the buffer to hold the the address
594 * of the softc structure for this interface. This is because
595 * ti_jfree() needs it, but it is called by the mbuf management
596 * code which will not pass it to us explicitly.
598 ptr = sc->ti_cdata.ti_jumbo_buf;
599 for (i = 0; i < TI_JSLOTS; i++) {
600 entry = &sc->ti_cdata.ti_jslots[i];
605 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link);
613 * Allocate a jumbo buffer.
615 static struct ti_jslot *
616 ti_jalloc(struct ti_softc *sc)
618 struct ti_jslot *entry;
620 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
623 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
627 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jslot_link);
633 * Adjust usage count on a jumbo buffer. In general this doesn't
634 * get used much because our jumbo buffers don't get passed around
635 * too much, but it's implemented for correctness.
640 struct ti_jslot *entry = (struct ti_jslot *)arg;
641 struct ti_softc *sc = entry->ti_sc;
644 panic("ti_jref: can't find softc pointer!");
646 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry)
647 panic("ti_jref: asked to reference buffer "
648 "that we don't manage!");
649 if (entry->ti_inuse == 0)
650 panic("ti_jref: buffer already free!");
655 * Release a jumbo buffer.
660 struct ti_jslot *entry = (struct ti_jslot *)arg;
661 struct ti_softc *sc = entry->ti_sc;
664 panic("ti_jref: can't find softc pointer!");
666 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry)
667 panic("ti_jref: asked to reference buffer "
668 "that we don't manage!");
669 if (entry->ti_inuse == 0)
670 panic("ti_jref: buffer already free!");
671 if (--entry->ti_inuse == 0)
672 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link);
677 * Intialize a standard receive ring descriptor.
680 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m)
683 struct ti_rx_desc *r;
686 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
690 MCLGET(m_new, MB_DONTWAIT);
691 if (!(m_new->m_flags & M_EXT)) {
695 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
698 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
699 m_new->m_data = m_new->m_ext.ext_buf;
702 m_adj(m_new, ETHER_ALIGN);
703 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
704 r = &sc->ti_rdata->ti_rx_std_ring[i];
705 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
706 r->ti_type = TI_BDTYPE_RECV_BD;
708 if (sc->arpcom.ac_if.if_hwassist)
709 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
710 r->ti_len = m_new->m_len;
717 * Intialize a mini receive ring descriptor. This only applies to
721 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m)
724 struct ti_rx_desc *r;
727 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
731 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
734 m_new->m_data = m_new->m_pktdat;
735 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
738 m_adj(m_new, ETHER_ALIGN);
739 r = &sc->ti_rdata->ti_rx_mini_ring[i];
740 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
741 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
742 r->ti_type = TI_BDTYPE_RECV_BD;
743 r->ti_flags = TI_BDFLAG_MINI_RING;
744 if (sc->arpcom.ac_if.if_hwassist)
745 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
746 r->ti_len = m_new->m_len;
753 * Initialize a jumbo receive ring descriptor. This allocates
754 * a jumbo buffer from the pool managed internally by the driver.
757 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
760 struct ti_rx_desc *r;
761 struct ti_jslot *buf;
764 /* Allocate the mbuf. */
765 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
770 /* Allocate the jumbo buffer */
774 printf("ti%d: jumbo allocation failed "
775 "-- packet dropped!\n", sc->ti_unit);
779 /* Attach the buffer to the mbuf. */
780 m_new->m_ext.ext_arg = buf;
781 m_new->m_ext.ext_nfree.new = ti_jfree;
782 m_new->m_ext.ext_nref.new = ti_jref;
783 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
785 m_new->m_data = m_new->m_ext.ext_buf;
786 m_new->m_flags |= M_EXT;
787 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
790 m_new->m_data = m_new->m_ext.ext_buf;
791 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
794 m_adj(m_new, ETHER_ALIGN);
795 /* Set up the descriptor. */
796 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
797 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
798 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
799 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
800 r->ti_flags = TI_BDFLAG_JUMBO_RING;
801 if (sc->arpcom.ac_if.if_hwassist)
802 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
803 r->ti_len = m_new->m_len;
810 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
811 * that's 1MB or memory, which is a lot. For now, we fill only the first
812 * 256 ring entries and hope that our CPU is fast enough to keep up with
816 ti_init_rx_ring_std(struct ti_softc *sc)
819 struct ti_cmd_desc cmd;
821 for (i = 0; i < TI_SSLOTS; i++) {
822 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
826 TI_UPDATE_STDPROD(sc, i - 1);
833 ti_free_rx_ring_std(struct ti_softc *sc)
837 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
838 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
839 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
840 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
842 bzero(&sc->ti_rdata->ti_rx_std_ring[i],
843 sizeof(struct ti_rx_desc));
848 ti_init_rx_ring_jumbo(struct ti_softc *sc)
851 struct ti_cmd_desc cmd;
853 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
854 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
858 TI_UPDATE_JUMBOPROD(sc, i - 1);
859 sc->ti_jumbo = i - 1;
865 ti_free_rx_ring_jumbo(struct ti_softc *sc)
869 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
870 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
871 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
872 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
874 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i],
875 sizeof(struct ti_rx_desc));
880 ti_init_rx_ring_mini(struct ti_softc *sc)
884 for (i = 0; i < TI_MSLOTS; i++) {
885 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
889 TI_UPDATE_MINIPROD(sc, i - 1);
896 ti_free_rx_ring_mini(struct ti_softc *sc)
900 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
901 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
902 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
903 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
905 bzero(&sc->ti_rdata->ti_rx_mini_ring[i],
906 sizeof(struct ti_rx_desc));
911 ti_free_tx_ring(struct ti_softc *sc)
915 if (sc->ti_rdata->ti_tx_ring == NULL)
918 for (i = 0; i < TI_TX_RING_CNT; i++) {
919 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
920 m_freem(sc->ti_cdata.ti_tx_chain[i]);
921 sc->ti_cdata.ti_tx_chain[i] = NULL;
923 bzero(&sc->ti_rdata->ti_tx_ring[i],
924 sizeof(struct ti_tx_desc));
929 ti_init_tx_ring(struct ti_softc *sc)
932 sc->ti_tx_saved_considx = 0;
933 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
938 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
939 * but we have to support the old way too so that Tigon 1 cards will
943 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
945 struct ti_cmd_desc cmd;
947 uint32_t ext[2] = {0, 0};
949 m = (uint16_t *)&addr->octet[0];
951 switch(sc->ti_hwrev) {
953 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
954 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
955 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
957 case TI_HWREV_TIGON_II:
958 ext[0] = htons(m[0]);
959 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
960 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
963 printf("ti%d: unknown hwrev\n", sc->ti_unit);
969 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
971 struct ti_cmd_desc cmd;
973 uint32_t ext[2] = {0, 0};
975 m = (uint16_t *)&addr->octet[0];
977 switch(sc->ti_hwrev) {
979 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
980 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
981 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
983 case TI_HWREV_TIGON_II:
984 ext[0] = htons(m[0]);
985 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
986 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
989 printf("ti%d: unknown hwrev\n", sc->ti_unit);
995 * Configure the Tigon's multicast address filter.
997 * The actual multicast table management is a bit of a pain, thanks to
998 * slight brain damage on the part of both Alteon and us. With our
999 * multicast code, we are only alerted when the multicast address table
1000 * changes and at that point we only have the current list of addresses:
1001 * we only know the current state, not the previous state, so we don't
1002 * actually know what addresses were removed or added. The firmware has
1003 * state, but we can't get our grubby mits on it, and there is no 'delete
1004 * all multicast addresses' command. Hence, we have to maintain our own
1005 * state so we know what addresses have been programmed into the NIC at
1009 ti_setmulti(struct ti_softc *sc)
1011 struct ifnet *ifp = &sc->arpcom.ac_if;
1012 struct ifmultiaddr *ifma;
1013 struct ti_cmd_desc cmd;
1014 struct ti_mc_entry *mc;
1017 if (ifp->if_flags & IFF_ALLMULTI) {
1018 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1022 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1024 /* Disable interrupts. */
1025 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1026 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1028 /* First, zot all the existing filters. */
1029 while (sc->ti_mc_listhead.slh_first != NULL) {
1030 mc = sc->ti_mc_listhead.slh_first;
1031 ti_del_mcast(sc, &mc->mc_addr);
1032 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1036 /* Now program new ones. */
1037 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1038 if (ifma->ifma_addr->sa_family != AF_LINK)
1040 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT);
1041 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1042 &mc->mc_addr, ETHER_ADDR_LEN);
1043 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1044 ti_add_mcast(sc, &mc->mc_addr);
1047 /* Re-enable interrupts. */
1048 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1052 * Check to see if the BIOS has configured us for a 64 bit slot when
1053 * we aren't actually in one. If we detect this condition, we can work
1054 * around it on the Tigon 2 by setting a bit in the PCI state register,
1055 * but for the Tigon 1 we must give up and abort the interface attach.
1058 ti_64bitslot_war(struct ti_softc *sc)
1060 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) {
1061 CSR_WRITE_4(sc, 0x600, 0);
1062 CSR_WRITE_4(sc, 0x604, 0);
1063 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1064 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1065 if (sc->ti_hwrev == TI_HWREV_TIGON)
1067 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_32BIT_BUS);
1076 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1077 * self-test results.
1080 ti_chipinit(struct ti_softc *sc)
1082 struct ifnet *ifp = &sc->arpcom.ac_if;
1084 uint32_t pci_writemax = 0;
1086 /* Initialize link to down state. */
1087 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1089 if (ifp->if_capenable & IFCAP_HWCSUM)
1090 ifp->if_hwassist = TI_CSUM_FEATURES;
1092 ifp->if_hwassist = 0;
1094 /* Set endianness before we access any non-PCI registers. */
1095 #if BYTE_ORDER == BIG_ENDIAN
1096 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1097 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1099 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1100 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1103 /* Check the ROM failed bit to see if self-tests passed. */
1104 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1105 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1110 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1112 /* Figure out the hardware revision. */
1113 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1114 case TI_REV_TIGON_I:
1115 sc->ti_hwrev = TI_HWREV_TIGON;
1117 case TI_REV_TIGON_II:
1118 sc->ti_hwrev = TI_HWREV_TIGON_II;
1121 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1125 /* Do special setup for Tigon 2. */
1126 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1127 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1128 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1129 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1132 /* Set up the PCI state register. */
1133 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1134 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1135 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1138 /* Clear the read/write max DMA parameters. */
1139 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1140 TI_PCISTATE_READ_MAXDMA));
1142 /* Get cache line size. */
1143 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1146 * If the system has set enabled the PCI memory write
1147 * and invalidate command in the command register, set
1148 * the write max parameter accordingly. This is necessary
1149 * to use MWI with the Tigon 2.
1151 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1161 /* Disable PCI memory write and invalidate. */
1163 printf("ti%d: cache line size %d not "
1164 "supported; disabling PCI MWI\n",
1165 sc->ti_unit, cacheline);
1166 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1167 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1172 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1174 /* This sets the min dma param all the way up (0xff). */
1175 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1177 /* Configure DMA variables. */
1178 #if BYTE_ORDER == BIG_ENDIAN
1179 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1180 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1181 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1182 TI_OPMODE_DONT_FRAG_JUMBO);
1184 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1185 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1186 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1190 * Only allow 1 DMA channel to be active at a time.
1191 * I don't think this is a good idea, but without it
1192 * the firmware racks up lots of nicDmaReadRingFull
1193 * errors. This is not compatible with hardware checksums.
1195 if (sc->arpcom.ac_if.if_hwassist == 0)
1196 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1198 /* Recommended settings from Tigon manual. */
1199 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1200 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1202 if (ti_64bitslot_war(sc)) {
1203 printf("ti%d: bios thinks we're in a 64 bit slot, "
1204 "but we aren't", sc->ti_unit);
1212 * Initialize the general information block and firmware, and
1213 * start the CPU(s) running.
1216 ti_gibinit(struct ti_softc *sc)
1218 struct ifnet *ifp = &sc->arpcom.ac_if;
1222 /* Disable interrupts for now. */
1223 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1225 /* Tell the chip where to find the general information block. */
1226 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1227 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1229 /* Load the firmware into SRAM. */
1232 /* Set up the contents of the general info and ring control blocks. */
1234 /* Set up the event ring and producer pointer. */
1235 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1237 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1239 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1240 vtophys(&sc->ti_ev_prodidx);
1241 sc->ti_ev_prodidx.ti_idx = 0;
1242 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1243 sc->ti_ev_saved_considx = 0;
1245 /* Set up the command ring and producer mailbox. */
1246 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1248 sc->ti_rdata->ti_cmd_ring =
1249 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1250 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1252 rcb->ti_max_len = 0;
1253 for (i = 0; i < TI_CMD_RING_CNT; i++)
1254 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1255 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1256 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1257 sc->ti_cmd_saved_prodidx = 0;
1260 * Assign the address of the stats refresh buffer.
1261 * We re-use the current stats buffer for this to
1264 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1265 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1267 /* Set up the standard receive ring. */
1268 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1269 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1270 rcb->ti_max_len = TI_FRAMELEN;
1272 if (ifp->if_hwassist)
1273 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1274 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1275 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1277 /* Set up the jumbo receive ring. */
1278 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1279 TI_HOSTADDR(rcb->ti_hostaddr) =
1280 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1281 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1283 if (ifp->if_hwassist)
1284 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1285 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1286 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1289 * Set up the mini ring. Only activated on the
1290 * Tigon 2 but the slot in the config block is
1291 * still there on the Tigon 1.
1293 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1294 TI_HOSTADDR(rcb->ti_hostaddr) =
1295 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1296 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1297 if (sc->ti_hwrev == TI_HWREV_TIGON)
1298 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1301 if (ifp->if_hwassist)
1302 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1303 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1304 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1307 * Set up the receive return ring.
1309 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1310 TI_HOSTADDR(rcb->ti_hostaddr) =
1311 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1313 rcb->ti_max_len = TI_RETURN_RING_CNT;
1314 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1315 vtophys(&sc->ti_return_prodidx);
1318 * Set up the tx ring. Note: for the Tigon 2, we have the option
1319 * of putting the transmit ring in the host's address space and
1320 * letting the chip DMA it instead of leaving the ring in the NIC's
1321 * memory and accessing it through the shared memory region. We
1322 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1323 * so we have to revert to the shared memory scheme if we detect
1326 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1327 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1328 sc->ti_rdata->ti_tx_ring_nic =
1329 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1331 bzero(sc->ti_rdata->ti_tx_ring,
1332 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1333 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1334 if (sc->ti_hwrev == TI_HWREV_TIGON)
1337 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1338 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1339 if (ifp->if_hwassist)
1340 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1341 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1342 rcb->ti_max_len = TI_TX_RING_CNT;
1343 if (sc->ti_hwrev == TI_HWREV_TIGON)
1344 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1346 TI_HOSTADDR(rcb->ti_hostaddr) =
1347 vtophys(&sc->ti_rdata->ti_tx_ring);
1348 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1349 vtophys(&sc->ti_tx_considx);
1351 /* Set up tuneables */
1352 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1353 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1354 (sc->ti_rx_coal_ticks / 10));
1356 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1357 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1358 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1359 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1360 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1361 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1363 /* Turn interrupts on. */
1364 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1365 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1368 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1374 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1375 * against our list and return its name if we find a match.
1378 ti_probe(device_t dev)
1381 uint16_t vendor, product;
1383 vendor = pci_get_vendor(dev);
1384 product = pci_get_device(dev);
1386 for (t = ti_devs; t->ti_name != NULL; t++) {
1387 if (vendor == t->ti_vid && product == t->ti_did) {
1388 device_set_desc(dev, t->ti_name);
1397 ti_attach(device_t dev)
1399 struct ti_softc *sc;
1401 int error = 0, rid, s, unit;
1406 sc = device_get_softc(dev);
1407 unit = device_get_unit(dev);
1408 ifp = &sc->arpcom.ac_if;
1409 ifp->if_capabilities = IFCAP_HWCSUM;
1410 ifp->if_capenable = sc->arpcom.ac_if.if_capabilities;
1413 * Map control/status registers.
1415 command = pci_read_config(dev, PCIR_COMMAND, 4);
1416 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1417 pci_write_config(dev, PCIR_COMMAND, command, 4);
1418 command = pci_read_config(dev, PCIR_COMMAND, 4);
1420 if ((command & PCIM_CMD_MEMEN) == 0) {
1421 printf("ti%d: failed to enable memory mapping!\n", unit);
1427 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1430 if (sc->ti_res == NULL) {
1431 printf ("ti%d: couldn't map memory\n", unit);
1436 sc->ti_btag = rman_get_bustag(sc->ti_res);
1437 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1438 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1440 /* Allocate interrupt */
1443 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1444 RF_SHAREABLE | RF_ACTIVE);
1446 if (sc->ti_irq == NULL) {
1447 printf("ti%d: couldn't map interrupt\n", unit);
1452 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1453 ti_intr, sc, &sc->ti_intrhand, NULL);
1456 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1457 bus_release_resource(dev, SYS_RES_MEMORY,
1458 TI_PCI_LOMEM, sc->ti_res);
1459 printf("ti%d: couldn't set up irq\n", unit);
1465 if (ti_chipinit(sc)) {
1466 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1467 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1468 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1469 bus_release_resource(dev, SYS_RES_MEMORY,
1470 TI_PCI_LOMEM, sc->ti_res);
1475 /* Zero out the NIC's on-board SRAM. */
1476 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1478 /* Init again -- zeroing memory may have clobbered some registers. */
1479 if (ti_chipinit(sc)) {
1480 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1481 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1482 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1483 bus_release_resource(dev, SYS_RES_MEMORY,
1484 TI_PCI_LOMEM, sc->ti_res);
1490 * Get station address from the EEPROM. Note: the manual states
1491 * that the MAC address is at offset 0x8c, however the data is
1492 * stored as two longwords (since that's how it's loaded into
1493 * the NIC). This means the MAC address is actually preceeded
1494 * by two zero bytes. We need to skip over those.
1496 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1497 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1498 printf("ti%d: failed to read station address\n", unit);
1499 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1500 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1501 bus_release_resource(dev, SYS_RES_MEMORY,
1502 TI_PCI_LOMEM, sc->ti_res);
1507 /* Allocate the general information block and ring buffers. */
1508 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1509 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1511 if (sc->ti_rdata == NULL) {
1512 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1513 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1514 bus_release_resource(dev, SYS_RES_MEMORY,
1515 TI_PCI_LOMEM, sc->ti_res);
1517 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1521 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1523 /* Try to allocate memory for jumbo buffers. */
1524 if (ti_alloc_jumbo_mem(sc)) {
1525 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1526 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1527 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1528 bus_release_resource(dev, SYS_RES_MEMORY,
1529 TI_PCI_LOMEM, sc->ti_res);
1530 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1537 * We really need a better way to tell a 1000baseTX card
1538 * from a 1000baseSX one, since in theory there could be
1539 * OEMed 1000baseTX cards from lame vendors who aren't
1540 * clever enough to change the PCI ID. For the moment
1541 * though, the AceNIC is the only copper card available.
1543 if (pci_get_vendor(dev) == ALT_VENDORID &&
1544 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1546 /* Ok, it's not the only copper card available. */
1547 if (pci_get_vendor(dev) == NG_VENDORID &&
1548 pci_get_device(dev) == NG_DEVICEID_GA620T)
1551 /* Set default tuneable values. */
1552 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1553 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1554 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1555 sc->ti_rx_max_coal_bds = 64;
1556 sc->ti_tx_max_coal_bds = 128;
1557 sc->ti_tx_buf_ratio = 21;
1559 /* Set up ifnet structure */
1561 if_initname(ifp, "ti", sc->ti_unit);
1562 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1563 ifp->if_ioctl = ti_ioctl;
1564 ifp->if_start = ti_start;
1565 ifp->if_watchdog = ti_watchdog;
1566 ifp->if_init = ti_init;
1567 ifp->if_mtu = ETHERMTU;
1568 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1);
1569 ifq_set_ready(&ifp->if_snd);
1571 /* Set up ifmedia support. */
1572 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1573 if (sc->ti_copper) {
1575 * Copper cards allow manual 10/100 mode selection,
1576 * but not manual 1000baseTX mode selection. Why?
1577 * Becuase currently there's no way to specify the
1578 * master/slave setting through the firmware interface,
1579 * so Alteon decided to just bag it and handle it
1580 * via autonegotiation.
1582 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1583 ifmedia_add(&sc->ifmedia,
1584 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1585 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1586 ifmedia_add(&sc->ifmedia,
1587 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1588 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
1589 ifmedia_add(&sc->ifmedia,
1590 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL);
1592 /* Fiber cards don't support 10/100 modes. */
1593 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1594 ifmedia_add(&sc->ifmedia,
1595 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1597 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1598 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1601 * Call MI attach routine.
1603 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1612 ti_detach(device_t dev)
1614 struct ti_softc *sc = device_get_softc(dev);
1615 struct ifnet *ifp = &sc->arpcom.ac_if;
1620 ether_ifdetach(ifp);
1623 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1624 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1625 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1627 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1628 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1629 ifmedia_removeall(&sc->ifmedia);
1637 * Frame reception handling. This is called if there's a frame
1638 * on the receive return list.
1640 * Note: we have to be able to handle three possibilities here:
1641 * 1) the frame is from the mini receive ring (can only happen)
1642 * on Tigon 2 boards)
1643 * 2) the frame is from the jumbo recieve ring
1644 * 3) the frame is from the standard receive ring
1647 ti_rxeof(struct ti_softc *sc)
1649 struct ifnet *ifp = &sc->arpcom.ac_if;
1650 struct ti_cmd_desc cmd;
1652 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1653 struct ti_rx_desc *cur_rx;
1656 uint16_t vlan_tag = 0;
1660 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1661 rxidx = cur_rx->ti_idx;
1662 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1664 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1666 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1669 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1670 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1671 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1672 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1673 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1675 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1678 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1680 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1683 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1684 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1685 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1686 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1687 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1689 ti_newbuf_mini(sc, sc->ti_mini, m);
1692 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1694 ti_newbuf_mini(sc, sc->ti_mini, m);
1698 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1699 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1700 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1701 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1703 ti_newbuf_std(sc, sc->ti_std, m);
1706 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1708 ti_newbuf_std(sc, sc->ti_std, m);
1713 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1715 m->m_pkthdr.rcvif = ifp;
1717 if (ifp->if_hwassist) {
1718 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1720 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1721 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1722 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1726 * If we received a packet with a vlan tag, pass it
1727 * to vlan_input() instead of ether_input().
1730 VLAN_INPUT_TAG(m, vlan_tag);
1732 (*ifp->if_input)(ifp, m);
1735 /* Only necessary on the Tigon 1. */
1736 if (sc->ti_hwrev == TI_HWREV_TIGON)
1737 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1738 sc->ti_rx_saved_considx);
1740 TI_UPDATE_STDPROD(sc, sc->ti_std);
1741 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1742 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1746 ti_txeof(struct ti_softc *sc)
1748 struct ifnet *ifp = &sc->arpcom.ac_if;
1749 struct ti_tx_desc *cur_tx = NULL;
1752 * Go through our tx ring and free mbufs for those
1753 * frames that have been sent.
1755 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1758 idx = sc->ti_tx_saved_considx;
1759 if (sc->ti_hwrev != TI_HWREV_TIGON) {
1761 CSR_WRITE_4(sc, TI_WINBASE,
1762 TI_TX_RING_BASE + 6144);
1764 CSR_WRITE_4(sc, TI_WINBASE,
1765 TI_TX_RING_BASE + 4096);
1767 CSR_WRITE_4(sc, TI_WINBASE,
1768 TI_TX_RING_BASE + 2048);
1770 CSR_WRITE_4(sc, TI_WINBASE,
1772 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1774 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1775 if (cur_tx->ti_flags & TI_BDFLAG_END)
1777 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1778 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1779 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1782 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1787 ifp->if_flags &= ~IFF_OACTIVE;
1793 struct ti_softc *sc = xsc;
1794 struct ifnet *ifp = &sc->arpcom.ac_if;
1797 /* Avoid this for now -- checking this register is expensive. */
1798 /* Make sure this is really our interrupt. */
1799 if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0)
1803 /* Ack interrupt and stop others from occuring. */
1804 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1806 if (ifp->if_flags & IFF_RUNNING) {
1807 /* Check RX return ring producer/consumer */
1810 /* Check TX ring producer/consumer */
1814 ti_handle_events(sc);
1816 /* Re-enable interrupts. */
1817 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1819 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1824 ti_stats_update(struct ti_softc *sc)
1826 struct ifnet *ifp = &sc->arpcom.ac_if;
1828 ifp->if_collisions +=
1829 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
1830 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
1831 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
1832 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
1837 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1838 * pointers to descriptors.
1841 ti_encap(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1843 struct ti_tx_desc *f = NULL;
1845 struct ifvlan *ifv = NULL;
1846 uint32_t cnt = 0, cur, frag;
1847 uint16_t csum_flags = 0;
1849 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1850 m_head->m_pkthdr.rcvif != NULL &&
1851 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1852 ifv = m_head->m_pkthdr.rcvif->if_softc;
1855 cur = frag = *txidx;
1857 if (m_head->m_pkthdr.csum_flags) {
1858 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1859 csum_flags |= TI_BDFLAG_IP_CKSUM;
1860 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1861 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
1862 if (m_head->m_flags & M_LASTFRAG)
1863 csum_flags |= TI_BDFLAG_IP_FRAG_END;
1864 else if (m_head->m_flags & M_FRAG)
1865 csum_flags |= TI_BDFLAG_IP_FRAG;
1868 * Start packing the mbufs in this chain into
1869 * the fragment pointers. Stop when we run out
1870 * of fragments or hit the end of the mbuf chain.
1872 for (m = m_head; m != NULL; m = m->m_next) {
1873 if (m->m_len != 0) {
1874 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1876 CSR_WRITE_4(sc, TI_WINBASE,
1877 TI_TX_RING_BASE + 6144);
1878 else if (frag > 255)
1879 CSR_WRITE_4(sc, TI_WINBASE,
1880 TI_TX_RING_BASE + 4096);
1881 else if (frag > 127)
1882 CSR_WRITE_4(sc, TI_WINBASE,
1883 TI_TX_RING_BASE + 2048);
1885 CSR_WRITE_4(sc, TI_WINBASE,
1887 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
1889 f = &sc->ti_rdata->ti_tx_ring[frag];
1890 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
1892 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
1893 f->ti_len = m->m_len;
1894 f->ti_flags = csum_flags;
1897 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
1898 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
1904 * Sanity check: avoid coming within 16 descriptors
1905 * of the end of the ring.
1907 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
1910 TI_INC(frag, TI_TX_RING_CNT);
1918 if (frag == sc->ti_tx_saved_considx)
1921 if (sc->ti_hwrev == TI_HWREV_TIGON)
1922 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
1925 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
1926 sc->ti_cdata.ti_tx_chain[cur] = m_head;
1927 sc->ti_txcnt += cnt;
1935 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1936 * to the mbuf data regions directly in the transmit descriptors.
1939 ti_start(struct ifnet *ifp)
1941 struct ti_softc *sc = ifp->if_softc;
1942 struct mbuf *m_head = NULL;
1943 uint32_t prodidx = 0;
1945 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
1947 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
1948 m_head = ifq_poll(&ifp->if_snd);
1954 * safety overkill. If this is a fragmented packet chain
1955 * with delayed TCP/UDP checksums, then only encapsulate
1956 * it if we have enough descriptors to handle the entire
1958 * (paranoia -- may not actually be needed)
1960 if (m_head->m_flags & M_FIRSTFRAG &&
1961 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
1962 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
1963 m_head->m_pkthdr.csum_data + 16) {
1964 ifp->if_flags |= IFF_OACTIVE;
1970 * Pack the data into the transmit ring. If we
1971 * don't have room, set the OACTIVE flag and wait
1972 * for the NIC to drain the ring.
1974 if (ti_encap(sc, m_head, &prodidx)) {
1975 ifp->if_flags |= IFF_OACTIVE;
1979 m_head = ifq_dequeue(&ifp->if_snd);
1980 BPF_MTAP(ifp, m_head);
1984 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
1987 * Set a timeout in case the chip goes out to lunch.
1995 struct ti_softc *sc = xsc;
2000 /* Cancel pending I/O and flush buffers. */
2003 /* Init the gen info block, ring control blocks and firmware. */
2004 if (ti_gibinit(sc)) {
2005 printf("ti%d: initialization failure\n", sc->ti_unit);
2014 ti_init2(struct ti_softc *sc)
2016 struct ifnet *ifp = &sc->arpcom.ac_if;
2017 struct ti_cmd_desc cmd;
2019 struct ifmedia *ifm;
2022 /* Specify MTU and interface index. */
2023 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit);
2024 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2025 ETHER_HDR_LEN + ETHER_CRC_LEN);
2026 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2028 /* Load our MAC address. */
2029 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2030 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2031 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2032 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2034 /* Enable or disable promiscuous mode as needed. */
2035 if (ifp->if_flags & IFF_PROMISC)
2036 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2038 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2040 /* Program multicast filter. */
2044 * If this is a Tigon 1, we should tell the
2045 * firmware to use software packet filtering.
2047 if (sc->ti_hwrev == TI_HWREV_TIGON)
2048 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2051 ti_init_rx_ring_std(sc);
2053 /* Init jumbo RX ring. */
2054 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2055 ti_init_rx_ring_jumbo(sc);
2058 * If this is a Tigon 2, we can also configure the
2061 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2062 ti_init_rx_ring_mini(sc);
2064 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2065 sc->ti_rx_saved_considx = 0;
2068 ti_init_tx_ring(sc);
2070 /* Tell firmware we're alive. */
2071 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2073 /* Enable host interrupts. */
2074 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2076 ifp->if_flags |= IFF_RUNNING;
2077 ifp->if_flags &= ~IFF_OACTIVE;
2080 * Make sure to set media properly. We have to do this
2081 * here since we have to issue commands in order to set
2082 * the link negotiation and we can't issue commands until
2083 * the firmware is running.
2086 tmp = ifm->ifm_media;
2087 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2088 ti_ifmedia_upd(ifp);
2089 ifm->ifm_media = tmp;
2093 * Set media options.
2096 ti_ifmedia_upd(struct ifnet *ifp)
2098 struct ti_softc *sc = ifp->if_softc;
2099 struct ifmedia *ifm = &sc->ifmedia;
2100 struct ti_cmd_desc cmd;
2102 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2105 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2107 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB |
2108 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y |
2109 TI_GLNK_AUTONEGENB | TI_GLNK_ENB);
2110 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB |
2111 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX |
2112 TI_LNK_AUTONEGENB | TI_LNK_ENB);
2113 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2114 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2118 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB |
2119 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB);
2120 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2121 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
2122 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2123 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2124 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2130 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2131 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF);
2132 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2133 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX)
2134 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2136 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2137 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
2138 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2140 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2141 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2142 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2150 * Report current media status.
2153 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2155 struct ti_softc *sc = ifp->if_softc;
2158 ifmr->ifm_status = IFM_AVALID;
2159 ifmr->ifm_active = IFM_ETHER;
2161 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2164 ifmr->ifm_status |= IFM_ACTIVE;
2166 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2167 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2169 ifmr->ifm_active |= IFM_1000_T;
2171 ifmr->ifm_active |= IFM_1000_SX;
2172 if (media & TI_GLNK_FULL_DUPLEX)
2173 ifmr->ifm_active |= IFM_FDX;
2175 ifmr->ifm_active |= IFM_HDX;
2176 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2177 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2178 if (sc->ti_copper) {
2179 if (media & TI_LNK_100MB)
2180 ifmr->ifm_active |= IFM_100_TX;
2181 if (media & TI_LNK_10MB)
2182 ifmr->ifm_active |= IFM_10_T;
2184 if (media & TI_LNK_100MB)
2185 ifmr->ifm_active |= IFM_100_FX;
2186 if (media & TI_LNK_10MB)
2187 ifmr->ifm_active |= IFM_10_FL;
2189 if (media & TI_LNK_FULL_DUPLEX)
2190 ifmr->ifm_active |= IFM_FDX;
2191 if (media & TI_LNK_HALF_DUPLEX)
2192 ifmr->ifm_active |= IFM_HDX;
2197 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2199 struct ti_softc *sc = ifp->if_softc;
2200 struct ifreq *ifr = (struct ifreq *) data;
2201 struct ti_cmd_desc cmd;
2202 int error = 0, mask, s;
2208 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2211 ifp->if_mtu = ifr->ifr_mtu;
2216 if (ifp->if_flags & IFF_UP) {
2218 * If only the state of the PROMISC flag changed,
2219 * then just use the 'set promisc mode' command
2220 * instead of reinitializing the entire NIC. Doing
2221 * a full re-init means reloading the firmware and
2222 * waiting for it to start up, which may take a
2225 if (ifp->if_flags & IFF_RUNNING &&
2226 ifp->if_flags & IFF_PROMISC &&
2227 !(sc->ti_if_flags & IFF_PROMISC)) {
2228 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2229 TI_CMD_CODE_PROMISC_ENB, 0);
2230 } else if (ifp->if_flags & IFF_RUNNING &&
2231 !(ifp->if_flags & IFF_PROMISC) &&
2232 sc->ti_if_flags & IFF_PROMISC) {
2233 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2234 TI_CMD_CODE_PROMISC_DIS, 0);
2237 } else if (ifp->if_flags & IFF_RUNNING) {
2240 sc->ti_if_flags = ifp->if_flags;
2245 if (ifp->if_flags & IFF_RUNNING) {
2252 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2255 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2256 if (mask & IFCAP_HWCSUM) {
2257 if (IFCAP_HWCSUM & ifp->if_capenable)
2258 ifp->if_capenable &= ~IFCAP_HWCSUM;
2260 ifp->if_capenable |= IFCAP_HWCSUM;
2261 if (ifp->if_flags & IFF_RUNNING)
2267 error = ether_ioctl(ifp, command, data);
2277 ti_watchdog(struct ifnet *ifp)
2279 struct ti_softc *sc = ifp->if_softc;
2281 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2289 * Stop the adapter and free any mbufs allocated to the
2293 ti_stop(struct ti_softc *sc)
2295 struct ifnet *ifp = &sc->arpcom.ac_if;
2296 struct ti_cmd_desc cmd;
2298 /* Disable host interrupts. */
2299 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2301 * Tell firmware we're shutting down.
2303 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2305 /* Halt and reinitialize. */
2307 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2310 /* Free the RX lists. */
2311 ti_free_rx_ring_std(sc);
2313 /* Free jumbo RX list. */
2314 ti_free_rx_ring_jumbo(sc);
2316 /* Free mini RX list. */
2317 ti_free_rx_ring_mini(sc);
2319 /* Free TX buffers. */
2320 ti_free_tx_ring(sc);
2322 sc->ti_ev_prodidx.ti_idx = 0;
2323 sc->ti_return_prodidx.ti_idx = 0;
2324 sc->ti_tx_considx.ti_idx = 0;
2325 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2327 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2331 * Stop all chip I/O so that the kernel's probe routines don't
2332 * get confused by errant DMAs when rebooting.
2335 ti_shutdown(device_t dev)
2337 struct ti_softc *sc = device_get_softc(dev);