2 * Copyright (c) 1991 The Regents of the University of California.
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33 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
34 * $DragonFly: src/sys/platform/pc32/isa/intr_machdep.h,v 1.25 2006/10/23 21:50:31 dillon Exp $
37 #ifndef _ARCH_ISA_INTR_MACHDEP_H_
38 #define _ARCH_ISA_INTR_MACHDEP_H_
41 #ifndef _SYS_INTERRUPT_H_
42 #include <sys/interrupt.h>
44 #ifndef _SYS_SERIALIZE_H_
45 #include <sys/serialize.h>
50 * Low level interrupt code.
59 * XXX FIXME: rethink location for all IPI vectors.
63 APIC TPR priority vector levels:
65 0xff (255) +-------------+
66 | | 15 (IPIs: Xspuriousint)
67 0xf0 (240) +-------------+
69 0xe0 (224) +-------------+
71 0xd0 (208) +-------------+
73 0xc0 (192) +-------------+
75 0xb0 (176) +-------------+
76 | | 10 (IPIs: Xcpustop)
77 0xa0 (160) +-------------+
78 | | 9 (IPIs: Xinvltlb)
79 0x90 (144) +-------------+
80 | | 8 (linux/BSD syscall, IGNORE FAST HW INTS)
81 0x80 (128) +-------------+
82 | | 7 (FAST_INTR 16-23)
83 0x70 (112) +-------------+
84 | | 6 (FAST_INTR 0-15)
85 0x60 (96) +-------------+
86 | | 5 (IGNORE HW INTS)
87 0x50 (80) +-------------+
89 0x40 (64) +------+------+
90 | | | 3 (upper APIC hardware INTs: PCI)
91 0x30 (48) +------+------+
92 | | 2 (start of hardware INTs: ISA)
93 0x20 (32) +-------------+
94 | | 1 (exceptions, traps, etc.)
95 0x10 (16) +-------------+
96 | | 0 (exceptions, traps, etc.)
97 0x00 (0) +-------------+
100 /* blocking values for local APIC Task Priority Register */
101 #define TPR_BLOCK_HWI 0x4f /* hardware INTs */
102 #define TPR_IGNORE_HWI 0x5f /* ignore INTs */
103 #define TPR_BLOCK_FHWI 0x7f /* hardware FAST INTs */
104 #define TPR_IGNORE_FHWI 0x8f /* ignore FAST INTs */
105 #define TPR_IPI_ONLY 0x8f /* ignore FAST INTs */
106 #define TPR_BLOCK_XINVLTLB 0x9f /* */
107 #define TPR_BLOCK_XCPUSTOP 0xaf /* */
108 #define TPR_BLOCK_ALL 0xff /* all INTs */
112 #define XINVLTLB_OFFSET (IDT_OFFSET + 112)
114 /* unused/open (was inter-cpu clock handling) */
115 #define XUNUSED113_OFFSET (IDT_OFFSET + 113)
117 /* inter-CPU rendezvous */
118 #define XUNUSED114_OFFSET (IDT_OFFSET + 114)
120 /* IPIQ rendezvous */
121 #define XIPIQ_OFFSET (IDT_OFFSET + 115)
123 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
124 #define XCPUSTOP_OFFSET (IDT_OFFSET + 128)
127 * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
129 #define XSPURIOUSINT_OFFSET (IDT_OFFSET + 223)
136 * Type of the first (asm) part of an interrupt handler.
138 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
139 typedef void unpendhand_t(void);
141 #define IDTVEC(name) __CONCAT(X,name)
145 Xinvltlb, /* TLB shootdowns */
146 Xcpuast, /* Additional software trap on other cpu */
147 Xforward_irq, /* Forward irq to cpu holding ISR lock */
148 Xcpustop, /* CPU stops & waits for another CPU to restart it */
149 Xspuriousint, /* handle APIC "spurious INTs" */
150 Xipiq; /* handle lwkt_send_ipiq() requests */
153 void call_fast_unpend(int irq);
154 void isa_defaultirq (void);
155 int isa_nmi (int cd);
156 void icu_reinit (void);
162 #endif /* !_ARCH_ISA_INTR_MACHDEP_H_ */