2 ***********************************************************************************************
4 ** FILE NAME : arcmsr.h
5 ** BY : Erich Chen, Ching Huang
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA SATA/SAS RAID HOST Adapter
8 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set]
9 ***********************************************************************************************
10 ************************************************************************
11 ** Copyright (C) 2002 - 2010, Areca Technology Corporation All rights reserved.
13 ** Web site: www.areca.com.tw
14 ** E-mail: erich@areca.com.tw; ching2048@areca.com.tw
16 ** Redistribution and use in source and binary forms,with or without
17 ** modification,are permitted provided that the following conditions
19 ** 1. Redistributions of source code must retain the above copyright
20 ** notice,this list of conditions and the following disclaimer.
21 ** 2. Redistributions in binary form must reproduce the above copyright
22 ** notice,this list of conditions and the following disclaimer in the
23 ** documentation and/or other materials provided with the distribution.
24 ** 3. The name of the author may not be used to endorse or promote products
25 ** derived from this software without specific prior written permission.
27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES
29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT,
31 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
32 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
34 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT
35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
36 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 **************************************************************************
38 * $FreeBSD: src/sys/dev/arcmsr/arcmsr.h,v 1.8 2010/11/13 08:58:36 delphij Exp $
41 #include <sys/ioccom.h>
43 #define ARCMSR_SCSI_INITIATOR_ID 255
44 #define ARCMSR_DEV_SECTOR_SIZE 512
45 #define ARCMSR_MAX_XFER_SECTORS 4096
46 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/
47 #define ARCMSR_MAX_TARGETLUN 8 /*8*/
48 #define ARCMSR_MAX_CHIPTYPE_NUM 4
49 #define ARCMSR_MAX_OUTSTANDING_CMD 256
50 #define ARCMSR_MAX_START_JOB 257
51 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
52 #define ARCMSR_MAX_FREESRB_NUM 320
53 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
54 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/
55 #define ARCMSR_MAX_ADAPTER 4
56 #define ARCMSR_RELEASE_SIMQ_LEVEL 230
57 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
59 *********************************************************************
68 # define INTR_ENTROPY 0
72 #define offsetof(type, member) ((size_t)(&((type *)0)->member))
75 **********************************************************************************
77 **********************************************************************************
79 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
80 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */
81 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */
82 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */
83 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */
84 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */
85 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */
86 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */
87 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */
88 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */
89 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */
90 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */
91 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */
92 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */
93 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */
94 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */
95 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */
96 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */
97 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */
98 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */
99 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
100 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
101 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */
103 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */
104 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */
105 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */
106 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */
107 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */
108 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */
109 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */
110 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */
111 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */
112 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */
113 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */
114 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */
115 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */
116 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */
117 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */
118 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */
119 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
120 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
121 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
122 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
123 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
124 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
127 #define PCIR_BARS 0x10
128 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
131 #define PCI_BASE_ADDR0 0x10
132 #define PCI_BASE_ADDR1 0x14
133 #define PCI_BASE_ADDR2 0x18
134 #define PCI_BASE_ADDR3 0x1C
135 #define PCI_BASE_ADDR4 0x20
136 #define PCI_BASE_ADDR5 0x24
138 **********************************************************************************
140 **********************************************************************************
142 #define ARCMSR_SCSICMD_IOCTL 0x77
143 #define ARCMSR_CDEVSW_IOCTL 0x88
144 #define ARCMSR_MESSAGE_FAIL 0x0001
145 #define ARCMSR_MESSAGE_SUCCESS 0x0000
147 **********************************************************************************
149 **********************************************************************************
151 #define arcmsr_ccbsrb_ptr spriv_ptr0
152 #define arcmsr_ccbacb_ptr spriv_ptr1
153 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16)
154 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
155 #define get_min(x,y) ((x) < (y) ? (x) : (y))
156 #define get_max(x,y) ((x) < (y) ? (y) : (x))
158 **********************************************************************************
160 **********************************************************************************
163 u_int32_t HeaderLength;
164 u_int8_t Signature[8];
166 u_int32_t ControlCode;
167 u_int32_t ReturnCode;
171 struct CMD_MESSAGE_FIELD {
172 struct CMD_MESSAGE cmdmessage; /* ioctl header */
173 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */
176 /************************************************************************/
177 /************************************************************************/
179 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001
180 #define ARCMSR_IOP_ERROR_VENDORID 0x0002
181 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002
182 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003
183 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004
184 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005
185 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006
186 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007
187 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008
188 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009
189 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A
192 #define ARECA_SATA_RAID 0x90000000
195 #define FUNCTION_READ_RQBUFFER 0x0801
196 #define FUNCTION_WRITE_WQBUFFER 0x0802
197 #define FUNCTION_CLEAR_RQBUFFER 0x0803
198 #define FUNCTION_CLEAR_WQBUFFER 0x0804
199 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
200 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806
201 #define FUNCTION_SAY_HELLO 0x0807
202 #define FUNCTION_SAY_GOODBYE 0x0808
203 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
205 ************************************************************************
206 ** IOCTL CONTROL CODE
207 ************************************************************************
209 /* ARECA IO CONTROL CODE*/
210 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD)
211 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD)
212 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD)
213 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD)
214 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD)
215 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD)
216 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD)
217 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD)
218 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD)
220 /* ARECA IOCTL ReturnCode */
221 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
222 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
223 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
224 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088
226 ************************************************************************
227 ** SPEC. for Areca HBB adapter
228 ************************************************************************
230 /* ARECA HBB COMMAND for its FIRMWARE */
231 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */
232 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
233 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */
234 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
236 /* ARECA FLAG LANGUAGE */
237 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
238 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */
239 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
240 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
242 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
243 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
244 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
246 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
247 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
248 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
249 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
250 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
251 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
252 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
253 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
254 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
255 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
257 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
258 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */
259 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
260 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
261 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */
263 /* data tunnel buffer between user space program and its firmware */
264 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */
265 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */
266 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */
267 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010
268 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018
269 #define ARCMSR_HBB_BASE0_LEN 0x00021000
270 #define ARCMSR_HBB_BASE1_LEN 0x00010000
272 ************************************************************************
273 ** SPEC. for Areca HBC adapter
274 ************************************************************************
276 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
277 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
278 /* Host Interrupt Mask */
279 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
280 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
281 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
282 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
283 /* Host Interrupt Status */
284 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
286 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
287 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
289 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
291 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
292 ** value. This bit clears only when Outbound Doorbell bits
293 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
294 ** Clear register clears bits in the Outbound Doorbell register.
296 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
298 ** Set whenever the Outbound Post List Producer/Consumer
299 ** Register (FIFO) is not empty. It clears when the Outbound
300 ** Post List FIFO is empty.
302 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
304 ** This bit indicates a SAS interrupt from a source external to
305 ** the PCIe core. This bit is not maskable.
308 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/
309 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/
310 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/
311 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/
312 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/
313 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/
314 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/
315 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/
316 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/
317 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/
318 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
321 *************************************************************
322 ** structure for holding DMA address data
323 *************************************************************
325 #define IS_SG64_ADDR 0x01000000 /* bit24 */
327 ************************************************************************************************
328 ** ARECA FIRMWARE SPEC
329 ************************************************************************************************
330 ** Usage of IOP331 adapter
331 ** (All In/Out is in IOP331's view)
332 ** 1. Message 0 --> InitThread message and retrun code
333 ** 2. Doorbell is used for RS-232 emulation
334 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK)
335 ** bit1 -- data out has been read (DRIVER DATA READ OK)
336 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK)
337 ** bit1 -- data in has been read (IOP331 DATA READ OK)
338 ** 3. Index Memory Usage
339 ** offset 0xf00 : for RS232 out (request buffer)
340 ** offset 0xe00 : for RS232 in (scratch buffer)
341 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
342 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver)
343 ** 4. RS-232 emulation
344 ** Currently 128 byte buffer is used
345 ** 1st u_int32_t : Data length (1--124)
346 ** Byte 4--127 : Max 124 bytes of data
348 ** All SCSI Command must be sent through postQ:
349 ** (inbound queue port) Request frame must be 32 bytes aligned
350 ** # bit27--bit31 => flag for post ccb
351 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
352 ** bit31 : 0 : 256 bytes frame
353 ** 1 : 512 bytes frame
354 ** bit30 : 0 : normal request
359 ** -------------------------------------------------------------------------------
360 ** (outbount queue port) Request reply
361 ** # bit27--bit31 => flag for reply
362 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
363 ** bit31 : must be 0 (for this type of reply)
364 ** bit30 : reserved for BIOS handshake
366 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
367 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData
370 ** All BIOS request is the same with request from PostQ
372 ** Request frame is sent from configuration space
373 ** offset: 0x78 : Request Frame (bit30 == 1)
374 ** offset: 0x18 : writeonly to generate IRQ to IOP331
375 ** Completion of request:
376 ** (bit30 == 0, bit28==err flag)
377 ** 7. Definition of SGL entry (structure)
378 ** 8. Message1 Out - Diag Status Code (????)
379 ** 9. Message0 message code :
381 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver)
382 ** Signature 0x87974060(4)
383 ** Request len 0x00000200(4)
384 ** numbers of queue 0x00000100(4)
385 ** SDRAM Size 0x00000100(4)-->256 MB
386 ** IDE Channels 0x00000008(4)
387 ** vendor 40 bytes char
388 ** model 8 bytes char
389 ** FirmVer 16 bytes char
390 ** Device Map 16 bytes char
392 ** FirmwareVersion DWORD <== Added for checking of new firmware capability
393 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
394 ** Signature 0x87974063(4)
395 ** UPPER32 of Request Frame (4)-->Driver Only
396 ** 0x03 : Reset (Abort all queued Command)
397 ** 0x04 : Stop Background Activity
398 ** 0x05 : Flush Cache
399 ** 0x06 : Start Background Activity (re-start if background is halted)
400 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
401 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331)
402 ** byte 0 : 0xaa <-- signature
403 ** byte 1 : 0x55 <-- signature
404 ** byte 2 : year (04)
405 ** byte 3 : month (1..12)
406 ** byte 4 : date (1..31)
407 ** byte 5 : hour (0..23)
408 ** byte 6 : minute (0..59)
409 ** byte 7 : second (0..59)
410 ** *********************************************************************************
411 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter
412 ** ==> Difference from IOP348
413 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code
414 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP)
415 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code
416 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code
417 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver)
418 ** <A> use doorbell to generate interrupt
420 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop)
421 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver)
423 ** a. Message1: Out - Diag Status Code (????)
425 ** b. Message0: message code
427 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver)
428 ** Signature 0x87974060(4)
429 ** Request len 0x00000200(4)
430 ** numbers of queue 0x00000100(4)
431 ** SDRAM Size 0x00000100(4)-->256 MB
432 ** IDE Channels 0x00000008(4)
433 ** vendor 40 bytes char
434 ** model 8 bytes char
435 ** FirmVer 16 bytes char
436 ** Device Map 16 bytes char
437 ** cfgVersion ULONG <== Added for checking of new firmware capability
438 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP)
439 ** Signature 0x87974063(4)
440 ** UPPER32 of Request Frame (4)-->Driver Only
441 ** 0x03 : Reset (Abort all queued Command)
442 ** 0x04 : Stop Background Activity
443 ** 0x05 : Flush Cache
444 ** 0x06 : Start Background Activity (re-start if background is halted)
445 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
446 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP)
447 ** byte 0 : 0xaa <-- signature
448 ** byte 1 : 0x55 <-- signature
449 ** byte 2 : year (04)
450 ** byte 3 : month (1..12)
451 ** byte 4 : date (1..31)
452 ** byte 5 : hour (0..23)
453 ** byte 6 : minute (0..59)
454 ** byte 7 : second (0..59)
456 ** <2> Doorbell Register is used for RS-232 emulation
457 ** <A> different clear register
458 ** <B> different bit0 definition (bit0 is reserved)
460 ** inbound doorbell : at offset 0x20
461 ** inbound doorbell clear : at offset 0x70
463 ** inbound doorbell : bit0 -- reserved
464 ** bit1 -- data in ready (DRIVER DATA WRITE OK)
465 ** bit2 -- data out has been read (DRIVER DATA READ OK)
466 ** bit3 -- inbound message 0 ready
467 ** bit4 -- more than 12 request completed in a time
469 ** outbound doorbell : at offset 0x9C
470 ** outbound doorbell clear : at offset 0xA0
472 ** outbound doorbell : bit0 -- reserved
473 ** bit1 -- data out ready (IOP DATA WRITE OK)
474 ** bit2 -- data in has been read (IOP DATA READ OK)
475 ** bit3 -- outbound message 0 ready
477 ** <3> Index Memory Usage (Buffer Area)
478 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer)
479 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer)
480 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver)
481 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP)
483 ** <4> PostQ (Command Post Address)
484 ** All SCSI Command must be sent through postQ:
485 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43
486 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper)
487 ** outbound queue port32 at offset 0x44
488 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper)
489 ** <A> For 32bit queue, access low part is enough to send/receive request
490 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the
491 ** same for outbound queue port
492 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction
493 ** to post inbound request in a single instruction, and use 64bit instruction
494 ** to retrieve outbound request in a single instruction.
495 ** If in 32bit environment, when sending inbound queue, write high part first
496 ** then write low part. For receiving outbound request, read high part first
497 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF.
498 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the
499 ** consistency of the FIFO. Another way to check empty is to check status flag
501 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned)
502 ** For BIOS, 16bytes aligned is OK
503 ** For Driver, 32bytes alignment is recommended.
504 ** POST Command bit0 to bit3 is defined differently
505 ** ----------------------------
506 ** bit0:1 for PULL mode (must be 1)
507 ** ----------------------------
508 ** bit3/2/1: for arcmsr cdb size (arccdbsize)
509 ** 000: <= 0x0080 (128)
510 ** 001: <= 0x0100 (256)
511 ** 010: <= 0x0180 (384)
512 ** 011: <= 0x0200 (512)
513 ** 100: <= 0x0280 (640)
514 ** 101: <= 0x0300 (768)
515 ** 110: <= 0x0300 (reserved)
516 ** 111: <= 0x0300 (reserved)
517 ** -----------------------------
518 ** if len > 0x300 the len always set as 0x300
519 ** -----------------------------
520 ** post addr = addr | ((len-1) >> 6) | 1
521 ** -----------------------------
522 ** page length in command buffer still required,
524 ** if page length > 3,
525 ** firmware will assume more request data need to be retrieved
527 ** <D> Outbound Posting
528 ** bit0:0 , no error, 1 with error, refer to status buffer
529 ** bit1:0 , reserved (will be 0)
530 ** bit2:0 , reserved (will be 0)
531 ** bit3:0 , reserved (will be 0)
532 ** bit63-4: Completed command address
534 ** <E> BIOS support, no special support is required.
535 ** LSI2108 support I/O register
536 ** All driver functionality is supported through I/O address
538 ** For further spec, refer to
539 ** \spec\lsi\2108 for Areca\2108\LSISAS2108_PG_NoEncryption.pdf : Chapter 8 (8-11/8-28)
540 ** \spec\lsi\2108 for Areca\2108\SAS2108_RM_20.pdf : for configuration space
541 ************************************************************************************************
543 /* signature of set and get firmware config */
544 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
545 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
546 /* message code of inbound message register */
547 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
548 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
549 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
550 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
551 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
552 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
553 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
554 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
555 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
556 /* doorbell interrupt generator */
557 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
558 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
559 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
560 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
561 /* srb areca cdb flag */
562 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000
563 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000
564 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000
565 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000
566 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000
567 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001
568 /* outbound firmware ok */
569 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
571 **********************************
573 **********************************
576 /* 32bit Scatter-Gather list */
577 struct SG32ENTRY { /* length bit 24 == 0 */
578 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
582 /* 64bit Scatter-Gather list */
583 struct SG64ENTRY { /* length bit 24 == 1 */
584 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
586 u_int32_t addresshigh;
588 struct SGENTRY_UNION {
590 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */
591 struct SG64ENTRY sg64entry; /* 30h */
595 **********************************
597 **********************************
604 ************************************************************************************************
606 ************************************************************************************************
608 #define ARCMSR_FW_MODEL_OFFSET 15
609 #define ARCMSR_FW_VERS_OFFSET 17
610 #define ARCMSR_FW_DEVMAP_OFFSET 21
611 #define ARCMSR_FW_CFGVER_OFFSET 25
613 struct FIRMWARE_INFO {
614 u_int32_t signature; /*0,00-03*/
615 u_int32_t request_len; /*1,04-07*/
616 u_int32_t numbers_queue; /*2,08-11*/
617 u_int32_t sdram_size; /*3,12-15*/
618 u_int32_t ide_channels; /*4,16-19*/
619 char vendor[40]; /*5,20-59*/
620 char model[8]; /*15,60-67*/
621 char firmware_ver[16]; /*17,68-83*/
622 char device_map[16]; /*21,84-99*/
623 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
624 char cfgSerial[16]; /*26,104-119*/
625 u_int32_t cfgPicStatus; /*30,120-123*/
627 /* (A) For cfgVersion in FIRMWARE_INFO
628 ** if low BYTE (byte#0) >= 3 (version 3)
629 ** then byte#1 report the capability of the firmware can xfer in a single request
639 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages
640 ** Driver support new xfer method need to set this field to indicate
641 ** large CDB block in 0x100 unit (we use 0x100 byte as one page)
642 ** e.g. If the length of CDB including MSG header and SGL is 0x1508
643 ** driver need to set the msgPages to 0x16
644 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length
645 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag
655 ************************************************************************************************
657 ************************************************************************************************
660 u_int8_t Bus; /* 00h should be 0 */
661 u_int8_t TargetID; /* 01h should be 0--15 */
662 u_int8_t LUN; /* 02h should be 0--7 */
663 u_int8_t Function; /* 03h should be 1 */
665 u_int8_t CdbLength; /* 04h not used now */
666 u_int8_t sgcount; /* 05h */
667 u_int8_t Flags; /* 06h */
668 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */
669 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */
670 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */
671 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
672 #define ARCMSR_CDB_FLAG_HEADQ 0x08
673 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
674 u_int8_t msgPages; /* 07h */
676 u_int32_t Context; /* 08h Address of this request */
677 u_int32_t DataLength; /* 0ch not used now */
679 u_int8_t Cdb[16]; /* 10h SCSI CDB */
681 ********************************************************
682 **Device Status : the same from SCSI bus if error occur
683 ** SCSI bus status codes.
684 ********************************************************
686 u_int8_t DeviceStatus; /* 20h if error */
687 #define SCSISTAT_GOOD 0x00
688 #define SCSISTAT_CHECK_CONDITION 0x02
689 #define SCSISTAT_CONDITION_MET 0x04
690 #define SCSISTAT_BUSY 0x08
691 #define SCSISTAT_INTERMEDIATE 0x10
692 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14
693 #define SCSISTAT_RESERVATION_CONFLICT 0x18
694 #define SCSISTAT_COMMAND_TERMINATED 0x22
695 #define SCSISTAT_QUEUE_FULL 0x28
696 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
697 #define ARCMSR_DEV_ABORTED 0xF1
698 #define ARCMSR_DEV_INIT_FAIL 0xF2
700 u_int8_t SenseData[15]; /* 21h output */
703 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */
704 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */
708 *********************************************************************
709 ** Command Control Block (SrbExtension)
710 ** SRB must be not cross page boundary,and the order from offset 0
711 ** structure describing an ATA disk request
712 ** this SRB length must be 32 bytes boundary
713 *********************************************************************
715 struct CommandControlBlock {
716 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
717 u_int32_t cdb_shifted_phyaddr; /* 504-507 */
718 u_int32_t arc_cdb_size; /* 508-511 */
719 /* ======================512+32 bytes============================ */
720 #if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__) || defined(__sparc64__) || defined(__powerpc__)
721 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
722 struct AdapterControlBlock *acb; /* 520-523 524-527 */
723 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
724 u_int16_t srb_flags; /* 536-537 */
725 u_int16_t startdone; /* 538-539 */
726 u_int32_t reserved2; /* 540-543 */
728 union ccb *pccb; /* 512-515 pointer of freebsd scsi command */
729 struct AdapterControlBlock *acb; /* 516-519 */
730 bus_dmamap_t dm_segs_dmamap; /* 520-523 */
731 u_int16_t srb_flags; /* 524-525 */
732 u_int16_t startdone; /* 526-527 */
733 u_int32_t reserved2[4]; /* 528-531 532-535 536-539 540-543 */
735 /* ========================================================== */
736 /* struct callout ccb_callout; */
739 #define SRB_FLAG_READ 0x0000
740 #define SRB_FLAG_WRITE 0x0001
741 #define SRB_FLAG_ERROR 0x0002
742 #define SRB_FLAG_FLUSHCACHE 0x0004
743 #define SRB_FLAG_MASTER_ABORTED 0x0008
744 #define SRB_FLAG_DMAVALID 0x0010
745 #define SRB_FLAG_DMACONSISTENT 0x0020
746 #define SRB_FLAG_DMAWRITE 0x0040
747 #define SRB_FLAG_PKTBIND 0x0080
749 #define ARCMSR_SRB_DONE 0x0000
750 #define ARCMSR_SRB_UNBUILD 0x0000
751 #define ARCMSR_SRB_TIMEOUT 0x1111
752 #define ARCMSR_SRB_RETRY 0x2222
753 #define ARCMSR_SRB_START 0x55AA
754 #define ARCMSR_SRB_PENDING 0xAA55
755 #define ARCMSR_SRB_RESET 0xA5A5
756 #define ARCMSR_SRB_ABORTED 0x5A5A
757 #define ARCMSR_SRB_ILLEGAL 0xFFFF
759 *********************************************************************
760 ** Adapter Control Block
761 *********************************************************************
763 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */
764 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */
765 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */
766 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */
768 struct AdapterControlBlock {
769 u_int32_t adapter_type; /* adapter A,B..... */
771 bus_space_tag_t btag[2];
772 bus_space_handle_t bhandle[2];
773 bus_dma_tag_t parent_dmat;
774 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */
775 bus_dma_tag_t srb_dmat; /* dmat for freesrb */
776 bus_dmamap_t srb_dmamap;
778 struct cdev * ioctl_dev;
781 struct resource * sys_res_arcmsr[2];
782 struct resource * irqres;
783 void * ih; /* interrupt handle */
785 /* Hooks into the CAM XPT */
786 struct cam_sim *psim;
787 struct cam_path *ppath;
788 u_int8_t * uncacheptr;
789 unsigned long vir2phy_offset;
791 unsigned long phyaddr;
793 u_int32_t phyadd_low;
794 u_int32_t phyadd_high;
797 // unsigned long srb_phyaddr;
798 /* Offset is used in making arc cdb physical to virtual calculations */
799 u_int32_t outbound_int_enable;
801 struct MessageUnit_UNION * pmu; /* message unit ATU inbound base address0 */
803 u_int8_t adapter_index; /* */
805 u_int16_t acb_flags; /* */
807 struct CommandControlBlock * psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */
808 struct CommandControlBlock * srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */
809 int32_t workingsrb_doneindex; /* done srb array index */
810 int32_t workingsrb_startindex; /* start srb array index */
811 int32_t srboutstandingcount;
813 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */
814 u_int32_t rqbuf_firstindex; /* first of read buffer */
815 u_int32_t rqbuf_lastindex; /* last of read buffer */
817 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */
818 u_int32_t wqbuf_firstindex; /* first of write buffer */
819 u_int32_t wqbuf_lastindex; /* last of write buffer */
821 arcmsr_lock_t workingQ_done_lock;
822 arcmsr_lock_t workingQ_start_lock;
823 arcmsr_lock_t qbuffer_lock;
825 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
826 u_int32_t num_resets;
827 u_int32_t num_aborts;
828 u_int32_t firm_request_len; /*1,04-07*/
829 u_int32_t firm_numbers_queue; /*2,08-11*/
830 u_int32_t firm_sdram_size; /*3,12-15*/
831 u_int32_t firm_ide_channels; /*4,16-19*/
832 u_int32_t firm_cfg_version;
833 char firm_model[12]; /*15,60-67*/
834 char firm_version[20]; /*17,68-83*/
835 char device_map[20]; /*21,84-99 */
836 struct callout devmap_callout;
837 };/* HW_DEVICE_EXTENSION */
839 #define ACB_F_SCSISTOPADAPTER 0x0001
840 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
841 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
842 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
843 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
844 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
845 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040
846 #define ACB_F_BUS_RESET 0x0080
847 #define ACB_F_IOP_INITED 0x0100 /* iop init */
848 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */
849 #define ACB_F_CAM_DEV_QFRZN 0x0400
850 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */
851 #define ACB_F_SRB_FUNCTION_POWER 0x1000
853 #define ARECA_RAID_GONE 0x55
854 #define ARECA_RAID_GOOD 0xaa
856 *********************************************************************
857 ** Message Unit structure
858 *********************************************************************
860 struct HBA_MessageUnit
862 u_int32_t resrved0[4]; /*0000 000F*/
863 u_int32_t inbound_msgaddr0; /*0010 0013*/
864 u_int32_t inbound_msgaddr1; /*0014 0017*/
865 u_int32_t outbound_msgaddr0; /*0018 001B*/
866 u_int32_t outbound_msgaddr1; /*001C 001F*/
867 u_int32_t inbound_doorbell; /*0020 0023*/
868 u_int32_t inbound_intstatus; /*0024 0027*/
869 u_int32_t inbound_intmask; /*0028 002B*/
870 u_int32_t outbound_doorbell; /*002C 002F*/
871 u_int32_t outbound_intstatus; /*0030 0033*/
872 u_int32_t outbound_intmask; /*0034 0037*/
873 u_int32_t reserved1[2]; /*0038 003F*/
874 u_int32_t inbound_queueport; /*0040 0043*/
875 u_int32_t outbound_queueport; /*0044 0047*/
876 u_int32_t reserved2[2]; /*0048 004F*/
877 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/
878 u_int32_t reserved4[128]; /*0800 09FF 128*/
879 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/
880 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/
881 u_int32_t reserved5[32]; /*0E80 0EFF 32*/
882 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/
883 u_int32_t reserved6[32]; /*0F80 0FFF 32*/
886 *********************************************************************
888 *********************************************************************
892 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */
893 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
894 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */
895 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */
896 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */
899 *********************************************************************
901 *********************************************************************
905 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */
906 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */
907 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
908 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/
909 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
912 *********************************************************************
914 *********************************************************************
916 struct HBB_MessageUnit
918 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */
919 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */
920 int32_t postq_index; /* post queue index */
921 int32_t doneq_index; /* done queue index */
922 struct HBB_DOORBELL *hbb_doorbell;
923 struct HBB_RWBUFFER *hbb_rwbuffer;
927 *********************************************************************
929 *********************************************************************
931 struct HBC_MessageUnit {
932 u_int32_t message_unit_status; /*0000 0003*/
933 u_int32_t slave_error_attribute; /*0004 0007*/
934 u_int32_t slave_error_address; /*0008 000B*/
935 u_int32_t posted_outbound_doorbell; /*000C 000F*/
936 u_int32_t master_error_attribute; /*0010 0013*/
937 u_int32_t master_error_address_low; /*0014 0017*/
938 u_int32_t master_error_address_high; /*0018 001B*/
939 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/
940 u_int32_t inbound_doorbell; /*0020 0023*/
941 u_int32_t diagnostic_rw_data; /*0024 0027*/
942 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
943 u_int32_t diagnostic_rw_address_high; /*002C 002F*/
944 u_int32_t host_int_status; /*0030 0033 host interrupt status*/
945 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
946 u_int32_t dcr_data; /*0038 003B*/
947 u_int32_t dcr_address; /*003C 003F*/
948 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
949 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
950 u_int32_t hcb_pci_address_low; /*0048 004B*/
951 u_int32_t hcb_pci_address_high; /*004C 004F*/
952 u_int32_t iop_int_status; /*0050 0053*/
953 u_int32_t iop_int_mask; /*0054 0057*/
954 u_int32_t iop_inbound_queue_port; /*0058 005B*/
955 u_int32_t iop_outbound_queue_port; /*005C 005F*/
956 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/
957 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/
958 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/
959 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/
960 u_int32_t inbound_doorbell_clear; /*0070 0073*/
961 u_int32_t i2o_message_unit_control; /*0074 0077*/
962 u_int32_t last_used_message_source_address_low; /*0078 007B*/
963 u_int32_t last_used_message_source_address_high; /*007C 007F*/
964 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/
965 u_int32_t message_dest_address_index; /*0090 0093*/
966 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
967 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
968 u_int32_t outbound_doorbell; /*009C 009F*/
969 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
970 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/
971 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/
972 u_int32_t reserved0; /*00AC 00AF*/
973 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
974 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
975 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
976 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
977 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
978 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
979 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
980 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
981 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
982 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
983 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
984 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
985 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/
986 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/
987 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/
988 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/
989 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/
990 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/
991 u_int32_t host_diagnostic; /*00F8 00FB*/
992 u_int32_t write_sequence; /*00FC 00FF*/
993 u_int32_t reserved1[34]; /*0100 0187*/
994 u_int32_t reserved2[1950]; /*0188 1FFF*/
995 u_int32_t message_wbuffer[32]; /*2000 207F*/
996 u_int32_t reserved3[32]; /*2080 20FF*/
997 u_int32_t message_rbuffer[32]; /*2100 217F*/
998 u_int32_t reserved4[32]; /*2180 21FF*/
999 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
1003 *********************************************************************
1005 *********************************************************************
1007 struct MessageUnit_UNION
1010 struct HBA_MessageUnit hbamu;
1011 struct HBB_MessageUnit hbbmu;
1012 struct HBC_MessageUnit hbcmu;
1017 *************************************************************
1018 *************************************************************
1021 u_int8_t ErrorCode:7;
1023 u_int8_t SegmentNumber;
1024 u_int8_t SenseKey:4;
1025 u_int8_t Reserved:1;
1026 u_int8_t IncorrectLength:1;
1027 u_int8_t EndOfMedia:1;
1028 u_int8_t FileMark:1;
1029 u_int8_t Information[4];
1030 u_int8_t AdditionalSenseLength;
1031 u_int8_t CommandSpecificInformation[4];
1032 u_int8_t AdditionalSenseCode;
1033 u_int8_t AdditionalSenseCodeQualifier;
1034 u_int8_t FieldReplaceableUnitCode;
1035 u_int8_t SenseKeySpecific[3];
1038 **********************************
1039 ** Peripheral Device Type definitions
1040 **********************************
1042 #define SCSI_DASD 0x00 /* Direct-access Device */
1043 #define SCSI_SEQACESS 0x01 /* Sequential-access device */
1044 #define SCSI_PRINTER 0x02 /* Printer device */
1045 #define SCSI_PROCESSOR 0x03 /* Processor device */
1046 #define SCSI_WRITEONCE 0x04 /* Write-once device */
1047 #define SCSI_CDROM 0x05 /* CD-ROM device */
1048 #define SCSI_SCANNER 0x06 /* Scanner device */
1049 #define SCSI_OPTICAL 0x07 /* Optical memory device */
1050 #define SCSI_MEDCHGR 0x08 /* Medium changer device */
1051 #define SCSI_COMM 0x09 /* Communications device */
1052 #define SCSI_NODEV 0x1F /* Unknown or no device type */
1054 ************************************************************************************************************
1055 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1056 ** 80331 PCI-to-PCI Bridge
1057 ** PCI Configuration Space
1059 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1060 ** Programming Interface
1061 ** ========================
1062 ** Configuration Register Address Space Groupings and Ranges
1063 ** =============================================================
1064 ** Register Group Configuration Offset
1065 ** -------------------------------------------------------------
1066 ** Standard PCI Configuration 00-3Fh
1067 ** -------------------------------------------------------------
1068 ** Device Specific Registers 40-A7h
1069 ** -------------------------------------------------------------
1071 ** -------------------------------------------------------------
1072 ** Enhanced Capability List CC-FFh
1073 ** ==========================================================================================================
1074 ** Standard PCI [Type 1] Configuration Space Address Map
1075 ** **********************************************************************************************************
1076 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1077 ** ----------------------------------------------------------------------------------------------------------
1078 ** | Device ID | Vendor ID | 00h
1079 ** ----------------------------------------------------------------------------------------------------------
1080 ** | Primary Status | Primary Command | 04h
1081 ** ----------------------------------------------------------------------------------------------------------
1082 ** | Class Code | RevID | 08h
1083 ** ----------------------------------------------------------------------------------------------------------
1084 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch
1085 ** ----------------------------------------------------------------------------------------------------------
1087 ** ----------------------------------------------------------------------------------------------------------
1089 ** ----------------------------------------------------------------------------------------------------------
1090 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h
1091 ** ----------------------------------------------------------------------------------------------------------
1092 ** | Secondary Status | I/O Limit | I/O Base | 1Ch
1093 ** ----------------------------------------------------------------------------------------------------------
1094 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h
1095 ** ----------------------------------------------------------------------------------------------------------
1096 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h
1097 ** ----------------------------------------------------------------------------------------------------------
1098 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h
1099 ** ----------------------------------------------------------------------------------------------------------
1100 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch
1101 ** ----------------------------------------------------------------------------------------------------------
1102 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h
1103 ** ----------------------------------------------------------------------------------------------------------
1104 ** | Reserved | Capabilities Pointer | 34h
1105 ** ----------------------------------------------------------------------------------------------------------
1107 ** ----------------------------------------------------------------------------------------------------------
1108 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch
1109 **=============================================================================================================
1112 **=============================================================================================================
1114 ** Bit Default Description
1115 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG.
1116 ** ID is unique per product speed as indicated.
1117 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor.
1118 **=============================================================================================================
1120 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/
1121 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/
1123 **==============================================================================
1124 ** 0x05-0x04 : command register
1125 ** Bit Default Description
1126 **15:11 00h Reserved
1127 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus.
1128 ** The bridge does not support interrupts.
1129 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back
1130 ** transactions on the primary bus.
1131 ** The bridge does not generate fast back to back
1132 ** transactions on the primary bus.
1133 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions.
1134 ** 0=The bridge does not assert P_SERR#.
1135 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria.
1136 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating
1137 ** that bridge does not perform address or data stepping,
1138 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error.
1139 ** 0=When a data parity error is detected bridge does not assert S_PERR#.
1140 ** Also bridge does not assert P_SERR# in response to
1141 ** a detected address or attribute parity error.
1142 ** 1=When a data parity error is detected bridge asserts S_PERR#.
1143 ** The bridge also asserts P_SERR#
1144 ** (when enabled globally via bit(8) of this register)
1145 ** in response to a detected address or attribute parity error.
1146 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions.
1147 ** VGA palette write transactions are I/O transactions
1148 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h
1149 ** P_AD[15:10] are not decoded (i.e. aliases are claimed),
1150 ** or are fully decoding
1151 ** (i.e., must be all 0's depending upon the VGA
1152 ** aliasing bit in the Bridge Control Register, offset 3Eh.
1153 ** P_AD[31:16] equal to 0000h
1154 ** 0=The bridge ignores VGA palette write transactions,
1155 ** unless decoded by the standard I/O address range window.
1156 ** 1=The bridge responds to VGA palette write transactions
1157 ** with medium DEVSEL# timing and forwards them to the secondary bus.
1158 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions.
1159 ** MWI transactions targeting resources on the opposite side of the bridge,
1160 ** however, are forwarded as MWI transactions.
1161 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions.
1162 ** This bit is read only and always returns 0 when read
1163 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface.
1164 ** Initiation of configuration transactions is not affected by the state of this bit.
1165 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface.
1166 ** 1=The bridge is enabled to function as an initiator on the primary interface.
1167 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface.
1168 ** 0=The bridge target response to memory transactions on the primary interface is disabled.
1169 ** 1=The bridge target response to memory transactions on the primary interface is enabled.
1170 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface.
1171 ** 0=The bridge target response to I/O transactions on the primary interface is disabled.
1172 ** 1=The bridge target response to I/O transactions on the primary interface is enabled.
1173 **==============================================================================
1175 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/
1176 #define PCI_DISABLE_INTERRUPT 0x0400
1178 **==============================================================================
1179 ** 0x07-0x06 : status register
1180 ** Bit Default Description
1181 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
1182 ** attribute or data parity error.
1183 ** This bit is set regardless of the state of the PER bit in the command register.
1184 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus.
1185 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when,
1186 ** acting as the initiator on the primary bus,
1187 ** its transaction (with the exception of special cycles)
1188 ** has been terminated with a Master Abort.
1189 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when,
1190 ** acting as the initiator on the primary bus,
1191 ** its transaction has been terminated with a Target Abort.
1192 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it,
1193 ** as the target of a transaction, terminates it with a Target Abort.
1194 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
1195 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface.
1196 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
1197 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
1198 ** The bridge is the current master on the primary bus
1199 ** S_PERR# is detected asserted or is asserted by bridge
1200 ** The Parity Error Response bit is set in the Command register
1201 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge
1202 ** is able to respond to fast back to back transactions on its primary interface.
1204 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable.
1206 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities.
1207 ** Offset 34h (Capability Pointer register)
1208 ** provides the offset for the first entry
1209 ** in the linked list of enhanced capabilities.
1210 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function.
1211 ** The bridge does not support interrupts.
1212 ** 02:00 000 Reserved
1213 **==============================================================================
1215 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */
1216 #define ARCMSR_ADAP_66MHZ 0x20
1218 **==============================================================================
1219 ** 0x08 : revision ID
1220 ** Bit Default Description
1221 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping.
1222 **==============================================================================
1224 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/
1226 **==============================================================================
1227 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode )
1228 ** Bit Default Description
1229 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device.
1230 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge.
1231 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge.
1232 **==============================================================================
1234 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/
1236 **==============================================================================
1237 ** 0x0c : cache line size
1238 ** Bit Default Description
1239 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units.
1240 ** The contents of this register are factored into
1241 ** internal policy decisions associated with memory read prefetching,
1242 ** and the promotion of Memory Write transactions to MWI transactions.
1243 ** Valid cache line sizes are 8 and 16 dwords.
1244 ** When the cache line size is set to an invalid value,
1245 ** bridge behaves as though the cache line size was set to 00h.
1246 **==============================================================================
1248 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/
1250 **==============================================================================
1251 ** 0x0d : latency timer (number of pci clock 00-ff )
1252 ** Bit Default Description
1253 ** Primary Latency Timer (PTV):
1254 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles,
1255 ** referenced from the assertion of FRAME# to the expiration of the timer,
1256 ** when bridge may continue as master of the current transaction. All bits are writable,
1257 ** resulting in a granularity of 1 PCI clock cycle.
1258 ** When the timer expires (i.e., equals 00h)
1259 ** bridge relinquishes the bus after the first data transfer
1260 ** when its PCI bus grant has been deasserted.
1261 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer.
1262 ** Indicates the number of PCI clock cycles,
1263 ** referenced from the assertion of FRAME# to the expiration of the timer,
1264 ** when bridge may continue as master of the current transaction.
1265 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle.
1266 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
1267 ** (Except in the case where MLT expires within 3 data phases
1268 ** of an ADB.In this case bridge continues on
1269 ** until it reaches the next ADB before relinquishing the bus.)
1270 **==============================================================================
1272 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/
1274 **==============================================================================
1275 ** 0x0e : (header type,single function )
1276 ** Bit Default Description
1277 ** 07 0 Multi-function device (MVD): 80331 is a single-function device.
1278 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space.
1279 ** Returns ¡§01h¡¨ when read indicating
1280 ** that the register layout conforms to the standard PCI-to-PCI bridge layout.
1281 **==============================================================================
1283 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/
1285 **==============================================================================
1287 **==============================================================================
1290 **==============================================================================
1292 ** PCI CFG Base Address #0 (0x10)
1293 **==============================================================================
1296 **==============================================================================
1298 ** PCI CFG Base Address #1 (0x14)
1299 **==============================================================================
1302 **==============================================================================
1304 ** PCI CFG Base Address #2 (0x18)
1305 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
1306 ** Bit Default Description
1307 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge.
1308 ** Any Type 1 configuration cycle
1309 ** on the primary bus whose bus number is greater than the secondary bus number,
1310 ** and less than or equal to the subordinate bus number
1311 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus.
1312 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected.
1313 ** Any Type 1 configuration cycle matching this bus number
1314 ** is translated to a Type 0 configuration cycle (or a Special Cycle)
1315 ** before being executed on bridge's secondary PCI bus.
1316 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number.
1317 ** Any Type 1 configuration cycle on the primary interface
1318 ** with a bus number that is less than the contents
1319 ** of this register field does not be claimed by bridge.
1320 **-----------------0x1B--Secondary Latency Timer Register - SLTR
1321 ** Bit Default Description
1322 ** Secondary Latency Timer (STV):
1323 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer.
1324 ** Indicates the number of PCI clock cycles,
1325 ** referenced from the assertion of FRAME# to the expiration of the timer,
1326 ** when bridge may continue as master of the current transaction. All bits are writable,
1327 ** resulting in a granularity of 1 PCI clock cycle.
1328 ** When the timer expires (i.e., equals 00h)
1329 ** bridge relinquishes the bus after the first data transfer
1330 ** when its PCI bus grant has been deasserted.
1331 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer.
1332 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME#
1333 ** to the expiration of the timer,
1334 ** when bridge may continue as master of the current transaction. All bits are writable,
1335 ** resulting in a granularity of 1 PCI clock cycle.
1336 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
1337 ** (Except in the case where MLT expires within 3 data phases of an ADB.
1338 ** In this case bridge continues on until it reaches the next ADB
1339 ** before relinquishing the bus)
1340 **==============================================================================
1342 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/
1343 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/
1344 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/
1345 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/
1347 **==============================================================================
1349 ** PCI CFG Base Address #3 (0x1C)
1350 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
1351 ** Bit Default Description
1352 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to
1353 ** determine when to forward I/O transactions from one interface to the other.
1354 ** These bits correspond to address lines 15:12 for 4KB alignment.
1355 ** Bits 11:0 are assumed to be FFFh.
1356 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing.
1357 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of
1358 ** an address range to determine when to forward I/O transactions
1359 ** from one interface to the other.
1360 ** These bits correspond to address lines 15:12 for 4KB alignment.
1361 ** Bits 11:0 are assumed to be 000h.
1362 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing.
1363 **-----------------0x1F,0x1E--Secondary Status Register - SSR
1364 ** Bit Default Description
1365 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
1366 ** attribute or data parity error on its secondary interface.
1367 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface.
1368 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when,
1369 ** acting as the initiator on the secondary bus,
1370 ** it's transaction (with the exception of special cycles)
1371 ** has been terminated with a Master Abort.
1372 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when,
1373 ** acting as the initiator on the secondary bus,
1374 ** it's transaction has been terminated with a Target Abort.
1375 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it,
1376 ** as the target of a transaction, terminates it with a Target Abort.
1377 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
1378 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface.
1379 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
1380 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
1381 ** The bridge is the current master on the secondary bus
1382 ** S_PERR# is detected asserted or is asserted by bridge
1383 ** The Parity Error Response bit is set in the Command register
1384 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles.
1386 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable.
1388 ** 04:00 00h Reserved
1389 **==============================================================================
1391 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/
1392 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/
1393 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */
1395 **==============================================================================
1397 ** PCI CFG Base Address #4 (0x20)
1398 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
1399 ** Bit Default Description
1400 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
1401 ** the upper 1MB aligned value (exclusive) of the range.
1402 ** The incoming address must be less than or equal to this value.
1403 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1404 ** are assumed to be F FFFFh.
1405 ** 19:16 0h Reserved.
1406 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20]
1407 ** of the incoming address to determine the lower 1MB
1408 ** aligned value (inclusive) of the range.
1409 ** The incoming address must be greater than or equal to this value.
1410 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1411 ** are assumed to be 0 0000h.
1412 ** 03:00 0h Reserved.
1413 **==============================================================================
1415 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */
1416 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */
1418 **==============================================================================
1420 ** PCI CFG Base Address #5 (0x24)
1421 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
1422 ** Bit Default Description
1423 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
1424 ** the upper 1MB aligned value (exclusive) of the range.
1425 ** The incoming address must be less than or equal to this value.
1426 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1427 ** are assumed to be F FFFFh.
1428 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported.
1429 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20]
1430 ** of the incoming address to determine the lower 1MB aligned value (inclusive)
1432 ** The incoming address must be greater than or equal to this value.
1433 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1434 ** are assumed to be 0 0000h.
1435 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported.
1436 **==============================================================================
1438 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */
1439 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */
1441 **==============================================================================
1443 ** Bit Default Description
1444 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable
1445 ** bridge supports full 64-bit addressing.
1446 **==============================================================================
1448 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */
1450 **==============================================================================
1452 ** Bit Default Description
1453 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable
1454 ** bridge supports full 64-bit addressing.
1455 **==============================================================================
1457 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */
1459 **==============================================================================
1461 ** Bit Default Description
1462 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration
1463 ** space. (Power Management Capability Registers)
1464 **==============================================================================
1466 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/
1468 **==============================================================================
1469 ** 0x3b-0x35 : reserved
1470 **==============================================================================
1473 **==============================================================================
1476 ** Bit Default Description
1477 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts.
1478 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'.
1479 **==============================================================================
1481 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/
1482 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/
1484 **==============================================================================
1486 ** Bit Default Description
1487 ** 15:12 0h Reserved
1488 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response
1489 ** to a timer discard on either the primary or secondary interface.
1490 ** 0b=SERR# is not asserted.
1491 ** 1b=SERR# is asserted.
1492 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires.
1493 ** The delayed completion is then discarded.
1494 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles
1495 ** that bridge waits for an initiator on the secondary bus
1496 ** to repeat a delayed transaction request.
1497 ** The counter starts when the delayed transaction completion is ready
1498 ** to be returned to the initiator.
1499 ** When the initiator has not repeated the transaction
1500 ** at least once before the counter expires,bridge
1501 ** discards the delayed transaction from its queues.
1502 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles.
1503 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles.
1504 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles
1505 ** that bridge waits for an initiator on the primary bus
1506 ** to repeat a delayed transaction request.
1507 ** The counter starts when the delayed transaction completion
1508 ** is ready to be returned to the initiator.
1509 ** When the initiator has not repeated the transaction
1510 ** at least once before the counter expires,
1511 ** bridge discards the delayed transaction from its queues.
1512 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles.
1513 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles.
1514 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions.
1515 ** 06 0b Secondary Bus Reset (SBR):
1516 ** When cleared to 0b: The bridge deasserts S_RST#,
1517 ** when it had been asserted by writing this bit to a 1b.
1518 ** When set to 1b: The bridge asserts S_RST#.
1519 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus
1520 ** when a master abort termination occurs in response to
1521 ** a delayed transaction initiated by bridge on the target bus.
1522 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,
1523 ** and returns FFFF FFFFh when a read.
1524 ** 1b=When the transaction had not yet been completed on the initiator bus
1525 ** (e.g.,delayed reads, or non-posted writes),
1526 ** then bridge returns a Target Abort in response to the original requester
1527 ** when it returns looking for its delayed completion on the initiator bus.
1528 ** When the transaction had completed on the initiator bus (e.g., a PMW),
1529 ** then bridge asserts P_SERR# (when enabled).
1530 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort
1531 ** while attempting to deliver a posted memory write on the destination bus.
1532 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit
1533 ** (also of this register),
1534 ** and the VGA Palette Snoop Enable bit (Command Register).
1535 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b)
1536 ** the VGA Aliasing bit for the corresponding enabled functionality,:
1537 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses.
1538 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses.
1539 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b),
1540 ** then this bit has no impact on bridge behavior.
1541 ** 03 0b VGA Enable: Setting this bit enables address decoding
1542 ** and transaction forwarding of the following VGA transactions from the primary bus
1543 ** to the secondary bus:
1544 ** frame buffer memory addresses 000A0000h:000BFFFFh,
1545 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=¡§0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares),
1546 ** or must be ¡§000000b¡¨
1547 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register)
1548 ** I/O and Memory Enable bits must be set in the Command register
1549 ** to enable forwarding of VGA cycles.
1550 ** 02 0b ISA Enable: Setting this bit enables special handling
1551 ** for the forwarding of ISA I/O transactions that fall within the address range
1552 ** specified by the I/O Base and Limit registers,
1553 ** and are within the lowest 64Kbyte of the I/O address map
1554 ** (i.e., 0000 0000h - 0000 FFFFh).
1555 ** 0b=All I/O transactions that fall within the I/O Base
1556 ** and Limit registers' specified range are forwarded
1557 ** from primary to secondary unfiltered.
1558 ** 1b=Blocks the forwarding from primary to secondary
1559 ** of the top 768 bytes of each 1Kbyte alias.
1560 ** On the secondary the top 768 bytes of each 1K alias
1561 ** are inversely decoded and forwarded
1562 ** from secondary to primary.
1563 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion.
1564 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected
1565 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
1566 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error
1567 ** that is detected on its secondary interface.
1568 ** 0b=When a data parity error is detected bridge does not assert S_PERR#.
1569 ** Also bridge does not assert P_SERR# in response to a detected address
1570 ** or attribute parity error.
1571 ** 1b=When a data parity error is detected bridge asserts S_PERR#.
1572 ** The bridge also asserts P_SERR# (when enabled globally via bit(8)
1573 ** of the Command register)
1574 ** in response to a detected address or attribute parity error.
1575 **==============================================================================
1577 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/
1579 **************************************************************************
1580 ** Device Specific Registers 40-A7h
1581 **************************************************************************
1582 ** ----------------------------------------------------------------------------------------------------------
1583 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1584 ** ----------------------------------------------------------------------------------------------------------
1585 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h
1586 ** ----------------------------------------------------------------------------------------------------------
1587 ** | Bridge Control 2 | Bridge Control 1 | 44h
1588 ** ----------------------------------------------------------------------------------------------------------
1589 ** | Reserved | Bridge Status | 48h
1590 ** ----------------------------------------------------------------------------------------------------------
1592 ** ----------------------------------------------------------------------------------------------------------
1593 ** | Prefetch Policy | Multi-Transaction Timer | 50h
1594 ** ----------------------------------------------------------------------------------------------------------
1595 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h
1596 ** ----------------------------------------------------------------------------------------------------------
1597 ** | Reserved | Reserved | Secondary Decode Enable | 58h
1598 ** ----------------------------------------------------------------------------------------------------------
1599 ** | Reserved | Secondary IDSEL | 5Ch
1600 ** ----------------------------------------------------------------------------------------------------------
1602 ** ----------------------------------------------------------------------------------------------------------
1603 ** | Reserved | 68h:CBh
1604 ** ----------------------------------------------------------------------------------------------------------
1605 **************************************************************************
1606 **==============================================================================
1607 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
1608 ** Bit Default Description
1609 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule
1610 ** (PCI=16 clocks,PCI-X=6 clocks).
1611 ** Note that this field is only meaningful when:
1612 ** # Bit[11] of this register is set to 1b,
1613 ** indicating that a Grant Time-out violation had occurred.
1614 ** # bridge internal arbiter is enabled.
1615 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number)
1616 ** 0000b REQ#/GNT#[0]
1617 ** 0001b REQ#/GNT#[1]
1618 ** 0010b REQ#/GNT#[2]
1619 ** 0011b REQ#/GNT#[3]
1620 ** 1111b Default Value (no violation detected)
1621 ** When bit[11] is cleared by software, this field reverts back to its default value.
1622 ** All other values are Reserved
1623 ** 11 0b Grant Time-out Occurred: When set to 1b,
1624 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents.
1625 ** Software clears this bit by writing a 1b to it.
1626 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus.
1627 ** 1=During bus idle, bridge parks the bus on itself.
1628 ** The bus grant is removed from the last master and internally asserted to bridge.
1629 ** 09:08 00b Reserved
1630 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority.
1631 ** Each bit of this field assigns its corresponding secondary
1632 ** bus master to either the high priority arbiter ring (1b)
1633 ** or to the low priority arbiter ring (0b).
1634 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively.
1635 ** Bit [6] corresponds to the bridge internal secondary bus request
1636 ** while Bit [7] corresponds to the SATU secondary bus request.
1637 ** Bits [5:4] are unused.
1638 ** 0b=Indicates that the master belongs to the low priority group.
1639 ** 1b=Indicates that the master belongs to the high priority group
1640 **=================================================================================
1641 ** 0x43: Bridge Control Register 0 - BCR0
1642 ** Bit Default Description
1643 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight
1644 ** and the Posted Write data is limited to 4KB.
1645 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to
1646 ** 14 Posted Memory Write transactions and 8KB of posted write data.
1647 ** 06:03 0H Reserved.
1648 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability
1649 ** to perform upstream prefetch operations for Memory
1650 ** Read requests received on its secondary interface.
1651 ** This bit also controls the bridge's ability to generate advanced read commands
1652 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus
1653 ** to a Conventional PCI bus.
1654 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory.
1655 ** The use of Memory Read Line and Memory Read
1656 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request
1657 ** to an upstream bus operating in Conventional PCI mode.
1658 ** 1b=bridge treats upstream PCI Memory Read requests as though
1659 ** they target non-prefetchable memory and forwards upstream PCI-X Memory
1660 ** Read Block commands as Memory Read
1661 ** when the primary bus is operating
1662 ** in Conventional PCI mode.
1663 ** NOTE: This bit does not affect bridge ability to perform read prefetching
1664 ** when the received command is Memory Read Line or Memory Read Multiple.
1665 **=================================================================================
1666 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
1667 ** Bit Default Description
1668 ** 15:08 0000000b Reserved
1669 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ¡§Alias¡¨ commands,
1670 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands.
1671 ** The three options for handling these alias commands are to either pass it as is,
1672 ** re-map to the actual block memory read/write command encoding, or ignore
1673 ** the transaction forcing a Master Abort to occur on the Origination Bus.
1674 ** Bit (7:6) Handling of command
1675 ** 0 0 Re-map to Memory Read/Write Block before forwarding
1676 ** 0 1 Enqueue and forward the alias command code unaltered
1677 ** 1 0 Ignore the transaction, forcing Master Abort
1679 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions.
1680 ** The watchdog timers are used to detect prohibitively long latencies in the system.
1681 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request,
1682 ** or Split Requests (PCI-X mode) is not completed within 2 24 events
1683 ** (¡§events¡¨ are defined as PCI Clocks when operating in PCI-X mode,
1684 ** and as the number of times being retried when operating in Conventional PCI mode)
1685 ** 0b=All 2 24 watchdog timers are enabled.
1686 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to
1687 ** the number of attempts bridge makes when initiating a PMW,
1688 ** transacting a Delayed Transaction, or how long it waits for
1689 ** a split completion corresponding to one of its requests.
1690 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism.
1691 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X.
1692 ** 0b=The Secondary bus arbiter times out an agent
1693 ** that does not assert FRAME# within 16/6 clocks of receiving its grant,
1694 ** once the bus has gone idle.
1695 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted.
1696 ** An infringing agent does not receive a subsequent GNT#
1697 ** until it de-asserts its REQ# for at least one clock cycle.
1698 ** 1b=GNT# time-out mechanism is disabled.
1700 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism.
1701 ** The time out mechanism is used to ensure that initiators
1702 ** of delayed transactions return for their delayed completion data/status
1703 ** within a reasonable amount of time after it is available from bridge.
1704 ** 0b=The secondary master time-out counter is enabled
1705 ** and uses the value specified by the Secondary Discard Timer bit
1706 ** (see Bridge Control Register).
1707 ** 1b=The secondary master time-out counter is disabled.
1708 ** The bridge waits indefinitely for a secondary bus master
1709 ** to repeat a delayed transaction.
1710 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism.
1711 ** The time out mechanism is used to ensure that initiators
1712 ** of delayed transactions return for their delayed completion data/status
1713 ** within a reasonable amount of time after it is available from bridge.
1714 ** 0b=The primary master time-out counter is enabled and uses the value specified
1715 ** by the Primary Discard Timer bit (see Bridge Control Register).
1716 ** 1b=The secondary master time-out counter is disabled.
1717 ** The bridge waits indefinitely for a secondary bus master
1718 ** to repeat a delayed transaction.
1720 **=================================================================================
1721 ** 0x47-0x46: Bridge Control Register 2 - BCR2
1722 ** Bit Default Description
1723 ** 15:07 0000b Reserved.
1724 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable):
1725 ** This bit disables all of the secondary PCI clock outputs including
1726 ** the feedback clock S_CLKOUT.
1727 ** This means that the user is required to provide an S_CLKIN input source.
1728 ** 05:04 11 (66 MHz) Preserved.
1731 ** 03:00 Fh (100 MHz & 66 MHz)
1733 ** This 4 bit field provides individual enable/disable mask bits for each of bridge
1734 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0])
1735 ** default to being enabled following the rising edge of P_RST#, depending on the
1736 ** frequency of the secondary bus clock:
1737 ** ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with
1738 ** all four S_CLKOs enabled by default. (SCLKO[3:0])¡P
1739 ** ¡E Designs with 133 MHz Secondary PCI clock power up
1740 ** with the lower order 3 S_CLKOs enabled by default.
1741 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected
1742 ** to downstream device clock inputs.
1743 **=================================================================================
1744 ** 0x49-0x48: Bridge Status Register - BSR
1745 ** Bit Default Description
1746 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
1747 ** is conditionally asserted when the secondary discard timer expires.
1748 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired:
1749 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1750 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry.
1751 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1752 ** when bridge discards an upstream split read request
1753 ** after waiting in excess of 2 24 clocks for the corresponding
1754 ** Split Completion to arrive.
1755 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired:
1756 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1757 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry.
1758 ** PCI-X Mode: This bit is set to a 1b and P_SERR#
1759 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding
1760 ** Split Completion to arrive.
1761 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
1762 ** is conditionally asserted when a Master Abort occurs as a result of an attempt,
1763 ** by bridge, to retire a PMW upstream.
1764 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
1765 ** is conditionally asserted when a Target Abort occurs as a result of an attempt,
1766 ** by bridge, to retire a PMW upstream.
1767 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
1768 ** is conditionally asserted when bridge discards an upstream PMW transaction
1769 ** after receiving 2 24 target retries from the primary bus target
1770 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
1771 ** is conditionally asserted when a data parity error is detected by bridge
1772 ** while attempting to retire a PMW upstream
1773 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR#
1774 ** is conditionally asserted when bridge detects an address parity error on
1775 ** the secondary bus.
1776 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
1777 ** is conditionally asserted when the primary bus discard timer expires.
1778 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired:
1779 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1780 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries
1781 ** from the secondary bus target.
1782 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1783 ** when bridge discards a downstream split read request
1784 ** after waiting in excess of 2 24 clocks for the corresponding
1785 ** Split Completion to arrive.
1786 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired:
1787 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1788 ** when bridge discards a downstream delayed write transaction request
1789 ** after receiving 2 24 target retries from the secondary bus target.
1790 ** PCI-X Mode: This bit is set to a 1b and P_SERR#
1791 ** is conditionally asserted when bridge discards a downstream
1792 ** split write request after waiting in excess of 2 24 clocks
1793 ** for the corresponding Split Completion to arrive.
1794 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR#
1795 ** is conditionally asserted when a Master Abort occurs as a result of an attempt,
1796 ** by bridge, to retire a PMW downstream.
1797 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted
1798 ** when a Target Abort occurs as a result of an attempt, by bridge,
1799 ** to retire a PMW downstream.
1800 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
1801 ** is conditionally asserted when bridge discards a downstream PMW transaction
1802 ** after receiving 2 24 target retries from the secondary bus target
1803 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
1804 ** is conditionally asserted when a data parity error is detected by bridge
1805 ** while attempting to retire a PMW downstream.
1806 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted
1807 ** when bridge detects an address parity error on the primary bus.
1808 **==================================================================================
1809 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
1810 ** Bit Default Description
1811 ** 15:13 000b Reserved
1812 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks)
1813 ** that a secondary bus master has its grant maintained in order to enable
1814 ** multiple transactions to execute within the same arbitration cycle.
1815 ** Bit[02:00] GNT# Extended Duration
1816 ** 000 MTT Disabled (Default=no GNT# extension)
1822 ** 110 Invalid (treated as 000)
1823 ** 111 Invalid (treated as 000)
1824 ** 09:08 00b Reserved
1825 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT#
1826 ** pair supported by bridge secondary arbiter.
1827 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair,
1828 ** bit(6) corresponds to bridge internal REQ#/GNT# pair,
1829 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc.
1830 ** When a given bit is set to 1b, its corresponding REQ#/GNT#
1831 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register.
1832 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT.
1833 **==================================================================================
1834 ** 0x53-0x52: Read Prefetch Policy Register - RPPR
1835 ** Bit Default Description
1836 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor
1837 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied
1838 ** using the FirstRead parameter.
1839 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
1840 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines
1841 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating
1842 ** the number of bytes to prefetch from the secondary bus interface
1843 ** on the initial PreFetch operation.
1844 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
1845 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
1846 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
1847 ** in calculating the number of bytes to prefetch from the primary
1848 ** bus interface on subsequent PreFetch operations given
1849 ** that the read demands were not satisfied using
1850 ** the FirstRead parameter.
1851 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a
1852 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines
1853 ** Memory Read Multiple 6 cache lines
1854 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
1855 ** in calculating the number of bytes to prefetch from
1856 ** the primary bus interface on the initial PreFetch operation.
1857 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount
1858 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
1859 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch
1860 ** algorithm for the secondary and the primary bus interfaces.
1861 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual
1862 ** enable bits for REQ#/GNT#[2:0].
1863 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...)
1864 ** 1b: enables the staged pre-fetch feature
1865 ** 0b: disables staged pre-fetch,
1866 ** and hardwires read pre-fetch policy to the following for
1868 ** Memory Read Line,
1869 ** and Memory Read Multiple commands:
1870 ** Command Type Hardwired Pre-Fetch Amount...
1871 ** Memory Read 4 DWORDs
1872 ** Memory Read Line 1 cache line
1873 ** Memory Read Multiple 2 cache lines
1874 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands
1875 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read
1876 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
1877 **==================================================================================
1878 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL
1879 ** Bit Default Description
1880 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior
1881 ** in response to its discarding of a delayed transaction that was initiated from the primary bus.
1882 ** 0b=bridge asserts P_SERR#.
1883 ** 1b=bridge does not assert P_SERR#
1884 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
1885 ** 0b=bridge asserts P_SERR#.
1886 ** 1b=bridge does not assert P_SERR#
1887 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
1888 ** 0b=bridge asserts P_SERR#.
1889 ** 1b=bridge does not assert P_SERR#
1890 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following
1891 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream.
1892 ** 0b=bridge asserts P_SERR#.
1893 ** 1b=bridge does not assert P_SERR#
1894 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following
1895 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream.
1896 ** 0b=bridge asserts P_SERR#.
1897 ** 1b=bridge does not assert P_SERR#
1898 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that
1899 ** it discards an upstream posted write transaction.
1900 ** 0b=bridge asserts P_SERR#.
1901 ** 1b=bridge does not assert P_SERR#
1902 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior
1903 ** when a data parity error is detected while attempting to retire on of its PMWs upstream.
1904 ** 0b=bridge asserts P_SERR#.
1905 ** 1b=bridge does not assert P_SERR#
1906 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior
1907 ** when it detects an address parity error on the secondary bus.
1908 ** 0b=bridge asserts P_SERR#.
1909 ** 1b=bridge does not assert P_SERR#
1910 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to
1911 ** its discarding of a delayed transaction that was initiated on the secondary bus.
1912 ** 0b=bridge asserts P_SERR#.
1913 ** 1b=bridge does not assert P_SERR#
1914 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
1915 ** 0b=bridge asserts P_SERR#.
1916 ** 1b=bridge does not assert P_SERR#
1917 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
1918 ** 0b=bridge asserts P_SERR#.
1919 ** 1b=bridge does not assert P_SERR#
1920 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following
1921 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream.
1922 ** 0b=bridge asserts P_SERR#.
1923 ** 1b=bridge does not assert P_SERR#
1924 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following
1925 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream.
1926 ** 0b=bridge asserts P_SERR#.
1927 ** 1b=bridge does not assert P_SERR#
1928 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event
1929 ** that it discards a downstream posted write transaction.
1930 ** 0b=bridge asserts P_SERR#.
1931 ** 1b=bridge does not assert P_SERR#
1932 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior
1933 ** when a data parity error is detected while attempting to retire on of its PMWs downstream.
1934 ** 0b=bridge asserts P_SERR#.
1935 ** 1b=bridge does not assert P_SERR#
1936 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior
1937 ** when it detects an address parity error on the primary bus.
1938 ** 0b=bridge asserts P_SERR#.
1939 ** 1b=bridge does not assert P_SERR#
1940 **===============================================================================
1941 ** 0x56: Pre-Boot Status Register - PBSR
1942 ** Bit Default Description
1944 ** 06 - Reserved - value indeterminate
1946 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting:
1947 ** This bit reflect captured S_133EN strap,
1948 ** indicating the maximum secondary bus clock frequency when in PCI-X mode.
1949 ** Max Allowable Secondary Bus Frequency
1950 ** ** S_133EN PCI-X Mode
1954 **===============================================================================
1955 ** 0x59-0x58: Secondary Decode Enable Register - SDER
1956 ** Bit Default Description
1957 ** 15:03 FFF1h Preserved.
1958 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set,
1959 ** bridge overrides its secondary inverse decode logic and not
1960 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b.
1961 ** This creates a private memory space on the Secondary PCI bus
1962 ** that allows peer-to-peer transactions.
1963 ** 01:00 10 2 Preserved.
1964 **===============================================================================
1965 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR
1966 ** Bit Default Description
1967 ** 15:10 000000 2 Reserved.
1968 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set,
1969 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion.
1970 ** When this bit is clear,
1971 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion.
1972 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set,
1973 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion.
1974 ** When this bit is clear,
1975 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion.
1976 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set,
1977 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion.
1978 ** When this bit is clear,
1979 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion.
1980 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set,
1981 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion.
1982 ** When this bit is clear,
1983 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion.
1984 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set,
1985 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion.
1986 ** When this bit is clear,
1987 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion.
1988 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set,
1989 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion.
1990 ** When this bit is clear,
1991 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion.
1992 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set,
1993 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion.
1994 ** When this bit is clear,
1995 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion.
1996 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set,
1997 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion.
1998 ** When this bit is clear,
1999 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion.
2000 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set,
2001 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion.
2002 ** When this bit is clear,
2003 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion.
2004 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set,
2005 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion.
2006 ** When this bit is clear,
2007 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion.
2008 **************************************************************************
2011 **************************************************************************
2013 **************************************************************************
2016 **************************************************************************
2017 ** PCI Extended Enhanced Capabilities List CC-FFh
2018 **************************************************************************
2019 ** ----------------------------------------------------------------------------------------------------------
2020 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
2021 ** ----------------------------------------------------------------------------------------------------------
2022 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh
2023 ** ----------------------------------------------------------------------------------------------------------
2024 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h
2025 ** ----------------------------------------------------------------------------------------------------------
2026 ** | Reserved | Reserved | Reserved | E4h
2027 ** ----------------------------------------------------------------------------------------------------------
2029 ** ----------------------------------------------------------------------------------------------------------
2030 ** | Reserved | Reserved | Reserved | Reserved | ECh
2031 ** ----------------------------------------------------------------------------------------------------------
2032 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h
2033 ** ----------------------------------------------------------------------------------------------------------
2034 ** | PCI-X Bridge Status | F4h
2035 ** ----------------------------------------------------------------------------------------------------------
2036 ** | PCI-X Upstream Split Transaction Control | F8h
2037 ** ----------------------------------------------------------------------------------------------------------
2038 ** | PCI-X Downstream Split Transaction Control | FCh
2039 ** ----------------------------------------------------------------------------------------------------------
2040 **===============================================================================
2041 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID
2042 ** Bit Default Description
2043 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block
2044 **===============================================================================
2045 ** 0xDD: Next Item Pointer - PM_NXTP
2046 ** Bit Default Description
2047 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header.
2048 **===============================================================================
2049 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR
2050 ** Bit Default Description
2051 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge.
2052 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state.
2053 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state.
2054 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.
2055 ** This returns 000b as PME# wake-up for bridge is not implemented.
2056 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge.
2057 ** 04:03 00 Reserved
2058 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1.
2059 **===============================================================================
2060 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR
2061 ** Bit Default Description
2062 ** 15:09 00h Reserved
2063 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#.
2064 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
2065 ** 07:02 00h Reserved
2066 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of
2067 ** a function and to set the Function into a new power state.
2071 ** 11 - D3 hot state
2072 **===============================================================================
2073 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
2074 ** Bit Default Description
2075 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled.
2076 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that
2077 ** is to occur as a direct result of programming the function to D3 hot.
2078 ** This bit is only meaningful when bit 7 (BPCC_En) is a ¡§1¡¨.
2079 ** 05:00 00h Reserved
2080 **===============================================================================
2081 ** 0xE3: Power Management Data Register - PMDR
2082 ** Bit Default Description
2083 ** 07:00 00h Reserved
2084 **===============================================================================
2085 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID
2086 ** Bit Default Description
2087 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list.
2088 **===============================================================================
2089 ** 0xF1: Next Item Pointer - PX_NXTP
2090 ** Bit Default Description
2091 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this
2092 ** register is 00h indicating that this is the last entry in the linked list of capabilities.
2093 **===============================================================================
2094 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
2095 ** Bit Default Description
2096 ** 15:09 00h Reserved
2097 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus.
2099 ** ** BitsMax FrequencyClock Period
2100 ** ** 000PCI ModeN/A
2104 ** ** 1xxreservedreserved
2105 ** ** The default value for this register is the operating frequency of the secondary bus
2106 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the
2107 ** secondary bus to the primary bus because there is not enough room within the limit
2108 ** specified in the Split Transaction Commitment Limit field in the Downstream Split
2109 ** Transaction Control register. The bridge does not set this bit.
2110 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full.
2111 ** The bridge does not set this bit.
2112 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID
2113 ** equal to bridge secondary bus number, device number 00h,
2114 ** and function number 0 is received on the secondary interface.
2115 ** This bit is cleared by software writing a '1'.
2116 ** 02 0b Split Completion Discarded (SCD): This bit is set
2117 ** when bridge discards a split completion moving toward the secondary bus
2118 ** because the requester would not accept it. This bit cleared by software writing a '1'.
2119 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz
2120 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits.
2121 **===============================================================================
2122 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
2123 ** Bit Default Description
2125 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge.
2126 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge
2127 ** because bridge throttles traffic on the completion side.
2128 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b
2129 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears
2130 ** this bit by writing a 1b to it.
2131 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b
2132 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it.
2133 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode.
2134 ** 0=The maximum operating frequency is 66 MHz.
2135 ** 1=The maximum operating frequency is 133 MHz.
2136 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface.
2137 ** 0=Primary Interface is connected as a 32-bit PCI bus.
2138 ** 1=Primary Interface is connected as a 64-bit PCI bus.
2139 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field
2140 ** of the BNUM register at offset 18h.
2141 ** Apparently it was deemed necessary reflect it here for diagnostic purposes.
2142 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes.
2143 ** May be updated whenever a PCI-X
2144 ** configuration write cycle that targets bridge scores a hit.
2145 ** 02:00 0h Function Number (FNUM): The bridge Function #
2146 **===============================================================================
2147 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
2148 ** Bit Default Description
2149 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
2150 ** Software is permitted to program this register to any value greater than or equal to
2151 ** the contents of the Split Transaction Capacity register. A value less than the contents
2152 ** of the Split Transaction Capacity register causes unspecified results.
2153 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any
2154 ** size regardless of the amount of buffer space available.
2155 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
2156 ** split completions. This register controls behavior of the bridge buffers for forwarding
2157 ** Split Transactions from a primary bus requester to a secondary bus completer.
2158 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes).
2159 **===============================================================================
2160 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
2161 ** Bit Default Description
2162 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
2163 ** Software is permitted to program this register to any value greater than or equal to
2164 ** the contents of the Split Transaction Capacity register. A value less than the contents
2165 ** of the Split Transaction Capacity register causes unspecified results.
2166 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any
2167 ** size regardless of the amount of buffer space available.
2168 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
2169 ** split completions. This register controls behavior of the bridge buffers for forwarding
2170 ** Split Transactions from a primary bus requester to a secondary bus completer.
2171 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs
2173 **************************************************************************
2180 *************************************************************************************************************************************
2181 ** 80331 Address Translation Unit Register Definitions
2182 ** ATU Interface Configuration Header Format
2183 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface.
2184 *************************************************************************************************************************************
2185 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset
2186 **===================================================================================================================================
2187 ** | ATU Device ID | Vendor ID | 00h
2188 ** ----------------------------------------------------------------------------------------------------------
2189 ** | Status | Command | 04H
2190 ** ----------------------------------------------------------------------------------------------------------
2191 ** | ATU Class Code | Revision ID | 08H
2192 ** ----------------------------------------------------------------------------------------------------------
2193 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH
2194 ** ----------------------------------------------------------------------------------------------------------
2195 ** | Inbound ATU Base Address 0 | 10H
2196 ** ----------------------------------------------------------------------------------------------------------
2197 ** | Inbound ATU Upper Base Address 0 | 14H
2198 ** ----------------------------------------------------------------------------------------------------------
2199 ** | Inbound ATU Base Address 1 | 18H
2200 ** ----------------------------------------------------------------------------------------------------------
2201 ** | Inbound ATU Upper Base Address 1 | 1CH
2202 ** ----------------------------------------------------------------------------------------------------------
2203 ** | Inbound ATU Base Address 2 | 20H
2204 ** ----------------------------------------------------------------------------------------------------------
2205 ** | Inbound ATU Upper Base Address 2 | 24H
2206 ** ----------------------------------------------------------------------------------------------------------
2208 ** ----------------------------------------------------------------------------------------------------------
2209 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH
2210 ** ----------------------------------------------------------------------------------------------------------
2211 ** | Expansion ROM Base Address | 30H
2212 ** ----------------------------------------------------------------------------------------------------------
2213 ** | Reserved Capabilities Pointer | 34H
2214 ** ----------------------------------------------------------------------------------------------------------
2216 ** ----------------------------------------------------------------------------------------------------------
2217 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH
2218 ** ----------------------------------------------------------------------------------------------------------
2219 *********************************************************************************************************************
2222 ***********************************************************************************
2223 ** ATU Vendor ID Register - ATUVID
2224 ** -----------------------------------------------------------------
2225 ** Bit Default Description
2226 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel.
2227 ** This register, combined with the DID, uniquely identify the PCI device.
2228 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID
2229 ** to simulate the interface of a standard mechanism currently used by existing application software.
2230 ***********************************************************************************
2232 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/
2234 ***********************************************************************************
2235 ** ATU Device ID Register - ATUDID
2236 ** -----------------------------------------------------------------
2237 ** Bit Default Description
2238 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU.
2239 ** This ID, combined with the VID, uniquely identify any PCI device.
2240 ***********************************************************************************
2242 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/
2244 ***********************************************************************************
2245 ** ATU Command Register - ATUCMD
2246 ** -----------------------------------------------------------------
2247 ** Bit Default Description
2248 ** 15:11 000000 2 Reserved
2249 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal.
2250 ** 0=enables the assertion of interrupt signal.
2251 ** 1=disables the assertion of its interrupt signal.
2252 ** 09 0 2 Fast Back to Back Enable - When cleared,
2253 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
2254 ** Ignored when operating in the PCI-X mode.
2255 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface.
2256 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The
2257 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles
2258 ** of address stepping for PCI-X mode.
2259 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error
2260 ** is detected. When cleared, parity checking is disabled.
2261 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore,
2262 ** does not perform VGA palette snooping.
2263 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands.
2264 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
2265 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way.
2266 ** Not implemented and a reserved bit field.
2267 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus.
2268 ** When cleared, disables the device from generating PCI accesses.
2269 ** When set, allows the device to behave as a PCI bus master.
2270 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless
2271 ** of the state of this bit.
2272 ** 01 0 2 Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses.
2273 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus.
2274 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions.
2275 ** Not implemented and a reserved bit field.
2276 ***********************************************************************************
2278 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/
2280 ***********************************************************************************
2281 ** ATU Status Register - ATUSR (Sheet 1 of 2)
2282 ** -----------------------------------------------------------------
2283 ** Bit Default Description
2284 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even
2285 ** when the ATUCMD register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
2286 ** ¡E Write Data Parity Error when the ATU is a target (inbound write).
2287 ** ¡E Read Data Parity Error when the ATU is a requester (outbound read).
2288 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU).
2289 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU.
2290 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort
2291 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
2292 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target
2293 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
2294 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target,
2295 ** terminates the transaction on the PCI bus with a target abort.
2296 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL#
2297 ** timing for a target device in Conventional PCI Mode regardless of the operating mode
2298 ** (except configuration accesses).
2303 ** The ATU interface uses Medium timing.
2304 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions:
2305 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
2306 ** ¡E And the ATU acted as the requester
2307 ** for the operation in which the error occurred.
2308 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
2309 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
2310 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
2311 ** 07 1 2 (Conventional mode)
2313 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back
2314 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast
2315 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode.
2316 ** 06 0 2 UDF Supported - User Definable Features are not supported
2317 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported.
2318 ** 04 1 2 Capabilities - When set, this function implements extended capabilities.
2319 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt
2320 ** when the Interrupt Disable bit in the command register is a 0.
2321 ** 0=ATU interrupt signal deasserted.
2322 ** 1=ATU interrupt signal asserted.
2323 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to
2324 ** Section 3.10.23, ¡§ATU Interrupt Pin Register - ATUIPR¡¨ on page 236 for details on the ATU
2325 ** interrupt signal.
2326 ** 02:00 00000 2 Reserved.
2327 ***********************************************************************************
2329 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/
2331 ***********************************************************************************
2332 ** ATU Revision ID Register - ATURID
2333 ** -----------------------------------------------------------------
2334 ** Bit Default Description
2335 ** 07:00 00H ATU Revision - identifies the 80331 revision number.
2336 ***********************************************************************************
2338 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/
2340 ***********************************************************************************
2341 ** ATU Class Code Register - ATUCCR
2342 ** -----------------------------------------------------------------
2343 ** Bit Default Description
2344 ** 23:16 05H Base Class - Memory Controller
2345 ** 15:08 80H Sub Class - Other Memory Controller
2346 ** 07:00 00H Programming Interface - None defined
2347 ***********************************************************************************
2349 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/
2351 ***********************************************************************************
2352 ** ATU Cacheline Size Register - ATUCLSR
2353 ** -----------------------------------------------------------------
2354 ** Bit Default Description
2355 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs.
2356 ***********************************************************************************
2358 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/
2360 ***********************************************************************************
2361 ** ATU Latency Timer Register - ATULT
2362 ** -----------------------------------------------------------------
2363 ** Bit Default Description
2364 ** 07:03 00000 2 (for Conventional mode)
2365 ** 01000 2 (for PCI-X mode)
2366 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks.
2367 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
2368 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer.
2369 ***********************************************************************************
2371 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/
2373 ***********************************************************************************
2374 ** ATU Header Type Register - ATUHTR
2375 ** -----------------------------------------------------------------
2376 ** Bit Default Description
2377 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device.
2378 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface
2379 ** header conforms to PCI Local Bus Specification, Revision 2.3.
2380 ***********************************************************************************
2382 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/
2384 ***********************************************************************************
2385 ** ATU BIST Register - ATUBISTR
2387 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is
2388 ** initiated. This register is the interface between the host processor requesting BIST functions and
2389 ** the 80331 replying with the results from the software implementation of the BIST functionality.
2390 ** -----------------------------------------------------------------
2391 ** Bit Default Description
2392 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit.
2393 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set:
2394 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function.
2395 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results
2396 ** found in ATUBISTR register bits [3:0].
2397 ** When the ATUCR BIST Interrupt Enable bit is clear:
2398 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed.
2399 ** The Intel XScale core does not clear this bit.
2400 ** 05:04 00 2 Reserved
2401 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6):
2402 ** The Intel XScale core places the results of the software BIST in these bits.
2403 ** A nonzero value indicates a device-specific error.
2404 ***********************************************************************************
2406 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/
2409 ***************************************************************************************
2410 ** ATU Base Registers and Associated Limit Registers
2411 ***************************************************************************************
2412 ** Base Address Register Limit Register Description
2413 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus.
2414 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs.
2415 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus.
2416 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs.
2417 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus.
2418 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs.
2419 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus.
2420 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs.
2421 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH).
2422 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM.
2423 **--------------------------------------------------------------------------------------
2424 ** ATU Inbound Window 1 is not a translate window.
2425 ** The ATU does not claim any PCI accesses that fall within this range.
2426 ** This window is used to allocate host memory for use by Private Devices.
2427 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus.
2428 ***********************************************************************************
2432 ***********************************************************************************
2433 ** Inbound ATU Base Address Register 0 - IABAR0
2435 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0)
2436 ** defines the block of memory addresses where the inbound translation window 0 begins.
2437 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
2438 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size.
2439 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0
2440 ** depending on the value located within the IALR0.
2441 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification.
2442 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit.
2443 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2445 ** When IALR0 is cleared prior to host configuration:
2446 ** the user should also clear the Prefetchable Indicator and the Type Indicator.
2447 ** Assuming IALR0 is not cleared:
2448 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
2449 ** when the Prefetchable Indicator is cleared prior to host configuration,
2450 ** the user should also set the Type Indicator for 32 bit addressability.
2451 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification,
2452 ** when the Prefetchable Indicator is set prior to host configuration, the user
2453 ** should also set the Type Indicator for 64 bit addressability.
2454 ** This is the default for IABAR0.
2455 ** -----------------------------------------------------------------
2456 ** Bit Default Description
2457 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location
2458 ** the translation function is to respond to when addressed from the PCI bus.
2459 ** 11:04 00H Reserved.
2460 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2461 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window:
2462 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2463 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2464 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2465 ** The ATU does not occupy I/O space,
2466 ** thus this bit must be zero.
2467 ***********************************************************************************
2469 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/
2470 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08
2471 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04
2473 ***********************************************************************************
2474 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0
2476 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
2477 ** Together with the Translation Base Address this register defines the actual location the translation
2478 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
2479 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2481 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability,
2482 ** the IAUBAR0 register attributes are read-only.
2483 ** -----------------------------------------------------------------
2484 ** Bit Default Description
2485 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the
2486 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
2487 ***********************************************************************************
2489 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/
2491 ***********************************************************************************
2492 ** Inbound ATU Base Address Register 1 - IABAR1
2494 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1)
2495 ** defines the block of memory addresses where the inbound translation window 1 begins.
2496 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
2497 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2498 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus.
2500 ** When a non-zero value is not written to IALR1 prior to host configuration,
2501 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability.
2502 ** This is the default for IABAR1.
2503 ** Assuming a non-zero value is written to IALR1,
2504 ** the user may set the Prefetchable Indicator
2505 ** or the Type Indicator:
2506 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address
2507 ** boundary, when the Prefetchable Indicator is not set prior to host configuration,
2508 ** the user should also leave the Type Indicator set for 32 bit addressability.
2509 ** This is the default for IABAR1.
2510 ** b. when the Prefetchable Indicator is set prior to host configuration,
2511 ** the user should also set the Type Indicator for 64 bit addressability.
2512 ** -----------------------------------------------------------------
2513 ** Bit Default Description
2514 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus.
2515 ** 11:04 00H Reserved.
2516 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2517 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
2518 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2519 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2520 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2521 ** The ATU does not occupy I/O space,
2522 ** thus this bit must be zero.
2523 ***********************************************************************************
2525 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/
2527 ***********************************************************************************
2528 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1
2530 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes.
2531 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs).
2532 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
2533 ** The programmed value within the base address register must comply with the PCI programming
2534 ** requirements for address alignment.
2535 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written
2536 ** from the PCI bus.
2538 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability,
2539 ** the IAUBAR1 register attributes are read-only.
2540 ** This is the default for IABAR1.
2541 ** -----------------------------------------------------------------
2542 ** Bit Default Description
2543 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1
2544 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes.
2545 ***********************************************************************************
2547 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/
2549 ***********************************************************************************
2550 ** Inbound ATU Base Address Register 2 - IABAR2
2552 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2)
2553 ** defines the block of memory addresses where the inbound translation window 2 begins.
2554 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
2555 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size
2556 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2.
2557 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2559 ** When a non-zero value is not written to IALR2 prior to host configuration,
2560 ** the user should not set either the Prefetchable Indicator
2561 ** or the Type Indicator for 64 bit addressability.
2562 ** This is the default for IABAR2.
2563 ** Assuming a non-zero value is written to IALR2,
2564 ** the user may set the Prefetchable Indicator
2565 ** or the Type Indicator:
2566 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
2567 ** when the Prefetchable Indicator is not set prior to host configuration,
2568 ** the user should also leave the Type Indicator set for 32 bit addressability.
2569 ** This is the default for IABAR2.
2570 ** b. when the Prefetchable Indicator is set prior to host configuration,
2571 ** the user should also set the Type Indicator for 64 bit addressability.
2572 ** -----------------------------------------------------------------
2573 ** Bit Default Description
2574 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location
2575 ** the translation function is to respond to when addressed from the PCI bus.
2576 ** 11:04 00H Reserved.
2577 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2578 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
2579 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2580 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2581 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2582 ** The ATU does not occupy I/O space,
2583 ** thus this bit must be zero.
2584 ***********************************************************************************
2586 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/
2588 ***********************************************************************************
2589 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2
2591 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
2592 ** Together with the Translation Base Address this register defines the actual location
2593 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
2594 ** The programmed value within the base address register must comply with the PCI programming
2595 ** requirements for address alignment.
2597 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability,
2598 ** the IAUBAR2 register attributes are read-only.
2599 ** This is the default for IABAR2.
2600 ** -----------------------------------------------------------------
2601 ** Bit Default Description
2602 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2
2603 ** these bits define the actual location the translation function is to respond to
2604 ** when addressed from the PCI bus for addresses > 4GBytes.
2605 ***********************************************************************************
2607 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/
2609 ***********************************************************************************
2610 ** ATU Subsystem Vendor ID Register - ASVIR
2611 ** -----------------------------------------------------------------
2612 ** Bit Default Description
2613 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor.
2614 ***********************************************************************************
2616 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/
2618 ***********************************************************************************
2619 ** ATU Subsystem ID Register - ASIR
2620 ** -----------------------------------------------------------------
2621 ** Bit Default Description
2622 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem.
2623 ***********************************************************************************
2625 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/
2627 ***********************************************************************************
2628 ** Expansion ROM Base Address Register -ERBAR
2629 ** -----------------------------------------------------------------
2630 ** Bit Default Description
2631 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location
2632 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary.
2633 ** 11:01 000H Reserved
2634 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address
2635 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled.
2636 ***********************************************************************************
2638 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/
2639 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01
2641 ***********************************************************************************
2642 ** ATU Capabilities Pointer Register - ATU_CAP_PTR
2643 ** -----------------------------------------------------------------
2644 ** Bit Default Description
2645 ** 07:00 C0H Capability List Pointer - This provides an offset in this function¡¦s configuration space
2646 ** that points to the 80331 PCl Bus Power Management extended capability.
2647 ***********************************************************************************
2649 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/
2651 ***********************************************************************************
2652 ** Determining Block Sizes for Base Address Registers
2653 ** The required address size and type can be determined by writing ones to a base address register and
2654 ** reading from the registers. By scanning the returned value from the least-significant bit of the base
2655 ** address registers upwards, the programmer can determine the required address space size. The
2656 ** binary-weighted value of the first non-zero bit found indicates the required amount of space.
2657 ** Table 105 describes the relationship between the values read back and the byte sizes the base
2658 ** address register requires.
2659 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0
2660 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires
2661 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning
2662 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this
2663 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space.
2664 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their
2665 ** associated limit registers to enable which bits within the base address register are read/write and
2666 ** which bits are read only (0). This allows the programming of these registers in a manner similar to
2667 ** other PCI devices even though the limit is variable.
2668 ** Table 105. Memory Block Size Read Response
2669 ** Response After Writing all 1s
2670 ** to the Base Address Register
2673 ** Response After Writing all 1s
2674 ** to the Base Address Register
2677 ** FFFFFFF0H 16 FFF00000H 1 M
2678 ** FFFFFFE0H 32 FFE00000H 2 M
2679 ** FFFFFFC0H 64 FFC00000H 4 M
2680 ** FFFFFF80H 128 FF800000H 8 M
2681 ** FFFFFF00H 256 FF000000H 16 M
2682 ** FFFFFE00H 512 FE000000H 32 M
2683 ** FFFFFC00H 1K FC000000H 64 M
2684 ** FFFFF800H 2K F8000000H 128 M
2685 ** FFFFF000H 4K F0000000H 256 M
2686 ** FFFFE000H 8K E0000000H 512 M
2687 ** FFFFC000H 16K C0000000H 1 G
2688 ** FFFF8000H 32K 80000000H 2 G
2701 ***************************************************************************************
2707 ***********************************************************************************
2708 ** ATU Interrupt Line Register - ATUILR
2709 ** -----------------------------------------------------------------
2710 ** Bit Default Description
2711 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller¡¦s interrupt
2712 ** request line connects to the device's PCI interrupt request lines
2713 ** (as specified in the interrupt pin register).
2714 ** A value of FFH signifies ¡§no connection¡¨ or ¡§unknown¡¨.
2715 ***********************************************************************************
2717 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/
2719 ***********************************************************************************
2720 ** ATU Interrupt Pin Register - ATUIPR
2721 ** -----------------------------------------------------------------
2722 ** Bit Default Description
2723 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin.
2724 ***********************************************************************************
2726 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/
2728 ***********************************************************************************
2729 ** ATU Minimum Grant Register - ATUMGNT
2730 ** -----------------------------------------------------------------
2731 ** Bit Default Description
2732 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks.
2733 ***********************************************************************************
2735 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/
2737 ***********************************************************************************
2738 ** ATU Maximum Latency Register - ATUMLAT
2739 ** -----------------------------------------------------------------
2740 ** Bit Default Description
2741 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus
2742 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement.
2743 ***********************************************************************************
2745 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/
2747 ***********************************************************************************
2748 ** Inbound Address Translation
2750 ** The ATU allows external PCI bus initiators to directly access the internal bus.
2751 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space.
2752 ** The process of inbound address translation involves two steps:
2753 ** 1. Address Detection.
2754 ** ¡E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
2755 ** within the address windows defined for the inbound ATU.
2756 ** ¡E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI
2757 ** mode and with Decode A DEVSEL# timing in the PCI-X mode.
2758 ** 2. Address Translation.
2759 ** ¡E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address.
2760 ** The ATU uses the following registers in inbound address window 0 translation:
2761 ** ¡E Inbound ATU Base Address Register 0
2762 ** ¡E Inbound ATU Limit Register 0
2763 ** ¡E Inbound ATU Translate Value Register 0
2764 ** The ATU uses the following registers in inbound address window 2 translation:
2765 ** ¡E Inbound ATU Base Address Register 2
2766 ** ¡E Inbound ATU Limit Register 2
2767 ** ¡E Inbound ATU Translate Value Register 2
2768 ** The ATU uses the following registers in inbound address window 3 translation:
2769 ** ¡E Inbound ATU Base Address Register 3
2770 ** ¡E Inbound ATU Limit Register 3
2771 ** ¡E Inbound ATU Translate Value Register 3
2772 ** Note: Inbound Address window 1 is not a translate window.
2773 ** Instead, window 1 may be used to allocate host memory for Private Devices.
2774 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH),
2775 ** thus the host BIOS does not configure window 3.
2776 ** Window 3 is intended to be used as a special window into local memory for private PCI
2777 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge.
2778 ** PCI-to-PCI Bridge in 80331 or
2779 ** Inbound address detection is determined from the 32-bit PCI address,
2780 ** (64-bit PCI address during DACs) the base address register and the limit register.
2781 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison.
2783 ** The algorithm for detection is:
2785 ** Equation 1. Inbound Address Detection
2786 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only)
2787 ** the PCI Address is claimed by the Inbound ATU.
2789 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed
2790 ** with the associated inbound limit register.
2791 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs),
2792 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU.
2794 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit.
2795 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit
2796 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the
2797 ** lower 32-bits are used during address translation.
2798 ** The algorithm is:
2801 ** Equation 2. Inbound Translation
2802 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0].
2804 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the
2805 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and
2806 ** the result is the internal bus address. This translation mechanism is used for all inbound memory
2807 ** read and write commands excluding inbound configuration read and writes.
2808 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear
2809 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase.
2810 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode.
2813 ** Base_Register=3A00 0000H
2814 ** Limit_Register=FF80 0000H (8 Mbyte limit value)
2815 ** Value_Register=B100 0000H
2816 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes)
2818 ** Address Detection (32-bit address)
2820 ** PCI_Address & Limit_Register == Base_Register
2821 ** 3A45 012CH & FF80 0000H == 3A00 0000H
2823 ** ANS: PCI_Address is in the Inbound Translation Window
2824 ** Address Translation (to get internal bus address)
2826 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg
2827 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H
2829 ** ANS:IB_Address=B145 012CH
2830 ***********************************************************************************
2836 ***********************************************************************************
2837 ** Inbound ATU Limit Register 0 - IALR0
2839 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI
2840 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
2841 ** PCI addresses to internal bus addresses.
2842 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
2843 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
2844 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
2845 ** Specification, Revision 2.3 for additional information on programming base address registers.
2846 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a
2847 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit
2848 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0
2849 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of
2850 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the
2851 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register.
2852 ** -----------------------------------------------------------------
2853 ** Bit Default Description
2854 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for
2855 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB.
2856 ** 11:00 000H Reserved
2857 ***********************************************************************************
2859 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/
2861 ***********************************************************************************
2862 ** Inbound ATU Translate Value Register 0 - IATVR0
2864 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to
2865 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
2866 ** inbound ATU address translation.
2867 ** -----------------------------------------------------------------
2868 ** Bit Default Description
2869 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses.
2870 ** This value must be 64-bit aligned on the internal bus.
2871 ** The default address allows the ATU to access the internal 80331 memory-mapped registers.
2872 ** 11:00 000H Reserved
2873 ***********************************************************************************
2875 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/
2877 ***********************************************************************************
2878 ** Expansion ROM Limit Register - ERLR
2880 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines
2881 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR.
2882 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one
2883 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within
2884 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes
2885 ** the corresponding bit within the ERBAR read/write from PCI.
2886 ** -----------------------------------------------------------------
2887 ** Bit Default Description
2888 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default
2889 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0.
2890 ** 11:00 000H Reserved.
2891 ***********************************************************************************
2893 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/
2895 ***********************************************************************************
2896 ** Expansion ROM Translate Value Register - ERTVR
2898 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the
2899 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the
2900 ** Expansion ROM address translation.
2901 ** -----------------------------------------------------------------
2902 ** Bit Default Description
2903 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses
2904 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus.
2905 ** 11:00 000H Reserved
2906 ***********************************************************************************
2908 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/
2910 ***********************************************************************************
2911 ** Inbound ATU Limit Register 1 - IALR1
2913 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a
2914 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit
2915 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1
2916 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of
2917 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the
2918 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only
2920 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does
2921 ** not process any PCI bus transactions to this memory range.
2922 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1,
2923 ** IAUBAR1, and IALR1.
2924 ** -----------------------------------------------------------------
2925 ** Bit Default Description
2926 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size
2927 ** required for the ATUs memory window 1.
2928 ** 11:00 000H Reserved
2929 ***********************************************************************************
2931 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/
2933 ***********************************************************************************
2934 ** Inbound ATU Limit Register 2 - IALR2
2936 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI
2937 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
2938 ** PCI addresses to internal bus addresses.
2939 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When
2940 ** determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit
2941 ** register provides the block size requirements for the base address register. The remaining registers
2942 ** used for performing address translation are discussed in Section 3.2.1.1.
2943 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
2944 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
2945 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
2946 ** Specification, Revision 2.3 for additional information on programming base address registers.
2947 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a
2948 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit
2949 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2
2950 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of
2951 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the
2952 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only
2954 ** -----------------------------------------------------------------
2955 ** Bit Default Description
2956 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size
2957 ** required for the ATUs memory window 2.
2958 ** 11:00 000H Reserved
2959 ***********************************************************************************
2961 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/
2963 ***********************************************************************************
2964 ** Inbound ATU Translate Value Register 2 - IATVR2
2966 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to
2967 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
2968 ** inbound ATU address translation.
2969 ** -----------------------------------------------------------------
2970 ** Bit Default Description
2971 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses.
2972 ** This value must be 64-bit aligned on the internal bus.
2973 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers.
2974 ** 11:00 000H Reserved
2975 ***********************************************************************************
2977 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/
2979 ***********************************************************************************
2980 ** Outbound I/O Window Translate Value Register - OIOWTVR
2982 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address
2983 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a
2984 ** result of the outbound ATU address translation.
2985 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed
2986 ** length of 64 Kbytes.
2987 ** -----------------------------------------------------------------
2988 ** Bit Default Description
2989 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses.
2990 ** 15:00 0000H Reserved
2991 ***********************************************************************************
2993 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/
2995 ***********************************************************************************
2996 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0
2998 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
2999 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is
3000 ** driven on the PCI bus as a result of the outbound ATU address translation.
3001 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length
3003 ** -----------------------------------------------------------------
3004 ** Bit Default Description
3005 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
3006 ** 25:02 00 0000H Reserved
3007 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst.
3008 ** Only linear incrementing mode is supported.
3009 ***********************************************************************************
3011 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/
3013 ***********************************************************************************
3014 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
3016 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
3017 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3018 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then
3019 ** a SAC is generated on the PCI bus.
3020 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed
3021 ** length of 64 Mbytes.
3022 ** -----------------------------------------------------------------
3023 ** Bit Default Description
3024 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
3025 ***********************************************************************************
3027 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/
3029 ***********************************************************************************
3030 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1
3032 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI
3033 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is
3034 ** driven on the PCI bus as a result of the outbound ATU address translation.
3035 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
3037 ** -----------------------------------------------------------------
3038 ** Bit Default Description
3039 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
3040 ** 25:02 00 0000H Reserved
3041 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst.
3042 ** Only linear incrementing mode is supported.
3043 ***********************************************************************************
3045 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/
3047 ***********************************************************************************
3048 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
3050 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines
3051 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3052 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then
3053 ** a SAC is generated on the PCI bus.
3054 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
3056 ** -----------------------------------------------------------------
3057 ** Bit Default Description
3058 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
3059 ***********************************************************************************
3061 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/
3063 ***********************************************************************************
3064 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR
3066 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the
3067 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing
3068 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
3069 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus.
3070 ** -----------------------------------------------------------------
3071 ** Bit Default Description
3072 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
3073 ***********************************************************************************
3075 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/
3077 ***********************************************************************************
3078 ** ATU Configuration Register - ATUCR
3080 ** The ATU Configuration Register controls the outbound address translation for address translation
3081 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard
3082 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST
3083 ** interrupt enabling.
3084 ** -----------------------------------------------------------------
3085 ** Bit Default Description
3086 ** 31:20 00H Reserved
3087 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a
3088 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read
3089 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not
3090 ** applicable in the PCI-X mode.
3091 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set,
3092 ** with Direct Addressing enabled (bit 7 of the ATUCR set),
3093 ** the ATU forwards internal bus cycles with an address between 0000.0040H and
3094 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH).
3095 ** When clear, no translation occurs.
3097 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until
3098 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified.
3099 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and
3100 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired.
3101 ** 14:10 00000 2 Reserved
3102 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt
3103 ** when the ATU detects that SERR# was asserted. When clear,
3104 ** the Intel XScale core is not interrupted when SERR# is detected.
3105 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU.
3106 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to
3107 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of
3109 ** 07:04 0000 2 Reserved
3110 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start
3111 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7
3112 ** in the ATUBISTR register.
3114 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit.
3115 ** When cleared, disables the outbound ATU.
3117 ***********************************************************************************
3119 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/
3121 ***********************************************************************************
3122 ** PCI Configuration and Status Register - PCSR
3124 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring
3125 ** various features of the PCI bus interface.
3126 ** -----------------------------------------------------------------
3127 ** Bit Default Description
3128 ** 31:19 0000H Reserved
3129 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address
3130 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error
3131 ** Response bit is cleared. Set under the following conditions:
3132 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU).
3133 ** 17:16 Varies with
3140 ** PCI-X capability - These two bits define the mode of
3141 ** the PCI bus (conventional or PCI-X) as well as the
3142 ** operating frequency in the case of PCI-X mode.
3143 ** 00 - Conventional PCI mode
3147 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification,
3148 ** Revision 1.0a, the operating
3149 ** mode is determined by an initialization pattern on the PCI bus during
3150 ** P_RST# assertion:
3151 ** DEVSEL# STOP# TRDY# Mode
3152 ** Deasserted Deasserted Deasserted Conventional
3153 ** Deasserted Deasserted Asserted PCI-X 66
3154 ** Deasserted Asserted Deasserted PCI-X 100
3155 ** Deasserted Asserted Asserted PCI-X 133
3156 ** All other patterns are reserved.
3158 ** Outbound Transaction Queue Busy:
3159 ** 0=Outbound Transaction Queue Empty
3160 ** 1=Outbound Transaction Queue Busy
3162 ** Inbound Transaction Queue Busy:
3163 ** 0=Inbound Transaction Queue Empty
3164 ** 1=Inbound Transaction Queue Busy
3166 ** 12 0 2 Discard Timer Value - This bit controls the time-out value
3167 ** for the four discard timers attached to the queues holding read data.
3168 ** A value of 0 indicates the time-out value is 2 15 clocks.
3169 ** A value of 1 indicates the time-out value is 2 10 clocks.
3176 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in
3177 ** Conventional PCI mode by the assertion of M66EN during bus initialization.
3178 ** When clear, the interface
3179 ** has been initialized as a 33 MHz bus.
3180 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode.
3187 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been
3188 ** configured as 64-bit capable by
3189 ** the assertion of REQ64# on the rising edge of P_RST#. When set,
3190 ** the PCI interface is configured as
3192 ** 07:06 00 2 Reserved.
3193 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core
3194 ** and all units on the internal
3195 ** bus. In addition to the internal bus initialization,
3196 ** this bit triggers the assertion of the M_RST# pin for
3197 ** initialization of registered DIMMs. When set:
3198 ** When operating in the conventional PCI mode:
3199 ** ¡E All current PCI transactions being mastered by the ATU completes,
3200 ** and the ATU master interfaces
3201 ** proceeds to an idle state. No additional transactions is mastered by these units
3202 ** until the internal bus reset is complete.
3203 ** ¡E All current transactions being slaved by the ATU on either the PCI bus
3204 ** or the internal bus
3205 ** completes, and the ATU target interfaces proceeds to an idle state.
3206 ** All future slave transactions master aborts,
3207 ** with the exception of the completion cycle for the transaction that set the Reset
3208 ** Internal Bus bit in the PCSR.
3209 ** ¡E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion)
3210 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete.
3211 ** ¡E The ATU ignores configuration cycles, and they appears as master aborts for: 32
3212 ** Internal Bus clocks.
3213 ** ¡E The 80331 hardware clears this bit after the reset operation completes.
3214 ** When operating in the PCI-X mode:
3215 ** The ATU hardware responds the same as in Conventional PCI-X mode.
3216 ** However, this may create a problem in PCI-X mode for split requests in
3217 ** that there may still be an outstanding split completion that the
3218 ** ATU is either waiting to receive (Outbound Request) or initiate
3219 ** (Inbound Read Request). For a cleaner
3220 ** internal bus reset, host software can take the following steps prior
3221 ** to asserting Reset Internal bus:
3222 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in
3223 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued.
3224 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction
3225 ** queue busy bits to be clear.
3226 ** 3. Set the Reset Internal Bus bit
3227 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode,
3228 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split
3229 ** completion transactions.
3230 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is
3231 ** guaranteed that any prior configuration cycles have properly completed since there is only a one
3232 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate
3233 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset.
3234 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the
3235 ** Bus Master Indicator signal P_BMI used
3236 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and
3237 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low).
3238 ** 03 Varies with external state of PRIVDEV during
3240 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device
3241 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register.
3242 ** 0=Private Device control Disabled - SISR register bits default to zero
3243 ** 1=Private Device control Enabled - SISR register bits default to one
3244 ** 02 Varies with external state of RETRY during P_RST#
3245 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all
3246 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate
3247 ** configuration cycles.
3248 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of
3249 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is
3250 ** low, the bit is cleared.
3251 ** 01 Varies with external state of CORE_RST# during P_RST#
3252 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is
3253 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is
3254 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel
3255 ** XScale core reset.
3256 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge
3257 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is
3258 ** high, the bit is clear.
3259 ** 00 Varies with external state of PRIVMEM during P_RST#
3260 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device
3261 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register.
3262 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero
3263 ** 1=Private Memory control Enabled - SDER register bits 2 default to one
3264 ***********************************************************************************
3266 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/
3268 ***********************************************************************************
3269 ** ATU Interrupt Status Register - ATUISR
3271 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU
3272 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit
3273 ** of the 80331. All bits in this register are Read/Clear.
3274 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register
3275 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set
3276 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The
3277 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this
3279 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core.
3280 ** -----------------------------------------------------------------
3281 ** Bit Default Description
3282 ** 31:18 0000H Reserved
3283 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR
3284 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set,
3285 ** this bit results in the assertion of the ATU Configure Register Write Interrupt.
3287 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register.
3288 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt.
3289 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write
3290 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these
3291 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU
3292 ** Configure Register Write Interrupt.
3293 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion
3294 ** Message on the PCI Bus with the Split Completion Error attribute bit set.
3295 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion
3296 ** Message from the PCI Bus with the Split Completion Error attribute bit set.
3297 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status
3298 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and
3299 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set.
3300 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU.
3301 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD
3302 ** register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
3303 ** ¡E Write Data Parity Error when the ATU is a target (inbound write).
3304 ** ¡E Read Data Parity Error when the ATU is an initiator (outbound read).
3305 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus.
3306 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor
3307 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR
3308 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR
3309 ** register bits 3:0.
3310 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion
3311 ** of the ATU Configure Register Write Interrupt.
3312 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort.
3313 ** 06:05 00 2 Reserved.
3314 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU.
3315 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort.
3316 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort.
3317 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort.
3318 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following
3320 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
3321 ** ¡E And the ATU acted as the requester for the operation in which the error occurred.
3322 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
3323 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
3324 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
3325 ***********************************************************************************
3327 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/
3329 ***********************************************************************************
3330 ** ATU Interrupt Mask Register - ATUIMR
3332 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts
3333 ** generated by the ATU.
3334 ** -----------------------------------------------------------------
3335 ** Bit Default Description
3336 ** 31:15 0 0000H Reserved
3337 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the
3338 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register.
3342 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the
3343 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register
3344 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR.
3347 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and
3348 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the
3349 ** IABAR1 register or the IAUBAR1 register.
3352 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and
3353 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message.
3356 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR
3357 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the
3358 ** PCIXSR being set.
3361 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the
3362 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the
3363 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0.
3366 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of
3367 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR.
3370 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the
3371 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set.
3374 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master.
3375 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the
3376 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set.
3379 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error
3380 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set
3383 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation
3384 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set.
3387 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation
3388 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set.
3391 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the
3392 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an
3393 ** inbound write transaction.
3394 ** 0=SERR# Not Asserted due to error
3395 ** 1=SERR# Asserted due to error
3396 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC
3397 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs
3398 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is
3399 ** actually requested from the inbound read queue.
3400 ** 0=Disconnect with data
3401 ** (the data being up to 64 bits of 1¡¦s)
3403 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h -
3404 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus,
3405 ** independent of the setting of this bit.
3406 ***********************************************************************************
3408 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/
3410 ***********************************************************************************
3411 ** Inbound ATU Base Address Register 3 - IABAR3
3413 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block
3414 ** of memory addresses where the inbound translation window 3 begins.
3415 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
3416 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size.
3417 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3.
3418 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
3420 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH),
3421 ** IABAR3 is not configured by the host during normal system initialization.
3423 ** When a non-zero value is not written to IALR3,
3424 ** the user should not set either the Prefetchable Indicator
3425 ** or the Type Indicator for 64 bit addressability.
3426 ** This is the default for IABAR3.
3427 ** Assuming a non-zero value is written to IALR3,
3428 ** the user may set the Prefetchable Indicator
3429 ** or the Type Indicator:
3430 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
3431 ** when the Prefetchable Indicator is not set,
3432 ** the user should also leave the Type Indicator set for 32 bit addressability.
3433 ** This is the default for IABAR3.
3434 ** b. when the Prefetchable Indicator is set,
3435 ** the user should also set the Type Indicator for 64 bit addressability.
3436 ** -----------------------------------------------------------------
3437 ** Bit Default Description
3438 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location
3439 ** the translation function is to respond to when addressed from the PCI bus.
3440 ** 11:04 00H Reserved.
3441 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
3442 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
3443 ** 00 - Memory Window is locatable anywhere in 32 bit address space
3444 ** 10 - Memory Window is locatable anywhere in 64 bit address space
3445 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
3446 ** The ATU does not occupy I/O space,
3447 ** thus this bit must be zero.
3448 ***********************************************************************************
3450 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/
3452 ***********************************************************************************
3453 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3
3455 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
3456 ** Together with the Translation Base Address this register defines the actual location
3457 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
3458 ** The programmed value within the base address register must comply with the PCI programming
3459 ** requirements for address alignment.
3461 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability,
3462 ** the IAUBAR3 register attributes are read-only.
3463 ** This is the default for IABAR3.
3464 ** -----------------------------------------------------------------
3465 ** Bit Default Description
3466 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define
3467 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
3468 ***********************************************************************************
3470 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/
3472 ***********************************************************************************
3473 ** Inbound ATU Limit Register 3 - IALR3
3475 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI
3476 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
3477 ** PCI addresses to internal bus addresses.
3478 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When
3479 ** determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit
3480 ** register provides the block size requirements for the base address register. The remaining registers
3481 ** used for performing address translation are discussed in Section 3.2.1.1.
3482 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
3483 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
3484 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
3485 ** Specification, Revision 2.3 for additional information on programming base address registers.
3486 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a
3487 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit
3488 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3
3489 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of
3490 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the
3491 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only
3493 ** -----------------------------------------------------------------
3494 ** Bit Default Description
3495 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required
3496 ** for the ATUs memory window 3.
3497 ** 11:00 000H Reserved
3498 ***********************************************************************************
3500 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/
3502 ***********************************************************************************
3503 ** Inbound ATU Translate Value Register 3 - IATVR3
3505 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to
3506 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
3507 ** inbound ATU address translation.
3508 ** -----------------------------------------------------------------
3509 ** Bit Default Description
3510 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses.
3511 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to
3512 ** access the internal 80331 memory-mapped registers.
3513 ** 11:00 000H Reserved
3514 ***********************************************************************************
3516 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/
3518 ***********************************************************************************
3519 ** Outbound Configuration Cycle Address Register - OCCAR
3521 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
3522 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then
3523 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or
3524 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the
3526 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently
3527 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a
3528 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for
3529 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears
3530 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X
3531 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats.
3532 ** -----------------------------------------------------------------
3533 ** Bit Default Description
3534 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound
3535 ** configuration read or write cycle.
3536 ***********************************************************************************
3538 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/
3540 ***********************************************************************************
3541 ** Outbound Configuration Cycle Data Register - OCCDR
3543 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write
3544 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a
3545 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to
3546 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a
3547 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ.
3548 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never
3549 ** actually entered into the data register (which does not physically exist).
3550 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value
3551 ** within the ATU configuration space.
3552 ** -----------------------------------------------------------------
3553 ** Bit Default Description
3554 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read
3556 ***********************************************************************************
3558 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/
3560 ***********************************************************************************
3561 ** VPD Capability Identifier Register - VPD_CAPID
3563 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
3564 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
3565 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability
3566 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3.
3567 ** -----------------------------------------------------------------
3568 ** Bit Default Description
3569 ** 07:00 03H Cap_Id - This field with its¡¦ 03H value identifies this item in the linked list of Extended Capability
3570 ** Headers as being the VPD capability registers.
3571 ***********************************************************************************
3573 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/
3575 ***********************************************************************************
3576 ** VPD Next Item Pointer Register - VPD_NXTP
3578 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
3579 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
3580 ** For the 80331, this the final capability list, and hence, this register is set to 00H.
3581 ** -----------------------------------------------------------------
3582 ** Bit Default Description
3583 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
3584 ** next item in the function¡¦s capability list. Since the VPD capabilities are the last in the linked list of
3585 ** extended capabilities in the 80331, the register is set to 00H.
3586 ***********************************************************************************
3588 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/
3590 ***********************************************************************************
3591 ** VPD Address Register - VPD_AR
3593 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be
3594 ** accessed. The register is read/write and the initial value at power-up is indeterminate.
3595 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use
3596 ** the Flag setting to determine whether the configuration write was intended to initiate a read or
3597 ** write of the VPD through the VPD Data Register.
3598 ** -----------------------------------------------------------------
3599 ** Bit Default Description
3600 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage
3601 ** component has completed. Please see Section 3.9, ¡§Vital Product Data¡¨ on page 201 for more details on
3602 ** how the 80331 handles the data transfer.
3603 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write
3604 ** Vital Product Data from the VPD storage component.
3605 ***********************************************************************************
3607 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/
3609 ***********************************************************************************
3610 ** VPD Data Register - VPD_DR
3612 ** This register is used to transfer data between the 80331 and the VPD storage component.
3613 ** -----------------------------------------------------------------
3614 ** Bit Default Description
3615 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component.
3616 ***********************************************************************************
3618 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/
3620 ***********************************************************************************
3621 ** Power Management Capability Identifier Register -PM_CAPID
3623 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
3624 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
3625 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power
3626 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management
3627 ** Interface Specification, Revision 1.1.
3628 ** -----------------------------------------------------------------
3629 ** Bit Default Description
3630 ** 07:00 01H Cap_Id - This field with its¡¦ 01H value identifies this item in the linked list of Extended Capability
3631 ** Headers as being the PCI Power Management Registers.
3632 ***********************************************************************************
3634 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/
3636 ***********************************************************************************
3637 ** Power Management Next Item Pointer Register - PM_NXTP
3639 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
3640 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
3641 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H.
3642 ** -----------------------------------------------------------------
3643 ** Bit Default Description
3644 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
3645 ** next item in the function¡¦s capability list which in the 80331 is the MSI extended capabilities header.
3646 ***********************************************************************************
3648 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/
3650 ***********************************************************************************
3651 ** Power Management Capabilities Register - PM_CAP
3653 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management
3654 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides
3655 ** information on the capabilities of the ATU function related to power management.
3656 ** -----------------------------------------------------------------
3657 ** Bit Default Description
3658 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME#
3659 ** is not supported by the 80331.
3660 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State
3661 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State
3662 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the
3663 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1
3664 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence
3665 ** following the transition to the D0 uninitialized state.
3667 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 .
3668 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management
3669 ** Interface Specification, Revision 1.1
3670 ***********************************************************************************
3672 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/
3674 ***********************************************************************************
3675 ** Power Management Control/Status Register - PM_CSR
3677 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power
3678 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status
3679 ** interface for the power management extended capability.
3680 ** -----------------------------------------------------------------
3681 ** Bit Default Description
3682 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not
3683 ** supported by the 80331.
3684 ** 14:9 00H Reserved
3685 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME#
3686 ** generation from any power state.
3687 ** 7:2 000000 2 Reserved
3688 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state
3689 ** of a function and to set the function into a new power state. The definition of the values is:
3692 ** 10 2 - D2 (Unsupported)
3694 ** The 80331 supports only the D0 and D3 hot states.
3696 ***********************************************************************************
3698 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/
3700 ***********************************************************************************
3701 ** PCI-X Capability Identifier Register - PX_CAPID
3703 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
3704 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
3705 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with
3706 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
3707 ** -----------------------------------------------------------------
3708 ** Bit Default Description
3709 ** 07:00 07H Cap_Id - This field with its¡¦ 07H value identifies this item in the linked list of Extended Capability
3710 ** Headers as being the PCI-X capability registers.
3711 ***********************************************************************************
3713 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/
3715 ***********************************************************************************
3716 ** PCI-X Next Item Pointer Register - PX_NXTP
3718 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
3719 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
3720 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults
3722 ** However, this register may be written to B8H prior to host configuration to include the VPD
3723 ** capability located at off-set B8H.
3724 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may
3725 ** produce unpredictable system behavior.
3726 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be
3727 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically,
3728 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in
3729 ** this case (bit 1 of PCSR), as well. Please see Table 125, ¡§PCI Configuration and Status Register -
3730 ** PCSR¡¨ on page 253 for more details on the 80331 initialization modes.
3731 ** -----------------------------------------------------------------
3732 ** Bit Default Description
3733 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
3734 ** next item in the function¡¦s capability list. Since the PCI-X capabilities are the last in the linked list of
3735 ** extended capabilities in the 80331, the register is set to 00H.
3736 ** However, this field may be written prior to host configuration with B8H to extend the list to include the
3737 ** VPD extended capabilities header.
3738 ***********************************************************************************
3740 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/
3742 ***********************************************************************************
3743 ** PCI-X Command Register - PX_CMD
3745 ** This register controls various modes and features of ATU and Message Unit when operating in the
3747 ** -----------------------------------------------------------------
3748 ** Bit Default Description
3749 ** 15:7 000000000 2 Reserved.
3750 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions
3751 ** the device is permitted to have outstanding at one time.
3752 ** Register Maximum Outstanding
3761 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when
3762 ** initiating a Sequence with one of the burst memory read commands.
3763 ** Register Maximum Byte Count
3769 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes
3771 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to
3772 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts
3773 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set.
3774 ***********************************************************************************
3776 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/
3778 ***********************************************************************************
3779 ** PCI-X Status Register - PX_SR
3781 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message
3782 ** Unit when operating in the PCI-X mode.
3783 ** -----------------------------------------------------------------
3784 ** Bit Default Description
3785 ** 31:30 00 2 Reserved
3786 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion
3787 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software
3788 ** writes a 1 to this location.
3789 ** 0=no Split Completion error message received.
3790 ** 1=a Split Completion error message has been received.
3791 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting
3792 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register:
3793 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting
3794 ** 1 16 512 (Default)
3798 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions.
3799 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up
3801 ** 20 1 2 80331 is a complex device.
3802 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device¡¦s
3803 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location.
3804 ** 0=no unexpected Split Completion has been received.
3805 ** 1=an unexpected Split Completion has been received.
3806 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the
3807 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus
3808 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this
3810 ** 0=no Split Completion has been discarded.
3811 ** 1=a Split Completion has been discarded.
3812 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read
3813 ** Requests with Split Responses (Memory or Register) that has ¡§read side effects.¡¨
3814 ** 17 1 2 80331 is a 133 MHz capable device.
3815 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus,
3816 ** therefore this bit is always set.
3817 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0),
3818 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#).
3819 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled
3820 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.
3821 ** 0=The bus is 32 bits wide.
3822 ** 1=The bus is 64 bits wide.
3823 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus
3824 ** segment for the device containing this function. The function uses this number as part of its Requester
3825 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed
3826 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0]
3827 ** of the attribute phase of the Configuration Write, regardless of which register in the function is
3828 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of
3829 ** the following are true:
3830 ** 1. The transaction uses a Configuration Write command.
3831 ** 2. IDSEL is asserted during the address phase.
3832 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
3833 ** 4. AD[10::08] of the configuration address contain the appropriate function number.
3834 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device
3835 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a
3836 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection
3837 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for
3838 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each
3839 ** time the function is addressed by a Configuration Write transaction, the device must update this register
3840 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which
3841 ** register in the function is addressed by the transaction. The function is addressed by a Configuration
3842 ** Write transaction when all of the following are true:
3843 ** 1. The transaction uses a Configuration Write command.
3844 ** 2. IDSEL is asserted during the address phase.
3845 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
3846 ** 4. AD[10::08] of the configuration address contain the appropriate function number.
3847 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this
3848 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0
3849 ** configuration transaction to which this function responds. The function uses this number as part of its
3850 ** Requester ID and Completer ID.
3852 **************************************************************************
3854 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/
3857 **************************************************************************
3858 ** Inbound Read Transaction
3859 ** ========================================================================
3860 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local
3861 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through
3862 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue
3864 ** When operating in the conventional PCI mode, all inbound read transactions are processed as
3865 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are
3866 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards
3867 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for
3868 ** an inbound read transaction on the PCI bus is summarized in the following statements:
3869 ** ¡E The ATU claims the PCI read transaction when the PCI address is within the inbound
3870 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base
3871 ** Address Register during DACs) and Inbound Limit Register.
3872 ** ¡E When operating in the conventional PCI mode, when the ITQ is currently holding transaction
3873 ** information from a previous delayed read, the current transaction information is compared to
3874 ** the previous transaction information (based on the setting of the DRC Alias bit in
3875 ** Section 3.10.39, ¡§ATU Configuration Register - ATUCR¡¨ on page 252). When there is a
3876 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a
3877 ** match and the data is not available, a Retry is signaled with no other action taken. When there
3878 ** is not a match and when the ITQ has less than eight entries, capture the transaction
3879 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and
3880 ** when the ITQ is full, then signal a Retry with no other action taken.
3881 ** ¡X When an address parity error is detected, the address parity response defined in
3882 ** Section 3.7 is used.
3883 ** ¡E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from
3884 ** the IRQ, it continues until one of the following is true:
3885 ** ¡X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the
3887 ** ¡X An internal bus Target Abort was detected. In this case, the QWORD associated with the
3888 ** Target Abort is never entered into the IRQ, and therefore is never returned.
3889 ** ¡X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error.
3890 ** ¡X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to
3891 ** the initiator on the last data word available.
3892 ** ¡E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and
3893 ** command are latched into the available ITQ and a Split Response Termination is signalled to
3895 ** ¡E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned
3896 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target
3897 ** before returning read data by generating the split completion transaction on the PCI-X bus.
3898 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the
3899 ** transfer by returning data in 1024 byte aligned chunks.
3900 ** ¡E When operating in the PCI-X mode, once a split completion transaction has started, it
3901 ** continues until one of the following is true:
3902 ** ¡X The requester (now the target) generates a Retry Termination, or a Disconnection at Next
3903 ** ADB (when the requester is a bridge)
3904 ** ¡X The byte count is satisfied.
3905 ** ¡X An internal bus Target Abort was detected. The ATU generates a Split Completion
3906 ** Message (message class=2h - completer error, and message index=81h - target abort) to
3907 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
3908 ** Refer to Section 3.7.1.
3909 ** ¡X An internal bus Master Abort was detected. The ATU generates a Split Completion
3910 ** Message (message class=2h - completer error, and message index=80h - Master abort) to
3911 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
3912 ** Refer to Section 3.7.1
3913 ** ¡E When operating in the conventional PCI mode, when the master inserts wait states on the PCI
3914 ** bus, the ATU PCI slave interface waits with no premature disconnects.
3915 ** ¡E When a data parity error occurs signified by PERR# asserted from the initiator, no action is
3916 ** taken by the target interface. Refer to Section 3.7.2.5.
3917 ** ¡E When operating in the conventional PCI mode, when the read on the internal bus is
3918 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is
3919 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a
3920 ** target abort is used, when clear, a disconnect is used.
3921 ** ¡E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h
3922 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates
3923 ** a Split Completion Message (message class=2h - completer error, and message index=81h -
3924 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU
3925 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending
3926 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this
3927 ** transaction is flushed. Refer to Section 3.7.1.
3928 ** ¡E When operating in the conventional PCI mode, when the transaction on the internal bus
3929 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the
3930 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1
3931 ** ¡E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a
3932 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer
3933 ** error, and message index=80h - internal bus master abort) to inform the requester about the
3934 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1.
3935 ** ¡E When operating in the PCI-X mode, when the Split Completion transaction completes with
3936 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that
3937 ** prevents it from accepting the completion it requested. In this case, since the Split Request
3938 ** addresses a location that has no read side effects, the completer must discard the Split
3939 ** Completion and take no further action.
3940 ** The data flow for an inbound read transaction on the internal bus is summarized in the following
3942 ** ¡E The ATU internal bus master interface requests the internal bus when a PCI address appears in
3943 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the
3944 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU
3945 ** always uses conventional PCI ordering rules.
3946 ** ¡E Once the internal bus is granted, the internal bus master interface drives the translated address
3947 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated.
3948 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded
3949 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI
3950 ** master has been delivered the target abort).
3951 ** ¡E Once the translated address is on the bus and the transaction has been accepted, the internal
3952 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously
3953 ** received by the IRQ until one of the following is true:
3954 ** ¡X The full byte count requested by the ATU read request is received. The ATU internal bus
3955 ** initiator interface performs a initiator completion in this case.
3956 ** ¡X When operating in the conventional PCI mode, a Target Abort is received on the internal
3957 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is
3959 ** ¡X When operating in the PCI-X mode, a Target Abort is received on the internal bus from
3960 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split
3961 ** Completion Message (message class=2h - completer error, and message index=81h -
3962 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The
3963 ** ITQ for this transaction is flushed.
3964 ** ¡X When operating in the conventional PCI mode, a single data phase disconnection is
3965 ** received from the internal bus target. When the data has not been received up to the next
3966 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus.
3967 ** When not, the bus returns to idle.
3968 ** ¡X When operating in the PCI-X mode, a single data phase disconnection is received from
3969 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to
3970 ** obtain remaining data.
3971 ** ¡X When operating in the conventional PCI mode, a disconnection at Next ADB is received
3972 ** from the internal bus target. The bus returns to idle.
3973 ** ¡X When operating in the PCI-X mode, a disconnection at Next ADB is received from the
3974 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain
3976 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to
3977 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read
3978 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue
3979 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the
3980 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For
3981 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read
3982 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address
3983 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return
3984 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the
3985 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read
3986 ** commands did not match, only the address.
3987 **************************************************************************
3990 **************************************************************************
3991 ** Inbound Write Transaction
3992 **========================================================================
3993 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local
3994 ** memory or a 80331 memory-mapped register.
3995 ** Data flow for an inbound write transaction on the PCI bus is summarized as:
3996 ** ¡E The ATU claims the PCI write transaction when the PCI address is within the inbound
3997 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper
3998 ** Base Address Register during DACs) and Inbound Limit Register.
3999 ** ¡E When the IWADQ has at least one address entry available and the IWQ has at least one buffer
4000 ** available, the address is captured and the first data phase is accepted.
4001 ** ¡E The PCI interface continues to accept write data until one of the following is true:
4002 ** ¡X The initiator performs a disconnect.
4003 ** ¡X The transaction crosses a buffer boundary.
4004 ** ¡E When an address parity error is detected during the address phase of the transaction, the
4005 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address
4006 ** parity error response.
4007 ** ¡E When operating in the PCI-X mode when an attribute parity error is detected, the attribute
4008 ** parity error mechanism described in Section 3.7.1 is used.
4009 ** ¡E When a data parity error is detected while accepting data, the slave interface sets the
4010 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6
4011 ** for details of the inbound write data parity error response.
4012 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient
4013 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus
4014 ** interface becomes aware of the inbound write. When there are additional write transactions ahead
4015 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been
4016 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU
4017 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI
4018 ** interface, when operating in the PCI mode.
4019 ** In the PCI-X mode memory writes are always executed as immediate transactions, while
4020 ** configuration write transactions are processed as split transactions. The ATU generates a Split
4021 ** Completion Message, (with Message class=0h - Write Completion Class and Message index =
4022 ** 00h - Write Completion Message) once a configuration write is successfully executed.
4023 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions.
4024 ** The ATU handles such transactions as independent transactions.
4025 ** Data flow for the inbound write transaction on the internal bus is summarized as:
4026 ** ¡E The ATU internal bus master requests the internal bus when IWADQ has at least one entry
4027 ** with associated data in the IWQ.
4028 ** ¡E When the internal bus is granted, the internal bus master interface initiates the write
4029 ** transaction by driving the translated address onto the internal bus. For details on inbound
4030 ** address translation.
4031 ** ¡E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus.
4032 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI
4034 ** ¡E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When
4035 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the
4036 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred
4037 ** from the IWQ to the internal bus when data is available and the internal bus interface retains
4038 ** internal bus ownership.
4039 ** ¡E The internal bus interface stops transferring data from the current transaction to the internal
4040 ** bus when one of the following conditions becomes true:
4041 ** ¡X The internal bus initiator interface loses bus ownership. The ATU internal initiator
4042 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB
4043 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to
4044 ** complete the delivery of remaining data using the same sequence ID but with the
4045 ** modified starting address and byte count.
4046 ** ¡X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When
4047 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the
4048 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to
4049 ** complete the delivery of remaining data using the same sequence ID but with the
4050 ** modified starting address and byte count.
4051 ** ¡X A Single Data Phase Disconnect is signaled on the internal bus from the internal target.
4052 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle.
4053 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the
4054 ** bus to complete the delivery of remaining data using the same sequence ID but with the
4055 ** modified starting address and byte count.
4056 ** ¡X The data from the current transaction has completed (satisfaction of byte count). An
4057 ** initiator termination is performed and the bus returns to idle.
4058 ** ¡X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus.
4059 ** Data is flushed from the IWQ.
4060 *****************************************************************
4066 **************************************************************************
4067 ** Inbound Read Completions Data Parity Errors
4068 **========================================================================
4069 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4070 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split
4071 ** completion transaction, the ATU attempts to complete the transaction normally and no further
4073 **************************************************************************
4077 **************************************************************************
4078 ** Inbound Configuration Write Completion Message Data Parity Errors
4079 **========================================================================
4080 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4081 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR#
4082 ** assertion during the split completion transaction, the ATU attempts to complete the transaction
4083 ** normally and no further action is taken.
4084 **************************************************************************
4088 **************************************************************************
4089 ** Inbound Read Request Data Parity Errors
4090 **===================== Immediate Data Transfer ==========================
4091 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes.
4092 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having
4093 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally
4094 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is
4095 ** required and no error bits are set.
4096 **=====================Split Response Termination=========================
4097 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4098 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may
4099 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no
4100 ** action is required and no error bits are set.
4101 **************************************************************************
4105 **************************************************************************
4106 ** Inbound Write Request Data Parity Errors
4107 **========================================================================
4108 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4109 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on
4110 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write
4111 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with
4112 ** the given constraints are taken by the ATU:
4113 ** ¡E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
4114 ** following the data phase in which the data parity error is detected on the bus. This is only
4115 ** done when the Parity Error Response bit in the ATUCMD is set.
4116 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4117 ** actions is taken:
4118 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4119 ** Detected Parity Error bit in the ATUISR. When set, no action.
4120 ***************************************************************************
4125 ***************************************************************************
4126 ** Inbound Configuration Write Request
4127 ** =====================================================================
4128 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4129 ** ===============================================
4130 ** Conventional PCI Mode
4131 ** ===============================================
4132 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the
4133 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a
4134 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following
4135 ** parts of the transactions:
4136 ** ¡E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the
4137 ** address/command and data for delayed delivery to the internal configuration register.
4138 ** ¡E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status
4139 ** of the operation back to the original master.
4140 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for
4141 ** inbound transactions during Delayed Write Request cycles with the given constraints:
4142 ** ¡E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY#
4143 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the
4144 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus.
4145 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the
4146 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be
4147 ** forwarded to the internal bus. PERR# is not asserted.
4148 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4149 ** actions is taken:
4150 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4151 ** Detected Parity Error bit in the ATUISR. When set, no action.
4152 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI
4153 ** bus and the ATU returns the status from the internal bus, completing the transaction.
4154 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and
4155 ** therefore does not agree with the status being returned from the internal bus (i.e. status being
4156 ** returned is normal completion) the ATU performs the following actions with the given constraints:
4157 ** ¡E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY#
4158 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in
4159 ** the IDWQ remains since the data of retried command did not match the data within the queue.
4160 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4161 ** actions is taken:
4162 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4163 ** Detected Parity Error bit in the ATUISR. When set, no action.
4164 ** ===================================================
4166 ** ===================================================
4167 ** Data parity errors occurring during configuration write operations received by the ATU may cause
4168 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error
4169 ** occurs, the ATU accepts the write data and complete with a Split Response Termination.
4170 ** Specifically, the following actions with the given constraints are then taken by the ATU:
4171 ** ¡E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks
4172 ** cycles following the Split Response Termination in which the data parity error is detected on
4173 ** the bus. When the ATU asserts PERR#, additional actions is taken:
4174 ** ¡X A Split Write Data Parity Error message (with message class=2h - completer error and
4175 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus
4176 ** that addresses the requester of the configuration write.
4177 ** ¡X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is
4178 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no
4180 ** ¡X The Split Write Request is not enqueued and forwarded to the internal bus.
4181 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4182 ** actions is taken:
4183 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4184 ** Detected Parity Error bit in the ATUISR. When set, no action.
4186 ***************************************************************************
4190 ***************************************************************************
4191 ** Split Completion Messages
4192 ** =======================================================================
4193 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4194 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert
4195 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the
4196 ** ATU accepts the data and complete normally. Specifically, the following actions with the given
4197 ** constraints are taken by the ATU:
4198 ** ¡E PERR# is asserted three clocks cycles following the data phase in which the data parity error
4199 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD
4200 ** is set. When the ATU asserts PERR#, additional actions is taken:
4201 ** ¡X The Master Parity Error bit in the ATUSR is set.
4202 ** ¡X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the
4203 ** PCI Master Parity Error bit in the ATUISR. When set, no action.
4204 ** ¡X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover
4205 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken.
4206 ** When the ATU asserts SERR#, additional actions is taken:
4207 ** Set the SERR# Asserted bit in the ATUSR.
4208 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the
4209 ** SERR# Asserted bit in the ATUISR. When set, no action.
4210 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the
4211 ** SERR# Detected bit in the ATUISR. When clear, no action.
4212 ** ¡E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during
4213 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set.
4214 ** When the ATU sets this bit, additional actions is taken:
4215 ** ¡X When the ATU Received Split Completion Error Message Interrupt Mask bit in the
4216 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR.
4217 ** When set, no action.
4218 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4219 ** actions is taken:
4220 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4221 ** Detected Parity Error bit in the ATUISR. When set, no action.
4222 ** ¡E The transaction associated with the Split Completion Message is discarded.
4223 ** ¡E When the discarded transaction was a read, a completion error message (with message
4224 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on
4225 ** the internal bus of the 80331.
4226 *****************************************************************************
4231 ******************************************************************************************************
4232 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
4233 ** ==================================================================================================
4234 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331
4235 ** notifies the respective system when new data arrives.
4236 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation.
4237 ** window defined by:
4238 ** 1.Inbound ATU Base Address Register 0 (IABAR0)
4239 ** 2.Inbound ATU Limit Register 0 (IALR0)
4240 ** All of the Messaging Unit errors are reported in the same manner as ATU errors.
4241 ** Error conditions and status can be found in :
4244 **====================================================================================================
4245 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt
4246 **----------------------------------------------------------------------------------------------------
4247 ** Message Registers 2 Inbound Optional Optional
4249 **----------------------------------------------------------------------------------------------------
4250 ** Doorbell Registers 1 Inbound Optional Optional
4252 **----------------------------------------------------------------------------------------------------
4253 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions
4254 **----------------------------------------------------------------------------------------------------
4255 ** Index Registers 1004 32-bit Memory Locations No Optional
4256 **====================================================================================================
4257 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space
4258 **====================================================================================================
4263 **------------------------------------------------------------------------
4264 ** 0010H Inbound Message Register 0 ]
4265 ** 0014H Inbound Message Register 1 ]
4266 ** 0018H Outbound Message Register 0 ]
4267 ** 001CH Outbound Message Register 1 ] 4 Message Registers
4268 **------------------------------------------------------------------------
4269 ** 0020H Inbound Doorbell Register ]
4270 ** 0024H Inbound Interrupt Status Register ]
4271 ** 0028H Inbound Interrupt Mask Register ]
4272 ** 002CH Outbound Doorbell Register ]
4273 ** 0030H Outbound Interrupt Status Register ]
4274 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers
4275 **------------------------------------------------------------------------
4278 **------------------------------------------------------------------------
4279 ** 0040H Inbound Queue Port ]
4280 ** 0044H Outbound Queue Port ] 2 Queue Ports
4281 **------------------------------------------------------------------------
4284 **------------------------------------------------------------------------
4287 ** : Intel Xscale Microarchitecture Local Memory ]
4289 ** 0FFCH ] 1004 Index Registers
4290 *******************************************************************************
4293 *****************************************************************************
4294 ** Theory of MU Operation
4295 *****************************************************************************
4296 **--------------------
4297 ** inbound_msgaddr0:
4298 ** inbound_msgaddr1:
4299 ** outbound_msgaddr0:
4300 ** outbound_msgaddr1:
4301 ** . The MU has four independent messaging mechanisms.
4302 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers.
4303 ** Each holds a 32-bit value and generates an interrupt when written.
4304 **--------------------
4305 ** inbound_doorbell:
4306 ** outbound_doorbell:
4307 ** . The two Doorbell Registers support software interrupts.
4308 ** When a bit is set in a Doorbell Register, an interrupt is generated.
4309 **--------------------
4310 ** inbound_queueport:
4311 ** outbound_queueport:
4314 ** . The Circular Queues support a message passing scheme that uses 4 circular queues.
4315 ** The 4 circular queues are implemented in 80331 local memory.
4316 ** Two queues are used for inbound messages and two are used for outbound messages.
4317 ** Interrupts may be generated when the queue is written.
4318 **--------------------
4319 ** local_buffer 0x0050 ....0x0FFF
4320 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers.
4321 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured.
4322 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register.
4323 ** Each interrupt generated by the Messaging Unit can be masked.
4324 **--------------------
4325 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit,
4326 ** with the exception of Multi-DWORD reads to the index registers.
4327 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions
4328 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports.
4329 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response
4330 ** and the data is returned through split completion transaction(s).
4331 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch
4332 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus.
4333 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect
4334 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written.
4335 **--------------------
4336 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers.
4337 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU).
4338 ** This PCI address window is used for PCI transactions that access the 80331 local memory.
4339 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register.
4340 **--------------------
4341 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit.
4342 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information.
4343 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register.
4344 ** The Messaging Unit reports all PCI errors in the ATU Status Register.
4345 **--------------------
4346 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device.
4347 ** The register interface, message registers, doorbell registers,
4348 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface.
4349 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads).
4350 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H.
4351 **************************************************************************
4354 **************************************************************************
4355 ** Message Registers
4356 ** ==============================
4357 ** . Messages can be sent and received by the 80331 through the use of the Message Registers.
4358 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor.
4359 ** . Inbound messages are sent by the host processor and received by the 80331.
4360 ** Outbound messages are sent by the 80331 and received by the host processor.
4361 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register.
4362 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register.
4364 ** Inbound Messages:
4365 ** -----------------
4366 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core.
4367 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register.
4368 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register.
4369 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register.
4370 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software.
4371 ** The interrupt is cleared when the Intel XScale core writes a value of
4372 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register.
4373 ** ------------------------------------------------------------------------
4374 ** Inbound Message Register - IMRx
4376 ** . There are two Inbound Message Registers: IMR0 and IMR1.
4377 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated.
4378 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked
4379 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register.
4380 ** -----------------------------------------------------------------
4381 ** Bit Default Description
4382 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent.
4383 ** When written, an interrupt to the Intel XScale core may be generated.
4384 **************************************************************************
4386 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/
4387 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/
4389 **************************************************************************
4390 ** Outbound Message Register - OMRx
4391 ** --------------------------------
4392 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is
4393 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt
4394 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound
4395 ** Interrupt Mask Register.
4397 ** Bit Default Description
4398 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an
4399 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register.
4400 **************************************************************************
4402 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/
4403 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/
4405 **************************************************************************
4406 ** Doorbell Registers
4407 ** ==============================
4408 ** There are two Doorbell Registers:
4409 ** Inbound Doorbell Register
4410 ** Outbound Doorbell Register
4411 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core.
4412 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt.
4413 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set.
4415 ** Inbound Doorbells:
4416 ** ------------------
4417 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core.
4418 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1.
4419 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated.
4420 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent.
4421 ** The interrupt is recorded in the Inbound Interrupt Status Register.
4422 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register.
4423 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit.
4424 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt
4425 ** and not the values written to the Inbound Doorbell Register.
4426 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt.
4427 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set.
4428 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt.
4429 ** ------------------------------------------------------------------------
4430 ** Inbound Doorbell Register - IDR
4432 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core.
4433 ** . Bit 31 is reserved for generating an Error Doorbell interrupt.
4434 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core.
4435 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted,
4436 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register.
4437 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core.
4438 ** ------------------------------------------------------------------------
4439 ** Bit Default Description
4440 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core.
4441 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core.
4442 ** When all bits are clear, do not generate a Normal Interrupt.
4443 **************************************************************************
4445 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/
4447 **************************************************************************
4448 ** Inbound Interrupt Status Register - IISR
4450 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status.
4451 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues.
4452 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core,
4453 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt;
4454 ** these two are routed to the Messaging Unit Error interrupt input.
4455 ** The generation of interrupts recorded in the Inbound Interrupt Status Register
4456 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register.
4457 ** Some of the bits in this register are Read Only.
4458 ** For those bits, the interrupt must be cleared through another register.
4460 ** Bit Default Description
4461 ** 31:07 0000000H 0 2 Reserved
4462 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware
4463 ** when an Index Register has been written after a PCI transaction.
4464 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set
4465 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
4466 ** An Error interrupt is generated for this condition.
4467 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written.
4468 ** Once cleared, an interrupt does NOT be generated
4469 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
4470 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared,
4471 ** software must retain the information that the Inbound Post queue status is not empty.
4472 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller.
4473 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set.
4474 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear.
4475 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one
4476 ** Normal Interrupt bit in the Inbound Doorbell Register is set.
4477 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear.
4478 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written.
4479 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written.
4480 **************************************************************************
4482 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/
4483 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40
4484 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20
4485 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10
4486 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08
4487 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04
4488 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02
4489 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01
4491 **************************************************************************
4492 ** Inbound Interrupt Mask Register - IIMR
4494 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit.
4495 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register.
4496 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register.
4497 ** They only affect the generation of the Intel XScale core interrupt.
4498 ** ------------------------------------------------------------------------
4499 ** Bit Default Description
4500 ** 31:07 000000H 0 2 Reserved
4501 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware
4502 ** when an Index Register has been written after a PCI transaction.
4503 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated
4504 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
4505 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated
4506 ** by the MU hardware when the Inbound Post Queue has been written.
4507 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt
4508 ** when the Error Interrupt bit of the Inbound Doorbell Register is set.
4509 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated
4510 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set.
4511 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1
4512 ** Interrupt generated by a write to the Inbound Message 1 Register.
4513 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set,
4514 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register.
4515 **************************************************************************
4517 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/
4518 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40
4519 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20
4520 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10
4521 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08
4522 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04
4523 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02
4524 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01
4526 **************************************************************************
4527 ** Outbound Doorbell Register - ODR
4529 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel
4530 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The
4531 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the
4532 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register.
4533 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only
4534 ** be cleared by an external PCI agent.
4535 ** ----------------------------------------------------------------------
4536 ** Bit Default Description
4540 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output
4541 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4542 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled).
4543 ** When this bit is cleared, the P_INTC# interrupt output
4544 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4545 ** signal is deasserted.
4546 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output
4547 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4548 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled).
4549 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low)
4550 ** signal is deasserted.
4551 **************************************************************************
4553 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/
4555 **************************************************************************
4556 ** Outbound Interrupt Status Register - OISR
4558 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the
4559 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular
4560 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may
4561 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the
4562 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another
4564 ** ----------------------------------------------------------------------
4565 ** Bit Default Description
4566 ** 31:05 000000H 000 2 Reserved
4567 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register.
4568 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared.
4569 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is
4570 ** cleared when any prefetch data has been read from the Outbound Queue Port.
4571 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound
4572 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound
4573 ** Doorbell Register must all be clear.
4574 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is
4575 ** written. Clearing this bit clears the interrupt.
4576 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is
4577 ** written. Clearing this bit clears the interrupt.
4578 **************************************************************************
4580 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/
4581 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
4582 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
4583 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
4584 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
4585 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
4587 **************************************************************************
4588 ** Outbound Interrupt Mask Register - OIMR
4589 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI
4590 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a
4591 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI
4592 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated.
4593 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They
4594 ** only affect the generation of the PCI interrupt.
4595 ** ----------------------------------------------------------------------
4596 ** Bit Default Description
4597 ** 31:05 000000H Reserved
4598 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28)
4599 ** in the Outbound Doorbell Register is set.
4600 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in
4601 ** the prefetch buffer is valid.
4602 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound
4603 ** Doorbell Register.
4604 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt
4605 ** generated by a write to the Outbound Message 1 Register.
4606 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt
4607 ** generated by a write to the Outbound Message 0 Register.
4608 **************************************************************************
4610 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/
4611 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
4612 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
4613 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
4614 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
4615 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
4616 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
4618 **************************************************************************
4620 **************************************************************************
4622 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/
4623 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/
4625 **************************************************************************
4627 ** ======================================================================
4628 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In
4629 ** this case, inbound and outbound refer to the direction of the flow of posted messages.
4630 ** Inbound messages are either:
4631 ** ¡E posted messages by other processors for the Intel XScale core to process or
4632 ** ¡E free (or empty) messages that can be reused by other processors.
4633 ** Outbound messages are either:
4634 ** ¡E posted messages by the Intel XScale core for other processors to process or
4635 ** ¡E free (or empty) messages that can be reused by the Intel XScale core.
4636 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331.
4637 ** The four Circular Queues are used to pass messages in the following manner.
4638 ** . The two inbound queues are used to handle inbound messages
4639 ** and the two outbound queues are used to handle outbound messages.
4640 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages.
4641 ** The other inbound queue is designated the Post queue and it contains inbound posted messages.
4642 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue.
4644 ** =============================================================================================================
4645 ** Circular Queue Summary
4646 ** _____________________________________________________________________________________________________________
4647 ** | Queue Name | Purpose | Action on PCI Interface|
4648 ** |______________________|____________________________________________________________|_________________________|
4649 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written |
4650 ** | | waiting to be processed by the 80331 | |
4651 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read |
4652 ** | | available for use by other processors | |
4653 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read |
4654 ** | | that are being posted to the other processors | |
4655 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written |
4656 ** | | available for use by the 80331 | |
4657 ** |______________________|____________________________________________________________|_________________________|
4659 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one
4660 ** queue and to receive free messages returning from the 80331.
4661 ** The host processor posts inbound messages,
4662 ** the Intel XScale core receives the posted message and when it is finished with the message,
4663 ** places it back on the inbound free queue for reuse by the host processor.
4665 ** The circular queues are accessed by external PCI agents through two port locations in the PCI
4667 ** Inbound Queue Port
4668 ** and Outbound Queue Port.
4669 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue.
4670 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue.
4671 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 )
4672 ** does not cause the MU hardware to increment the queue pointers.
4673 ** This is treated as when the PCI transaction did not occur.
4674 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
4675 ** ======================================================================================
4676 ** Overview of Circular Queue Operation
4677 ** ======================================================================================
4678 ** . The data storage for the circular queues must be provided by the 80331 local memory.
4679 ** . The base address of the circular queues is contained in the Queue Base Address Register.
4680 ** Each entry in the queue is a 32-bit data value.
4681 ** . Each read from or write to the queue may access only one queue entry.
4682 ** . Multi-DWORD accesses to the circular queues are not allowed.
4683 ** Sub-DWORD accesses are promoted to DWORD accesses.
4684 ** . Each circular queue has a head pointer and a tail pointer.
4685 ** The pointers are offsets from the Queue Base Address.
4686 ** . Writes to a queue occur at the head of the queue and reads occur from the tail.
4687 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware.
4688 ** Which unit maintains the pointer is determined by the writer of the queue.
4689 ** More details about the pointers are given in the queue descriptions below.
4690 ** The pointers are incremented after the queue access.
4691 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size.
4693 ** Messaging Unit...
4695 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions.
4696 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted.
4697 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes).
4698 ** . All four queues must be the same size and may be contiguous.
4699 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes.
4700 ** The Queue size is determined by the Queue Size field in the MU Configuration Register.
4701 ** . There is one base address for all four queues.
4702 ** It is stored in the Queue Base Address Register (QBAR).
4703 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field.
4704 ** here shows an example of how the circular queues should be set up based on the
4705 ** Intelligent I/O (I 2 O) Architecture Specification.
4706 ** Other ordering of the circular queues is possible.
4708 ** Queue Starting Address
4709 ** Inbound Free Queue QBAR
4710 ** Inbound Post Queue QBAR + Queue Size
4711 ** Outbound Post Queue QBAR + 2 * Queue Size
4712 ** Outbound Free Queue QBAR + 3 * Queue Size
4713 ** ===================================================================================
4714 ** Inbound Post Queue
4715 ** ------------------
4716 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process.
4717 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents.
4718 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware.
4719 ** For a PCI write transaction that accesses the Inbound Queue Port,
4720 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register.
4721 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register.
4722 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written.
4723 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status.
4724 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared.
4725 ** The interrupt can be masked by the Inbound Interrupt Mask Register.
4726 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee
4727 ** that the full condition is recognized by the core processor.
4728 ** In addition, to guarantee that the queue does not get overwritten,
4729 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt.
4730 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
4731 ** Only a new message posting the in the inbound queue generates a new interrupt.
4732 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared,
4733 ** software must retain the information that the Inbound Post queue status.
4734 ** From the time that the PCI write transaction is received until the data is written
4735 ** in local memory and the Inbound Post Head Pointer Register is incremented,
4736 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry.
4737 ** The Intel XScale core may read messages from the Inbound Post Queue
4738 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register.
4739 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register.
4740 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware),
4741 ** the hardware retries any PCI writes until a slot in the queue becomes available.
4742 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer.
4743 ** ===================================================================================
4744 ** Inbound Free Queue
4745 ** ------------------
4746 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use.
4747 ** This queue is read from the queue tail by external PCI agents.
4748 ** It is written to the queue head by the Intel XScale core.
4749 ** The tail pointer is maintained by the MU hardware.
4750 ** The head pointer is maintained by the Intel XScale core.
4751 ** For a PCI read transaction that accesses the Inbound Queue Port,
4752 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer.
4753 ** When the queue is not empty (head and tail pointers are not equal)
4754 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned.
4755 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware),
4756 ** the value of -1 (FFFF.FFFFH) is returned.
4757 ** When the queue was not empty and the MU succeeded in returning the data at the tail,
4758 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register.
4759 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue.
4760 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register.
4761 ** When the PCI read access occurs, the data is read directly from the prefetch register.
4762 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register
4763 ** when the head and tail pointers are equal and the queue is empty.
4764 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty,
4765 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH
4766 ** and the Inbound Free Head Pointer Register is written.
4767 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue.
4768 ** A prefetch must appear atomic from the perspective of the external PCI agent.
4769 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed.
4770 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the
4771 ** local memory location pointed to by the Inbound Free Head Pointer Register.
4772 ** The processor must then increment the Inbound Free Head Pointer Register.
4773 ** ==================================================================================
4774 ** Outbound Post Queue
4775 ** -------------------
4776 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale
4777 ** core for other processors to process. This queue is read from the queue tail by external PCI agents.
4778 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the
4779 ** MU hardware. The head pointer is maintained by the Intel XScale core.
4780 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the
4781 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not
4782 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head
4783 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail
4784 ** pointers are equal and the head pointer was last updated by hardware), the value of -1
4785 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the
4786 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer
4788 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate
4789 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the
4790 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access
4791 ** occurs, the data is read directly from the prefetch register.
4792 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head
4793 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when
4794 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically
4795 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head
4796 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head
4797 ** Pointer Register when it adds messages to the queue.
4798 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is
4799 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry
4800 ** until the prefetch is completed.
4801 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch
4802 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound
4803 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the
4804 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound
4805 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register.
4806 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to
4807 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then
4808 ** increment the Outbound Post Head Pointer Register.
4809 ** ==================================================
4810 ** Outbound Free Queue
4811 ** -----------------------
4812 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel
4813 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is
4814 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel
4815 ** XScale core. The head pointer is maintained by the MU hardware.
4816 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the
4817 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the
4818 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free
4819 ** Head Pointer Register.
4820 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal
4821 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is
4822 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free
4823 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can
4824 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the
4825 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the
4827 ** From the time that a PCI write transaction is received until the data is written in local memory and
4828 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to
4829 ** access the Outbound Free Queue Port is signalled a retry.
4830 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data
4831 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must
4832 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full,
4833 ** the hardware must retry any PCI writes until a slot in the queue becomes available.
4835 ** ==================================================================================
4836 ** Circular Queue Summary
4837 ** ----------------------
4838 ** ________________________________________________________________________________________________________________________________________________
4839 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by|
4840 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
4841 ** |Inbound Post | Inbound Queue | | | | |
4842 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale |
4843 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
4844 ** |Inbound Free | Inbound Queue | | | | |
4845 ** | Queue | Port | NO | NO | Intel XScale | MU hardware |
4846 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
4847 ** ==================================================================================
4848 ** Circular Queue Status Summary
4849 ** ----------------------
4850 ** ____________________________________________________________________________________________________
4851 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update |
4852 ** |_____________________|________________|_____________________|_______________________________________|
4853 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software |
4854 ** |_____________________|________________|_____________________|_______________________________________|
4855 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware |
4856 ** |_____________________|________________|_____________________|_______________________________________|
4857 **************************************************************************
4861 **************************************************************************
4863 ** ========================
4864 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core.
4865 ** These registers are for inbound messages only.
4866 ** The interrupt is recorded in the Inbound Interrupt Status Register.
4867 ** The storage for the Index Registers is allocated from the 80331 local memory.
4868 ** PCI write accesses to the Index Registers write the data to local memory.
4869 ** PCI read accesses to the Index Registers read the data from local memory.
4870 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H
4871 ** to Inbound ATU Translate Value Register + FFFH.
4872 ** . The address of the first write access is stored in the Index Address Register.
4873 ** This register is written during the earliest write access and provides a means to determine which Index Register was written.
4874 ** Once updated by the MU, the Index Address Register is not updated until the Index Register
4875 ** Interrupt bit in the Inbound Interrupt Status Register is cleared.
4876 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access.
4877 ** Writes by the Intel XScale core to the local memory used by the Index Registers
4878 ** does not cause an interrupt and does not update the Index Address Register.
4879 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes.
4880 **************************************************************************
4883 **************************************************************************
4884 ** Messaging Unit Internal Bus Memory Map
4885 ** =======================================
4886 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_
4887 ** FFFF E300H reserved |
4889 ** FFFF E30CH reserved |
4890 ** FFFF E310H Inbound Message Register 0 | Available through
4891 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window
4892 ** FFFF E318H Outbound Message Register 0 |
4893 ** FFFF E31CH Outbound Message Register 1 | or
4894 ** FFFF E320H Inbound Doorbell Register |
4895 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to
4896 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core
4897 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address
4898 ** FFFF E330H Outbound Interrupt Status Register |
4899 ** FFFF E334H Outbound Interrupt Mask Register |
4900 ** ______________________________________________________________________|________________________________________
4901 ** FFFF E338H reserved |
4902 ** FFFF E33CH reserved |
4903 ** FFFF E340H reserved |
4904 ** FFFF E344H reserved |
4905 ** FFFF E348H reserved |
4906 ** FFFF E34CH reserved |
4907 ** FFFF E350H MU Configuration Register |
4908 ** FFFF E354H Queue Base Address Register |
4909 ** FFFF E358H reserved |
4910 ** FFFF E35CH reserved | must translate PCI address to
4911 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core
4912 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address
4913 ** FFFF E368H Inbound Post Head pointer Register |
4914 ** FFFF E36CH Inbound Post Tail Pointer Register |
4915 ** FFFF E370H Outbound Free Head Pointer Register |
4916 ** FFFF E374H Outbound Free Tail Pointer Register |
4917 ** FFFF E378H Outbound Post Head pointer Register |
4918 ** FFFF E37CH Outbound Post Tail Pointer Register |
4919 ** FFFF E380H Index Address Register |
4920 ** FFFF E384H reserved |
4922 ** FFFF E3FCH reserved |
4923 ** ______________________________________________________________________|_______________________________________
4924 **************************************************************************
4927 **************************************************************************
4928 ** MU Configuration Register - MUCR FFFF.E350H
4930 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue.
4931 ** . The Circular Queue Enable bit enables or disables the Circular Queues.
4932 ** The Circular Queues are disabled at reset to allow the software to initialize the head
4933 ** and tail pointer registers before any PCI accesses to the Queue Ports.
4934 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues.
4935 ** ------------------------------------------------------------------------
4936 ** Bit Default Description
4937 ** 31:06 000000H 00 2 Reserved
4938 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue.
4939 ** All four queues are the same size.
4940 ** ¡E 00001 2 - 4K Entries (16 Kbytes)
4941 ** ¡E 00010 2 - 8K Entries (32 Kbytes)
4942 ** ¡E 00100 2 - 16K Entries (64 Kbytes)
4943 ** ¡E 01000 2 - 32K Entries (128 Kbytes)
4944 ** ¡E 10000 2 - 64K Entries (256 Kbytes)
4945 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular
4946 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores
4947 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when
4948 ** disabled. When set, the Circular Queues are fully enabled.
4949 **************************************************************************
4951 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350
4952 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020
4953 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010
4954 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008
4955 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004
4956 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002
4957 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/
4959 **************************************************************************
4960 ** Queue Base Address Register - QBAR
4962 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues.
4963 ** The base address is required to be located on a 1 Mbyte address boundary.
4964 ** . All Circular Queue head and tail pointers are based on the QBAR.
4965 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits.
4966 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register.
4968 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface
4969 ** ------------------------------------------------------------------------
4970 ** Bit Default Description
4971 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
4972 ** 19:00 00000H Reserved
4973 **************************************************************************
4975 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354
4977 **************************************************************************
4978 ** Inbound Free Head Pointer Register - IFHPR
4980 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from
4981 ** the Queue Base Address of the head pointer for the Inbound Free Queue.
4982 ** The Head Pointer must be aligned on a DWORD address boundary.
4983 ** When read, the Queue Base Address is provided in the upper 12 bits of the register.
4984 ** Writes to the upper 12 bits of the register are ignored.
4985 ** This register is maintained by software.
4986 ** ------------------------------------------------------------------------
4987 ** Bit Default Description
4988 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
4989 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue.
4990 ** 01:00 00 2 Reserved
4991 **************************************************************************
4993 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360
4995 **************************************************************************
4996 ** Inbound Free Tail Pointer Register - IFTPR
4998 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue
4999 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a
5000 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
5001 ** of the register. Writes to the upper 12 bits of the register are ignored.
5002 ** ------------------------------------------------------------------------
5003 ** Bit Default Description
5004 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
5005 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue.
5006 ** 01:00 00 2 Reserved
5007 **************************************************************************
5009 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364
5011 **************************************************************************
5012 ** Inbound Post Head Pointer Register - IPHPR
5014 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue
5015 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on
5016 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
5017 ** of the register. Writes to the upper 12 bits of the register are ignored.
5018 ** ------------------------------------------------------------------------
5019 ** Bit Default Description
5020 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
5021 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue.
5022 ** 01:00 00 2 Reserved
5023 **************************************************************************
5025 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368
5027 **************************************************************************
5028 ** Inbound Post Tail Pointer Register - IPTPR
5030 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue
5031 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a
5032 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
5033 ** of the register. Writes to the upper 12 bits of the register are ignored.
5034 ** ------------------------------------------------------------------------
5035 ** Bit Default Description
5036 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
5037 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue.
5038 ** 01:00 00 2 Reserved
5039 **************************************************************************
5041 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C
5043 **************************************************************************
5044 ** Index Address Register - IAR
5046 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register.
5047 ** It is written by the MU when the Index Registers are written by a PCI agent.
5048 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared.
5049 ** . The local memory address of the Index Register least recently accessed is computed
5050 ** by adding the Index Address Register to the Inbound ATU Translate Value Register.
5051 ** ------------------------------------------------------------------------
5052 ** Bit Default Description
5053 ** 31:12 000000H Reserved
5054 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH)
5055 ** 01:00 00 2 Reserved
5056 **************************************************************************
5058 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/
5060 **********************************************************************************************************
5061 ** RS-232 Interface for Areca Raid Controller
5062 ** The low level command interface is exclusive with VT100 terminal
5063 ** --------------------------------------------------------------------
5064 ** 1. Sequence of command execution
5065 ** --------------------------------------------------------------------
5066 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
5067 ** (B) Command block : variable length of data including length, command code, data and checksum byte
5068 ** (C) Return data : variable length of data
5069 ** --------------------------------------------------------------------
5071 ** --------------------------------------------------------------------
5072 ** (A) 1st byte : command block length (low byte)
5073 ** (B) 2nd byte : command block length (high byte)
5074 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes
5075 ** (C) 3rd byte : command code
5076 ** (D) 4th and following bytes : variable length data bytes depends on command code
5077 ** (E) last byte : checksum byte (sum of 1st byte until last data byte)
5078 ** --------------------------------------------------------------------
5079 ** 3. Command code and associated data
5080 ** --------------------------------------------------------------------
5081 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management,
5082 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access.
5083 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command.
5086 ** GUI_SET_SERIAL=0x10,
5090 ** GUI_CHECK_PASSWORD,
5093 ** GUI_SET_ETHERNET_ADDR,
5097 ** GUI_GET_HW_MONITOR,
5099 ** // GUI_QUICK_CREATE=0x20, (function removed)
5100 ** GUI_GET_INFO_R=0x20,
5106 ** GUI_MUTE_BEEPER=0x30,
5107 ** GUI_BEEPER_SETTING,
5108 ** GUI_SET_PASSWORD,
5109 ** GUI_HOST_INTERFACE_MODE,
5110 ** GUI_REBUILD_PRIORITY,
5111 ** GUI_MAX_ATA_MODE,
5112 ** GUI_RESET_CONTROLLER,
5113 ** GUI_COM_PORT_SETTING,
5114 ** GUI_NO_OPERATION,
5117 ** GUI_CREATE_PASS_THROUGH=0x40,
5118 ** GUI_MODIFY_PASS_THROUGH,
5119 ** GUI_DELETE_PASS_THROUGH,
5120 ** GUI_IDENTIFY_DEVICE,
5122 ** GUI_CREATE_RAIDSET=0x50,
5123 ** GUI_DELETE_RAIDSET,
5124 ** GUI_EXPAND_RAIDSET,
5125 ** GUI_ACTIVATE_RAIDSET,
5126 ** GUI_CREATE_HOT_SPARE,
5127 ** GUI_DELETE_HOT_SPARE,
5129 ** GUI_CREATE_VOLUME=0x60,
5130 ** GUI_MODIFY_VOLUME,
5131 ** GUI_DELETE_VOLUME,
5132 ** GUI_START_CHECK_VOLUME,
5133 ** GUI_STOP_CHECK_VOLUME
5136 ** Command description :
5138 ** GUI_SET_SERIAL : Set the controller serial#
5139 ** byte 0,1 : length
5140 ** byte 2 : command code 0x10
5141 ** byte 3 : password length (should be 0x0f)
5142 ** byte 4-0x13 : should be "ArEcATecHnoLogY"
5143 ** byte 0x14--0x23 : Serial number string (must be 16 bytes)
5144 ** GUI_SET_VENDOR : Set vendor string for the controller
5145 ** byte 0,1 : length
5146 ** byte 2 : command code 0x11
5147 ** byte 3 : password length (should be 0x08)
5148 ** byte 4-0x13 : should be "ArEcAvAr"
5149 ** byte 0x14--0x3B : vendor string (must be 40 bytes)
5150 ** GUI_SET_MODEL : Set the model name of the controller
5151 ** byte 0,1 : length
5152 ** byte 2 : command code 0x12
5153 ** byte 3 : password length (should be 0x08)
5154 ** byte 4-0x13 : should be "ArEcAvAr"
5155 ** byte 0x14--0x1B : model string (must be 8 bytes)
5156 ** GUI_IDENTIFY : Identify device
5157 ** byte 0,1 : length
5158 ** byte 2 : command code 0x13
5159 ** return "Areca RAID Subsystem "
5160 ** GUI_CHECK_PASSWORD : Verify password
5161 ** byte 0,1 : length
5162 ** byte 2 : command code 0x14
5163 ** byte 3 : password length
5164 ** byte 4-0x?? : user password to be checked
5165 ** GUI_LOGOUT : Logout GUI (force password checking on next command)
5166 ** byte 0,1 : length
5167 ** byte 2 : command code 0x15
5168 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16)
5170 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address
5171 ** byte 0,1 : length
5172 ** byte 2 : command code 0x17
5173 ** byte 3 : password length (should be 0x08)
5174 ** byte 4-0x13 : should be "ArEcAvAr"
5175 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes)
5176 ** GUI_SET_LOGO : Set logo in HTTP
5177 ** byte 0,1 : length
5178 ** byte 2 : command code 0x18
5179 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo)
5180 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a
5181 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes)
5182 ** note .... page0 1st 2 byte must be actual length of the JPG file
5183 ** GUI_POLL_EVENT : Poll If Event Log Changed
5184 ** byte 0,1 : length
5185 ** byte 2 : command code 0x19
5186 ** GUI_GET_EVENT : Read Event
5187 ** byte 0,1 : length
5188 ** byte 2 : command code 0x1a
5189 ** byte 3 : Event Page (0:1st page/1/2/3:last page)
5190 ** GUI_GET_HW_MONITOR : Get HW monitor data
5191 ** byte 0,1 : length
5192 ** byte 2 : command code 0x1b
5193 ** byte 3 : # of FANs(example 2)
5194 ** byte 4 : # of Voltage sensor(example 3)
5195 ** byte 5 : # of temperature sensor(example 2)
5196 ** byte 6 : # of power
5197 ** byte 7/8 : Fan#0 (RPM)
5198 ** byte 9/10 : Fan#1
5199 ** byte 11/12 : Voltage#0 original value in *1000
5200 ** byte 13/14 : Voltage#0 value
5201 ** byte 15/16 : Voltage#1 org
5202 ** byte 17/18 : Voltage#1
5203 ** byte 19/20 : Voltage#2 org
5204 ** byte 21/22 : Voltage#2
5207 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1)
5208 ** byte 26 : UPS indicator
5209 ** GUI_QUICK_CREATE : Quick create raid/volume set
5210 ** byte 0,1 : length
5211 ** byte 2 : command code 0x20
5212 ** byte 3/4/5/6 : raw capacity
5213 ** byte 7 : raid level
5214 ** byte 8 : stripe size
5216 ** byte 10/11/12/13: device mask (the devices to create raid/volume)
5217 ** This function is removed, application like to implement quick create function
5218 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function.
5219 ** GUI_GET_INFO_R : Get Raid Set Information
5220 ** byte 0,1 : length
5221 ** byte 2 : command code 0x20
5222 ** byte 3 : raidset#
5224 ** typedef struct sGUI_RAIDSET
5226 ** BYTE grsRaidSetName[16];
5227 ** DWORD grsCapacity;
5228 ** DWORD grsCapacityX;
5229 ** DWORD grsFailMask;
5230 ** BYTE grsDevArray[32];
5231 ** BYTE grsMemberDevices;
5232 ** BYTE grsNewMemberDevices;
5233 ** BYTE grsRaidState;
5235 ** BYTE grsVolumeList[16];
5239 ** BYTE grsFreeSegments;
5240 ** DWORD grsRawStripes[8];
5242 ** DWORD grsRes5; // Total to 128 bytes
5243 ** DWORD grsRes6; // Total to 128 bytes
5244 ** } sGUI_RAIDSET, *pGUI_RAIDSET;
5245 ** GUI_GET_INFO_V : Get Volume Set Information
5246 ** byte 0,1 : length
5247 ** byte 2 : command code 0x21
5248 ** byte 3 : volumeset#
5250 ** typedef struct sGUI_VOLUMESET
5252 ** BYTE gvsVolumeName[16]; // 16
5253 ** DWORD gvsCapacity;
5254 ** DWORD gvsCapacityX;
5255 ** DWORD gvsFailMask;
5256 ** DWORD gvsStripeSize;
5257 ** DWORD gvsNewFailMask;
5258 ** DWORD gvsNewStripeSize;
5259 ** DWORD gvsVolumeStatus;
5260 ** DWORD gvsProgress; // 32
5261 ** sSCSI_ATTR gvsScsi;
5262 ** BYTE gvsMemberDisks;
5263 ** BYTE gvsRaidLevel; // 8
5265 ** BYTE gvsNewMemberDisks;
5266 ** BYTE gvsNewRaidLevel;
5267 ** BYTE gvsRaidSetNumber;
5268 ** BYTE gvsRes0; // 4
5269 ** BYTE gvsRes1[4]; // 64 bytes
5270 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET;
5272 ** GUI_GET_INFO_P : Get Physical Drive Information
5273 ** byte 0,1 : length
5274 ** byte 2 : command code 0x22
5275 ** byte 3 : drive # (from 0 to max-channels - 1)
5277 ** typedef struct sGUI_PHY_DRV
5279 ** BYTE gpdModelName[40];
5280 ** BYTE gpdSerialNumber[20];
5281 ** BYTE gpdFirmRev[8];
5282 ** DWORD gpdCapacity;
5283 ** DWORD gpdCapacityX; // Reserved for expansion
5284 ** BYTE gpdDeviceState;
5286 ** BYTE gpdCurrentUdmaMode;
5287 ** BYTE gpdUdmaMode;
5288 ** BYTE gpdDriveSelect;
5289 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set
5290 ** sSCSI_ATTR gpdScsi;
5291 ** BYTE gpdReserved[40]; // Total to 128 bytes
5292 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV;
5294 ** GUI_GET_INFO_S : Get System Information
5295 ** byte 0,1 : length
5296 ** byte 2 : command code 0x23
5298 ** typedef struct sCOM_ATTR
5300 ** BYTE comBaudRate;
5301 ** BYTE comDataBits;
5302 ** BYTE comStopBits;
5304 ** BYTE comFlowControl;
5305 ** } sCOM_ATTR, *pCOM_ATTR;
5307 ** typedef struct sSYSTEM_INFO
5309 ** BYTE gsiVendorName[40];
5310 ** BYTE gsiSerialNumber[16];
5311 ** BYTE gsiFirmVersion[16];
5312 ** BYTE gsiBootVersion[16];
5313 ** BYTE gsiMbVersion[16];
5314 ** BYTE gsiModelName[8];
5315 ** BYTE gsiLocalIp[4];
5316 ** BYTE gsiCurrentIp[4];
5317 ** DWORD gsiTimeTick;
5318 ** DWORD gsiCpuSpeed;
5322 ** DWORD gsiMemorySize;
5323 ** DWORD gsiMemorySpeed;
5325 ** BYTE gsiMacAddress[6];
5328 ** BYTE gsiChannelUsage;
5329 ** BYTE gsiMaxAtaMode;
5330 ** BYTE gsiSdramEcc; // 1:if ECC enabled
5331 ** BYTE gsiRebuildPriority;
5332 ** sCOM_ATTR gsiComA; // 5 bytes
5333 ** sCOM_ATTR gsiComB; // 5 bytes
5334 ** BYTE gsiIdeChannels;
5335 ** BYTE gsiScsiHostChannels;
5336 ** BYTE gsiIdeHostChannels;
5337 ** BYTE gsiMaxVolumeSet;
5338 ** BYTE gsiMaxRaidSet;
5339 ** BYTE gsiEtherPort; // 1:if ether net port supported
5340 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported
5342 ** } sSYSTEM_INFO, *pSYSTEM_INFO;
5344 ** GUI_CLEAR_EVENT : Clear System Event
5345 ** byte 0,1 : length
5346 ** byte 2 : command code 0x24
5348 ** GUI_MUTE_BEEPER : Mute current beeper
5349 ** byte 0,1 : length
5350 ** byte 2 : command code 0x30
5352 ** GUI_BEEPER_SETTING : Disable beeper
5353 ** byte 0,1 : length
5354 ** byte 2 : command code 0x31
5355 ** byte 3 : 0->disable, 1->enable
5357 ** GUI_SET_PASSWORD : Change password
5358 ** byte 0,1 : length
5359 ** byte 2 : command code 0x32
5360 ** byte 3 : pass word length ( must <= 15 )
5361 ** byte 4 : password (must be alpha-numerical)
5363 ** GUI_HOST_INTERFACE_MODE : Set host interface mode
5364 ** byte 0,1 : length
5365 ** byte 2 : command code 0x33
5366 ** byte 3 : 0->Independent, 1->cluster
5368 ** GUI_REBUILD_PRIORITY : Set rebuild priority
5369 ** byte 0,1 : length
5370 ** byte 2 : command code 0x34
5371 ** byte 3 : 0/1/2/3 (low->high)
5373 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used
5374 ** byte 0,1 : length
5375 ** byte 2 : command code 0x35
5376 ** byte 3 : 0/1/2/3 (133/100/66/33)
5378 ** GUI_RESET_CONTROLLER : Reset Controller
5379 ** byte 0,1 : length
5380 ** byte 2 : command code 0x36
5381 ** *Response with VT100 screen (discard it)
5383 ** GUI_COM_PORT_SETTING : COM port setting
5384 ** byte 0,1 : length
5385 ** byte 2 : command code 0x37
5386 ** byte 3 : 0->COMA (term port), 1->COMB (debug port)
5387 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200)
5388 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit)
5389 ** byte 6 : stop bit (0:1, 1:2 stop bits)
5390 ** byte 7 : parity (0:none, 1:off, 2:even)
5391 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none)
5393 ** GUI_NO_OPERATION : No operation
5394 ** byte 0,1 : length
5395 ** byte 2 : command code 0x38
5397 ** GUI_DHCP_IP : Set DHCP option and local IP address
5398 ** byte 0,1 : length
5399 ** byte 2 : command code 0x39
5400 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled
5401 ** byte 4/5/6/7 : IP address
5403 ** GUI_CREATE_PASS_THROUGH : Create pass through disk
5404 ** byte 0,1 : length
5405 ** byte 2 : command code 0x40
5406 ** byte 3 : device #
5407 ** byte 4 : scsi channel (0/1)
5408 ** byte 5 : scsi id (0-->15)
5409 ** byte 6 : scsi lun (0-->7)
5410 ** byte 7 : tagged queue (1 : enabled)
5411 ** byte 8 : cache mode (1 : enabled)
5412 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
5413 ** (0/1/2/3/4, 33/66/100/133/150 for ide )
5415 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk
5416 ** byte 0,1 : length
5417 ** byte 2 : command code 0x41
5418 ** byte 3 : device #
5419 ** byte 4 : scsi channel (0/1)
5420 ** byte 5 : scsi id (0-->15)
5421 ** byte 6 : scsi lun (0-->7)
5422 ** byte 7 : tagged queue (1 : enabled)
5423 ** byte 8 : cache mode (1 : enabled)
5424 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
5425 ** (0/1/2/3/4, 33/66/100/133/150 for ide )
5427 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk
5428 ** byte 0,1 : length
5429 ** byte 2 : command code 0x42
5430 ** byte 3 : device# to be deleted
5432 ** GUI_IDENTIFY_DEVICE : Identify Device
5433 ** byte 0,1 : length
5434 ** byte 2 : command code 0x43
5435 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected)
5436 ** byte 4/5/6/7 : IDE device mask to be flashed
5437 ** note .... no response data available
5439 ** GUI_CREATE_RAIDSET : Create Raid Set
5440 ** byte 0,1 : length
5441 ** byte 2 : command code 0x50
5442 ** byte 3/4/5/6 : device mask
5443 ** byte 7-22 : raidset name (if byte 7 == 0:use default)
5445 ** GUI_DELETE_RAIDSET : Delete Raid Set
5446 ** byte 0,1 : length
5447 ** byte 2 : command code 0x51
5448 ** byte 3 : raidset#
5450 ** GUI_EXPAND_RAIDSET : Expand Raid Set
5451 ** byte 0,1 : length
5452 ** byte 2 : command code 0x52
5453 ** byte 3 : raidset#
5454 ** byte 4/5/6/7 : device mask for expansion
5455 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K )
5456 ** byte 11/12/13 : repeat for each volume in the raidset ....
5458 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set
5459 ** byte 0,1 : length
5460 ** byte 2 : command code 0x53
5461 ** byte 3 : raidset#
5463 ** GUI_CREATE_HOT_SPARE : Create hot spare disk
5464 ** byte 0,1 : length
5465 ** byte 2 : command code 0x54
5466 ** byte 3/4/5/6 : device mask for hot spare creation
5468 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk
5469 ** byte 0,1 : length
5470 ** byte 2 : command code 0x55
5471 ** byte 3/4/5/6 : device mask for hot spare deletion
5473 ** GUI_CREATE_VOLUME : Create volume set
5474 ** byte 0,1 : length
5475 ** byte 2 : command code 0x60
5476 ** byte 3 : raidset#
5477 ** byte 4-19 : volume set name (if byte4 == 0, use default)
5478 ** byte 20-27 : volume capacity (blocks)
5479 ** byte 28 : raid level
5480 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5481 ** byte 30 : channel
5484 ** byte 33 : 1 enable tag
5485 ** byte 34 : 1 enable cache
5486 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5487 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5488 ** byte 36 : 1 to select quick init
5490 ** GUI_MODIFY_VOLUME : Modify volume Set
5491 ** byte 0,1 : length
5492 ** byte 2 : command code 0x61
5493 ** byte 3 : volumeset#
5494 ** byte 4-19 : new volume set name (if byte4 == 0, not change)
5495 ** byte 20-27 : new volume capacity (reserved)
5496 ** byte 28 : new raid level
5497 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5498 ** byte 30 : new channel
5500 ** byte 32 : new LUN
5501 ** byte 33 : 1 enable tag
5502 ** byte 34 : 1 enable cache
5503 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5504 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5506 ** GUI_DELETE_VOLUME : Delete volume set
5507 ** byte 0,1 : length
5508 ** byte 2 : command code 0x62
5509 ** byte 3 : volumeset#
5511 ** GUI_START_CHECK_VOLUME : Start volume consistency check
5512 ** byte 0,1 : length
5513 ** byte 2 : command code 0x63
5514 ** byte 3 : volumeset#
5516 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check
5517 ** byte 0,1 : length
5518 ** byte 2 : command code 0x64
5519 ** ---------------------------------------------------------------------
5521 ** ---------------------------------------------------------------------
5522 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
5523 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte)
5524 ** (C) status or data :
5525 ** <1> If length == 1 ==> 1 byte status code
5526 ** #define GUI_OK 0x41
5527 ** #define GUI_RAIDSET_NOT_NORMAL 0x42
5528 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43
5529 ** #define GUI_NO_RAIDSET 0x44
5530 ** #define GUI_NO_VOLUMESET 0x45
5531 ** #define GUI_NO_PHYSICAL_DRIVE 0x46
5532 ** #define GUI_PARAMETER_ERROR 0x47
5533 ** #define GUI_UNSUPPORTED_COMMAND 0x48
5534 ** #define GUI_DISK_CONFIG_CHANGED 0x49
5535 ** #define GUI_INVALID_PASSWORD 0x4a
5536 ** #define GUI_NO_DISK_SPACE 0x4b
5537 ** #define GUI_CHECKSUM_ERROR 0x4c
5538 ** #define GUI_PASSWORD_REQUIRED 0x4d
5539 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code
5540 ** (E) Checksum : checksum of length and status or data byte
5541 **************************************************************************
projects / dragonfly.git / blob