1 /* $FreeBSD: src/sys/dev/ct/bshwvar.h,v 1.2.2.1 2001/07/26 02:32:18 nyan Exp $ */
2 /* $DragonFly: src/sys/dev/disk/ct/Attic/bshwvar.h,v 1.3 2003/08/27 10:35:16 rob Exp $ */
3 /* $NecBSD: bshwvar.h,v 1.3.14.3 2001/06/21 04:07:37 honda Exp $ */
7 * [NetBSD for NEC PC-98 series]
8 * Copyright (c) 1994, 1995, 1996, 1997, 1998
9 * NetBSD/pc98 porting staff. All rights reserved.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
39 * NEC 55 compatible board specific definitions
42 #define BSHW_DEFAULT_CHIPCLK 20 /* 20MHz */
43 #define BSHW_DEFAULT_HOSTID 7
46 #define BSHW_SYNC_RELOAD 0x01
47 #define BSHW_SMFIFO 0x02
48 #define BSHW_DOUBLE_DMACHAN 0x04
52 int ((*hw_dma_init) (struct ct_softc *));
53 void ((*hw_dma_start) (struct ct_softc *));
54 void ((*hw_dma_stop) (struct ct_softc *));
66 u_int sc_sdatalen; /* SMIT */
67 u_int sc_edatalen; /* SMIT */
70 u_int8_t *sc_bounce_phys;
71 u_int8_t *sc_bounce_addr;
73 bus_addr_t sc_minphys;
76 #define BSHW_READ_INTERRUPT_DRIVEN 0x0001
77 #define BSHW_WRITE_INTERRUPT_DRIVEN 0x0002
78 #define BSHW_DMA_BLOCK 0x0010
79 #define BSHW_SMIT_BLOCK 0x0020
84 void ((*sc_dmasync_before)) (struct ct_softc *);
85 void ((*sc_dmasync_after)) (struct ct_softc *);
88 void bshw_synch_setup (struct ct_softc *, struct targ_info *);
89 void bshw_bus_reset (struct ct_softc *);
90 int bshw_read_settings (struct ct_bus_access_handle *, struct bshw_softc *);
91 int bshw_smit_xfer_start (struct ct_softc *);
92 void bshw_smit_xfer_stop (struct ct_softc *);
93 int bshw_dma_xfer_start (struct ct_softc *);
94 void bshw_dma_xfer_stop (struct ct_softc *);
96 extern struct dvcfg_hwsel bshw_hwsel;
97 #endif /* !_BSHWVAR_H_ */