2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.14 2004/07/23 07:16:29 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
39 * VIA Rhine fast ethernet PCI NIC driver
41 * Supports various network adapters based on the VIA Rhine
42 * and Rhine II PCI controllers, including the D-Link DFE530TX.
43 * Datasheets are available at http://www.via.com.tw.
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The VIA Rhine controllers are similar in some respects to the
52 * the DEC tulip chips, except less complicated. The controller
53 * uses an MII bus and an external physical layer interface. The
54 * receiver has a one entry perfect filter and a 64-bit hash table
55 * multicast filter. Transmit and receive descriptors are similar
58 * The Rhine has a serious flaw in its transmit DMA mechanism:
59 * transmit buffers must be longword aligned. Unfortunately,
60 * FreeBSD doesn't guarantee that mbufs will be filled in starting
61 * at longword boundaries, so we have to do a buffer copy before
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/sockio.h>
69 #include <sys/malloc.h>
70 #include <sys/kernel.h>
71 #include <sys/socket.h>
74 #include <net/if_arp.h>
75 #include <net/ethernet.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
81 #include <vm/vm.h> /* for vtophys */
82 #include <vm/pmap.h> /* for vtophys */
83 #include <machine/clock.h> /* for DELAY */
84 #include <machine/bus_pio.h>
85 #include <machine/bus_memio.h>
86 #include <machine/bus.h>
87 #include <machine/resource.h>
91 #include "../mii_layer/mii.h"
92 #include "../mii_layer/miivar.h"
94 #include <bus/pci/pcireg.h>
95 #include <bus/pci/pcivar.h>
101 /* "controller miibus0" required. See GENERIC if you get errors here. */
102 #include "miibus_if.h"
107 * Various supported device vendors/types and their names.
109 static struct vr_type vr_devs[] = {
110 { VIA_VENDORID, VIA_DEVICEID_RHINE,
111 "VIA VT3043 Rhine I 10/100BaseTX" },
112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
113 "VIA VT86C100A Rhine II 10/100BaseTX" },
114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
115 "VIA VT6102 Rhine II 10/100BaseTX" },
116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
117 "VIA VT6105 Rhine III 10/100BaseTX" },
118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
119 "VIA VT6105M Rhine III 10/100BaseTX" },
120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
121 "Delta Electronics Rhine II 10/100BaseTX" },
122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
123 "Addtron Technology Rhine II 10/100BaseTX" },
127 static int vr_probe (device_t);
128 static int vr_attach (device_t);
129 static int vr_detach (device_t);
131 static int vr_newbuf (struct vr_softc *,
132 struct vr_chain_onefrag *,
134 static int vr_encap (struct vr_softc *, struct vr_chain *,
137 static void vr_rxeof (struct vr_softc *);
138 static void vr_rxeoc (struct vr_softc *);
139 static void vr_txeof (struct vr_softc *);
140 static void vr_txeoc (struct vr_softc *);
141 static void vr_tick (void *);
142 static void vr_intr (void *);
143 static void vr_start (struct ifnet *);
144 static int vr_ioctl (struct ifnet *, u_long, caddr_t,
146 static void vr_init (void *);
147 static void vr_stop (struct vr_softc *);
148 static void vr_watchdog (struct ifnet *);
149 static void vr_shutdown (device_t);
150 static int vr_ifmedia_upd (struct ifnet *);
151 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *);
154 static void vr_mii_sync (struct vr_softc *);
155 static void vr_mii_send (struct vr_softc *, u_int32_t, int);
157 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *);
158 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *);
159 static int vr_miibus_readreg (device_t, int, int);
160 static int vr_miibus_writereg (device_t, int, int, int);
161 static void vr_miibus_statchg (device_t);
163 static void vr_setcfg (struct vr_softc *, int);
164 static u_int8_t vr_calchash (u_int8_t *);
165 static void vr_setmulti (struct vr_softc *);
166 static void vr_reset (struct vr_softc *);
167 static int vr_list_rx_init (struct vr_softc *);
168 static int vr_list_tx_init (struct vr_softc *);
171 #define VR_RES SYS_RES_IOPORT
172 #define VR_RID VR_PCI_LOIO
174 #define VR_RES SYS_RES_MEMORY
175 #define VR_RID VR_PCI_LOMEM
178 static device_method_t vr_methods[] = {
179 /* Device interface */
180 DEVMETHOD(device_probe, vr_probe),
181 DEVMETHOD(device_attach, vr_attach),
182 DEVMETHOD(device_detach, vr_detach),
183 DEVMETHOD(device_shutdown, vr_shutdown),
186 DEVMETHOD(bus_print_child, bus_generic_print_child),
187 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
190 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
191 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
192 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
197 static driver_t vr_driver = {
200 sizeof(struct vr_softc)
203 static devclass_t vr_devclass;
205 DECLARE_DUMMY_MODULE(if_vr);
206 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
207 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
209 #define VR_SETBIT(sc, reg, x) \
210 CSR_WRITE_1(sc, reg, \
211 CSR_READ_1(sc, reg) | x)
213 #define VR_CLRBIT(sc, reg, x) \
214 CSR_WRITE_1(sc, reg, \
215 CSR_READ_1(sc, reg) & ~x)
217 #define VR_SETBIT16(sc, reg, x) \
218 CSR_WRITE_2(sc, reg, \
219 CSR_READ_2(sc, reg) | x)
221 #define VR_CLRBIT16(sc, reg, x) \
222 CSR_WRITE_2(sc, reg, \
223 CSR_READ_2(sc, reg) & ~x)
225 #define VR_SETBIT32(sc, reg, x) \
226 CSR_WRITE_4(sc, reg, \
227 CSR_READ_4(sc, reg) | x)
229 #define VR_CLRBIT32(sc, reg, x) \
230 CSR_WRITE_4(sc, reg, \
231 CSR_READ_4(sc, reg) & ~x)
234 CSR_WRITE_1(sc, VR_MIICMD, \
235 CSR_READ_1(sc, VR_MIICMD) | x)
238 CSR_WRITE_1(sc, VR_MIICMD, \
239 CSR_READ_1(sc, VR_MIICMD) & ~x)
243 * Sync the PHYs by setting data bit and strobing the clock 32 times.
245 static void vr_mii_sync(sc)
250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
252 for (i = 0; i < 32; i++) {
253 SIO_SET(VR_MIICMD_CLK);
255 SIO_CLR(VR_MIICMD_CLK);
263 * Clock a series of bits through the MII.
265 static void vr_mii_send(sc, bits, cnt)
272 SIO_CLR(VR_MIICMD_CLK);
274 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
276 SIO_SET(VR_MIICMD_DATAIN);
278 SIO_CLR(VR_MIICMD_DATAIN);
281 SIO_CLR(VR_MIICMD_CLK);
283 SIO_SET(VR_MIICMD_CLK);
289 * Read an PHY register through the MII.
291 static int vr_mii_readreg(sc, frame)
293 struct vr_mii_frame *frame;
302 * Set up frame for RX.
304 frame->mii_stdelim = VR_MII_STARTDELIM;
305 frame->mii_opcode = VR_MII_READOP;
306 frame->mii_turnaround = 0;
309 CSR_WRITE_1(sc, VR_MIICMD, 0);
310 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
315 SIO_SET(VR_MIICMD_DIR);
320 * Send command/address info.
322 vr_mii_send(sc, frame->mii_stdelim, 2);
323 vr_mii_send(sc, frame->mii_opcode, 2);
324 vr_mii_send(sc, frame->mii_phyaddr, 5);
325 vr_mii_send(sc, frame->mii_regaddr, 5);
328 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
330 SIO_SET(VR_MIICMD_CLK);
334 SIO_CLR(VR_MIICMD_DIR);
337 SIO_CLR(VR_MIICMD_CLK);
339 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
340 SIO_SET(VR_MIICMD_CLK);
344 * Now try reading data bits. If the ack failed, we still
345 * need to clock through 16 cycles to keep the PHY(s) in sync.
348 for(i = 0; i < 16; i++) {
349 SIO_CLR(VR_MIICMD_CLK);
351 SIO_SET(VR_MIICMD_CLK);
357 for (i = 0x8000; i; i >>= 1) {
358 SIO_CLR(VR_MIICMD_CLK);
361 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
362 frame->mii_data |= i;
365 SIO_SET(VR_MIICMD_CLK);
371 SIO_CLR(VR_MIICMD_CLK);
373 SIO_SET(VR_MIICMD_CLK);
388 /* Set the PHY-adress */
389 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
392 /* Set the register-adress */
393 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
394 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
396 for (i = 0; i < 10000; i++) {
397 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
402 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
412 * Write to a PHY register through the MII.
414 static int vr_mii_writereg(sc, frame)
416 struct vr_mii_frame *frame;
424 CSR_WRITE_1(sc, VR_MIICMD, 0);
425 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
428 * Set up frame for TX.
431 frame->mii_stdelim = VR_MII_STARTDELIM;
432 frame->mii_opcode = VR_MII_WRITEOP;
433 frame->mii_turnaround = VR_MII_TURNAROUND;
436 * Turn on data output.
438 SIO_SET(VR_MIICMD_DIR);
442 vr_mii_send(sc, frame->mii_stdelim, 2);
443 vr_mii_send(sc, frame->mii_opcode, 2);
444 vr_mii_send(sc, frame->mii_phyaddr, 5);
445 vr_mii_send(sc, frame->mii_regaddr, 5);
446 vr_mii_send(sc, frame->mii_turnaround, 2);
447 vr_mii_send(sc, frame->mii_data, 16);
450 SIO_SET(VR_MIICMD_CLK);
452 SIO_CLR(VR_MIICMD_CLK);
458 SIO_CLR(VR_MIICMD_DIR);
470 /* Set the PHY-adress */
471 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
474 /* Set the register-adress and data to write */
475 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
476 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
478 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
480 for (i = 0; i < 10000; i++) {
481 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
492 static int vr_miibus_readreg(dev, phy, reg)
497 struct vr_mii_frame frame;
499 sc = device_get_softc(dev);
501 switch (sc->vr_revid) {
502 case REV_ID_VT6102_APOLLO:
509 bzero((char *)&frame, sizeof(frame));
511 frame.mii_phyaddr = phy;
512 frame.mii_regaddr = reg;
513 vr_mii_readreg(sc, &frame);
515 return(frame.mii_data);
518 static int vr_miibus_writereg(dev, phy, reg, data)
520 u_int16_t phy, reg, data;
523 struct vr_mii_frame frame;
525 sc = device_get_softc(dev);
527 switch (sc->vr_revid) {
528 case REV_ID_VT6102_APOLLO:
535 bzero((char *)&frame, sizeof(frame));
537 frame.mii_phyaddr = phy;
538 frame.mii_regaddr = reg;
539 frame.mii_data = data;
541 vr_mii_writereg(sc, &frame);
546 static void vr_miibus_statchg(dev)
550 struct mii_data *mii;
552 sc = device_get_softc(dev);
553 mii = device_get_softc(sc->vr_miibus);
554 vr_setcfg(sc, mii->mii_media_active);
560 * Calculate CRC of a multicast group address, return the lower 6 bits.
562 static u_int8_t vr_calchash(addr)
565 u_int32_t crc, carry;
569 /* Compute CRC for the address value. */
570 crc = 0xFFFFFFFF; /* initial value */
572 for (i = 0; i < 6; i++) {
574 for (j = 0; j < 8; j++) {
575 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
579 crc = (crc ^ 0x04c11db6) | carry;
583 /* return the filter bit position */
584 return((crc >> 26) & 0x0000003F);
588 * Program the 64-bit multicast hash filter.
590 static void vr_setmulti(sc)
595 u_int32_t hashes[2] = { 0, 0 };
596 struct ifmultiaddr *ifma;
600 ifp = &sc->arpcom.ac_if;
602 rxfilt = CSR_READ_1(sc, VR_RXCFG);
604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
605 rxfilt |= VR_RXCFG_RX_MULTI;
606 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
607 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
608 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
612 /* first, zot all the existing hash bits */
613 CSR_WRITE_4(sc, VR_MAR0, 0);
614 CSR_WRITE_4(sc, VR_MAR1, 0);
616 /* now program new ones */
617 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
618 ifma = ifma->ifma_link.le_next) {
619 if (ifma->ifma_addr->sa_family != AF_LINK)
621 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
623 hashes[0] |= (1 << h);
625 hashes[1] |= (1 << (h - 32));
630 rxfilt |= VR_RXCFG_RX_MULTI;
632 rxfilt &= ~VR_RXCFG_RX_MULTI;
634 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
635 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
636 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
642 * In order to fiddle with the
643 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
644 * first have to put the transmit and/or receive logic in the idle state.
646 static void vr_setcfg(sc, media)
652 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
654 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
657 if ((media & IFM_GMASK) == IFM_FDX)
658 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
660 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
668 static void vr_reset(sc)
673 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
675 for (i = 0; i < VR_TIMEOUT; i++) {
677 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
680 if (i == VR_TIMEOUT) {
681 if (sc->vr_revid < REV_ID_VT3065_A)
682 printf("vr%d: reset never completed!\n", sc->vr_unit);
684 /* Use newer force reset command */
685 printf("vr%d: Using force reset command.\n", sc->vr_unit);
686 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
690 /* Wait a little while for the chip to get its brains in order. */
697 * Probe for a VIA Rhine chip. Check the PCI vendor and device
698 * IDs against our list and return a device name if we find a match.
700 static int vr_probe(dev)
707 while(t->vr_name != NULL) {
708 if ((pci_get_vendor(dev) == t->vr_vid) &&
709 (pci_get_device(dev) == t->vr_did)) {
710 device_set_desc(dev, t->vr_name);
720 * Attach the interface. Allocate softc structures, do ifmedia
721 * setup and ethernet/BPF attach.
723 static int vr_attach(dev)
727 u_char eaddr[ETHER_ADDR_LEN];
731 int unit, error = 0, rid;
735 sc = device_get_softc(dev);
736 unit = device_get_unit(dev);
737 bzero(sc, sizeof(struct vr_softc *));
740 * Handle power management nonsense.
743 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF;
744 if (command == 0x01) {
746 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4);
747 if (command & VR_PSTATE_MASK) {
748 u_int32_t iobase, membase, irq;
750 /* Save important PCI config data. */
751 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
752 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
753 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
755 /* Reset the power state. */
756 printf("vr%d: chip is in D%d power mode "
757 "-- setting to D0\n", unit, command & VR_PSTATE_MASK);
758 command &= 0xFFFFFFFC;
759 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4);
761 /* Restore PCI config data. */
762 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
763 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
764 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
769 * Map control/status registers.
771 command = pci_read_config(dev, PCIR_COMMAND, 4);
772 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
773 pci_write_config(dev, PCIR_COMMAND, command, 4);
774 command = pci_read_config(dev, PCIR_COMMAND, 4);
775 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF;
778 if (!(command & PCIM_CMD_PORTEN)) {
779 printf("vr%d: failed to enable I/O ports!\n", unit);
784 if (!(command & PCIM_CMD_MEMEN)) {
785 printf("vr%d: failed to enable memory mapping!\n", unit);
791 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid,
792 0, ~0, 1, RF_ACTIVE);
794 if (sc->vr_res == NULL) {
795 printf("vr%d: couldn't map ports/memory\n", unit);
800 sc->vr_btag = rman_get_bustag(sc->vr_res);
801 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
803 /* Allocate interrupt */
805 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
806 RF_SHAREABLE | RF_ACTIVE);
808 if (sc->vr_irq == NULL) {
809 printf("vr%d: couldn't map interrupt\n", unit);
810 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
815 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET,
816 vr_intr, sc, &sc->vr_intrhand);
819 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
820 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
821 printf("vr%d: couldn't set up irq\n", unit);
826 * Windows may put the chip in suspend mode when it
827 * shuts down. Be sure to kick it in the head to wake it
830 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
832 /* Reset the adapter. */
836 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
837 * initialization and disable AUTOPOLL.
839 pci_write_config(dev, VR_PCI_MODE,
840 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
841 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
844 * Get station address. The way the Rhine chips work,
845 * you're not allowed to directly access the EEPROM once
846 * they've been programmed a special way. Consequently,
847 * we need to read the node address from the PAR0 and PAR1
850 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
852 for (i = 0; i < ETHER_ADDR_LEN; i++)
853 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
857 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
858 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
860 if (sc->vr_ldata == NULL) {
861 printf("vr%d: no memory for list buffers!\n", unit);
862 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
863 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
864 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
869 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
871 ifp = &sc->arpcom.ac_if;
873 if_initname(ifp, "vr", unit);
874 ifp->if_mtu = ETHERMTU;
875 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
876 ifp->if_ioctl = vr_ioctl;
877 ifp->if_start = vr_start;
878 ifp->if_watchdog = vr_watchdog;
879 ifp->if_init = vr_init;
880 ifp->if_baudrate = 10000000;
881 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1;
886 if (mii_phy_probe(dev, &sc->vr_miibus,
887 vr_ifmedia_upd, vr_ifmedia_sts)) {
888 printf("vr%d: MII without any phy!\n", sc->vr_unit);
889 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
891 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
892 contigfree(sc->vr_ldata,
893 sizeof(struct vr_list_data), M_DEVBUF);
898 callout_handle_init(&sc->vr_stat_ch);
901 * Call MI attach routine.
903 ether_ifattach(ifp, eaddr);
910 static int vr_detach(dev)
919 sc = device_get_softc(dev);
920 ifp = &sc->arpcom.ac_if;
925 bus_generic_detach(dev);
926 device_delete_child(dev, sc->vr_miibus);
928 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
929 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
930 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
932 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
940 * Initialize the transmit descriptors.
942 static int vr_list_tx_init(sc)
945 struct vr_chain_data *cd;
946 struct vr_list_data *ld;
951 for (i = 0; i < VR_TX_LIST_CNT; i++) {
952 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
953 if (i == (VR_TX_LIST_CNT - 1))
954 cd->vr_tx_chain[i].vr_nextdesc =
957 cd->vr_tx_chain[i].vr_nextdesc =
958 &cd->vr_tx_chain[i + 1];
961 cd->vr_tx_free = &cd->vr_tx_chain[0];
962 cd->vr_tx_tail = cd->vr_tx_head = NULL;
969 * Initialize the RX descriptors and allocate mbufs for them. Note that
970 * we arrange the descriptors in a closed ring, so that the last descriptor
971 * points back to the first.
973 static int vr_list_rx_init(sc)
976 struct vr_chain_data *cd;
977 struct vr_list_data *ld;
983 for (i = 0; i < VR_RX_LIST_CNT; i++) {
984 cd->vr_rx_chain[i].vr_ptr =
985 (struct vr_desc *)&ld->vr_rx_list[i];
986 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
988 if (i == (VR_RX_LIST_CNT - 1)) {
989 cd->vr_rx_chain[i].vr_nextdesc =
991 ld->vr_rx_list[i].vr_next =
992 vtophys(&ld->vr_rx_list[0]);
994 cd->vr_rx_chain[i].vr_nextdesc =
995 &cd->vr_rx_chain[i + 1];
996 ld->vr_rx_list[i].vr_next =
997 vtophys(&ld->vr_rx_list[i + 1]);
1001 cd->vr_rx_head = &cd->vr_rx_chain[0];
1007 * Initialize an RX descriptor and attach an MBUF cluster.
1008 * Note: the length fields are only 11 bits wide, which means the
1009 * largest size we can specify is 2047. This is important because
1010 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
1011 * overflow the field and make a mess.
1013 static int vr_newbuf(sc, c, m)
1014 struct vr_softc *sc;
1015 struct vr_chain_onefrag *c;
1018 struct mbuf *m_new = NULL;
1021 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1025 MCLGET(m_new, MB_DONTWAIT);
1026 if (!(m_new->m_flags & M_EXT)) {
1030 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1033 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1034 m_new->m_data = m_new->m_ext.ext_buf;
1037 m_adj(m_new, sizeof(u_int64_t));
1040 c->vr_ptr->vr_status = VR_RXSTAT;
1041 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
1042 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
1048 * A frame has been uploaded: pass the resulting mbuf chain up to
1049 * the higher level protocols.
1051 static void vr_rxeof(sc)
1052 struct vr_softc *sc;
1056 struct vr_chain_onefrag *cur_rx;
1060 ifp = &sc->arpcom.ac_if;
1062 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
1064 struct mbuf *m0 = NULL;
1066 cur_rx = sc->vr_cdata.vr_rx_head;
1067 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
1068 m = cur_rx->vr_mbuf;
1071 * If an error occurs, update stats, clear the
1072 * status word and leave the mbuf cluster in place:
1073 * it should simply get re-used next time this descriptor
1074 * comes up in the ring.
1076 if (rxstat & VR_RXSTAT_RXERR) {
1078 printf("vr%d: rx error (%02x):",
1079 sc->vr_unit, rxstat & 0x000000ff);
1080 if (rxstat & VR_RXSTAT_CRCERR)
1081 printf(" crc error");
1082 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1083 printf(" frame alignment error\n");
1084 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1085 printf(" FIFO overflow");
1086 if (rxstat & VR_RXSTAT_GIANT)
1087 printf(" received giant packet");
1088 if (rxstat & VR_RXSTAT_RUNT)
1089 printf(" received runt packet");
1090 if (rxstat & VR_RXSTAT_BUSERR)
1091 printf(" system bus error");
1092 if (rxstat & VR_RXSTAT_BUFFERR)
1093 printf("rx buffer error");
1095 vr_newbuf(sc, cur_rx, m);
1099 /* No errors; receive the packet. */
1100 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1103 * XXX The VIA Rhine chip includes the CRC with every
1104 * received frame, and there's no way to turn this
1105 * behavior off (at least, I can't find anything in
1106 * the manual that explains how to do it) so we have
1107 * to trim off the CRC manually.
1109 total_len -= ETHER_CRC_LEN;
1111 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1112 total_len + ETHER_ALIGN, 0, ifp, NULL);
1113 vr_newbuf(sc, cur_rx, m);
1118 m_adj(m0, ETHER_ALIGN);
1122 (*ifp->if_input)(ifp, m);
1129 struct vr_softc *sc;
1134 ifp = &sc->arpcom.ac_if;
1138 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1142 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1144 ; /* Wait for receiver to stop */
1147 printf("vr%d: rx shutdown error!\n", sc->vr_unit);
1148 sc->vr_flags |= VR_F_RESTART;
1154 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1155 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1156 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1162 * A frame was downloaded to the chip. It's safe for us to clean up
1166 static void vr_txeof(sc)
1167 struct vr_softc *sc;
1169 struct vr_chain *cur_tx;
1172 ifp = &sc->arpcom.ac_if;
1174 /* Reset the timeout timer; if_txeoc will clear it. */
1178 if (sc->vr_cdata.vr_tx_head == NULL)
1182 * Go through our tx list and free mbufs for those
1183 * frames that have been transmitted.
1185 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) {
1189 cur_tx = sc->vr_cdata.vr_tx_head;
1190 txstat = cur_tx->vr_ptr->vr_status;
1192 if ((txstat & VR_TXSTAT_ABRT) ||
1193 (txstat & VR_TXSTAT_UDF)) {
1195 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1197 ; /* Wait for chip to shutdown */
1199 printf("vr%d: tx shutdown timeout\n", sc->vr_unit);
1200 sc->vr_flags |= VR_F_RESTART;
1203 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1204 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1208 if (txstat & VR_TXSTAT_OWN)
1211 if (txstat & VR_TXSTAT_ERRSUM) {
1213 if (txstat & VR_TXSTAT_DEFER)
1214 ifp->if_collisions++;
1215 if (txstat & VR_TXSTAT_LATECOLL)
1216 ifp->if_collisions++;
1219 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1222 if (cur_tx->vr_mbuf != NULL) {
1223 m_freem(cur_tx->vr_mbuf);
1224 cur_tx->vr_mbuf = NULL;
1227 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) {
1228 sc->vr_cdata.vr_tx_head = NULL;
1229 sc->vr_cdata.vr_tx_tail = NULL;
1233 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc;
1240 * TX 'end of channel' interrupt handler.
1242 static void vr_txeoc(sc)
1243 struct vr_softc *sc;
1247 ifp = &sc->arpcom.ac_if;
1249 if (sc->vr_cdata.vr_tx_head == NULL) {
1250 ifp->if_flags &= ~IFF_OACTIVE;
1251 sc->vr_cdata.vr_tx_tail = NULL;
1258 static void vr_tick(xsc)
1261 struct vr_softc *sc;
1262 struct mii_data *mii;
1268 if (sc->vr_flags & VR_F_RESTART) {
1269 printf("vr%d: restarting\n", sc->vr_unit);
1273 sc->vr_flags &= ~VR_F_RESTART;
1276 mii = device_get_softc(sc->vr_miibus);
1279 sc->vr_stat_ch = timeout(vr_tick, sc, hz);
1286 static void vr_intr(arg)
1289 struct vr_softc *sc;
1294 ifp = &sc->arpcom.ac_if;
1296 /* Supress unwanted interrupts. */
1297 if (!(ifp->if_flags & IFF_UP)) {
1302 /* Disable interrupts. */
1303 if ((ifp->if_flags & IFF_POLLING) == 0)
1304 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1308 status = CSR_READ_2(sc, VR_ISR);
1310 CSR_WRITE_2(sc, VR_ISR, status);
1312 if ((status & VR_INTRS) == 0)
1315 if (status & VR_ISR_RX_OK)
1318 if (status & VR_ISR_RX_DROPPED) {
1319 printf("vr%d: rx packet lost\n", sc->vr_unit);
1323 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1324 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1325 printf("vr%d: receive error (%04x)",
1326 sc->vr_unit, status);
1327 if (status & VR_ISR_RX_NOBUF)
1328 printf(" no buffers");
1329 if (status & VR_ISR_RX_OFLOW)
1330 printf(" overflow");
1331 if (status & VR_ISR_RX_DROPPED)
1332 printf(" packet lost");
1337 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1343 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1344 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1346 if ((status & VR_ISR_UDFI) ||
1347 (status & VR_ISR_TX_ABRT2) ||
1348 (status & VR_ISR_TX_ABRT)) {
1350 if (sc->vr_cdata.vr_tx_head != NULL) {
1351 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
1352 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1360 /* Re-enable interrupts. */
1361 if ((ifp->if_flags & IFF_POLLING) == 0)
1362 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1364 if (ifp->if_snd.ifq_head != NULL) {
1372 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1373 * pointers to the fragment pointers.
1375 static int vr_encap(sc, c, m_head)
1376 struct vr_softc *sc;
1378 struct mbuf *m_head;
1381 struct vr_desc *f = NULL;
1389 * The VIA Rhine wants packet buffers to be longword
1390 * aligned, but very often our mbufs aren't. Rather than
1391 * waste time trying to decide when to copy and when not
1392 * to copy, just do it all the time.
1395 struct mbuf *m_new = NULL;
1397 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1398 if (m_new == NULL) {
1399 printf("vr%d: no memory for tx list\n", sc->vr_unit);
1402 if (m_head->m_pkthdr.len > MHLEN) {
1403 MCLGET(m_new, MB_DONTWAIT);
1404 if (!(m_new->m_flags & M_EXT)) {
1406 printf("vr%d: no memory for tx list\n",
1411 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1412 mtod(m_new, caddr_t));
1413 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1417 * The Rhine chip doesn't auto-pad, so we have to make
1418 * sure to pad short frames out to the minimum frame length
1421 if (m_head->m_len < VR_MIN_FRAMELEN) {
1422 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1423 m_new->m_len = m_new->m_pkthdr.len;
1426 f->vr_data = vtophys(mtod(m_new, caddr_t));
1427 f->vr_ctl = total_len = m_new->m_len;
1428 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG;
1433 c->vr_mbuf = m_head;
1434 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT;
1435 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr);
1441 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1442 * to the mbuf data regions directly in the transmit lists. We also save a
1443 * copy of the pointers since the transmit list fragment pointers are
1444 * physical addresses.
1447 static void vr_start(ifp)
1450 struct vr_softc *sc;
1451 struct mbuf *m_head = NULL;
1452 struct vr_chain *cur_tx = NULL, *start_tx;
1456 if (ifp->if_flags & IFF_OACTIVE)
1460 * Check for an available queue slot. If there are none,
1463 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) {
1464 ifp->if_flags |= IFF_OACTIVE;
1468 start_tx = sc->vr_cdata.vr_tx_free;
1470 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) {
1471 IF_DEQUEUE(&ifp->if_snd, m_head);
1475 /* Pick a descriptor off the free list. */
1476 cur_tx = sc->vr_cdata.vr_tx_free;
1477 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
1479 /* Pack the data into the descriptor. */
1480 if (vr_encap(sc, cur_tx, m_head)) {
1481 IF_PREPEND(&ifp->if_snd, m_head);
1482 ifp->if_flags |= IFF_OACTIVE;
1487 if (cur_tx != start_tx)
1488 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1491 * If there's a BPF listener, bounce a copy of this frame
1495 bpf_mtap(ifp, cur_tx->vr_mbuf);
1497 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1498 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1502 * If there are no frames queued, bail.
1507 sc->vr_cdata.vr_tx_tail = cur_tx;
1509 if (sc->vr_cdata.vr_tx_head == NULL)
1510 sc->vr_cdata.vr_tx_head = start_tx;
1513 * Set a timeout in case the chip goes out to lunch.
1520 static void vr_init(xsc)
1523 struct vr_softc *sc = xsc;
1524 struct ifnet *ifp = &sc->arpcom.ac_if;
1525 struct mii_data *mii;
1530 mii = device_get_softc(sc->vr_miibus);
1533 * Cancel pending I/O and free all RX/TX buffers.
1539 * Set our station address.
1541 for (i = 0; i < ETHER_ADDR_LEN; i++)
1542 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1545 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1546 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1549 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1550 * so we must set both.
1552 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1553 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1555 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1556 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1558 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1559 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1561 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1562 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1564 /* Init circular RX list. */
1565 if (vr_list_rx_init(sc) == ENOBUFS) {
1566 printf("vr%d: initialization failed: no "
1567 "memory for rx buffers\n", sc->vr_unit);
1574 * Init tx descriptors.
1576 vr_list_tx_init(sc);
1578 /* If we want promiscuous mode, set the allframes bit. */
1579 if (ifp->if_flags & IFF_PROMISC)
1580 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1582 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1584 /* Set capture broadcast bit to capture broadcast frames. */
1585 if (ifp->if_flags & IFF_BROADCAST)
1586 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1588 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1591 * Program the multicast filter, if necessary.
1596 * Load the address of the RX list.
1598 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1600 /* Enable receiver and transmitter. */
1601 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1602 VR_CMD_TX_ON|VR_CMD_RX_ON|
1605 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1608 * Enable interrupts, unless we are polling.
1610 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1611 if ((ifp->if_flags & IFF_POLLING) == 0)
1612 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1616 ifp->if_flags |= IFF_RUNNING;
1617 ifp->if_flags &= ~IFF_OACTIVE;
1621 sc->vr_stat_ch = timeout(vr_tick, sc, hz);
1627 * Set media options.
1629 static int vr_ifmedia_upd(ifp)
1632 struct vr_softc *sc;
1636 if (ifp->if_flags & IFF_UP)
1643 * Report current media status.
1645 static void vr_ifmedia_sts(ifp, ifmr)
1647 struct ifmediareq *ifmr;
1649 struct vr_softc *sc;
1650 struct mii_data *mii;
1653 mii = device_get_softc(sc->vr_miibus);
1655 ifmr->ifm_active = mii->mii_media_active;
1656 ifmr->ifm_status = mii->mii_media_status;
1661 static int vr_ioctl(ifp, command, data, cr)
1667 struct vr_softc *sc = ifp->if_softc;
1668 struct ifreq *ifr = (struct ifreq *) data;
1669 struct mii_data *mii;
1678 error = ether_ioctl(ifp, command, data);
1681 if (ifp->if_flags & IFF_UP) {
1684 if (ifp->if_flags & IFF_RUNNING)
1696 mii = device_get_softc(sc->vr_miibus);
1697 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1709 #ifdef DEVICE_POLLING
1713 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1715 struct vr_softc *sc = ifp->if_softc;
1717 if (cmd == POLL_DEREGISTER) {
1718 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1726 static void vr_watchdog(ifp)
1729 struct vr_softc *sc;
1734 printf("vr%d: watchdog timeout\n", sc->vr_unit);
1736 #ifdef DEVICE_POLLING
1737 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) {
1738 printf("vr%d ints don't seem to be working, "
1739 "emergency switch to polling\n", sc->vr_unit);
1740 emergency_poll_enable("if_vr");
1741 if (ether_poll_register(vr_poll, ifp)) {
1742 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1752 if (ifp->if_snd.ifq_head != NULL)
1757 * Stop the adapter and free any mbufs allocated to the
1760 static void vr_stop(sc)
1761 struct vr_softc *sc;
1766 ifp = &sc->arpcom.ac_if;
1769 untimeout(vr_tick, sc, sc->vr_stat_ch);
1771 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1772 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1773 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1774 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1775 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1778 * Free data in the RX lists.
1780 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1781 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1782 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1783 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1786 bzero((char *)&sc->vr_ldata->vr_rx_list,
1787 sizeof(sc->vr_ldata->vr_rx_list));
1790 * Free the TX list buffers.
1792 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1793 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1794 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1795 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1799 bzero((char *)&sc->vr_ldata->vr_tx_list,
1800 sizeof(sc->vr_ldata->vr_tx_list));
1802 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1808 * Stop all chip I/O so that the kernel's probe routines don't
1809 * get confused by errant DMAs when rebooting.
1811 static void vr_shutdown(dev)
1814 struct vr_softc *sc;
1816 sc = device_get_softc(dev);