sys/dev/disk/aic7xxx/aic7xxx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      3940, 2940, aic7895, aic7890, aic7880,
   4  *      aic7870, aic7860 and aic7850 SCSI controllers
   5  *
   6  * Copyright (c) 1994-2001 Justin T. Gibbs.
   7  * Copyright (c) 2000-2001 Adaptec Inc.
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions, and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    substantially similar to the "NO WARRANTY" disclaimer below
  18  *    ("Disclaimer") and any redistribution must be conditioned upon
  19  *    including a substantially similar Disclaimer requirement for further
  20  *    binary redistribution.
  21  * 3. Neither the names of the above-listed copyright holders nor the names
  22  *    of any contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  * Alternatively, this software may be distributed under the terms of the
  26  * GNU General Public License ("GPL") version 2 as published by the Free
  27  * Software Foundation.
  28  *
  29  * NO WARRANTY
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  36  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  37  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  38  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  39  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  40  * POSSIBILITY OF SUCH DAMAGES.
  41  *
  42  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#69 $
  43  *
  44  * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.2.2.17 2003/06/10 03:26:09 gibbs Exp $
  45  * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx_pci.c,v 1.3 2003/08/07 21:16:51 dillon Exp $
  46  */
  47
  48 #ifdef __linux__
  49 #include "aic7xxx_osm.h"
  50 #include "aic7xxx_inline.h"
  51 #include "aic7xxx_93cx6.h"
  52 #else
  53 #include "aic7xxx_osm.h"
  54 #include "aic7xxx_inline.h"
  55 #include "aic7xxx_93cx6.h"
  56 #endif
  57
  58 #define AHC_PCI_IOADDR  PCIR_MAPS       /* I/O Address */
  59 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
  60
  61 static __inline uint64_t
  62 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  63 {
  64         uint64_t id;
  65
  66         id = subvendor
  67            | (subdevice << 16)
  68            | ((uint64_t)vendor << 32)
  69            | ((uint64_t)device << 48);
  70
  71         return (id);
  72 }
  73
  74 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  75 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  76 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  77 #define ID_9005_SISL_MASK               0x000FFFFF00000000ull
  78 #define ID_9005_SISL_ID                 0x0005900500000000ull
  79 #define ID_AIC7850                      0x5078900400000000ull
  80 #define ID_AHA_2902_04_10_15_20C_30C    0x5078900478509004ull
  81 #define ID_AIC7855                      0x5578900400000000ull
  82 #define ID_AIC7859                      0x3860900400000000ull
  83 #define ID_AHA_2930CU                   0x3860900438699004ull
  84 #define ID_AIC7860                      0x6078900400000000ull
  85 #define ID_AIC7860C                     0x6078900478609004ull
  86 #define ID_AHA_1480A                    0x6075900400000000ull
  87 #define ID_AHA_2940AU_0                 0x6178900400000000ull
  88 #define ID_AHA_2940AU_1                 0x6178900478619004ull
  89 #define ID_AHA_2940AU_CN                0x2178900478219004ull
  90 #define ID_AHA_2930C_VAR                0x6038900438689004ull
  91
  92 #define ID_AIC7870                      0x7078900400000000ull
  93 #define ID_AHA_2940                     0x7178900400000000ull
  94 #define ID_AHA_3940                     0x7278900400000000ull
  95 #define ID_AHA_398X                     0x7378900400000000ull
  96 #define ID_AHA_2944                     0x7478900400000000ull
  97 #define ID_AHA_3944                     0x7578900400000000ull
  98 #define ID_AHA_4944                     0x7678900400000000ull
  99
 100 #define ID_AIC7880                      0x8078900400000000ull
 101 #define ID_AIC7880_B                    0x8078900478809004ull
 102 #define ID_AHA_2940U                    0x8178900400000000ull
 103 #define ID_AHA_3940U                    0x8278900400000000ull
 104 #define ID_AHA_2944U                    0x8478900400000000ull
 105 #define ID_AHA_3944U                    0x8578900400000000ull
 106 #define ID_AHA_398XU                    0x8378900400000000ull
 107 #define ID_AHA_4944U                    0x8678900400000000ull
 108 #define ID_AHA_2940UB                   0x8178900478819004ull
 109 #define ID_AHA_2930U                    0x8878900478889004ull
 110 #define ID_AHA_2940U_PRO                0x8778900478879004ull
 111 #define ID_AHA_2940U_CN                 0x0078900478009004ull
 112
 113 #define ID_AIC7895                      0x7895900478959004ull
 114 #define ID_AIC7895_ARO                  0x7890900478939004ull
 115 #define ID_AIC7895_ARO_MASK             0xFFF0FFFFFFFFFFFFull
 116 #define ID_AHA_2940U_DUAL               0x7895900478919004ull
 117 #define ID_AHA_3940AU                   0x7895900478929004ull
 118 #define ID_AHA_3944AU                   0x7895900478949004ull
 119
 120 #define ID_AIC7890                      0x001F9005000F9005ull
 121 #define ID_AIC7890_ARO                  0x00139005000F9005ull
 122 #define ID_AAA_131U2                    0x0013900500039005ull
 123 #define ID_AHA_2930U2                   0x0011900501819005ull
 124 #define ID_AHA_2940U2B                  0x00109005A1009005ull
 125 #define ID_AHA_2940U2_OEM               0x0010900521809005ull
 126 #define ID_AHA_2940U2                   0x00109005A1809005ull
 127 #define ID_AHA_2950U2B                  0x00109005E1009005ull
 128
 129 #define ID_AIC7892                      0x008F9005FFFF9005ull
 130 #define ID_AIC7892_ARO                  0x00839005FFFF9005ull
 131 #define ID_AHA_29160                    0x00809005E2A09005ull
 132 #define ID_AHA_29160_CPQ                0x00809005E2A00E11ull
 133 #define ID_AHA_29160N                   0x0080900562A09005ull
 134 #define ID_AHA_29160C                   0x0080900562209005ull
 135 #define ID_AHA_29160B                   0x00809005E2209005ull
 136 #define ID_AHA_19160B                   0x0081900562A19005ull
 137
 138 #define ID_AIC7896                      0x005F9005FFFF9005ull
 139 #define ID_AIC7896_ARO                  0x00539005FFFF9005ull
 140 #define ID_AHA_3950U2B_0                0x00509005FFFF9005ull
 141 #define ID_AHA_3950U2B_1                0x00509005F5009005ull
 142 #define ID_AHA_3950U2D_0                0x00519005FFFF9005ull
 143 #define ID_AHA_3950U2D_1                0x00519005B5009005ull
 144
 145 #define ID_AIC7899                      0x00CF9005FFFF9005ull
 146 #define ID_AIC7899_ARO                  0x00C39005FFFF9005ull
 147 #define ID_AHA_3960D                    0x00C09005F6209005ull
 148 #define ID_AHA_3960D_CPQ                0x00C09005F6200E11ull
 149
 150 #define ID_AIC7810                      0x1078900400000000ull
 151 #define ID_AIC7815                      0x7815900400000000ull
 152
 153 #define DEVID_9005_TYPE(id) ((id) & 0xF)
 154 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
 155 #define         DEVID_9005_TYPE_AAA             0x3     /* RAID Card */
 156 #define         DEVID_9005_TYPE_SISL            0x5     /* Container ROMB */
 157 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 158
 159 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
 160 #define         DEVID_9005_MAXRATE_U160         0x0
 161 #define         DEVID_9005_MAXRATE_ULTRA2       0x1
 162 #define         DEVID_9005_MAXRATE_ULTRA        0x2
 163 #define         DEVID_9005_MAXRATE_FAST         0x3
 164
 165 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
 166
 167 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
 168 #define         DEVID_9005_CLASS_SPI            0x0     /* Parallel SCSI */
 169
 170 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 171 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 172 #define         SUBID_9005_TYPE_CARD            0x0     /* Standard Card */
 173 #define         SUBID_9005_TYPE_LCCARD          0x1     /* Low Cost Card */
 174 #define         SUBID_9005_TYPE_RAID            0x3     /* Combined with Raid */
 175
 176 #define SUBID_9005_TYPE_KNOWN(id)                       \
 177           ((((id) & 0xF) == SUBID_9005_TYPE_MB)         \
 178         || (((id) & 0xF) == SUBID_9005_TYPE_CARD)       \
 179         || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD)     \
 180         || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
 181
 182 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
 183 #define         SUBID_9005_MAXRATE_ULTRA2       0x0
 184 #define         SUBID_9005_MAXRATE_ULTRA        0x1
 185 #define         SUBID_9005_MAXRATE_U160         0x2
 186 #define         SUBID_9005_MAXRATE_RESERVED     0x3
 187
 188 #define SUBID_9005_SEEPTYPE(id)                                         \
 189         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 190          ? ((id) & 0xC0) >> 6                                           \
 191          : ((id) & 0x300) >> 8)
 192 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 193 #define         SUBID_9005_SEEPTYPE_1K          0x1
 194 #define         SUBID_9005_SEEPTYPE_2K_4K       0x2
 195 #define         SUBID_9005_SEEPTYPE_RESERVED    0x3
 196 #define SUBID_9005_AUTOTERM(id)                                         \
 197         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 198          ? (((id) & 0x400) >> 10) == 0                                  \
 199          : (((id) & 0x40) >> 6) == 0)
 200
 201 #define SUBID_9005_NUMCHAN(id)                                          \
 202         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 203          ? ((id) & 0x300) >> 8                                          \
 204          : ((id) & 0xC00) >> 10)
 205
 206 #define SUBID_9005_LEGACYCONN(id)                                       \
 207         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 208          ? 0                                                            \
 209          : ((id) & 0x80) >> 7)
 210
 211 #define SUBID_9005_MFUNCENB(id)                                         \
 212         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 213          ? ((id) & 0x800) >> 11                                         \
 214          : ((id) & 0x1000) >> 12)
 215 /*
 216  * Informational only. Should use chip register to be
 217  * certain, but may be use in identification strings.
 218  */
 219 #define SUBID_9005_CARD_SCSIWIDTH_MASK  0x2000
 220 #define SUBID_9005_CARD_PCIWIDTH_MASK   0x4000
 221 #define SUBID_9005_CARD_SEDIFF_MASK     0x8000
 222
 223 static ahc_device_setup_t ahc_aic785X_setup;
 224 static ahc_device_setup_t ahc_aic7860_setup;
 225 static ahc_device_setup_t ahc_apa1480_setup;
 226 static ahc_device_setup_t ahc_aic7870_setup;
 227 static ahc_device_setup_t ahc_aha394X_setup;
 228 static ahc_device_setup_t ahc_aha494X_setup;
 229 static ahc_device_setup_t ahc_aha398X_setup;
 230 static ahc_device_setup_t ahc_aic7880_setup;
 231 static ahc_device_setup_t ahc_aha2940Pro_setup;
 232 static ahc_device_setup_t ahc_aha394XU_setup;
 233 static ahc_device_setup_t ahc_aha398XU_setup;
 234 static ahc_device_setup_t ahc_aic7890_setup;
 235 static ahc_device_setup_t ahc_aic7892_setup;
 236 static ahc_device_setup_t ahc_aic7895_setup;
 237 static ahc_device_setup_t ahc_aic7896_setup;
 238 static ahc_device_setup_t ahc_aic7899_setup;
 239 static ahc_device_setup_t ahc_aha29160C_setup;
 240 static ahc_device_setup_t ahc_raid_setup;
 241 static ahc_device_setup_t ahc_aha394XX_setup;
 242 static ahc_device_setup_t ahc_aha494XX_setup;
 243 static ahc_device_setup_t ahc_aha398XX_setup;
 244
 245 struct ahc_pci_identity ahc_pci_ident_table [] =
 246 {
 247         /* aic7850 based controllers */
 248         {
 249                 ID_AHA_2902_04_10_15_20C_30C,
 250                 ID_ALL_MASK,
 251                 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
 252                 ahc_aic785X_setup
 253         },
 254         /* aic7860 based controllers */
 255         {
 256                 ID_AHA_2930CU,
 257                 ID_ALL_MASK,
 258                 "Adaptec 2930CU SCSI adapter",
 259                 ahc_aic7860_setup
 260         },
 261         {
 262                 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
 263                 ID_DEV_VENDOR_MASK,
 264                 "Adaptec 1480A Ultra SCSI adapter",
 265                 ahc_apa1480_setup
 266         },
 267         {
 268                 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
 269                 ID_DEV_VENDOR_MASK,
 270                 "Adaptec 2940A Ultra SCSI adapter",
 271                 ahc_aic7860_setup
 272         },
 273         {
 274                 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
 275                 ID_DEV_VENDOR_MASK,
 276                 "Adaptec 2940A/CN Ultra SCSI adapter",
 277                 ahc_aic7860_setup
 278         },
 279         {
 280                 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
 281                 ID_DEV_VENDOR_MASK,
 282                 "Adaptec 2930C Ultra SCSI adapter (VAR)",
 283                 ahc_aic7860_setup
 284         },
 285         /* aic7870 based controllers */
 286         {
 287                 ID_AHA_2940,
 288                 ID_ALL_MASK,
 289                 "Adaptec 2940 SCSI adapter",
 290                 ahc_aic7870_setup
 291         },
 292         {
 293                 ID_AHA_3940,
 294                 ID_ALL_MASK,
 295                 "Adaptec 3940 SCSI adapter",
 296                 ahc_aha394X_setup
 297         },
 298         {
 299                 ID_AHA_398X,
 300                 ID_ALL_MASK,
 301                 "Adaptec 398X SCSI RAID adapter",
 302                 ahc_aha398X_setup
 303         },
 304         {
 305                 ID_AHA_2944,
 306                 ID_ALL_MASK,
 307                 "Adaptec 2944 SCSI adapter",
 308                 ahc_aic7870_setup
 309         },
 310         {
 311                 ID_AHA_3944,
 312                 ID_ALL_MASK,
 313                 "Adaptec 3944 SCSI adapter",
 314                 ahc_aha394X_setup
 315         },
 316         {
 317                 ID_AHA_4944,
 318                 ID_ALL_MASK,
 319                 "Adaptec 4944 SCSI adapter",
 320                 ahc_aha494X_setup
 321         },
 322         /* aic7880 based controllers */
 323         {
 324                 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
 325                 ID_DEV_VENDOR_MASK,
 326                 "Adaptec 2940 Ultra SCSI adapter",
 327                 ahc_aic7880_setup
 328         },
 329         {
 330                 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
 331                 ID_DEV_VENDOR_MASK,
 332                 "Adaptec 3940 Ultra SCSI adapter",
 333                 ahc_aha394XU_setup
 334         },
 335         {
 336                 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
 337                 ID_DEV_VENDOR_MASK,
 338                 "Adaptec 2944 Ultra SCSI adapter",
 339                 ahc_aic7880_setup
 340         },
 341         {
 342                 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
 343                 ID_DEV_VENDOR_MASK,
 344                 "Adaptec 3944 Ultra SCSI adapter",
 345                 ahc_aha394XU_setup
 346         },
 347         {
 348                 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
 349                 ID_DEV_VENDOR_MASK,
 350                 "Adaptec 398X Ultra SCSI RAID adapter",
 351                 ahc_aha398XU_setup
 352         },
 353         {
 354                 /*
 355                  * XXX Don't know the slot numbers
 356                  * so we can't identify channels
 357                  */
 358                 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
 359                 ID_DEV_VENDOR_MASK,
 360                 "Adaptec 4944 Ultra SCSI adapter",
 361                 ahc_aic7880_setup
 362         },
 363         {
 364                 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
 365                 ID_DEV_VENDOR_MASK,
 366                 "Adaptec 2930 Ultra SCSI adapter",
 367                 ahc_aic7880_setup
 368         },
 369         {
 370                 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
 371                 ID_DEV_VENDOR_MASK,
 372                 "Adaptec 2940 Pro Ultra SCSI adapter",
 373                 ahc_aha2940Pro_setup
 374         },
 375         {
 376                 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
 377                 ID_DEV_VENDOR_MASK,
 378                 "Adaptec 2940/CN Ultra SCSI adapter",
 379                 ahc_aic7880_setup
 380         },
 381         /* Ignore all SISL (AAC on MB) based controllers. */
 382         {
 383                 ID_9005_SISL_ID,
 384                 ID_9005_SISL_MASK,
 385                 NULL,
 386                 NULL
 387         },
 388         /* aic7890 based controllers */
 389         {
 390                 ID_AHA_2930U2,
 391                 ID_ALL_MASK,
 392                 "Adaptec 2930 Ultra2 SCSI adapter",
 393                 ahc_aic7890_setup
 394         },
 395         {
 396                 ID_AHA_2940U2B,
 397                 ID_ALL_MASK,
 398                 "Adaptec 2940B Ultra2 SCSI adapter",
 399                 ahc_aic7890_setup
 400         },
 401         {
 402                 ID_AHA_2940U2_OEM,
 403                 ID_ALL_MASK,
 404                 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
 405                 ahc_aic7890_setup
 406         },
 407         {
 408                 ID_AHA_2940U2,
 409                 ID_ALL_MASK,
 410                 "Adaptec 2940 Ultra2 SCSI adapter",
 411                 ahc_aic7890_setup
 412         },
 413         {
 414                 ID_AHA_2950U2B,
 415                 ID_ALL_MASK,
 416                 "Adaptec 2950 Ultra2 SCSI adapter",
 417                 ahc_aic7890_setup
 418         },
 419         {
 420                 ID_AIC7890_ARO,
 421                 ID_ALL_MASK,
 422                 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
 423                 ahc_aic7890_setup
 424         },
 425         {
 426                 ID_AAA_131U2,
 427                 ID_ALL_MASK,
 428                 "Adaptec AAA-131 Ultra2 RAID adapter",
 429                 ahc_aic7890_setup
 430         },
 431         /* aic7892 based controllers */
 432         {
 433                 ID_AHA_29160,
 434                 ID_ALL_MASK,
 435                 "Adaptec 29160 Ultra160 SCSI adapter",
 436                 ahc_aic7892_setup
 437         },
 438         {
 439                 ID_AHA_29160_CPQ,
 440                 ID_ALL_MASK,
 441                 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
 442                 ahc_aic7892_setup
 443         },
 444         {
 445                 ID_AHA_29160N,
 446                 ID_ALL_MASK,
 447                 "Adaptec 29160N Ultra160 SCSI adapter",
 448                 ahc_aic7892_setup
 449         },
 450         {
 451                 ID_AHA_29160C,
 452                 ID_ALL_MASK,
 453                 "Adaptec 29160C Ultra160 SCSI adapter",
 454                 ahc_aha29160C_setup
 455         },
 456         {
 457                 ID_AHA_29160B,
 458                 ID_ALL_MASK,
 459                 "Adaptec 29160B Ultra160 SCSI adapter",
 460                 ahc_aic7892_setup
 461         },
 462         {
 463                 ID_AHA_19160B,
 464                 ID_ALL_MASK,
 465                 "Adaptec 19160B Ultra160 SCSI adapter",
 466                 ahc_aic7892_setup
 467         },
 468         {
 469                 ID_AIC7892_ARO,
 470                 ID_ALL_MASK,
 471                 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
 472                 ahc_aic7892_setup
 473         },
 474         /* aic7895 based controllers */
 475         {
 476                 ID_AHA_2940U_DUAL,
 477                 ID_ALL_MASK,
 478                 "Adaptec 2940/DUAL Ultra SCSI adapter",
 479                 ahc_aic7895_setup
 480         },
 481         {
 482                 ID_AHA_3940AU,
 483                 ID_ALL_MASK,
 484                 "Adaptec 3940A Ultra SCSI adapter",
 485                 ahc_aic7895_setup
 486         },
 487         {
 488                 ID_AHA_3944AU,
 489                 ID_ALL_MASK,
 490                 "Adaptec 3944A Ultra SCSI adapter",
 491                 ahc_aic7895_setup
 492         },
 493         {
 494                 ID_AIC7895_ARO,
 495                 ID_AIC7895_ARO_MASK,
 496                 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
 497                 ahc_aic7895_setup
 498         },
 499         /* aic7896/97 based controllers */
 500         {
 501                 ID_AHA_3950U2B_0,
 502                 ID_ALL_MASK,
 503                 "Adaptec 3950B Ultra2 SCSI adapter",
 504                 ahc_aic7896_setup
 505         },
 506         {
 507                 ID_AHA_3950U2B_1,
 508                 ID_ALL_MASK,
 509                 "Adaptec 3950B Ultra2 SCSI adapter",
 510                 ahc_aic7896_setup
 511         },
 512         {
 513                 ID_AHA_3950U2D_0,
 514                 ID_ALL_MASK,
 515                 "Adaptec 3950D Ultra2 SCSI adapter",
 516                 ahc_aic7896_setup
 517         },
 518         {
 519                 ID_AHA_3950U2D_1,
 520                 ID_ALL_MASK,
 521                 "Adaptec 3950D Ultra2 SCSI adapter",
 522                 ahc_aic7896_setup
 523         },
 524         {
 525                 ID_AIC7896_ARO,
 526                 ID_ALL_MASK,
 527                 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
 528                 ahc_aic7896_setup
 529         },
 530         /* aic7899 based controllers */
 531         {
 532                 ID_AHA_3960D,
 533                 ID_ALL_MASK,
 534                 "Adaptec 3960D Ultra160 SCSI adapter",
 535                 ahc_aic7899_setup
 536         },
 537         {
 538                 ID_AHA_3960D_CPQ,
 539                 ID_ALL_MASK,
 540                 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
 541                 ahc_aic7899_setup
 542         },
 543         {
 544                 ID_AIC7899_ARO,
 545                 ID_ALL_MASK,
 546                 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
 547                 ahc_aic7899_setup
 548         },
 549         /* Generic chip probes for devices we don't know 'exactly' */
 550         {
 551                 ID_AIC7850 & ID_DEV_VENDOR_MASK,
 552                 ID_DEV_VENDOR_MASK,
 553                 "Adaptec aic7850 SCSI adapter",
 554                 ahc_aic785X_setup
 555         },
 556         {
 557                 ID_AIC7855 & ID_DEV_VENDOR_MASK,
 558                 ID_DEV_VENDOR_MASK,
 559                 "Adaptec aic7855 SCSI adapter",
 560                 ahc_aic785X_setup
 561         },
 562         {
 563                 ID_AIC7859 & ID_DEV_VENDOR_MASK,
 564                 ID_DEV_VENDOR_MASK,
 565                 "Adaptec aic7859 SCSI adapter",
 566                 ahc_aic7860_setup
 567         },
 568         {
 569                 ID_AIC7860 & ID_DEV_VENDOR_MASK,
 570                 ID_DEV_VENDOR_MASK,
 571                 "Adaptec aic7860 Ultra SCSI adapter",
 572                 ahc_aic7860_setup
 573         },
 574         {
 575                 ID_AIC7870 & ID_DEV_VENDOR_MASK,
 576                 ID_DEV_VENDOR_MASK,
 577                 "Adaptec aic7870 SCSI adapter",
 578                 ahc_aic7870_setup
 579         },
 580         {
 581                 ID_AIC7880 & ID_DEV_VENDOR_MASK,
 582                 ID_DEV_VENDOR_MASK,
 583                 "Adaptec aic7880 Ultra SCSI adapter",
 584                 ahc_aic7880_setup
 585         },
 586         {
 587                 ID_AIC7890 & ID_9005_GENERIC_MASK,
 588                 ID_9005_GENERIC_MASK,
 589                 "Adaptec aic7890/91 Ultra2 SCSI adapter",
 590                 ahc_aic7890_setup
 591         },
 592         {
 593                 ID_AIC7892 & ID_9005_GENERIC_MASK,
 594                 ID_9005_GENERIC_MASK,
 595                 "Adaptec aic7892 Ultra160 SCSI adapter",
 596                 ahc_aic7892_setup
 597         },
 598         {
 599                 ID_AIC7895 & ID_DEV_VENDOR_MASK,
 600                 ID_DEV_VENDOR_MASK,
 601                 "Adaptec aic7895 Ultra SCSI adapter",
 602                 ahc_aic7895_setup
 603         },
 604         {
 605                 ID_AIC7896 & ID_9005_GENERIC_MASK,
 606                 ID_9005_GENERIC_MASK,
 607                 "Adaptec aic7896/97 Ultra2 SCSI adapter",
 608                 ahc_aic7896_setup
 609         },
 610         {
 611                 ID_AIC7899 & ID_9005_GENERIC_MASK,
 612                 ID_9005_GENERIC_MASK,
 613                 "Adaptec aic7899 Ultra160 SCSI adapter",
 614                 ahc_aic7899_setup
 615         },
 616         {
 617                 ID_AIC7810 & ID_DEV_VENDOR_MASK,
 618                 ID_DEV_VENDOR_MASK,
 619                 "Adaptec aic7810 RAID memory controller",
 620                 ahc_raid_setup
 621         },
 622         {
 623                 ID_AIC7815 & ID_DEV_VENDOR_MASK,
 624                 ID_DEV_VENDOR_MASK,
 625                 "Adaptec aic7815 RAID memory controller",
 626                 ahc_raid_setup
 627         }
 628 };
 629
 630 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
 631
 632 #define AHC_394X_SLOT_CHANNEL_A 4
 633 #define AHC_394X_SLOT_CHANNEL_B 5
 634
 635 #define AHC_398X_SLOT_CHANNEL_A 4
 636 #define AHC_398X_SLOT_CHANNEL_B 8
 637 #define AHC_398X_SLOT_CHANNEL_C 12
 638
 639 #define AHC_494X_SLOT_CHANNEL_A 4
 640 #define AHC_494X_SLOT_CHANNEL_B 5
 641 #define AHC_494X_SLOT_CHANNEL_C 6
 642 #define AHC_494X_SLOT_CHANNEL_D 7
 643
 644 #define DEVCONFIG               0x40
 645 #define         PCIERRGENDIS    0x80000000ul
 646 #define         SCBSIZE32       0x00010000ul    /* aic789X only */
 647 #define         REXTVALID       0x00001000ul    /* ultra cards only */
 648 #define         MPORTMODE       0x00000400ul    /* aic7870+ only */
 649 #define         RAMPSM          0x00000200ul    /* aic7870+ only */
 650 #define         VOLSENSE        0x00000100ul
 651 #define         PCI64BIT        0x00000080ul    /* 64Bit PCI bus (Ultra2 Only)*/
 652 #define         SCBRAMSEL       0x00000080ul
 653 #define         MRDCEN          0x00000040ul
 654 #define         EXTSCBTIME      0x00000020ul    /* aic7870 only */
 655 #define         EXTSCBPEN       0x00000010ul    /* aic7870 only */
 656 #define         BERREN          0x00000008ul
 657 #define         DACEN           0x00000004ul
 658 #define         STPWLEVEL       0x00000002ul
 659 #define         DIFACTNEGEN     0x00000001ul    /* aic7870 only */
 660
 661 #define CSIZE_LATTIME           0x0c
 662 #define         CACHESIZE       0x0000003ful    /* only 5 bits */
 663 #define         LATTIME         0x0000ff00ul
 664
 665 /* PCI STATUS definitions */
 666 #define DPE     0x80
 667 #define SSE     0x40
 668 #define RMA     0x20
 669 #define RTA     0x10
 670 #define STA     0x08
 671 #define DPR     0x01
 672
 673 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
 674                                      uint16_t subvendor, uint16_t subdevice);
 675 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
 676 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
 677                                   int pcheck, int fast, int large);
 678 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
 679 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
 680 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
 681                                  struct seeprom_config *sc);
 682 static void configure_termination(struct ahc_softc *ahc,
 683                                   struct seeprom_descriptor *sd,
 684                                   u_int adapter_control,
 685                                   u_int *sxfrctl1);
 686
 687 static void ahc_new_term_detect(struct ahc_softc *ahc,
 688                                 int *enableSEC_low,
 689                                 int *enableSEC_high,
 690                                 int *enablePRI_low,
 691                                 int *enablePRI_high,
 692                                 int *eeprom_present);
 693 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
 694                                  int *internal68_present,
 695                                  int *externalcable_present,
 696                                  int *eeprom_present);
 697 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
 698                                  int *externalcable_present,
 699                                  int *eeprom_present);
 700 static void    write_brdctl(struct ahc_softc *ahc, uint8_t value);
 701 static uint8_t read_brdctl(struct ahc_softc *ahc);
 702 static void ahc_pci_intr(struct ahc_softc *ahc);
 703 static int  ahc_pci_chip_init(struct ahc_softc *ahc);
 704 static int  ahc_pci_suspend(struct ahc_softc *ahc);
 705 static int  ahc_pci_resume(struct ahc_softc *ahc);
 706
 707 static int
 708 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
 709                           uint16_t subdevice, uint16_t subvendor)
 710 {
 711         int result;
 712
 713         /* Default to invalid. */
 714         result = 0;
 715         if (vendor == 0x9005
 716          && subvendor == 0x9005
 717          && subdevice != device
 718          && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
 719
 720                 switch (SUBID_9005_TYPE(subdevice)) {
 721                 case SUBID_9005_TYPE_MB:
 722                         break;
 723                 case SUBID_9005_TYPE_CARD:
 724                 case SUBID_9005_TYPE_LCCARD:
 725                         /*
 726                          * Currently only trust Adaptec cards to
 727                          * get the sub device info correct.
 728                          */
 729                         if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
 730                                 result = 1;
 731                         break;
 732                 case SUBID_9005_TYPE_RAID:
 733                         break;
 734                 default:
 735                         break;
 736                 }
 737         }
 738         return (result);
 739 }
 740
 741 struct ahc_pci_identity *
 742 ahc_find_pci_device(ahc_dev_softc_t pci)
 743 {
 744         uint64_t  full_id;
 745         uint16_t  device;
 746         uint16_t  vendor;
 747         uint16_t  subdevice;
 748         uint16_t  subvendor;
 749         struct    ahc_pci_identity *entry;
 750         u_int     i;
 751
 752         vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 753         device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 754         subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 755         subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 756         full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
 757
 758         /*
 759          * If the second function is not hooked up, ignore it.
 760          * Unfortunately, not all MB vendors implement the
 761          * subdevice ID as per the Adaptec spec, so do our best
 762          * to sanity check it prior to accepting the subdevice
 763          * ID as valid.
 764          */
 765         if (ahc_get_pci_function(pci) > 0
 766          && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
 767          && SUBID_9005_MFUNCENB(subdevice) == 0)
 768                 return (NULL);
 769
 770         for (i = 0; i < ahc_num_pci_devs; i++) {
 771                 entry = &ahc_pci_ident_table[i];
 772                 if (entry->full_id == (full_id & entry->id_mask)) {
 773                         /* Honor exclusion entries. */
 774                         if (entry->name == NULL)
 775                                 return (NULL);
 776                         return (entry);
 777                 }
 778         }
 779         return (NULL);
 780 }
 781
 782 int
 783 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
 784 {
 785         u_long   l;
 786         u_int    command;
 787         u_int    our_id;
 788         u_int    sxfrctl1;
 789         u_int    scsiseq;
 790         u_int    dscommand0;
 791         uint32_t devconfig;
 792         int      error;
 793         uint8_t  sblkctl;
 794
 795         our_id = 0;
 796         error = entry->setup(ahc);
 797         if (error != 0)
 798                 return (error);
 799         ahc->chip |= AHC_PCI;
 800         ahc->description = entry->name;
 801
 802         ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
 803
 804         error = ahc_pci_map_registers(ahc);
 805         if (error != 0)
 806                 return (error);
 807
 808         /*
 809          * Before we continue probing the card, ensure that
 810          * its interrupts are *disabled*.  We don't want
 811          * a misstep to hang the machine in an interrupt
 812          * storm.
 813          */
 814         ahc_intr_enable(ahc, FALSE);
 815
 816         devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
 817
 818         /*
 819          * If we need to support high memory, enable dual
 820          * address cycles.  This bit must be set to enable
 821          * high address bit generation even if we are on a
 822          * 64bit bus (PCI64BIT set in devconfig).
 823          */
 824         if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
 825
 826                 if (bootverbose)
 827                         printf("%s: Enabling 39Bit Addressing\n",
 828                                ahc_name(ahc));
 829                 devconfig |= DACEN;
 830         }
 831
 832         /* Ensure that pci error generation, a test feature, is disabled. */
 833         devconfig |= PCIERRGENDIS;
 834
 835         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 836
 837         /* Ensure busmastering is enabled */
 838         command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
 839         command |= PCIM_CMD_BUSMASTEREN;
 840
 841         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 842
 843         /* On all PCI adapters, we allow SCB paging */
 844         ahc->flags |= AHC_PAGESCBS;
 845
 846         error = ahc_softc_init(ahc);
 847         if (error != 0)
 848                 return (error);
 849
 850         /*
 851          * Disable PCI parity error checking.  Users typically
 852          * do this to work around broken PCI chipsets that get
 853          * the parity timing wrong and thus generate lots of spurious
 854          * errors.  The chip only allows us to disable *all* parity
 855          * error reporting when doing this, so CIO bus, scb ram, and
 856          * scratch ram parity errors will be ignored too.
 857          */
 858         if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
 859                 ahc->seqctl |= FAILDIS;
 860
 861         ahc->bus_intr = ahc_pci_intr;
 862         ahc->bus_chip_init = ahc_pci_chip_init;
 863         ahc->bus_suspend = ahc_pci_suspend;
 864         ahc->bus_resume = ahc_pci_resume;
 865
 866         /* Remeber how the card was setup in case there is no SEEPROM */
 867         if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
 868                 ahc_pause(ahc);
 869                 if ((ahc->features & AHC_ULTRA2) != 0)
 870                         our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
 871                 else
 872                         our_id = ahc_inb(ahc, SCSIID) & OID;
 873                 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
 874                 scsiseq = ahc_inb(ahc, SCSISEQ);
 875         } else {
 876                 sxfrctl1 = STPWEN;
 877                 our_id = 7;
 878                 scsiseq = 0;
 879         }
 880
 881         error = ahc_reset(ahc, /*reinit*/FALSE);
 882         if (error != 0)
 883                 return (ENXIO);
 884
 885         if ((ahc->features & AHC_DT) != 0) {
 886                 u_int sfunct;
 887
 888                 /* Perform ALT-Mode Setup */
 889                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
 890                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
 891                 ahc_outb(ahc, OPTIONMODE,
 892                          OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
 893                 ahc_outb(ahc, SFUNCT, sfunct);
 894
 895                 /* Normal mode setup */
 896                 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
 897                                           |TARGCRCENDEN);
 898         }
 899
 900         dscommand0 = ahc_inb(ahc, DSCOMMAND0);
 901         dscommand0 |= MPARCKEN|CACHETHEN;
 902         if ((ahc->features & AHC_ULTRA2) != 0) {
 903
 904                 /*
 905                  * DPARCKEN doesn't work correctly on
 906                  * some MBs so don't use it.
 907                  */
 908                 dscommand0 &= ~DPARCKEN;
 909         }
 910
 911         /*
 912          * Handle chips that must have cache line
 913          * streaming (dis/en)abled.
 914          */
 915         if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
 916                 dscommand0 |= CACHETHEN;
 917
 918         if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
 919                 dscommand0 &= ~CACHETHEN;
 920
 921         ahc_outb(ahc, DSCOMMAND0, dscommand0);
 922
 923         ahc->pci_cachesize =
 924             ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
 925                                 /*bytes*/1) & CACHESIZE;
 926         ahc->pci_cachesize *= 4;
 927
 928         if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
 929          && ahc->pci_cachesize == 4) {
 930
 931                 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
 932                                      0, /*bytes*/1);
 933                 ahc->pci_cachesize = 0;
 934         }
 935
 936         /*
 937          * We cannot perform ULTRA speeds without the presense
 938          * of the external precision resistor.
 939          */
 940         if ((ahc->features & AHC_ULTRA) != 0) {
 941                 uint32_t devconfig;
 942
 943                 devconfig = ahc_pci_read_config(ahc->dev_softc,
 944                                                 DEVCONFIG, /*bytes*/4);
 945                 if ((devconfig & REXTVALID) == 0)
 946                         ahc->features &= ~AHC_ULTRA;
 947         }
 948
 949         /* See if we have a SEEPROM and perform auto-term */
 950         check_extport(ahc, &sxfrctl1);
 951
 952         /*
 953          * Take the LED out of diagnostic mode
 954          */
 955         sblkctl = ahc_inb(ahc, SBLKCTL);
 956         ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
 957
 958         if ((ahc->features & AHC_ULTRA2) != 0) {
 959                 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
 960         } else {
 961                 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
 962         }
 963
 964         if (ahc->flags & AHC_USEDEFAULTS) {
 965                 /*
 966                  * PCI Adapter default setup
 967                  * Should only be used if the adapter does not have
 968                  * a SEEPROM.
 969                  */
 970                 /* See if someone else set us up already */
 971                 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
 972                  && scsiseq != 0) {
 973                         printf("%s: Using left over BIOS settings\n",
 974                                 ahc_name(ahc));
 975                         ahc->flags &= ~AHC_USEDEFAULTS;
 976                         ahc->flags |= AHC_BIOS_ENABLED;
 977                 } else {
 978                         /*
 979                          * Assume only one connector and always turn
 980                          * on termination.
 981                          */
 982                         our_id = 0x07;
 983                         sxfrctl1 = STPWEN;
 984                 }
 985                 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
 986
 987                 ahc->our_id = our_id;
 988         }
 989
 990         /*
 991          * Take a look to see if we have external SRAM.
 992          * We currently do not attempt to use SRAM that is
 993          * shared among multiple controllers.
 994          */
 995         ahc_probe_ext_scbram(ahc);
 996
 997         /*
 998          * Record our termination setting for the
 999          * generic initialization routine.
1000          */
1001         if ((sxfrctl1 & STPWEN) != 0)
1002                 ahc->flags |= AHC_TERM_ENB_A;
1003
1004         /*
1005          * Save chip register configuration data for chip resets
1006          * that occur during runtime and resume events.
1007          */
1008         ahc->bus_softc.pci_softc.devconfig =
1009             ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1010         ahc->bus_softc.pci_softc.command =
1011             ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1012         ahc->bus_softc.pci_softc.csize_lattime =
1013             ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1014         ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1015         ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1016         if ((ahc->features & AHC_DT) != 0) {
1017                 u_int sfunct;
1018
1019                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1020                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1021                 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1022                 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1023                 ahc_outb(ahc, SFUNCT, sfunct);
1024                 ahc->bus_softc.pci_softc.crccontrol1 =
1025                     ahc_inb(ahc, CRCCONTROL1);
1026         }
1027         if ((ahc->features & AHC_MULTI_FUNC) != 0)
1028                 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1029
1030         if ((ahc->features & AHC_ULTRA2) != 0)
1031                 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1032
1033         /* Core initialization */
1034         error = ahc_init(ahc);
1035         if (error != 0)
1036                 return (error);
1037
1038         /*
1039          * Allow interrupts now that we are completely setup.
1040          */
1041         error = ahc_pci_map_int(ahc);
1042         if (error != 0)
1043                 return (error);
1044
1045         ahc_list_lock(&l);
1046         /*
1047          * Link this softc in with all other ahc instances.
1048          */
1049         ahc_softc_insert(ahc);
1050         ahc_list_unlock(&l);
1051         return (0);
1052 }
1053
1054 /*
1055  * Test for the presense of external sram in an
1056  * "unshared" configuration.
1057  */
1058 static int
1059 ahc_ext_scbram_present(struct ahc_softc *ahc)
1060 {
1061         u_int chip;
1062         int ramps;
1063         int single_user;
1064         uint32_t devconfig;
1065
1066         chip = ahc->chip & AHC_CHIPID_MASK;
1067         devconfig = ahc_pci_read_config(ahc->dev_softc,
1068                                         DEVCONFIG, /*bytes*/4);
1069         single_user = (devconfig & MPORTMODE) != 0;
1070
1071         if ((ahc->features & AHC_ULTRA2) != 0)
1072                 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1073         else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1074                 /*
1075                  * External SCBRAM arbitration is flakey
1076                  * on these chips.  Unfortunately this means
1077                  * we don't use the extra SCB ram space on the
1078                  * 3940AUW.
1079                  */
1080                 ramps = 0;
1081         else if (chip >= AHC_AIC7870)
1082                 ramps = (devconfig & RAMPSM) != 0;
1083         else
1084                 ramps = 0;
1085
1086         if (ramps && single_user)
1087                 return (1);
1088         return (0);
1089 }
1090
1091 /*
1092  * Enable external scbram.
1093  */
1094 static void
1095 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1096                   int fast, int large)
1097 {
1098         uint32_t devconfig;
1099
1100         if (ahc->features & AHC_MULTI_FUNC) {
1101                 /*
1102                  * Set the SCB Base addr (highest address bit)
1103                  * depending on which channel we are.
1104                  */
1105                 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1106         }
1107
1108         ahc->flags &= ~AHC_LSCBS_ENABLED;
1109         if (large)
1110                 ahc->flags |= AHC_LSCBS_ENABLED;
1111         devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1112         if ((ahc->features & AHC_ULTRA2) != 0) {
1113                 u_int dscommand0;
1114
1115                 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1116                 if (enable)
1117                         dscommand0 &= ~INTSCBRAMSEL;
1118                 else
1119                         dscommand0 |= INTSCBRAMSEL;
1120                 if (large)
1121                         dscommand0 &= ~USCBSIZE32;
1122                 else
1123                         dscommand0 |= USCBSIZE32;
1124                 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1125         } else {
1126                 if (fast)
1127                         devconfig &= ~EXTSCBTIME;
1128                 else
1129                         devconfig |= EXTSCBTIME;
1130                 if (enable)
1131                         devconfig &= ~SCBRAMSEL;
1132                 else
1133                         devconfig |= SCBRAMSEL;
1134                 if (large)
1135                         devconfig &= ~SCBSIZE32;
1136                 else
1137                         devconfig |= SCBSIZE32;
1138         }
1139         if (pcheck)
1140                 devconfig |= EXTSCBPEN;
1141         else
1142                 devconfig &= ~EXTSCBPEN;
1143
1144         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1145 }
1146
1147 /*
1148  * Take a look to see if we have external SRAM.
1149  * We currently do not attempt to use SRAM that is
1150  * shared among multiple controllers.
1151  */
1152 static void
1153 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1154 {
1155         int num_scbs;
1156         int test_num_scbs;
1157         int enable;
1158         int pcheck;
1159         int fast;
1160         int large;
1161
1162         enable = FALSE;
1163         pcheck = FALSE;
1164         fast = FALSE;
1165         large = FALSE;
1166         num_scbs = 0;
1167
1168         if (ahc_ext_scbram_present(ahc) == 0)
1169                 goto done;
1170
1171         /*
1172          * Probe for the best parameters to use.
1173          */
1174         ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1175         num_scbs = ahc_probe_scbs(ahc);
1176         if (num_scbs == 0) {
1177                 /* The SRAM wasn't really present. */
1178                 goto done;
1179         }
1180         enable = TRUE;
1181
1182         /*
1183          * Clear any outstanding parity error
1184          * and ensure that parity error reporting
1185          * is enabled.
1186          */
1187         ahc_outb(ahc, SEQCTL, 0);
1188         ahc_outb(ahc, CLRINT, CLRPARERR);
1189         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1190
1191         /* Now see if we can do parity */
1192         ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1193         num_scbs = ahc_probe_scbs(ahc);
1194         if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1195          || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1196                 pcheck = TRUE;
1197
1198         /* Clear any resulting parity error */
1199         ahc_outb(ahc, CLRINT, CLRPARERR);
1200         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1201
1202         /* Now see if we can do fast timing */
1203         ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1204         test_num_scbs = ahc_probe_scbs(ahc);
1205         if (test_num_scbs == num_scbs
1206          && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1207           || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1208                 fast = TRUE;
1209
1210         /*
1211          * See if we can use large SCBs and still maintain
1212          * the same overall count of SCBs.
1213          */
1214         if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1215                 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1216                 test_num_scbs = ahc_probe_scbs(ahc);
1217                 if (test_num_scbs >= num_scbs) {
1218                         large = TRUE;
1219                         num_scbs = test_num_scbs;
1220                         if (num_scbs >= 64) {
1221                                 /*
1222                                  * We have enough space to move the
1223                                  * "busy targets table" into SCB space
1224                                  * and make it qualify all the way to the
1225                                  * lun level.
1226                                  */
1227                                 ahc->flags |= AHC_SCB_BTT;
1228                         }
1229                 }
1230         }
1231 done:
1232         /*
1233          * Disable parity error reporting until we
1234          * can load instruction ram.
1235          */
1236         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1237         /* Clear any latched parity error */
1238         ahc_outb(ahc, CLRINT, CLRPARERR);
1239         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1240         if (bootverbose && enable) {
1241                 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1242                        ahc_name(ahc), fast ? "fast" : "slow",
1243                        pcheck ? ", parity checking enabled" : "",
1244                        large ? 64 : 32);
1245         }
1246         ahc_scbram_config(ahc, enable, pcheck, fast, large);
1247 }
1248
1249 /*
1250  * Perform some simple tests that should catch situations where
1251  * our registers are invalidly mapped.
1252  */
1253 int
1254 ahc_pci_test_register_access(struct ahc_softc *ahc)
1255 {
1256         int      error;
1257         u_int    status1;
1258         uint32_t cmd;
1259         uint8_t  hcntrl;
1260
1261         error = EIO;
1262
1263         /*
1264          * Enable PCI error interrupt status, but suppress NMIs
1265          * generated by SERR raised due to target aborts.
1266          */
1267         cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1268         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1269                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1270
1271         /*
1272          * First a simple test to see if any
1273          * registers can be read.  Reading
1274          * HCNTRL has no side effects and has
1275          * at least one bit that is guaranteed to
1276          * be zero so it is a good register to
1277          * use for this test.
1278          */
1279         hcntrl = ahc_inb(ahc, HCNTRL);
1280         if (hcntrl == 0xFF)
1281                 goto fail;
1282
1283         /*
1284          * Next create a situation where write combining
1285          * or read prefetching could be initiated by the
1286          * CPU or host bridge.  Our device does not support
1287          * either, so look for data corruption and/or flagged
1288          * PCI errors.
1289          */
1290         ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1291         while (ahc_is_paused(ahc) == 0)
1292                 ;
1293
1294         /* Clear any PCI errors that occurred before our driver attached. */
1295         status1 = ahc_pci_read_config(ahc->dev_softc,
1296                                       PCIR_STATUS + 1, /*bytes*/1);
1297         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1298                              status1, /*bytes*/1);
1299         ahc_outb(ahc, CLRINT, CLRPARERR);
1300
1301         ahc_outb(ahc, SEQCTL, PERRORDIS);
1302         ahc_outb(ahc, SCBPTR, 0);
1303         ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1304         if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1305                 goto fail;
1306
1307         status1 = ahc_pci_read_config(ahc->dev_softc,
1308                                       PCIR_STATUS + 1, /*bytes*/1);
1309         if ((status1 & STA) != 0)
1310                 goto fail;
1311
1312         error = 0;
1313
1314 fail:
1315         /* Silently clear any latched errors. */
1316         status1 = ahc_pci_read_config(ahc->dev_softc,
1317                                       PCIR_STATUS + 1, /*bytes*/1);
1318         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1319                              status1, /*bytes*/1);
1320         ahc_outb(ahc, CLRINT, CLRPARERR);
1321         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1322         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1323         return (error);
1324 }
1325
1326 /*
1327  * Check the external port logic for a serial eeprom
1328  * and termination/cable detection contrls.
1329  */
1330 static void
1331 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1332 {
1333         struct  seeprom_descriptor sd;
1334         struct  seeprom_config *sc;
1335         int     have_seeprom;
1336         int     have_autoterm;
1337
1338         sd.sd_ahc = ahc;
1339         sd.sd_control_offset = SEECTL;
1340         sd.sd_status_offset = SEECTL;
1341         sd.sd_dataout_offset = SEECTL;
1342         sc = ahc->seep_config;
1343
1344         /*
1345          * For some multi-channel devices, the c46 is simply too
1346          * small to work.  For the other controller types, we can
1347          * get our information from either SEEPROM type.  Set the
1348          * type to start our probe with accordingly.
1349          */
1350         if (ahc->flags & AHC_LARGE_SEEPROM)
1351                 sd.sd_chip = C56_66;
1352         else
1353                 sd.sd_chip = C46;
1354
1355         sd.sd_MS = SEEMS;
1356         sd.sd_RDY = SEERDY;
1357         sd.sd_CS = SEECS;
1358         sd.sd_CK = SEECK;
1359         sd.sd_DO = SEEDO;
1360         sd.sd_DI = SEEDI;
1361
1362         have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1363         if (have_seeprom) {
1364
1365                 if (bootverbose)
1366                         printf("%s: Reading SEEPROM...", ahc_name(ahc));
1367
1368                 for (;;) {
1369                         u_int start_addr;
1370
1371                         start_addr = 32 * (ahc->channel - 'A');
1372
1373                         have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1374                                                         start_addr,
1375                                                         sizeof(*sc)/2);
1376
1377                         if (have_seeprom)
1378                                 have_seeprom = ahc_verify_cksum(sc);
1379
1380                         if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1381                                 if (bootverbose) {
1382                                         if (have_seeprom == 0)
1383                                                 printf ("checksum error\n");
1384                                         else
1385                                                 printf ("done.\n");
1386                                 }
1387                                 break;
1388                         }
1389                         sd.sd_chip = C56_66;
1390                 }
1391                 ahc_release_seeprom(&sd);
1392         }
1393
1394         if (!have_seeprom) {
1395                 /*
1396                  * Pull scratch ram settings and treat them as
1397                  * if they are the contents of an seeprom if
1398                  * the 'ADPT' signature is found in SCB2.
1399                  * We manually compose the data as 16bit values
1400                  * to avoid endian issues.
1401                  */
1402                 ahc_outb(ahc, SCBPTR, 2);
1403                 if (ahc_inb(ahc, SCB_BASE) == 'A'
1404                  && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1405                  && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1406                  && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1407                         uint16_t *sc_data;
1408                         int       i;
1409
1410                         sc_data = (uint16_t *)sc;
1411                         for (i = 0; i < 32; i++, sc_data++) {
1412                                 int     j;
1413
1414                                 j = i * 2;
1415                                 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1416                                          | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1417                         }
1418                         have_seeprom = ahc_verify_cksum(sc);
1419                         if (have_seeprom)
1420                                 ahc->flags |= AHC_SCB_CONFIG_USED;
1421                 }
1422                 /*
1423                  * Clear any SCB parity errors in case this data and
1424                  * its associated parity was not initialized by the BIOS
1425                  */
1426                 ahc_outb(ahc, CLRINT, CLRPARERR);
1427                 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1428         }
1429
1430         if (!have_seeprom) {
1431                 if (bootverbose)
1432                         printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1433                 ahc->flags |= AHC_USEDEFAULTS;
1434                 free(ahc->seep_config, M_DEVBUF);
1435                 ahc->seep_config = NULL;
1436                 sc = NULL;
1437         } else {
1438                 ahc_parse_pci_eeprom(ahc, sc);
1439         }
1440
1441         /*
1442          * Cards that have the external logic necessary to talk to
1443          * a SEEPROM, are almost certain to have the remaining logic
1444          * necessary for auto-termination control.  This assumption
1445          * hasn't failed yet...
1446          */
1447         have_autoterm = have_seeprom;
1448
1449         /*
1450          * Some low-cost chips have SEEPROM and auto-term control built
1451          * in, instead of using a GAL.  They can tell us directly
1452          * if the termination logic is enabled.
1453          */
1454         if ((ahc->features & AHC_SPIOCAP) != 0) {
1455                 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1456                         have_autoterm = FALSE;
1457         }
1458
1459         if (have_autoterm) {
1460                 ahc->flags |= AHC_HAS_TERM_LOGIC;
1461                 ahc_acquire_seeprom(ahc, &sd);
1462                 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1463                 ahc_release_seeprom(&sd);
1464         } else if (have_seeprom) {
1465                 *sxfrctl1 &= ~STPWEN;
1466                 if ((sc->adapter_control & CFSTERM) != 0)
1467                         *sxfrctl1 |= STPWEN;
1468                 if (bootverbose)
1469                         printf("%s: Low byte termination %sabled\n",
1470                                ahc_name(ahc),
1471                                (*sxfrctl1 & STPWEN) ? "en" : "dis");
1472         }
1473 }
1474
1475 static void
1476 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1477 {
1478         /*
1479          * Put the data we've collected down into SRAM
1480          * where ahc_init will find it.
1481          */
1482         int      i;
1483         int      max_targ = sc->max_targets & CFMAXTARG;
1484         u_int    scsi_conf;
1485         uint16_t discenable;
1486         uint16_t ultraenb;
1487
1488         discenable = 0;
1489         ultraenb = 0;
1490         if ((sc->adapter_control & CFULTRAEN) != 0) {
1491                 /*
1492                  * Determine if this adapter has a "newstyle"
1493                  * SEEPROM format.
1494                  */
1495                 for (i = 0; i < max_targ; i++) {
1496                         if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1497                                 ahc->flags |= AHC_NEWEEPROM_FMT;
1498                                 break;
1499                         }
1500                 }
1501         }
1502
1503         for (i = 0; i < max_targ; i++) {
1504                 u_int     scsirate;
1505                 uint16_t target_mask;
1506
1507                 target_mask = 0x01 << i;
1508                 if (sc->device_flags[i] & CFDISC)
1509                         discenable |= target_mask;
1510                 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1511                         if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1512                                 ultraenb |= target_mask;
1513                 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1514                         ultraenb |= target_mask;
1515                 }
1516                 if ((sc->device_flags[i] & CFXFER) == 0x04
1517                  && (ultraenb & target_mask) != 0) {
1518                         /* Treat 10MHz as a non-ultra speed */
1519                         sc->device_flags[i] &= ~CFXFER;
1520                         ultraenb &= ~target_mask;
1521                 }
1522                 if ((ahc->features & AHC_ULTRA2) != 0) {
1523                         u_int offset;
1524
1525                         if (sc->device_flags[i] & CFSYNCH)
1526                                 offset = MAX_OFFSET_ULTRA2;
1527                         else
1528                                 offset = 0;
1529                         ahc_outb(ahc, TARG_OFFSET + i, offset);
1530
1531                         /*
1532                          * The ultra enable bits contain the
1533                          * high bit of the ultra2 sync rate
1534                          * field.
1535                          */
1536                         scsirate = (sc->device_flags[i] & CFXFER)
1537                                  | ((ultraenb & target_mask) ? 0x8 : 0x0);
1538                         if (sc->device_flags[i] & CFWIDEB)
1539                                 scsirate |= WIDEXFER;
1540                 } else {
1541                         scsirate = (sc->device_flags[i] & CFXFER) << 4;
1542                         if (sc->device_flags[i] & CFSYNCH)
1543                                 scsirate |= SOFS;
1544                         if (sc->device_flags[i] & CFWIDEB)
1545                                 scsirate |= WIDEXFER;
1546                 }
1547                 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1548         }
1549         ahc->our_id = sc->brtime_id & CFSCSIID;
1550
1551         scsi_conf = (ahc->our_id & 0x7);
1552         if (sc->adapter_control & CFSPARITY)
1553                 scsi_conf |= ENSPCHK;
1554         if (sc->adapter_control & CFRESETB)
1555                 scsi_conf |= RESET_SCSI;
1556
1557         ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1558
1559         if (sc->bios_control & CFEXTEND)
1560                 ahc->flags |= AHC_EXTENDED_TRANS_A;
1561
1562         if (sc->bios_control & CFBIOSEN)
1563                 ahc->flags |= AHC_BIOS_ENABLED;
1564         if (ahc->features & AHC_ULTRA
1565          && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1566                 /* Should we enable Ultra mode? */
1567                 if (!(sc->adapter_control & CFULTRAEN))
1568                         /* Treat us as a non-ultra card */
1569                         ultraenb = 0;
1570         }
1571
1572         if (sc->signature == CFSIGNATURE
1573          || sc->signature == CFSIGNATURE2) {
1574                 uint32_t devconfig;
1575
1576                 /* Honor the STPWLEVEL settings */
1577                 devconfig = ahc_pci_read_config(ahc->dev_softc,
1578                                                 DEVCONFIG, /*bytes*/4);
1579                 devconfig &= ~STPWLEVEL;
1580                 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1581                         devconfig |= STPWLEVEL;
1582                 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1583                                      devconfig, /*bytes*/4);
1584         }
1585         /* Set SCSICONF info */
1586         ahc_outb(ahc, SCSICONF, scsi_conf);
1587         ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1588         ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1589         ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1590         ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1591 }
1592
1593 static void
1594 configure_termination(struct ahc_softc *ahc,
1595                       struct seeprom_descriptor *sd,
1596                       u_int adapter_control,
1597                       u_int *sxfrctl1)
1598 {
1599         uint8_t brddat;
1600
1601         brddat = 0;
1602
1603         /*
1604          * Update the settings in sxfrctl1 to match the
1605          * termination settings
1606          */
1607         *sxfrctl1 = 0;
1608
1609         /*
1610          * SEECS must be on for the GALS to latch
1611          * the data properly.  Be sure to leave MS
1612          * on or we will release the seeprom.
1613          */
1614         SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1615         if ((adapter_control & CFAUTOTERM) != 0
1616          || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1617                 int internal50_present;
1618                 int internal68_present;
1619                 int externalcable_present;
1620                 int eeprom_present;
1621                 int enableSEC_low;
1622                 int enableSEC_high;
1623                 int enablePRI_low;
1624                 int enablePRI_high;
1625                 int sum;
1626
1627                 enableSEC_low = 0;
1628                 enableSEC_high = 0;
1629                 enablePRI_low = 0;
1630                 enablePRI_high = 0;
1631                 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1632                         ahc_new_term_detect(ahc, &enableSEC_low,
1633                                             &enableSEC_high,
1634                                             &enablePRI_low,
1635                                             &enablePRI_high,
1636                                             &eeprom_present);
1637                         if ((adapter_control & CFSEAUTOTERM) == 0) {
1638                                 if (bootverbose)
1639                                         printf("%s: Manual SE Termination\n",
1640                                                ahc_name(ahc));
1641                                 enableSEC_low = (adapter_control & CFSELOWTERM);
1642                                 enableSEC_high =
1643                                     (adapter_control & CFSEHIGHTERM);
1644                         }
1645                         if ((adapter_control & CFAUTOTERM) == 0) {
1646                                 if (bootverbose)
1647                                         printf("%s: Manual LVD Termination\n",
1648                                                ahc_name(ahc));
1649                                 enablePRI_low = (adapter_control & CFSTERM);
1650                                 enablePRI_high = (adapter_control & CFWSTERM);
1651                         }
1652                         /* Make the table calculations below happy */
1653                         internal50_present = 0;
1654                         internal68_present = 1;
1655                         externalcable_present = 1;
1656                 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1657                         aic785X_cable_detect(ahc, &internal50_present,
1658                                              &externalcable_present,
1659                                              &eeprom_present);
1660                         /* Can never support a wide connector. */
1661                         internal68_present = 0;
1662                 } else {
1663                         aic787X_cable_detect(ahc, &internal50_present,
1664                                              &internal68_present,
1665                                              &externalcable_present,
1666                                              &eeprom_present);
1667                 }
1668
1669                 if ((ahc->features & AHC_WIDE) == 0)
1670                         internal68_present = 0;
1671
1672                 if (bootverbose
1673                  && (ahc->features & AHC_ULTRA2) == 0) {
1674                         printf("%s: internal 50 cable %s present",
1675                                ahc_name(ahc),
1676                                internal50_present ? "is":"not");
1677
1678                         if ((ahc->features & AHC_WIDE) != 0)
1679                                 printf(", internal 68 cable %s present",
1680                                        internal68_present ? "is":"not");
1681                         printf("\n%s: external cable %s present\n",
1682                                ahc_name(ahc),
1683                                externalcable_present ? "is":"not");
1684                 }
1685                 if (bootverbose)
1686                         printf("%s: BIOS eeprom %s present\n",
1687                                ahc_name(ahc), eeprom_present ? "is" : "not");
1688
1689                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1690                         /*
1691                          * The 50 pin connector is a separate bus,
1692                          * so force it to always be terminated.
1693                          * In the future, perform current sensing
1694                          * to determine if we are in the middle of
1695                          * a properly terminated bus.
1696                          */
1697                         internal50_present = 0;
1698                 }
1699
1700                 /*
1701                  * Now set the termination based on what
1702                  * we found.
1703                  * Flash Enable = BRDDAT7
1704                  * Secondary High Term Enable = BRDDAT6
1705                  * Secondary Low Term Enable = BRDDAT5 (7890)
1706                  * Primary High Term Enable = BRDDAT4 (7890)
1707                  */
1708                 if ((ahc->features & AHC_ULTRA2) == 0
1709                  && (internal50_present != 0)
1710                  && (internal68_present != 0)
1711                  && (externalcable_present != 0)) {
1712                         printf("%s: Illegal cable configuration!!. "
1713                                "Only two connectors on the "
1714                                "adapter may be used at a "
1715                                "time!\n", ahc_name(ahc));
1716
1717                         /*
1718                          * Pretend there are no cables in the hope
1719                          * that having all of the termination on
1720                          * gives us a more stable bus.
1721                          */
1722                         internal50_present = 0;
1723                         internal68_present = 0;
1724                         externalcable_present = 0;
1725                 }
1726
1727                 if ((ahc->features & AHC_WIDE) != 0
1728                  && ((externalcable_present == 0)
1729                   || (internal68_present == 0)
1730                   || (enableSEC_high != 0))) {
1731                         brddat |= BRDDAT6;
1732                         if (bootverbose) {
1733                                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1734                                         printf("%s: 68 pin termination "
1735                                                "Enabled\n", ahc_name(ahc));
1736                                 else
1737                                         printf("%s: %sHigh byte termination "
1738                                                "Enabled\n", ahc_name(ahc),
1739                                                enableSEC_high ? "Secondary "
1740                                                               : "");
1741                         }
1742                 }
1743
1744                 sum = internal50_present + internal68_present
1745                     + externalcable_present;
1746                 if (sum < 2 || (enableSEC_low != 0)) {
1747                         if ((ahc->features & AHC_ULTRA2) != 0)
1748                                 brddat |= BRDDAT5;
1749                         else
1750                                 *sxfrctl1 |= STPWEN;
1751                         if (bootverbose) {
1752                                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1753                                         printf("%s: 50 pin termination "
1754                                                "Enabled\n", ahc_name(ahc));
1755                                 else
1756                                         printf("%s: %sLow byte termination "
1757                                                "Enabled\n", ahc_name(ahc),
1758                                                enableSEC_low ? "Secondary "
1759                                                              : "");
1760                         }
1761                 }
1762
1763                 if (enablePRI_low != 0) {
1764                         *sxfrctl1 |= STPWEN;
1765                         if (bootverbose)
1766                                 printf("%s: Primary Low Byte termination "
1767                                        "Enabled\n", ahc_name(ahc));
1768                 }
1769
1770                 /*
1771                  * Setup STPWEN before setting up the rest of
1772                  * the termination per the tech note on the U160 cards.
1773                  */
1774                 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1775
1776                 if (enablePRI_high != 0) {
1777                         brddat |= BRDDAT4;
1778                         if (bootverbose)
1779                                 printf("%s: Primary High Byte "
1780                                        "termination Enabled\n",
1781                                        ahc_name(ahc));
1782                 }
1783
1784                 write_brdctl(ahc, brddat);
1785
1786         } else {
1787                 if ((adapter_control & CFSTERM) != 0) {
1788                         *sxfrctl1 |= STPWEN;
1789
1790                         if (bootverbose)
1791                                 printf("%s: %sLow byte termination Enabled\n",
1792                                        ahc_name(ahc),
1793                                        (ahc->features & AHC_ULTRA2) ? "Primary "
1794                                                                     : "");
1795                 }
1796
1797                 if ((adapter_control & CFWSTERM) != 0
1798                  && (ahc->features & AHC_WIDE) != 0) {
1799                         brddat |= BRDDAT6;
1800                         if (bootverbose)
1801                                 printf("%s: %sHigh byte termination Enabled\n",
1802                                        ahc_name(ahc),
1803                                        (ahc->features & AHC_ULTRA2)
1804                                      ? "Secondary " : "");
1805                 }
1806
1807                 /*
1808                  * Setup STPWEN before setting up the rest of
1809                  * the termination per the tech note on the U160 cards.
1810                  */
1811                 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1812
1813                 if ((ahc->features & AHC_WIDE) != 0)
1814                         write_brdctl(ahc, brddat);
1815         }
1816         SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1817 }
1818
1819 static void
1820 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1821                     int *enableSEC_high, int *enablePRI_low,
1822                     int *enablePRI_high, int *eeprom_present)
1823 {
1824         uint8_t brdctl;
1825
1826         /*
1827          * BRDDAT7 = Eeprom
1828          * BRDDAT6 = Enable Secondary High Byte termination
1829          * BRDDAT5 = Enable Secondary Low Byte termination
1830          * BRDDAT4 = Enable Primary high byte termination
1831          * BRDDAT3 = Enable Primary low byte termination
1832          */
1833         brdctl = read_brdctl(ahc);
1834         *eeprom_present = brdctl & BRDDAT7;
1835         *enableSEC_high = (brdctl & BRDDAT6);
1836         *enableSEC_low = (brdctl & BRDDAT5);
1837         *enablePRI_high = (brdctl & BRDDAT4);
1838         *enablePRI_low = (brdctl & BRDDAT3);
1839 }
1840
1841 static void
1842 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1843                      int *internal68_present, int *externalcable_present,
1844                      int *eeprom_present)
1845 {
1846         uint8_t brdctl;
1847
1848         /*
1849          * First read the status of our cables.
1850          * Set the rom bank to 0 since the
1851          * bank setting serves as a multiplexor
1852          * for the cable detection logic.
1853          * BRDDAT5 controls the bank switch.
1854          */
1855         write_brdctl(ahc, 0);
1856
1857         /*
1858          * Now read the state of the internal
1859          * connectors.  BRDDAT6 is INT50 and
1860          * BRDDAT7 is INT68.
1861          */
1862         brdctl = read_brdctl(ahc);
1863         *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1864         *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1865
1866         /*
1867          * Set the rom bank to 1 and determine
1868          * the other signals.
1869          */
1870         write_brdctl(ahc, BRDDAT5);
1871
1872         /*
1873          * Now read the state of the external
1874          * connectors.  BRDDAT6 is EXT68 and
1875          * BRDDAT7 is EPROMPS.
1876          */
1877         brdctl = read_brdctl(ahc);
1878         *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1879         *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1880 }
1881
1882 static void
1883 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1884                      int *externalcable_present, int *eeprom_present)
1885 {
1886         uint8_t brdctl;
1887         uint8_t spiocap;
1888
1889         spiocap = ahc_inb(ahc, SPIOCAP);
1890         spiocap &= ~SOFTCMDEN;
1891         spiocap |= EXT_BRDCTL;
1892         ahc_outb(ahc, SPIOCAP, spiocap);
1893         ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1894         ahc_flush_device_writes(ahc);
1895         ahc_delay(500);
1896         ahc_outb(ahc, BRDCTL, 0);
1897         ahc_flush_device_writes(ahc);
1898         ahc_delay(500);
1899         brdctl = ahc_inb(ahc, BRDCTL);
1900         *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1901         *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1902         *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1903 }
1904
1905 int
1906 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1907 {
1908         int wait;
1909
1910         if ((ahc->features & AHC_SPIOCAP) != 0
1911          && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1912                 return (0);
1913
1914         /*
1915          * Request access of the memory port.  When access is
1916          * granted, SEERDY will go high.  We use a 1 second
1917          * timeout which should be near 1 second more than
1918          * is needed.  Reason: after the chip reset, there
1919          * should be no contention.
1920          */
1921         SEEPROM_OUTB(sd, sd->sd_MS);
1922         wait = 1000;  /* 1 second timeout in msec */
1923         while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1924                 ahc_delay(1000);  /* delay 1 msec */
1925         }
1926         if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1927                 SEEPROM_OUTB(sd, 0);
1928                 return (0);
1929         }
1930         return(1);
1931 }
1932
1933 void
1934 ahc_release_seeprom(struct seeprom_descriptor *sd)
1935 {
1936         /* Release access to the memory port and the serial EEPROM. */
1937         SEEPROM_OUTB(sd, 0);
1938 }
1939
1940 static void
1941 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1942 {
1943         uint8_t brdctl;
1944
1945         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1946                 brdctl = BRDSTB;
1947                 if (ahc->channel == 'B')
1948                         brdctl |= BRDCS;
1949         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1950                 brdctl = 0;
1951         } else {
1952                 brdctl = BRDSTB|BRDCS;
1953         }
1954         ahc_outb(ahc, BRDCTL, brdctl);
1955         ahc_flush_device_writes(ahc);
1956         brdctl |= value;
1957         ahc_outb(ahc, BRDCTL, brdctl);
1958         ahc_flush_device_writes(ahc);
1959         if ((ahc->features & AHC_ULTRA2) != 0)
1960                 brdctl |= BRDSTB_ULTRA2;
1961         else
1962                 brdctl &= ~BRDSTB;
1963         ahc_outb(ahc, BRDCTL, brdctl);
1964         ahc_flush_device_writes(ahc);
1965         if ((ahc->features & AHC_ULTRA2) != 0)
1966                 brdctl = 0;
1967         else
1968                 brdctl &= ~BRDCS;
1969         ahc_outb(ahc, BRDCTL, brdctl);
1970 }
1971
1972 static uint8_t
1973 read_brdctl(struct ahc_softc *ahc)
1974 {
1975         uint8_t brdctl;
1976         uint8_t value;
1977
1978         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1979                 brdctl = BRDRW;
1980                 if (ahc->channel == 'B')
1981                         brdctl |= BRDCS;
1982         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1983                 brdctl = BRDRW_ULTRA2;
1984         } else {
1985                 brdctl = BRDRW|BRDCS;
1986         }
1987         ahc_outb(ahc, BRDCTL, brdctl);
1988         ahc_flush_device_writes(ahc);
1989         value = ahc_inb(ahc, BRDCTL);
1990         ahc_outb(ahc, BRDCTL, 0);
1991         return (value);
1992 }
1993
1994 static void
1995 ahc_pci_intr(struct ahc_softc *ahc)
1996 {
1997         u_int error;
1998         u_int status1;
1999
2000         error = ahc_inb(ahc, ERROR);
2001         if ((error & PCIERRSTAT) == 0)
2002                 return;
2003
2004         status1 = ahc_pci_read_config(ahc->dev_softc,
2005                                       PCIR_STATUS + 1, /*bytes*/1);
2006
2007         printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2008               ahc_name(ahc),
2009               ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2010
2011         if (status1 & DPE) {
2012                 ahc->pci_target_perr_count++;
2013                 printf("%s: Data Parity Error Detected during address "
2014                        "or write data phase\n", ahc_name(ahc));
2015         }
2016         if (status1 & SSE) {
2017                 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2018         }
2019         if (status1 & RMA) {
2020                 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2021         }
2022         if (status1 & RTA) {
2023                 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2024         }
2025         if (status1 & STA) {
2026                 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2027         }
2028         if (status1 & DPR) {
2029                 printf("%s: Data Parity Error has been reported via PERR#\n",
2030                        ahc_name(ahc));
2031         }
2032
2033         /* Clear latched errors. */
2034         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2035                              status1, /*bytes*/1);
2036
2037         if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2038                 printf("%s: Latched PCIERR interrupt with "
2039                        "no status bits set\n", ahc_name(ahc));
2040         } else {
2041                 ahc_outb(ahc, CLRINT, CLRPARERR);
2042         }
2043
2044         if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
2045                 printf(
2046 "%s: WARNING WARNING WARNING WARNING\n"
2047 "%s: Too many PCI parity errors observed as a target.\n"
2048 "%s: Some device on this bus is generating bad parity.\n"
2049 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
2050 "%s: PCI parity error checking has been disabled.\n"
2051 "%s: WARNING WARNING WARNING WARNING\n",
2052                        ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2053                        ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
2054                 ahc->seqctl |= FAILDIS;
2055                 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2056         }
2057         ahc_unpause(ahc);
2058 }
2059
2060 static int
2061 ahc_pci_chip_init(struct ahc_softc *ahc)
2062 {
2063         ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2064         ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2065         if ((ahc->features & AHC_DT) != 0) {
2066                 u_int sfunct;
2067
2068                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2069                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2070                 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2071                 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2072                 ahc_outb(ahc, SFUNCT, sfunct);
2073                 ahc_outb(ahc, CRCCONTROL1,
2074                          ahc->bus_softc.pci_softc.crccontrol1);
2075         }
2076         if ((ahc->features & AHC_MULTI_FUNC) != 0)
2077                 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2078
2079         if ((ahc->features & AHC_ULTRA2) != 0)
2080                 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2081
2082         return (ahc_chip_init(ahc));
2083 }
2084
2085 static int
2086 ahc_pci_suspend(struct ahc_softc *ahc)
2087 {
2088         return (ahc_suspend(ahc));
2089 }
2090
2091 static int
2092 ahc_pci_resume(struct ahc_softc *ahc)
2093 {
2094
2095         ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
2096
2097         /*
2098          * We assume that the OS has restored our register
2099          * mappings, etc.  Just update the config space registers
2100          * that the OS doesn't know about and rely on our chip
2101          * reset handler to handle the rest.
2102          */
2103         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4,
2104                              ahc->bus_softc.pci_softc.devconfig);
2105         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1,
2106                              ahc->bus_softc.pci_softc.command);
2107         ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1,
2108                              ahc->bus_softc.pci_softc.csize_lattime);
2109         if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2110                 struct  seeprom_descriptor sd;
2111                 u_int   sxfrctl1;
2112
2113                 sd.sd_ahc = ahc;
2114                 sd.sd_control_offset = SEECTL;
2115                 sd.sd_status_offset = SEECTL;
2116                 sd.sd_dataout_offset = SEECTL;
2117
2118                 ahc_acquire_seeprom(ahc, &sd);
2119                 configure_termination(ahc, &sd,
2120                                       ahc->seep_config->adapter_control,
2121                                       &sxfrctl1);
2122                 ahc_release_seeprom(&sd);
2123         }
2124         return (ahc_resume(ahc));
2125 }
2126
2127 static int
2128 ahc_aic785X_setup(struct ahc_softc *ahc)
2129 {
2130         ahc_dev_softc_t pci;
2131         uint8_t rev;
2132
2133         pci = ahc->dev_softc;
2134         ahc->channel = 'A';
2135         ahc->chip = AHC_AIC7850;
2136         ahc->features = AHC_AIC7850_FE;
2137         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2138         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2139         if (rev >= 1)
2140                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2141         ahc->instruction_ram_size = 512;
2142         return (0);
2143 }
2144
2145 static int
2146 ahc_aic7860_setup(struct ahc_softc *ahc)
2147 {
2148         ahc_dev_softc_t pci;
2149         uint8_t rev;
2150
2151         pci = ahc->dev_softc;
2152         ahc->channel = 'A';
2153         ahc->chip = AHC_AIC7860;
2154         ahc->features = AHC_AIC7860_FE;
2155         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2156         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2157         if (rev >= 1)
2158                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2159         ahc->instruction_ram_size = 512;
2160         return (0);
2161 }
2162
2163 static int
2164 ahc_apa1480_setup(struct ahc_softc *ahc)
2165 {
2166         int error;
2167
2168         error = ahc_aic7860_setup(ahc);
2169         if (error != 0)
2170                 return (error);
2171         ahc->features |= AHC_REMOVABLE;
2172         return (0);
2173 }
2174
2175 static int
2176 ahc_aic7870_setup(struct ahc_softc *ahc)
2177 {
2178
2179         ahc->channel = 'A';
2180         ahc->chip = AHC_AIC7870;
2181         ahc->features = AHC_AIC7870_FE;
2182         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2183         ahc->instruction_ram_size = 512;
2184         return (0);
2185 }
2186
2187 static int
2188 ahc_aha394X_setup(struct ahc_softc *ahc)
2189 {
2190         int error;
2191
2192         error = ahc_aic7870_setup(ahc);
2193         if (error == 0)
2194                 error = ahc_aha394XX_setup(ahc);
2195         return (error);
2196 }
2197
2198 static int
2199 ahc_aha398X_setup(struct ahc_softc *ahc)
2200 {
2201         int error;
2202
2203         error = ahc_aic7870_setup(ahc);
2204         if (error == 0)
2205                 error = ahc_aha398XX_setup(ahc);
2206         return (error);
2207 }
2208
2209 static int
2210 ahc_aha494X_setup(struct ahc_softc *ahc)
2211 {
2212         int error;
2213
2214         error = ahc_aic7870_setup(ahc);
2215         if (error == 0)
2216                 error = ahc_aha494XX_setup(ahc);
2217         return (error);
2218 }
2219
2220 static int
2221 ahc_aic7880_setup(struct ahc_softc *ahc)
2222 {
2223         ahc_dev_softc_t pci;
2224         uint8_t rev;
2225
2226         pci = ahc->dev_softc;
2227         ahc->channel = 'A';
2228         ahc->chip = AHC_AIC7880;
2229         ahc->features = AHC_AIC7880_FE;
2230         ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2231         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2232         if (rev >= 1) {
2233                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2234         } else {
2235                 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2236         }
2237         ahc->instruction_ram_size = 512;
2238         return (0);
2239 }
2240
2241 static int
2242 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2243 {
2244
2245         ahc->flags |= AHC_INT50_SPEEDFLEX;
2246         return (ahc_aic7880_setup(ahc));
2247 }
2248
2249 static int
2250 ahc_aha394XU_setup(struct ahc_softc *ahc)
2251 {
2252         int error;
2253
2254         error = ahc_aic7880_setup(ahc);
2255         if (error == 0)
2256                 error = ahc_aha394XX_setup(ahc);
2257         return (error);
2258 }
2259
2260 static int
2261 ahc_aha398XU_setup(struct ahc_softc *ahc)
2262 {
2263         int error;
2264
2265         error = ahc_aic7880_setup(ahc);
2266         if (error == 0)
2267                 error = ahc_aha398XX_setup(ahc);
2268         return (error);
2269 }
2270
2271 static int
2272 ahc_aic7890_setup(struct ahc_softc *ahc)
2273 {
2274         ahc_dev_softc_t pci;
2275         uint8_t rev;
2276
2277         pci = ahc->dev_softc;
2278         ahc->channel = 'A';
2279         ahc->chip = AHC_AIC7890;
2280         ahc->features = AHC_AIC7890_FE;
2281         ahc->flags |= AHC_NEWEEPROM_FMT;
2282         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2283         if (rev == 0)
2284                 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2285         ahc->instruction_ram_size = 768;
2286         return (0);
2287 }
2288
2289 static int
2290 ahc_aic7892_setup(struct ahc_softc *ahc)
2291 {
2292
2293         ahc->channel = 'A';
2294         ahc->chip = AHC_AIC7892;
2295         ahc->features = AHC_AIC7892_FE;
2296         ahc->flags |= AHC_NEWEEPROM_FMT;
2297         ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2298         ahc->instruction_ram_size = 1024;
2299         return (0);
2300 }
2301
2302 static int
2303 ahc_aic7895_setup(struct ahc_softc *ahc)
2304 {
2305         ahc_dev_softc_t pci;
2306         uint8_t rev;
2307
2308         pci = ahc->dev_softc;
2309         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2310         /*
2311          * The 'C' revision of the aic7895 has a few additional features.
2312          */
2313         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2314         if (rev >= 4) {
2315                 ahc->chip = AHC_AIC7895C;
2316                 ahc->features = AHC_AIC7895C_FE;
2317         } else  {
2318                 u_int command;
2319
2320                 ahc->chip = AHC_AIC7895;
2321                 ahc->features = AHC_AIC7895_FE;
2322
2323                 /*
2324                  * The BIOS disables the use of MWI transactions
2325                  * since it does not have the MWI bug work around
2326                  * we have.  Disabling MWI reduces performance, so
2327                  * turn it on again.
2328                  */
2329                 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2330                 command |= PCIM_CMD_MWRICEN;
2331                 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2332                 ahc->bugs |= AHC_PCI_MWI_BUG;
2333         }
2334         /*
2335          * XXX Does CACHETHEN really not work???  What about PCI retry?
2336          * on C level chips.  Need to test, but for now, play it safe.
2337          */
2338         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2339                   |  AHC_CACHETHEN_BUG;
2340
2341 #if 0
2342         uint32_t devconfig;
2343
2344         /*
2345          * Cachesize must also be zero due to stray DAC
2346          * problem when sitting behind some bridges.
2347          */
2348         ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2349         devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2350         devconfig |= MRDCEN;
2351         ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2352 #endif
2353         ahc->flags |= AHC_NEWEEPROM_FMT;
2354         ahc->instruction_ram_size = 512;
2355         return (0);
2356 }
2357
2358 static int
2359 ahc_aic7896_setup(struct ahc_softc *ahc)
2360 {
2361         ahc_dev_softc_t pci;
2362
2363         pci = ahc->dev_softc;
2364         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2365         ahc->chip = AHC_AIC7896;
2366         ahc->features = AHC_AIC7896_FE;
2367         ahc->flags |= AHC_NEWEEPROM_FMT;
2368         ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2369         ahc->instruction_ram_size = 768;
2370         return (0);
2371 }
2372
2373 static int
2374 ahc_aic7899_setup(struct ahc_softc *ahc)
2375 {
2376         ahc_dev_softc_t pci;
2377
2378         pci = ahc->dev_softc;
2379         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2380         ahc->chip = AHC_AIC7899;
2381         ahc->features = AHC_AIC7899_FE;
2382         ahc->flags |= AHC_NEWEEPROM_FMT;
2383         ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2384         ahc->instruction_ram_size = 1024;
2385         return (0);
2386 }
2387
2388 static int
2389 ahc_aha29160C_setup(struct ahc_softc *ahc)
2390 {
2391         int error;
2392
2393         error = ahc_aic7899_setup(ahc);
2394         if (error != 0)
2395                 return (error);
2396         ahc->features |= AHC_REMOVABLE;
2397         return (0);
2398 }
2399
2400 static int
2401 ahc_raid_setup(struct ahc_softc *ahc)
2402 {
2403         printf("RAID functionality unsupported\n");
2404         return (ENXIO);
2405 }
2406
2407 static int
2408 ahc_aha394XX_setup(struct ahc_softc *ahc)
2409 {
2410         ahc_dev_softc_t pci;
2411
2412         pci = ahc->dev_softc;
2413         switch (ahc_get_pci_slot(pci)) {
2414         case AHC_394X_SLOT_CHANNEL_A:
2415                 ahc->channel = 'A';
2416                 break;
2417         case AHC_394X_SLOT_CHANNEL_B:
2418                 ahc->channel = 'B';
2419                 break;
2420         default:
2421                 printf("adapter at unexpected slot %d\n"
2422                        "unable to map to a channel\n",
2423                        ahc_get_pci_slot(pci));
2424                 ahc->channel = 'A';
2425         }
2426         return (0);
2427 }
2428
2429 static int
2430 ahc_aha398XX_setup(struct ahc_softc *ahc)
2431 {
2432         ahc_dev_softc_t pci;
2433
2434         pci = ahc->dev_softc;
2435         switch (ahc_get_pci_slot(pci)) {
2436         case AHC_398X_SLOT_CHANNEL_A:
2437                 ahc->channel = 'A';
2438                 break;
2439         case AHC_398X_SLOT_CHANNEL_B:
2440                 ahc->channel = 'B';
2441                 break;
2442         case AHC_398X_SLOT_CHANNEL_C:
2443                 ahc->channel = 'C';
2444                 break;
2445         default:
2446                 printf("adapter at unexpected slot %d\n"
2447                        "unable to map to a channel\n",
2448                        ahc_get_pci_slot(pci));
2449                 ahc->channel = 'A';
2450                 break;
2451         }
2452         ahc->flags |= AHC_LARGE_SEEPROM;
2453         return (0);
2454 }
2455
2456 static int
2457 ahc_aha494XX_setup(struct ahc_softc *ahc)
2458 {
2459         ahc_dev_softc_t pci;
2460
2461         pci = ahc->dev_softc;
2462         switch (ahc_get_pci_slot(pci)) {
2463         case AHC_494X_SLOT_CHANNEL_A:
2464                 ahc->channel = 'A';
2465                 break;
2466         case AHC_494X_SLOT_CHANNEL_B:
2467                 ahc->channel = 'B';
2468                 break;
2469         case AHC_494X_SLOT_CHANNEL_C:
2470                 ahc->channel = 'C';
2471                 break;
2472         case AHC_494X_SLOT_CHANNEL_D:
2473                 ahc->channel = 'D';
2474                 break;
2475         default:
2476                 printf("adapter at unexpected slot %d\n"
2477                        "unable to map to a channel\n",
2478                        ahc_get_pci_slot(pci));
2479                 ahc->channel = 'A';
2480         }
2481         ahc->flags |= AHC_LARGE_SEEPROM;
2482         return (0);
2483 }