2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 * $DragonFly: src/sys/platform/pc32/i386/identcpu.c,v 1.19 2007/11/07 17:42:50 dillon Exp $
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
60 #include <machine_base/isa/intr_machdep.h>
62 #define IDENTBLUE_CYRIX486 0
63 #define IDENTBLUE_IBMCPU 1
64 #define IDENTBLUE_CYRIXM2 2
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void finishidentcpu(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void enable_K5_wt_alloc(void);
71 void enable_K6_wt_alloc(void);
72 void enable_K6_2_wt_alloc(void);
74 void panicifcpuunsupported(void);
76 static void identifycyrix(void);
77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78 static void print_AMD_features(void);
80 static void print_AMD_info(void);
81 static void print_AMD_assoc(int i);
82 static void print_transmeta_info(void);
83 static void setup_tmx86_longrun(void);
85 int cpu_class = CPUCLASS_386;
86 u_int cpu_exthigh; /* Highest arg to extended CPUID */
87 u_int cyrix_did; /* Device ID of Cyrix CPU */
88 char machine[] = MACHINE;
89 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
90 machine, 0, "Machine class");
92 static char cpu_model[128];
93 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
94 cpu_model, 0, "Machine model");
96 static char cpu_brand[48];
98 #define MAX_ADDITIONAL_INFO 16
100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
101 static u_int additional_cpu_info_count;
103 #define MAX_BRAND_INDEX 23
106 * Brand ID's according to Intel document AP-485, number 241618-31, published
107 * September 2006, page 42.
109 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
113 "Intel Pentium III Xeon",
115 NULL, /* Unspecified */
116 "Mobile Intel Pentium III-M",
117 "Mobile Intel Celeron",
123 NULL, /* Unspecified */
124 "Mobile Intel Pentium 4-M",
125 "Mobile Intel Celeron",
126 NULL, /* Unspecified */
127 "Mobile Genuine Intel",
129 "Mobile Intel Celeron",
131 "Mobile Genuine Intel",
133 "Mobile Intel Celeron"
136 static struct cpu_nameclass i386_cpus[] = {
137 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
138 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
139 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
140 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
141 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
142 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
143 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
144 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
145 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
146 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
147 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
148 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
149 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
150 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
151 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
152 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
153 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
156 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
157 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
163 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
168 cpu_class = i386_cpus[cpu].cpu_class;
170 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
172 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
173 /* Check for extended CPUID information and a processor name. */
175 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
176 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
177 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
178 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
179 do_cpuid(0x80000000, regs);
180 if (regs[0] >= 0x80000000) {
181 cpu_exthigh = regs[0];
182 if (cpu_exthigh >= 0x80000004) {
184 for (i = 0x80000002; i < 0x80000005; i++) {
186 memcpy(brand, regs, sizeof(regs));
187 brand += sizeof(regs);
193 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
194 if ((cpu_id & 0xf00) > 0x300) {
199 switch (cpu_id & 0x3000) {
201 strcpy(cpu_model, "Overdrive ");
204 strcpy(cpu_model, "Dual ");
208 switch (cpu_id & 0xf00) {
210 strcat(cpu_model, "i486 ");
211 /* Check the particular flavor of 486 */
212 switch (cpu_id & 0xf0) {
215 strcat(cpu_model, "DX");
218 strcat(cpu_model, "SX");
221 strcat(cpu_model, "DX2");
224 strcat(cpu_model, "SL");
227 strcat(cpu_model, "SX2");
231 "DX2 Write-Back Enhanced");
234 strcat(cpu_model, "DX4");
239 /* Check the particular flavor of 586 */
240 strcat(cpu_model, "Pentium");
241 switch (cpu_id & 0xf0) {
243 strcat(cpu_model, " A-step");
246 strcat(cpu_model, "/P5");
249 strcat(cpu_model, "/P54C");
252 strcat(cpu_model, "/P54T Overdrive");
255 strcat(cpu_model, "/P55C");
258 strcat(cpu_model, "/P54C");
261 strcat(cpu_model, "/P55C (quarter-micron)");
267 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
269 * XXX - If/when Intel fixes the bug, this
270 * should also check the version of the
271 * CPU, not just that it's a Pentium.
277 /* Check the particular flavor of 686 */
278 switch (cpu_id & 0xf0) {
280 strcat(cpu_model, "Pentium Pro A-step");
283 strcat(cpu_model, "Pentium Pro");
289 "Pentium II/Pentium II Xeon/Celeron");
297 "Pentium III/Pentium III Xeon/Celeron");
301 strcat(cpu_model, "Unknown 80686");
306 strcat(cpu_model, "Pentium 4");
310 strcat(cpu_model, "unknown");
315 * If we didn't get a brand name from the extended
316 * CPUID, try to look it up in the brand table.
318 if (cpu_high > 0 && *cpu_brand == '\0') {
319 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
320 if (brand_index <= MAX_BRAND_INDEX &&
321 cpu_brandtable[brand_index] != NULL)
323 cpu_brandtable[brand_index]);
326 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
328 * Values taken from AMD Processor Recognition
329 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
330 * (also describes ``Features'' encodings.
332 strcpy(cpu_model, "AMD ");
333 switch (cpu_id & 0xFF0) {
335 strcat(cpu_model, "Standard Am486DX");
338 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
341 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
344 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
347 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
350 strcat(cpu_model, "Am5x86 Write-Through");
353 strcat(cpu_model, "Am5x86 Write-Back");
356 strcat(cpu_model, "K5 model 0");
360 strcat(cpu_model, "K5 model 1");
363 strcat(cpu_model, "K5 PR166 (model 2)");
366 strcat(cpu_model, "K5 PR200 (model 3)");
369 strcat(cpu_model, "K6");
372 strcat(cpu_model, "K6 266 (model 1)");
375 strcat(cpu_model, "K6-2");
378 strcat(cpu_model, "K6-III");
381 strcat(cpu_model, "Unknown");
384 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
385 if ((cpu_id & 0xf00) == 0x500) {
386 if (((cpu_id & 0x0f0) > 0)
387 && ((cpu_id & 0x0f0) < 0x60)
388 && ((cpu_id & 0x00f) > 3))
389 enable_K5_wt_alloc();
390 else if (((cpu_id & 0x0f0) > 0x80)
391 || (((cpu_id & 0x0f0) == 0x80)
392 && (cpu_id & 0x00f) > 0x07))
393 enable_K6_2_wt_alloc();
394 else if ((cpu_id & 0x0f0) > 0x50)
395 enable_K6_wt_alloc();
398 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
399 strcpy(cpu_model, "Cyrix ");
400 switch (cpu_id & 0xff0) {
402 strcat(cpu_model, "MediaGX");
405 strcat(cpu_model, "6x86");
408 cpu_class = CPUCLASS_586;
409 strcat(cpu_model, "GXm");
412 strcat(cpu_model, "6x86MX");
416 * Even though CPU supports the cpuid
417 * instruction, it can be disabled.
418 * Therefore, this routine supports all Cyrix
421 switch (cyrix_did & 0xf0) {
423 switch (cyrix_did & 0x0f) {
425 strcat(cpu_model, "486SLC");
428 strcat(cpu_model, "486DLC");
431 strcat(cpu_model, "486SLC2");
434 strcat(cpu_model, "486DLC2");
437 strcat(cpu_model, "486SRx");
440 strcat(cpu_model, "486DRx");
443 strcat(cpu_model, "486SRx2");
446 strcat(cpu_model, "486DRx2");
449 strcat(cpu_model, "486SRu");
452 strcat(cpu_model, "486DRu");
455 strcat(cpu_model, "486SRu2");
458 strcat(cpu_model, "486DRu2");
461 strcat(cpu_model, "Unknown");
466 switch (cyrix_did & 0x0f) {
468 strcat(cpu_model, "486S");
471 strcat(cpu_model, "486S2");
474 strcat(cpu_model, "486Se");
477 strcat(cpu_model, "486S2e");
480 strcat(cpu_model, "486DX");
483 strcat(cpu_model, "486DX2");
486 strcat(cpu_model, "486DX4");
489 strcat(cpu_model, "Unknown");
494 if ((cyrix_did & 0x0f) < 8)
495 strcat(cpu_model, "6x86"); /* Where did you get it? */
497 strcat(cpu_model, "5x86");
500 strcat(cpu_model, "6x86");
503 if ((cyrix_did & 0xf000) == 0x3000) {
504 cpu_class = CPUCLASS_586;
505 strcat(cpu_model, "GXm");
507 strcat(cpu_model, "MediaGX");
510 strcat(cpu_model, "6x86MX");
513 switch (cyrix_did & 0x0f) {
515 strcat(cpu_model, "Overdrive CPU");
517 strcpy(cpu_model, "Texas Instruments 486SXL");
520 strcat(cpu_model, "486SLC/DLC");
523 strcat(cpu_model, "Unknown");
528 strcat(cpu_model, "Unknown");
533 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
534 strcpy(cpu_model, "Rise ");
535 switch (cpu_id & 0xff0) {
537 strcat(cpu_model, "mP6");
540 strcat(cpu_model, "Unknown");
542 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
543 switch (cpu_id & 0xff0) {
545 strcpy(cpu_model, "IDT WinChip C6");
549 strcpy(cpu_model, "IDT WinChip 2");
552 strcpy(cpu_model, "VIA C3 Samuel");
556 strcpy(cpu_model, "VIA C3 Ezra");
558 strcpy(cpu_model, "VIA C3 Samuel 2");
561 strcpy(cpu_model, "VIA C3 Ezra-T");
564 strcpy(cpu_model, "VIA C3 Nehemiah");
565 do_cpuid(0xc0000000, regs);
566 if (regs[0] == 0xc0000001) {
567 do_cpuid(0xc0000001, regs);
568 if ((cpu_id & 0xf) >= 3)
569 if ((regs[3] & 0x0c) == 0x0c)
570 strcat(cpu_model, "+RNG");
571 if ((cpu_id & 0xf) >= 8)
572 if ((regs[3] & 0xc0) == 0xc0)
573 strcat(cpu_model, "+ACE");
577 strcpy(cpu_model, "VIA/IDT Unknown");
579 } else if (strcmp(cpu_vendor, "IBM") == 0) {
580 strcpy(cpu_model, "Blue Lightning CPU");
584 * Replace cpu_model with cpu_brand minus leading spaces if
588 while (*brand == ' ')
591 strcpy(cpu_model, brand);
595 kprintf("%s (", cpu_model);
603 #if defined(I486_CPU)
606 /* bzero = i486_bzero; */
609 #if defined(I586_CPU)
611 kprintf("%d.%02d-MHz ",
612 (tsc_freq + 4999) / 1000000,
613 ((tsc_freq + 4999) / 10000) % 100);
617 #if defined(I686_CPU)
619 kprintf("%d.%02d-MHz ",
620 (tsc_freq + 4999) / 1000000,
621 ((tsc_freq + 4999) / 10000) % 100);
626 kprintf("Unknown"); /* will panic below... */
628 kprintf("-class CPU)\n");
629 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
631 kprintf(" Origin = \"%s\"",cpu_vendor);
633 kprintf(" Id = 0x%x", cpu_id);
635 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
636 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
637 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
638 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
639 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
640 ((cpu_id & 0xf00) > 0x500))) {
641 kprintf(" Stepping = %u", cpu_id & 0xf);
642 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
643 kprintf(" DIR=0x%04x", cyrix_did);
646 * Here we should probably set up flags indicating
647 * whether or not various features are available.
648 * The interesting ones are probably VME, PSE, PAE,
649 * and PGE. The code already assumes without bothering
650 * to check that all CPUs >= Pentium have a TSC and
653 kprintf("\n Features=0x%b", cpu_feature,
655 "\001FPU" /* Integral FPU */
656 "\002VME" /* Extended VM86 mode support */
657 "\003DE" /* Debugging Extensions (CR4.DE) */
658 "\004PSE" /* 4MByte page tables */
659 "\005TSC" /* Timestamp counter */
660 "\006MSR" /* Machine specific registers */
661 "\007PAE" /* Physical address extension */
662 "\010MCE" /* Machine Check support */
663 "\011CX8" /* CMPEXCH8 instruction */
664 "\012APIC" /* SMP local APIC */
665 "\013oldMTRR" /* Previous implementation of MTRR */
666 "\014SEP" /* Fast System Call */
667 "\015MTRR" /* Memory Type Range Registers */
668 "\016PGE" /* PG_G (global bit) support */
669 "\017MCA" /* Machine Check Architecture */
670 "\020CMOV" /* CMOV instruction */
671 "\021PAT" /* Page attributes table */
672 "\022PSE36" /* 36 bit address space support */
673 "\023PN" /* Processor Serial number */
674 "\024CLFLUSH" /* Has the CLFLUSH instruction */
676 "\026DTS" /* Debug Trace Store */
677 "\027ACPI" /* ACPI support */
678 "\030MMX" /* MMX instructions */
679 "\031FXSR" /* FXSAVE/FXRSTOR */
680 "\032SSE" /* Streaming SIMD Extensions */
681 "\033SSE2" /* Streaming SIMD Extensions #2 */
682 "\034SS" /* Self snoop */
683 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
684 "\036TM" /* Thermal Monitor clock slowdown */
685 "\037IA64" /* CPU can execute IA64 instructions */
686 "\040PBE" /* Pending Break Enable */
689 if (cpu_feature2 != 0) {
690 kprintf("\n Features2=0x%b", cpu_feature2,
692 "\001SSE3" /* SSE3 */
694 "\003RSVD2" /* "Reserved" bit 2 */
695 "\004MON" /* MONITOR/MWAIT Instructions */
696 "\005DS_CPL" /* CPL Qualified Debug Store */
697 "\006VMX" /* Virtual Machine Extensions */
699 "\010EST" /* Enhanced SpeedStep */
700 "\011TM2" /* Thermal Monitor 2 */
701 "\012SSSE3" /* Supplemental SSE3 */
702 "\013CNTX-ID" /* L1 context ID available */
705 "\016CX16" /* CMPXCHG16B Instruction */
706 "\017XTPR" /* Send Task Priority Messages*/
707 "\020RSVD15" /* "Reserved" bit 15 */
728 * If this CPU supports hyperthreading then mention
729 * the number of logical CPU's it contains.
731 if (cpu_feature & CPUID_HTT &&
732 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
733 kprintf("\n Hyperthreading: %d logical CPUs",
734 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
736 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
737 cpu_exthigh >= 0x80000001)
738 print_AMD_features();
739 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
740 kprintf(" DIR=0x%04x", cyrix_did);
741 kprintf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
742 kprintf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
743 #ifndef CYRIX_CACHE_REALLY_WORKS
744 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
745 kprintf("\n CPU cache: write-through mode");
748 /* Avoid ugly blank lines: only print newline when we have to. */
749 if (*cpu_vendor || cpu_id)
753 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
754 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
755 setup_tmx86_longrun();
758 for (i = 0; i < additional_cpu_info_count; ++i) {
759 kprintf(" %s\n", additional_cpu_info_ary[i]);
765 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
767 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
768 strcmp(cpu_vendor, "TransmetaCPU") == 0)
769 print_transmeta_info();
773 * XXX - Do PPro CPUID level=2 stuff here?
775 * No, but maybe in a print_Intel_info() function called from here.
781 panicifcpuunsupported(void)
784 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
785 #error This kernel is not configured for one of the supported CPUs
788 * Now that we have told the user what they have,
789 * let them know if that machine type isn't configured.
793 * A 286 and 386 should not make it this far, anyway.
797 #if !defined(I486_CPU)
800 #if !defined(I586_CPU)
803 #if !defined(I686_CPU)
806 panic("CPU class not configured");
813 static volatile u_int trap_by_rdmsr;
816 * Special exception 6 handler.
817 * The rdmsr instruction generates invalid opcodes fault on 486-class
818 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
819 * function identblue() when this handler is called. Stacked eip should
826 " .p2align 2,0x90 \n"
827 " .type " __XSTRING(CNAME(bluetrap6)) ",@function \n"
828 __XSTRING(CNAME(bluetrap6)) ": \n"
830 " movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
831 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
836 * Special exception 13 handler.
837 * Accessing non-existent MSR generates general protection fault.
839 inthand_t bluetrap13;
843 " .p2align 2,0x90 \n"
844 " .type " __XSTRING(CNAME(bluetrap13)) ",@function \n"
845 __XSTRING(CNAME(bluetrap13)) ": \n"
847 " movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
848 " popl %eax # discard errorcode. \n"
849 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
854 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
855 * support cpuid instruction. This function should be called after
856 * loading interrupt descriptor table register.
858 * I don't like this method that handles fault, but I couldn't get
859 * information for any other methods. Does blue giant know?
868 * Cyrix 486-class CPU does not support rdmsr instruction.
869 * The rdmsr instruction generates invalid opcode fault, and exception
870 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
871 * bluetrap6() set the magic number to trap_by_rdmsr.
873 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
876 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
877 * In this case, rdmsr generates general protection fault, and
878 * exception will be trapped by bluetrap13().
880 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
882 rdmsr(0x1002); /* Cyrix CPU generates fault. */
884 if (trap_by_rdmsr == 0xa8c1d)
885 return IDENTBLUE_CYRIX486;
886 else if (trap_by_rdmsr == 0xa89c4)
887 return IDENTBLUE_CYRIXM2;
888 return IDENTBLUE_IBMCPU;
893 * identifycyrix() set lower 16 bits of cyrix_did as follows:
895 * F E D C B A 9 8 7 6 5 4 3 2 1 0
896 * +-------+-------+---------------+
897 * | SID | RID | Device ID |
898 * | (DIR 1) | (DIR 0) |
899 * +-------+-------+---------------+
904 int ccr2_test = 0, dir_test = 0;
909 ccr2 = read_cyrix_reg(CCR2);
910 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
911 read_cyrix_reg(CCR2);
912 if (read_cyrix_reg(CCR2) != ccr2)
914 write_cyrix_reg(CCR2, ccr2);
916 ccr3 = read_cyrix_reg(CCR3);
917 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
918 read_cyrix_reg(CCR3);
919 if (read_cyrix_reg(CCR3) != ccr3)
920 dir_test = 1; /* CPU supports DIRs. */
921 write_cyrix_reg(CCR3, ccr3);
924 /* Device ID registers are available. */
925 cyrix_did = read_cyrix_reg(DIR1) << 8;
926 cyrix_did += read_cyrix_reg(DIR0);
927 } else if (ccr2_test)
928 cyrix_did = 0x0010; /* 486S A-step */
930 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
936 * Final stage of CPU identification. -- Should I check TI?
945 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
946 if (cpu == CPU_486) {
948 * These conditions are equivalent to:
949 * - CPU does not support cpuid instruction.
950 * - Cyrix/IBM CPU is detected.
952 isblue = identblue();
953 if (isblue == IDENTBLUE_IBMCPU) {
954 strcpy(cpu_vendor, "IBM");
959 switch (cpu_id & 0xf00) {
962 * Cyrix's datasheet does not describe DIRs.
963 * Therefor, I assume it does not have them
964 * and use the result of the cpuid instruction.
965 * XXX they seem to have it for now at least. -Peter
973 * This routine contains a trick.
974 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
976 switch (cyrix_did & 0x00f0) {
985 if ((cyrix_did & 0x000f) < 8)
998 /* M2 and later CPUs are treated as M2. */
1002 * enable cpuid instruction.
1004 ccr3 = read_cyrix_reg(CCR3);
1005 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1006 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1007 write_cyrix_reg(CCR3, ccr3);
1010 cpu_high = regs[0]; /* eax */
1012 cpu_id = regs[0]; /* eax */
1013 cpu_feature = regs[3]; /* edx */
1017 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1019 * There are BlueLightning CPUs that do not change
1020 * undefined flags by dividing 5 by 2. In this case,
1021 * the CPU identification routine in locore.s leaves
1022 * cpu_vendor null string and puts CPU_486 into the
1025 isblue = identblue();
1026 if (isblue == IDENTBLUE_IBMCPU) {
1027 strcpy(cpu_vendor, "IBM");
1035 print_AMD_assoc(int i)
1038 kprintf(", fully associative\n");
1040 kprintf(", %d-way associative\n", i);
1044 print_AMD_info(void)
1048 if (cpu_exthigh >= 0x80000005) {
1051 do_cpuid(0x80000005, regs);
1052 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1053 print_AMD_assoc(regs[1] >> 24);
1054 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1055 print_AMD_assoc((regs[1] >> 8) & 0xff);
1056 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1057 kprintf(", %d bytes/line", regs[2] & 0xff);
1058 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1059 print_AMD_assoc((regs[2] >> 16) & 0xff);
1060 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1061 kprintf(", %d bytes/line", regs[3] & 0xff);
1062 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1063 print_AMD_assoc((regs[3] >> 16) & 0xff);
1064 if (cpu_exthigh >= 0x80000006) { /* K6-III, or later */
1065 do_cpuid(0x80000006, regs);
1067 * Report right L2 cache size on Duron rev. A0.
1069 if ((cpu_id & 0xFF0) == 0x630)
1070 kprintf("L2 internal cache: 64 kbytes");
1072 kprintf("L2 internal cache: %d kbytes",
1075 kprintf(", %d bytes/line", regs[2] & 0xff);
1076 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1077 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1080 if (((cpu_id & 0xf00) == 0x500)
1081 && (((cpu_id & 0x0f0) > 0x80)
1082 || (((cpu_id & 0x0f0) == 0x80)
1083 && (cpu_id & 0x00f) > 0x07))) {
1084 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1085 amd_whcr = rdmsr(0xc0000082);
1086 if (!(amd_whcr & (0x3ff << 22))) {
1087 kprintf("Write Allocate Disable\n");
1089 kprintf("Write Allocate Enable Limit: %dM bytes\n",
1090 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1091 kprintf("Write Allocate 15-16M bytes: %s\n",
1092 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1094 } else if (((cpu_id & 0xf00) == 0x500)
1095 && ((cpu_id & 0x0f0) > 0x50)) {
1096 /* K6, K6-2(old core) */
1097 amd_whcr = rdmsr(0xc0000082);
1098 if (!(amd_whcr & (0x7f << 1))) {
1099 kprintf("Write Allocate Disable\n");
1101 kprintf("Write Allocate Enable Limit: %dM bytes\n",
1102 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1103 kprintf("Write Allocate 15-16M bytes: %s\n",
1104 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1105 kprintf("Hardware Write Allocate Control: %s\n",
1106 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1111 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1113 print_AMD_features(void)
1118 * Values taken from AMD Processor Recognition
1119 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1121 do_cpuid(0x80000001, regs);
1122 kprintf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1124 "\001FPU" /* Integral FPU */
1125 "\002VME" /* Extended VM86 mode support */
1126 "\003DE" /* Debug extensions */
1127 "\004PSE" /* 4MByte page tables */
1128 "\005TSC" /* Timestamp counter */
1129 "\006MSR" /* Machine specific registers */
1130 "\007PAE" /* Physical address extension */
1131 "\010MCE" /* Machine Check support */
1132 "\011CX8" /* CMPEXCH8 instruction */
1133 "\012APIC" /* SMP local APIC */
1135 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1136 "\015MTRR" /* Memory Type Range Registers */
1137 "\016PGE" /* PG_G (global bit) support */
1138 "\017MCA" /* Machine Check Architecture */
1139 "\020ICMOV" /* CMOV instruction */
1140 "\021PAT" /* Page attributes table */
1141 "\022PGE36" /* 36 bit address space support */
1142 "\023RSVD" /* Reserved, unknown */
1143 "\024MP" /* Multiprocessor Capable */
1146 "\027AMIE" /* AMD MMX Instruction Extensions */
1148 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1154 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1161 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1164 #define MSR_TMx86_LONGRUN 0x80868010
1165 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1167 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1168 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1169 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1171 #define LONGRUN_MODE_MINFREQUENCY 0x00
1172 #define LONGRUN_MODE_ECONOMY 0x01
1173 #define LONGRUN_MODE_PERFORMANCE 0x02
1174 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1175 #define LONGRUN_MODE_UNKNOWN 0x04
1176 #define LONGRUN_MODE_MAX 0x04
1183 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1184 /* MSR low, MSR high, flags bit0 */
1185 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1186 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1187 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1188 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1192 tmx86_get_longrun_mode(void)
1194 union msrinfo msrinfo;
1195 u_int low, high, flags, mode;
1199 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1200 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1201 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1202 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1204 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1205 if (low == longrun_modes[mode][0] &&
1206 high == longrun_modes[mode][1] &&
1207 flags == longrun_modes[mode][2]) {
1211 mode = LONGRUN_MODE_UNKNOWN;
1218 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1224 do_cpuid(0x80860007, regs);
1225 *frequency = regs[0];
1227 *percentage = regs[2];
1234 tmx86_set_longrun_mode(u_int mode)
1236 union msrinfo msrinfo;
1238 if (mode >= LONGRUN_MODE_UNKNOWN) {
1244 /* Write LongRun mode values to Model Specific Register. */
1245 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1246 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1247 longrun_modes[mode][0]);
1248 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1249 longrun_modes[mode][1]);
1250 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1252 /* Write LongRun mode flags to Model Specific Register. */
1253 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1254 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1255 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1261 static u_int crusoe_longrun;
1262 static u_int crusoe_frequency;
1263 static u_int crusoe_voltage;
1264 static u_int crusoe_percentage;
1265 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1266 static struct sysctl_oid *crusoe_sysctl_tree;
1269 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1274 crusoe_longrun = tmx86_get_longrun_mode();
1275 mode = crusoe_longrun;
1276 error = sysctl_handle_int(oidp, &mode, 0, req);
1277 if (error || !req->newptr) {
1280 if (mode >= LONGRUN_MODE_UNKNOWN) {
1284 if (crusoe_longrun != mode) {
1285 crusoe_longrun = mode;
1286 tmx86_set_longrun_mode(crusoe_longrun);
1293 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1298 tmx86_get_longrun_status(&crusoe_frequency,
1299 &crusoe_voltage, &crusoe_percentage);
1300 val = *(u_int *)oidp->oid_arg1;
1301 error = sysctl_handle_int(oidp, &val, 0, req);
1306 setup_tmx86_longrun(void)
1308 static int done = 0;
1314 sysctl_ctx_init(&crusoe_sysctl_ctx);
1315 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1316 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1317 "crusoe", CTLFLAG_RD, 0,
1318 "Transmeta Crusoe LongRun support");
1319 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1320 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1321 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1322 "LongRun mode [0-3]");
1323 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1324 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1325 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1326 "Current frequency (MHz)");
1327 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1328 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1329 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1330 "Current voltage (mV)");
1331 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1332 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1333 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1334 "Processing performance (%)");
1338 print_transmeta_info(void)
1340 u_int regs[4], nreg = 0;
1342 do_cpuid(0x80860000, regs);
1344 if (nreg >= 0x80860001) {
1345 do_cpuid(0x80860001, regs);
1346 kprintf(" Processor revision %u.%u.%u.%u\n",
1347 (regs[1] >> 24) & 0xff,
1348 (regs[1] >> 16) & 0xff,
1349 (regs[1] >> 8) & 0xff,
1352 if (nreg >= 0x80860002) {
1353 do_cpuid(0x80860002, regs);
1354 kprintf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1355 (regs[1] >> 24) & 0xff,
1356 (regs[1] >> 16) & 0xff,
1357 (regs[1] >> 8) & 0xff,
1361 if (nreg >= 0x80860006) {
1363 do_cpuid(0x80860003, (u_int*) &info[0]);
1364 do_cpuid(0x80860004, (u_int*) &info[16]);
1365 do_cpuid(0x80860005, (u_int*) &info[32]);
1366 do_cpuid(0x80860006, (u_int*) &info[48]);
1368 kprintf(" %s\n", info);
1371 crusoe_longrun = tmx86_get_longrun_mode();
1372 tmx86_get_longrun_status(&crusoe_frequency,
1373 &crusoe_voltage, &crusoe_percentage);
1374 kprintf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1375 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1379 additional_cpu_info(const char *line)
1383 if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1384 additional_cpu_info_ary[i] = line;
1385 ++additional_cpu_info_count;