2 * Copyright (c) 2000 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/pci/agp_amd.c,v 1.3.2.4 2002/04/25 23:41:36 cokane Exp $
27 * $DragonFly: src/sys/dev/agp/agp_amd.c,v 1.4 2003/12/09 19:40:56 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
36 #include <sys/kernel.h>
40 #include <bus/pci/pcivar.h>
41 #include <bus/pci/pcireg.h>
46 #include <vm/vm_object.h>
48 #include <machine/clock.h>
49 #include <machine/bus.h>
50 #include <machine/resource.h>
53 MALLOC_DECLARE(M_AGP);
55 #define READ2(off) bus_space_read_2(sc->bst, sc->bsh, off)
56 #define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off)
57 #define WRITE2(off,v) bus_space_write_2(sc->bst, sc->bsh, off, v)
58 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v)
62 u_int32_t *ag_virtual; /* virtual address of gatt */
63 vm_offset_t ag_physical;
64 u_int32_t *ag_vdir; /* virtual address of page dir */
65 vm_offset_t ag_pdir; /* physical address of page dir */
68 struct agp_amd_softc {
70 struct resource *regs; /* memory mapped control registers */
71 bus_space_tag_t bst; /* bus_space tag */
72 bus_space_handle_t bsh; /* bus_space handle */
73 u_int32_t initial_aperture; /* aperture size at startup */
74 struct agp_amd_gatt *gatt;
77 static struct agp_amd_gatt *
78 agp_amd_alloc_gatt(device_t dev)
80 u_int32_t apsize = AGP_GET_APERTURE(dev);
81 u_int32_t entries = apsize >> AGP_PAGE_SHIFT;
82 struct agp_amd_gatt *gatt;
83 int i, npages, pdir_offset;
87 "allocating GATT for aperture of size %dM\n",
88 apsize / (1024*1024));
90 gatt = malloc(sizeof(struct agp_amd_gatt), M_AGP, M_NOWAIT);
95 * The AMD751 uses a page directory to map a non-contiguous
96 * gatt so we don't need to use contigmalloc.
97 * Malloc individual gatt pages and map them into the page
100 gatt->ag_entries = entries;
101 gatt->ag_virtual = malloc(entries * sizeof(u_int32_t),
103 if (!gatt->ag_virtual) {
105 device_printf(dev, "allocation failed\n");
109 bzero(gatt->ag_virtual, entries * sizeof(u_int32_t));
112 * Allocate the page directory.
114 gatt->ag_vdir = malloc(AGP_PAGE_SIZE, M_AGP, M_NOWAIT);
116 if (!gatt->ag_vdir) {
119 "failed to allocate page directory\n");
120 free(gatt->ag_virtual, M_AGP);
124 bzero(gatt->ag_vdir, AGP_PAGE_SIZE);
125 gatt->ag_pdir = vtophys((vm_offset_t) gatt->ag_vdir);
127 device_printf(dev, "gatt -> ag_pdir %8x\n",
128 (vm_offset_t)gatt->ag_pdir);
130 * Allocate the gatt pages
132 gatt->ag_entries = entries;
134 device_printf(dev, "allocating GATT for %d AGP page entries\n",
136 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
139 * Map the pages of the GATT into the page directory.
141 * The GATT page addresses are mapped into the directory offset by
142 * an amount dependent on the base address of the aperture. This
143 * is and offset into the page directory, not an offset added to
144 * the addresses of the gatt pages.
147 pdir_offset = pci_read_config(dev, AGP_AMD751_APBASE, 4) >> 22;
149 npages = ((entries * sizeof(u_int32_t) + AGP_PAGE_SIZE - 1)
152 for (i = 0; i < npages; i++) {
156 va = ((vm_offset_t) gatt->ag_virtual) + i * AGP_PAGE_SIZE;
158 gatt->ag_vdir[i + pdir_offset] = pa | 1;
162 * Make sure the chipset can see everything.
170 agp_amd_free_gatt(struct agp_amd_gatt *gatt)
172 free(gatt->ag_virtual, M_AGP);
173 free(gatt->ag_vdir, M_AGP);
178 agp_amd_match(device_t dev)
180 if (pci_get_class(dev) != PCIC_BRIDGE
181 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
184 if (agp_find_caps(dev) == 0)
187 switch (pci_get_devid(dev)) {
190 return ("AMD 751 host to AGP bridge");
193 return ("AMD 761 host to AGP bridge");
196 return ("AMD 762 host to AGP bridge");
204 agp_amd_probe(device_t dev)
208 desc = agp_amd_match(dev);
211 device_set_desc(dev, desc);
219 agp_amd_attach(device_t dev)
221 struct agp_amd_softc *sc = device_get_softc(dev);
222 struct agp_amd_gatt *gatt;
225 error = agp_generic_attach(dev);
229 rid = AGP_AMD751_REGISTERS;
230 sc->regs = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
231 0, ~0, 1, RF_ACTIVE);
233 agp_generic_detach(dev);
237 sc->bst = rman_get_bustag(sc->regs);
238 sc->bsh = rman_get_bushandle(sc->regs);
240 sc->initial_aperture = AGP_GET_APERTURE(dev);
241 if (sc->initial_aperture == 0) {
242 device_printf(dev, "bad initial aperture size, disabling\n");
247 gatt = agp_amd_alloc_gatt(dev);
252 * Probably contigmalloc failure. Try reducing the
253 * aperture so that the gatt size reduces.
255 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
260 /* Install the gatt. */
261 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir);
263 /* Enable synchronisation between host and agp. */
264 pci_write_config(dev,
266 AGP_AMD751_MODECTRL_SYNEN, 1);
268 /* Set indexing mode for two-level and enable page dir cache */
269 pci_write_config(dev,
270 AGP_AMD751_MODECTRL2,
271 AGP_AMD751_MODECTRL2_GPDCE, 1);
273 /* Enable the TLB and flush */
274 WRITE2(AGP_AMD751_STATUS,
275 READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE);
282 agp_amd_detach(device_t dev)
284 struct agp_amd_softc *sc = device_get_softc(dev);
287 error = agp_generic_detach(dev);
291 /* Disable the TLB.. */
292 WRITE2(AGP_AMD751_STATUS,
293 READ2(AGP_AMD751_STATUS) & ~AGP_AMD751_STATUS_GCE);
295 /* Disable host-agp sync */
296 pci_write_config(dev, AGP_AMD751_MODECTRL, 0x00, 1);
298 /* Clear the GATT base */
299 WRITE4(AGP_AMD751_ATTBASE, 0);
301 /* Put the aperture back the way it started. */
302 AGP_SET_APERTURE(dev, sc->initial_aperture);
304 agp_amd_free_gatt(sc->gatt);
306 bus_release_resource(dev, SYS_RES_MEMORY,
307 AGP_AMD751_REGISTERS, sc->regs);
313 agp_amd_get_aperture(device_t dev)
318 * The aperture size is equal to 32M<<vas.
320 vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x06) >> 1;
321 return (32*1024*1024) << vas;
325 agp_amd_set_aperture(device_t dev, u_int32_t aperture)
330 * Check for a power of two and make sure its within the
331 * programmable range.
333 if (aperture & (aperture - 1)
334 || aperture < 32*1024*1024
335 || aperture > 2U*1024*1024*1024)
338 vas = ffs(aperture / 32*1024*1024) - 1;
341 * While the size register is bits 1-3 of APCTRL, bit 0 must be
342 * set for the size value to be 'valid'
344 pci_write_config(dev, AGP_AMD751_APCTRL,
345 (((pci_read_config(dev, AGP_AMD751_APCTRL, 1) & ~0x06)
346 | ((vas << 1) | 1))), 1);
352 agp_amd_bind_page(device_t dev, int offset, vm_offset_t physical)
354 struct agp_amd_softc *sc = device_get_softc(dev);
356 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
359 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 1;
361 /* invalidate the cache */
367 agp_amd_unbind_page(device_t dev, int offset)
369 struct agp_amd_softc *sc = device_get_softc(dev);
371 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
374 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
379 agp_amd_flush_tlb(device_t dev)
381 struct agp_amd_softc *sc = device_get_softc(dev);
383 /* Set the cache invalidate bit and wait for the chipset to clear */
384 WRITE4(AGP_AMD751_TLBCTRL, 1);
387 } while (READ4(AGP_AMD751_TLBCTRL));
390 static device_method_t agp_amd_methods[] = {
391 /* Device interface */
392 DEVMETHOD(device_probe, agp_amd_probe),
393 DEVMETHOD(device_attach, agp_amd_attach),
394 DEVMETHOD(device_detach, agp_amd_detach),
395 DEVMETHOD(device_shutdown, bus_generic_shutdown),
396 DEVMETHOD(device_suspend, bus_generic_suspend),
397 DEVMETHOD(device_resume, bus_generic_resume),
400 DEVMETHOD(agp_get_aperture, agp_amd_get_aperture),
401 DEVMETHOD(agp_set_aperture, agp_amd_set_aperture),
402 DEVMETHOD(agp_bind_page, agp_amd_bind_page),
403 DEVMETHOD(agp_unbind_page, agp_amd_unbind_page),
404 DEVMETHOD(agp_flush_tlb, agp_amd_flush_tlb),
405 DEVMETHOD(agp_enable, agp_generic_enable),
406 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
407 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
408 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
409 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
414 static driver_t agp_amd_driver = {
417 sizeof(struct agp_amd_softc),
420 static devclass_t agp_devclass;
422 DRIVER_MODULE(agp_amd, pci, agp_amd_driver, agp_devclass, 0, 0);
423 MODULE_DEPEND(agp_amd, agp, 1, 1, 1);
424 MODULE_DEPEND(agp_amd, pci, 1, 1, 1);