2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.7 2004/01/06 01:40:50 dillon Exp $
35 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
39 * Winbond fast ethernet PCI NIC driver
41 * Supports various cheap network adapters based on the Winbond W89C840F
42 * fast ethernet controller chip. This includes adapters manufactured by
43 * Winbond itself and some made by Linksys.
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The Winbond W89C840F chip is a bus master; in some ways it resembles
52 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
53 * one major difference which is that while the registers do many of
54 * the same things as a tulip adapter, the offsets are different: where
55 * tulip registers are typically spaced 8 bytes apart, the Winbond
56 * registers are spaced 4 bytes apart. The receiver filter is also
57 * programmed differently.
59 * Like the tulip, the Winbond chip uses small descriptors containing
60 * a status word, a control word and 32-bit areas that can either be used
61 * to point to two external data blocks, or to point to a single block
62 * and another descriptor in a linked list. Descriptors can be grouped
63 * together in blocks to form fixed length rings or can be chained
64 * together in linked lists. A single packet may be spread out over
65 * several descriptors if necessary.
67 * For the receive ring, this driver uses a linked list of descriptors,
68 * each pointing to a single mbuf cluster buffer, which us large enough
69 * to hold an entire packet. The link list is looped back to created a
72 * For transmission, the driver creates a linked list of 'super descriptors'
73 * which each contain several individual descriptors linked toghether.
74 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
75 * abuse as fragment pointers. This allows us to use a buffer managment
76 * scheme very similar to that used in the ThunderLAN and Etherlink XL
79 * Autonegotiation is performed using the external PHY via the MII bus.
80 * The sample boards I have all use a Davicom PHY.
82 * Note: the author of the Linux driver for the Winbond chip alludes
83 * to some sort of flaw in the chip's design that seems to mandate some
84 * drastic workaround which signigicantly impairs transmit performance.
85 * I have no idea what he's on about: transmit performance with all
86 * three of my test boards seems fine.
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
98 #include <sys/queue.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
108 #include <vm/vm.h> /* for vtophys */
109 #include <vm/pmap.h> /* for vtophys */
110 #include <machine/clock.h> /* for DELAY */
111 #include <machine/bus_memio.h>
112 #include <machine/bus_pio.h>
113 #include <machine/bus.h>
114 #include <machine/resource.h>
116 #include <sys/rman.h>
118 #include <bus/pci/pcireg.h>
119 #include <bus/pci/pcivar.h>
121 #include "../mii_layer/mii.h"
122 #include "../mii_layer/miivar.h"
124 /* "controller miibus0" required. See GENERIC if you get errors here. */
125 #include "miibus_if.h"
127 #define WB_USEIOSPACE
129 #include "if_wbreg.h"
132 * Various supported device vendors/types and their names.
134 static struct wb_type wb_devs[] = {
135 { WB_VENDORID, WB_DEVICEID_840F,
136 "Winbond W89C840F 10/100BaseTX" },
137 { CP_VENDORID, CP_DEVICEID_RL100,
138 "Compex RL100-ATX 10/100baseTX" },
142 static int wb_probe (device_t);
143 static int wb_attach (device_t);
144 static int wb_detach (device_t);
146 static void wb_bfree (caddr_t, u_int);
147 static int wb_newbuf (struct wb_softc *,
148 struct wb_chain_onefrag *,
150 static int wb_encap (struct wb_softc *, struct wb_chain *,
153 static void wb_rxeof (struct wb_softc *);
154 static void wb_rxeoc (struct wb_softc *);
155 static void wb_txeof (struct wb_softc *);
156 static void wb_txeoc (struct wb_softc *);
157 static void wb_intr (void *);
158 static void wb_tick (void *);
159 static void wb_start (struct ifnet *);
160 static int wb_ioctl (struct ifnet *, u_long, caddr_t);
161 static void wb_init (void *);
162 static void wb_stop (struct wb_softc *);
163 static void wb_watchdog (struct ifnet *);
164 static void wb_shutdown (device_t);
165 static int wb_ifmedia_upd (struct ifnet *);
166 static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *);
168 static void wb_eeprom_putbyte (struct wb_softc *, int);
169 static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *);
170 static void wb_read_eeprom (struct wb_softc *, caddr_t, int,
172 static void wb_mii_sync (struct wb_softc *);
173 static void wb_mii_send (struct wb_softc *, u_int32_t, int);
174 static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *);
175 static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *);
177 static void wb_setcfg (struct wb_softc *, u_int32_t);
178 static u_int8_t wb_calchash (caddr_t);
179 static void wb_setmulti (struct wb_softc *);
180 static void wb_reset (struct wb_softc *);
181 static void wb_fixmedia (struct wb_softc *);
182 static int wb_list_rx_init (struct wb_softc *);
183 static int wb_list_tx_init (struct wb_softc *);
185 static int wb_miibus_readreg (device_t, int, int);
186 static int wb_miibus_writereg (device_t, int, int, int);
187 static void wb_miibus_statchg (device_t);
190 #define WB_RES SYS_RES_IOPORT
191 #define WB_RID WB_PCI_LOIO
193 #define WB_RES SYS_RES_MEMORY
194 #define WB_RID WB_PCI_LOMEM
197 static device_method_t wb_methods[] = {
198 /* Device interface */
199 DEVMETHOD(device_probe, wb_probe),
200 DEVMETHOD(device_attach, wb_attach),
201 DEVMETHOD(device_detach, wb_detach),
202 DEVMETHOD(device_shutdown, wb_shutdown),
204 /* bus interface, for miibus */
205 DEVMETHOD(bus_print_child, bus_generic_print_child),
206 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
209 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
210 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
211 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
215 static driver_t wb_driver = {
218 sizeof(struct wb_softc)
221 static devclass_t wb_devclass;
223 DECLARE_DUMMY_MODULE(if_wb);
224 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
225 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
227 #define WB_SETBIT(sc, reg, x) \
228 CSR_WRITE_4(sc, reg, \
229 CSR_READ_4(sc, reg) | x)
231 #define WB_CLRBIT(sc, reg, x) \
232 CSR_WRITE_4(sc, reg, \
233 CSR_READ_4(sc, reg) & ~x)
236 CSR_WRITE_4(sc, WB_SIO, \
237 CSR_READ_4(sc, WB_SIO) | x)
240 CSR_WRITE_4(sc, WB_SIO, \
241 CSR_READ_4(sc, WB_SIO) & ~x)
244 * Send a read command and address to the EEPROM, check for ACK.
246 static void wb_eeprom_putbyte(sc, addr)
252 d = addr | WB_EECMD_READ;
255 * Feed in each bit and stobe the clock.
257 for (i = 0x400; i; i >>= 1) {
259 SIO_SET(WB_SIO_EE_DATAIN);
261 SIO_CLR(WB_SIO_EE_DATAIN);
264 SIO_SET(WB_SIO_EE_CLK);
266 SIO_CLR(WB_SIO_EE_CLK);
274 * Read a word of data stored in the EEPROM at address 'addr.'
276 static void wb_eeprom_getword(sc, addr, dest)
284 /* Enter EEPROM access mode. */
285 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
288 * Send address of word we want to read.
290 wb_eeprom_putbyte(sc, addr);
292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
295 * Start reading bits from EEPROM.
297 for (i = 0x8000; i; i >>= 1) {
298 SIO_SET(WB_SIO_EE_CLK);
300 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
302 SIO_CLR(WB_SIO_EE_CLK);
306 /* Turn off EEPROM access mode. */
307 CSR_WRITE_4(sc, WB_SIO, 0);
315 * Read a sequence of words from the EEPROM.
317 static void wb_read_eeprom(sc, dest, off, cnt, swap)
325 u_int16_t word = 0, *ptr;
327 for (i = 0; i < cnt; i++) {
328 wb_eeprom_getword(sc, off + i, &word);
329 ptr = (u_int16_t *)(dest + (i * 2));
340 * Sync the PHYs by setting data bit and strobing the clock 32 times.
342 static void wb_mii_sync(sc)
347 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
349 for (i = 0; i < 32; i++) {
350 SIO_SET(WB_SIO_MII_CLK);
352 SIO_CLR(WB_SIO_MII_CLK);
360 * Clock a series of bits through the MII.
362 static void wb_mii_send(sc, bits, cnt)
369 SIO_CLR(WB_SIO_MII_CLK);
371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
373 SIO_SET(WB_SIO_MII_DATAIN);
375 SIO_CLR(WB_SIO_MII_DATAIN);
378 SIO_CLR(WB_SIO_MII_CLK);
380 SIO_SET(WB_SIO_MII_CLK);
385 * Read an PHY register through the MII.
387 static int wb_mii_readreg(sc, frame)
389 struct wb_mii_frame *frame;
397 * Set up frame for RX.
399 frame->mii_stdelim = WB_MII_STARTDELIM;
400 frame->mii_opcode = WB_MII_READOP;
401 frame->mii_turnaround = 0;
404 CSR_WRITE_4(sc, WB_SIO, 0);
409 SIO_SET(WB_SIO_MII_DIR);
414 * Send command/address info.
416 wb_mii_send(sc, frame->mii_stdelim, 2);
417 wb_mii_send(sc, frame->mii_opcode, 2);
418 wb_mii_send(sc, frame->mii_phyaddr, 5);
419 wb_mii_send(sc, frame->mii_regaddr, 5);
422 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
424 SIO_SET(WB_SIO_MII_CLK);
428 SIO_CLR(WB_SIO_MII_DIR);
430 SIO_CLR(WB_SIO_MII_CLK);
432 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
433 SIO_SET(WB_SIO_MII_CLK);
435 SIO_CLR(WB_SIO_MII_CLK);
437 SIO_SET(WB_SIO_MII_CLK);
441 * Now try reading data bits. If the ack failed, we still
442 * need to clock through 16 cycles to keep the PHY(s) in sync.
445 for(i = 0; i < 16; i++) {
446 SIO_CLR(WB_SIO_MII_CLK);
448 SIO_SET(WB_SIO_MII_CLK);
454 for (i = 0x8000; i; i >>= 1) {
455 SIO_CLR(WB_SIO_MII_CLK);
458 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
459 frame->mii_data |= i;
462 SIO_SET(WB_SIO_MII_CLK);
468 SIO_CLR(WB_SIO_MII_CLK);
470 SIO_SET(WB_SIO_MII_CLK);
481 * Write to a PHY register through the MII.
483 static int wb_mii_writereg(sc, frame)
485 struct wb_mii_frame *frame;
492 * Set up frame for TX.
495 frame->mii_stdelim = WB_MII_STARTDELIM;
496 frame->mii_opcode = WB_MII_WRITEOP;
497 frame->mii_turnaround = WB_MII_TURNAROUND;
500 * Turn on data output.
502 SIO_SET(WB_SIO_MII_DIR);
506 wb_mii_send(sc, frame->mii_stdelim, 2);
507 wb_mii_send(sc, frame->mii_opcode, 2);
508 wb_mii_send(sc, frame->mii_phyaddr, 5);
509 wb_mii_send(sc, frame->mii_regaddr, 5);
510 wb_mii_send(sc, frame->mii_turnaround, 2);
511 wb_mii_send(sc, frame->mii_data, 16);
514 SIO_SET(WB_SIO_MII_CLK);
516 SIO_CLR(WB_SIO_MII_CLK);
522 SIO_CLR(WB_SIO_MII_DIR);
529 static int wb_miibus_readreg(dev, phy, reg)
534 struct wb_mii_frame frame;
536 sc = device_get_softc(dev);
538 bzero((char *)&frame, sizeof(frame));
540 frame.mii_phyaddr = phy;
541 frame.mii_regaddr = reg;
542 wb_mii_readreg(sc, &frame);
544 return(frame.mii_data);
547 static int wb_miibus_writereg(dev, phy, reg, data)
552 struct wb_mii_frame frame;
554 sc = device_get_softc(dev);
556 bzero((char *)&frame, sizeof(frame));
558 frame.mii_phyaddr = phy;
559 frame.mii_regaddr = reg;
560 frame.mii_data = data;
562 wb_mii_writereg(sc, &frame);
567 static void wb_miibus_statchg(dev)
571 struct mii_data *mii;
573 sc = device_get_softc(dev);
574 mii = device_get_softc(sc->wb_miibus);
575 wb_setcfg(sc, mii->mii_media_active);
580 static u_int8_t wb_calchash(addr)
583 u_int32_t crc, carry;
587 /* Compute CRC for the address value. */
588 crc = 0xFFFFFFFF; /* initial value */
590 for (i = 0; i < 6; i++) {
592 for (j = 0; j < 8; j++) {
593 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
597 crc = (crc ^ 0x04c11db6) | carry;
602 * return the filter bit position
603 * Note: I arrived at the following nonsense
604 * through experimentation. It's not the usual way to
605 * generate the bit position but it's the only thing
606 * I could come up with that works.
608 return(~(crc >> 26) & 0x0000003F);
612 * Program the 64-bit multicast hash filter.
614 static void wb_setmulti(sc)
619 u_int32_t hashes[2] = { 0, 0 };
620 struct ifmultiaddr *ifma;
624 ifp = &sc->arpcom.ac_if;
626 rxfilt = CSR_READ_4(sc, WB_NETCFG);
628 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
629 rxfilt |= WB_NETCFG_RX_MULTI;
630 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
631 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
632 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
636 /* first, zot all the existing hash bits */
637 CSR_WRITE_4(sc, WB_MAR0, 0);
638 CSR_WRITE_4(sc, WB_MAR1, 0);
640 /* now program new ones */
641 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
642 ifma = ifma->ifma_link.le_next) {
643 if (ifma->ifma_addr->sa_family != AF_LINK)
645 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
647 hashes[0] |= (1 << h);
649 hashes[1] |= (1 << (h - 32));
654 rxfilt |= WB_NETCFG_RX_MULTI;
656 rxfilt &= ~WB_NETCFG_RX_MULTI;
658 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
659 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
660 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
666 * The Winbond manual states that in order to fiddle with the
667 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
668 * first have to put the transmit and/or receive logic in the idle state.
670 static void wb_setcfg(sc, media)
676 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
678 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
680 for (i = 0; i < WB_TIMEOUT; i++) {
682 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
683 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
688 printf("wb%d: failed to force tx and "
689 "rx to idle state\n", sc->wb_unit);
692 if (IFM_SUBTYPE(media) == IFM_10_T)
693 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
695 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
697 if ((media & IFM_GMASK) == IFM_FDX)
698 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
703 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
708 static void wb_reset(sc)
712 struct mii_data *mii;
714 CSR_WRITE_4(sc, WB_NETCFG, 0);
715 CSR_WRITE_4(sc, WB_BUSCTL, 0);
716 CSR_WRITE_4(sc, WB_TXADDR, 0);
717 CSR_WRITE_4(sc, WB_RXADDR, 0);
719 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
720 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
722 for (i = 0; i < WB_TIMEOUT; i++) {
724 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
728 printf("wb%d: reset never completed!\n", sc->wb_unit);
730 /* Wait a little while for the chip to get its brains in order. */
733 if (sc->wb_miibus == NULL)
736 mii = device_get_softc(sc->wb_miibus);
740 if (mii->mii_instance) {
741 struct mii_softc *miisc;
742 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
743 miisc = LIST_NEXT(miisc, mii_list))
744 mii_phy_reset(miisc);
750 static void wb_fixmedia(sc)
753 struct mii_data *mii = NULL;
757 if (sc->wb_miibus == NULL)
760 mii = device_get_softc(sc->wb_miibus);
761 ifp = &sc->arpcom.ac_if;
764 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
765 media = mii->mii_media_active & ~IFM_10_T;
767 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
768 media = mii->mii_media_active & ~IFM_100_TX;
773 ifmedia_set(&mii->mii_media, media);
779 * Probe for a Winbond chip. Check the PCI vendor and device
780 * IDs against our list and return a device name if we find a match.
782 static int wb_probe(dev)
789 while(t->wb_name != NULL) {
790 if ((pci_get_vendor(dev) == t->wb_vid) &&
791 (pci_get_device(dev) == t->wb_did)) {
792 device_set_desc(dev, t->wb_name);
802 * Attach the interface. Allocate softc structures, do ifmedia
803 * setup and ethernet/BPF attach.
805 static int wb_attach(dev)
809 u_char eaddr[ETHER_ADDR_LEN];
813 int unit, error = 0, rid;
817 sc = device_get_softc(dev);
818 unit = device_get_unit(dev);
821 * Handle power management nonsense.
824 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
825 if (command == 0x01) {
827 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
828 if (command & WB_PSTATE_MASK) {
829 u_int32_t iobase, membase, irq;
831 /* Save important PCI config data. */
832 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
833 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
834 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
836 /* Reset the power state. */
837 printf("wb%d: chip is in D%d power mode "
838 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
839 command &= 0xFFFFFFFC;
840 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
842 /* Restore PCI config data. */
843 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
844 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
845 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
850 * Map control/status registers.
852 command = pci_read_config(dev, PCIR_COMMAND, 4);
853 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
854 pci_write_config(dev, PCIR_COMMAND, command, 4);
855 command = pci_read_config(dev, PCIR_COMMAND, 4);
858 if (!(command & PCIM_CMD_PORTEN)) {
859 printf("wb%d: failed to enable I/O ports!\n", unit);
864 if (!(command & PCIM_CMD_MEMEN)) {
865 printf("wb%d: failed to enable memory mapping!\n", unit);
872 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
873 0, ~0, 1, RF_ACTIVE);
875 if (sc->wb_res == NULL) {
876 printf("wb%d: couldn't map ports/memory\n", unit);
881 sc->wb_btag = rman_get_bustag(sc->wb_res);
882 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
884 /* Allocate interrupt */
886 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
887 RF_SHAREABLE | RF_ACTIVE);
889 if (sc->wb_irq == NULL) {
890 printf("wb%d: couldn't map interrupt\n", unit);
891 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
896 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
897 wb_intr, sc, &sc->wb_intrhand);
900 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
901 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
902 printf("wb%d: couldn't set up irq\n", unit);
906 /* Save the cache line size. */
907 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
909 /* Reset the adapter. */
913 * Get station address from the EEPROM.
915 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
918 * A Winbond chip was detected. Inform the world.
920 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":");
923 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
925 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
926 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
928 if (sc->wb_ldata == NULL) {
929 printf("wb%d: no memory for list buffers!\n", unit);
930 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
931 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
932 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
937 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
939 ifp = &sc->arpcom.ac_if;
941 if_initname(ifp, "wb", unit);
942 ifp->if_mtu = ETHERMTU;
943 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
944 ifp->if_ioctl = wb_ioctl;
945 ifp->if_output = ether_output;
946 ifp->if_start = wb_start;
947 ifp->if_watchdog = wb_watchdog;
948 ifp->if_init = wb_init;
949 ifp->if_baudrate = 10000000;
950 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
955 if (mii_phy_probe(dev, &sc->wb_miibus,
956 wb_ifmedia_upd, wb_ifmedia_sts)) {
957 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
959 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
961 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
967 * Call MI attach routine.
969 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
973 device_delete_child(dev, sc->wb_miibus);
979 static int wb_detach(dev)
988 sc = device_get_softc(dev);
989 ifp = &sc->arpcom.ac_if;
992 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
994 /* Delete any miibus and phy devices attached to this interface */
995 bus_generic_detach(dev);
996 device_delete_child(dev, sc->wb_miibus);
998 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1000 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1002 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
1011 * Initialize the transmit descriptors.
1013 static int wb_list_tx_init(sc)
1014 struct wb_softc *sc;
1016 struct wb_chain_data *cd;
1017 struct wb_list_data *ld;
1023 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1024 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1025 if (i == (WB_TX_LIST_CNT - 1)) {
1026 cd->wb_tx_chain[i].wb_nextdesc =
1027 &cd->wb_tx_chain[0];
1029 cd->wb_tx_chain[i].wb_nextdesc =
1030 &cd->wb_tx_chain[i + 1];
1034 cd->wb_tx_free = &cd->wb_tx_chain[0];
1035 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1042 * Initialize the RX descriptors and allocate mbufs for them. Note that
1043 * we arrange the descriptors in a closed ring, so that the last descriptor
1044 * points back to the first.
1046 static int wb_list_rx_init(sc)
1047 struct wb_softc *sc;
1049 struct wb_chain_data *cd;
1050 struct wb_list_data *ld;
1056 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1057 cd->wb_rx_chain[i].wb_ptr =
1058 (struct wb_desc *)&ld->wb_rx_list[i];
1059 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1060 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1062 if (i == (WB_RX_LIST_CNT - 1)) {
1063 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1064 ld->wb_rx_list[i].wb_next =
1065 vtophys(&ld->wb_rx_list[0]);
1067 cd->wb_rx_chain[i].wb_nextdesc =
1068 &cd->wb_rx_chain[i + 1];
1069 ld->wb_rx_list[i].wb_next =
1070 vtophys(&ld->wb_rx_list[i + 1]);
1074 cd->wb_rx_head = &cd->wb_rx_chain[0];
1079 static void wb_bfree(buf, size)
1087 * Initialize an RX descriptor and attach an MBUF cluster.
1089 static int wb_newbuf(sc, c, m)
1090 struct wb_softc *sc;
1091 struct wb_chain_onefrag *c;
1094 struct mbuf *m_new = NULL;
1097 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1101 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
1102 m_new->m_flags |= M_EXT;
1103 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1104 m_new->m_len = WB_BUFBYTES;
1105 m_new->m_ext.ext_free = wb_bfree;
1106 m_new->m_ext.ext_ref = wb_bfree;
1109 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1110 m_new->m_data = m_new->m_ext.ext_buf;
1113 m_adj(m_new, sizeof(u_int64_t));
1116 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1117 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1118 c->wb_ptr->wb_status = WB_RXSTAT;
1124 * A frame has been uploaded: pass the resulting mbuf chain up to
1125 * the higher level protocols.
1127 static void wb_rxeof(sc)
1128 struct wb_softc *sc;
1130 struct ether_header *eh;
1131 struct mbuf *m = NULL;
1133 struct wb_chain_onefrag *cur_rx;
1137 ifp = &sc->arpcom.ac_if;
1139 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1141 struct mbuf *m0 = NULL;
1143 cur_rx = sc->wb_cdata.wb_rx_head;
1144 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1146 m = cur_rx->wb_mbuf;
1148 if ((rxstat & WB_RXSTAT_MIIERR) ||
1149 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1150 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1151 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1152 !(rxstat & WB_RXSTAT_RXCMP)) {
1154 wb_newbuf(sc, cur_rx, m);
1155 printf("wb%x: receiver babbling: possible chip "
1156 "bug, forcing reset\n", sc->wb_unit);
1163 if (rxstat & WB_RXSTAT_RXERR) {
1165 wb_newbuf(sc, cur_rx, m);
1169 /* No errors; receive the packet. */
1170 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1173 * XXX The Winbond chip includes the CRC with every
1174 * received frame, and there's no way to turn this
1175 * behavior off (at least, I can't find anything in
1176 * the manual that explains how to do it) so we have
1177 * to trim off the CRC manually.
1179 total_len -= ETHER_CRC_LEN;
1181 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1182 total_len + ETHER_ALIGN, 0, ifp, NULL);
1183 wb_newbuf(sc, cur_rx, m);
1188 m_adj(m0, ETHER_ALIGN);
1192 eh = mtod(m, struct ether_header *);
1194 /* Remove header from mbuf and pass it on. */
1195 m_adj(m, sizeof(struct ether_header));
1196 ether_input(ifp, eh, m);
1201 struct wb_softc *sc;
1205 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1206 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1207 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1208 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1209 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1215 * A frame was downloaded to the chip. It's safe for us to clean up
1218 static void wb_txeof(sc)
1219 struct wb_softc *sc;
1221 struct wb_chain *cur_tx;
1224 ifp = &sc->arpcom.ac_if;
1226 /* Clear the timeout timer. */
1229 if (sc->wb_cdata.wb_tx_head == NULL)
1233 * Go through our tx list and free mbufs for those
1234 * frames that have been transmitted.
1236 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1239 cur_tx = sc->wb_cdata.wb_tx_head;
1240 txstat = WB_TXSTATUS(cur_tx);
1242 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1245 if (txstat & WB_TXSTAT_TXERR) {
1247 if (txstat & WB_TXSTAT_ABORT)
1248 ifp->if_collisions++;
1249 if (txstat & WB_TXSTAT_LATECOLL)
1250 ifp->if_collisions++;
1253 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1256 m_freem(cur_tx->wb_mbuf);
1257 cur_tx->wb_mbuf = NULL;
1259 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1260 sc->wb_cdata.wb_tx_head = NULL;
1261 sc->wb_cdata.wb_tx_tail = NULL;
1265 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1272 * TX 'end of channel' interrupt handler.
1274 static void wb_txeoc(sc)
1275 struct wb_softc *sc;
1279 ifp = &sc->arpcom.ac_if;
1283 if (sc->wb_cdata.wb_tx_head == NULL) {
1284 ifp->if_flags &= ~IFF_OACTIVE;
1285 sc->wb_cdata.wb_tx_tail = NULL;
1287 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1288 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1290 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1297 static void wb_intr(arg)
1300 struct wb_softc *sc;
1305 ifp = &sc->arpcom.ac_if;
1307 if (!(ifp->if_flags & IFF_UP))
1310 /* Disable interrupts. */
1311 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1315 status = CSR_READ_4(sc, WB_ISR);
1317 CSR_WRITE_4(sc, WB_ISR, status);
1319 if ((status & WB_INTRS) == 0)
1322 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1325 if (status & WB_ISR_RX_ERR)
1331 if (status & WB_ISR_RX_OK)
1334 if (status & WB_ISR_RX_IDLE)
1337 if (status & WB_ISR_TX_OK)
1340 if (status & WB_ISR_TX_NOBUF)
1343 if (status & WB_ISR_TX_IDLE) {
1345 if (sc->wb_cdata.wb_tx_head != NULL) {
1346 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1347 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1351 if (status & WB_ISR_TX_UNDERRUN) {
1354 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1355 /* Jack up TX threshold */
1356 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1357 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1358 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1359 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1362 if (status & WB_ISR_BUS_ERR) {
1369 /* Re-enable interrupts. */
1370 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1372 if (ifp->if_snd.ifq_head != NULL) {
1379 static void wb_tick(xsc)
1382 struct wb_softc *sc;
1383 struct mii_data *mii;
1389 mii = device_get_softc(sc->wb_miibus);
1393 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1401 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1402 * pointers to the fragment pointers.
1404 static int wb_encap(sc, c, m_head)
1405 struct wb_softc *sc;
1407 struct mbuf *m_head;
1410 struct wb_desc *f = NULL;
1415 * Start packing the mbufs in this chain into
1416 * the fragment pointers. Stop when we run out
1417 * of fragments or hit the end of the mbuf chain.
1422 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1423 if (m->m_len != 0) {
1424 if (frag == WB_MAXFRAGS)
1426 total_len += m->m_len;
1427 f = &c->wb_ptr->wb_frag[frag];
1428 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1430 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1433 f->wb_status = WB_TXSTAT_OWN;
1434 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1435 f->wb_data = vtophys(mtod(m, vm_offset_t));
1441 * Handle special case: we used up all 16 fragments,
1442 * but we have more mbufs left in the chain. Copy the
1443 * data into an mbuf cluster. Note that we don't
1444 * bother clearing the values in the other fragment
1445 * pointers/counters; it wouldn't gain us anything,
1446 * and would waste cycles.
1449 struct mbuf *m_new = NULL;
1451 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1454 if (m_head->m_pkthdr.len > MHLEN) {
1455 MCLGET(m_new, M_DONTWAIT);
1456 if (!(m_new->m_flags & M_EXT)) {
1461 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1462 mtod(m_new, caddr_t));
1463 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1466 f = &c->wb_ptr->wb_frag[0];
1468 f->wb_data = vtophys(mtod(m_new, caddr_t));
1469 f->wb_ctl = total_len = m_new->m_len;
1470 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1474 if (total_len < WB_MIN_FRAMELEN) {
1475 f = &c->wb_ptr->wb_frag[frag];
1476 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1477 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1478 f->wb_ctl |= WB_TXCTL_TLINK;
1479 f->wb_status = WB_TXSTAT_OWN;
1483 c->wb_mbuf = m_head;
1484 c->wb_lastdesc = frag - 1;
1485 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1486 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1492 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1493 * to the mbuf data regions directly in the transmit lists. We also save a
1494 * copy of the pointers since the transmit list fragment pointers are
1495 * physical addresses.
1498 static void wb_start(ifp)
1501 struct wb_softc *sc;
1502 struct mbuf *m_head = NULL;
1503 struct wb_chain *cur_tx = NULL, *start_tx;
1508 * Check for an available queue slot. If there are none,
1511 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1512 ifp->if_flags |= IFF_OACTIVE;
1516 start_tx = sc->wb_cdata.wb_tx_free;
1518 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1519 IF_DEQUEUE(&ifp->if_snd, m_head);
1523 /* Pick a descriptor off the free list. */
1524 cur_tx = sc->wb_cdata.wb_tx_free;
1525 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1527 /* Pack the data into the descriptor. */
1528 wb_encap(sc, cur_tx, m_head);
1530 if (cur_tx != start_tx)
1531 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1534 * If there's a BPF listener, bounce a copy of this frame
1538 bpf_mtap(ifp, cur_tx->wb_mbuf);
1542 * If there are no packets queued, bail.
1548 * Place the request for the upload interrupt
1549 * in the last descriptor in the chain. This way, if
1550 * we're chaining several packets at once, we'll only
1551 * get an interupt once for the whole chain rather than
1552 * once for each packet.
1554 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1555 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1556 sc->wb_cdata.wb_tx_tail = cur_tx;
1558 if (sc->wb_cdata.wb_tx_head == NULL) {
1559 sc->wb_cdata.wb_tx_head = start_tx;
1560 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1561 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1564 * We need to distinguish between the case where
1565 * the own bit is clear because the chip cleared it
1566 * and where the own bit is clear because we haven't
1567 * set it yet. The magic value WB_UNSET is just some
1568 * ramdomly chosen number which doesn't have the own
1569 * bit set. When we actually transmit the frame, the
1570 * status word will have _only_ the own bit set, so
1571 * the txeoc handler will be able to tell if it needs
1572 * to initiate another transmission to flush out pending
1575 WB_TXOWN(start_tx) = WB_UNSENT;
1579 * Set a timeout in case the chip goes out to lunch.
1586 static void wb_init(xsc)
1589 struct wb_softc *sc = xsc;
1590 struct ifnet *ifp = &sc->arpcom.ac_if;
1592 struct mii_data *mii;
1596 mii = device_get_softc(sc->wb_miibus);
1599 * Cancel pending I/O and free all RX/TX buffers.
1604 sc->wb_txthresh = WB_TXTHRESH_INIT;
1607 * Set cache alignment and burst length.
1610 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1612 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1615 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1616 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1617 switch(sc->wb_cachesize) {
1619 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1622 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1625 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1629 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1633 /* This doesn't tend to work too well at 100Mbps. */
1634 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1636 /* Init our MAC address */
1637 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1638 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1641 /* Init circular RX list. */
1642 if (wb_list_rx_init(sc) == ENOBUFS) {
1643 printf("wb%d: initialization failed: no "
1644 "memory for rx buffers\n", sc->wb_unit);
1650 /* Init TX descriptors. */
1651 wb_list_tx_init(sc);
1653 /* If we want promiscuous mode, set the allframes bit. */
1654 if (ifp->if_flags & IFF_PROMISC) {
1655 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1657 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1661 * Set capture broadcast bit to capture broadcast frames.
1663 if (ifp->if_flags & IFF_BROADCAST) {
1664 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1666 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1670 * Program the multicast filter, if necessary.
1675 * Load the address of the RX list.
1677 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1678 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1681 * Enable interrupts.
1683 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1684 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1686 /* Enable receiver and transmitter. */
1687 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1688 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1690 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1691 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1692 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1696 ifp->if_flags |= IFF_RUNNING;
1697 ifp->if_flags &= ~IFF_OACTIVE;
1701 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1707 * Set media options.
1709 static int wb_ifmedia_upd(ifp)
1712 struct wb_softc *sc;
1716 if (ifp->if_flags & IFF_UP)
1723 * Report current media status.
1725 static void wb_ifmedia_sts(ifp, ifmr)
1727 struct ifmediareq *ifmr;
1729 struct wb_softc *sc;
1730 struct mii_data *mii;
1734 mii = device_get_softc(sc->wb_miibus);
1737 ifmr->ifm_active = mii->mii_media_active;
1738 ifmr->ifm_status = mii->mii_media_status;
1743 static int wb_ioctl(ifp, command, data)
1748 struct wb_softc *sc = ifp->if_softc;
1749 struct mii_data *mii;
1750 struct ifreq *ifr = (struct ifreq *) data;
1759 error = ether_ioctl(ifp, command, data);
1762 if (ifp->if_flags & IFF_UP) {
1765 if (ifp->if_flags & IFF_RUNNING)
1777 mii = device_get_softc(sc->wb_miibus);
1778 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1790 static void wb_watchdog(ifp)
1793 struct wb_softc *sc;
1798 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1800 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1801 printf("wb%d: no carrier - transceiver cable problem?\n",
1808 if (ifp->if_snd.ifq_head != NULL)
1815 * Stop the adapter and free any mbufs allocated to the
1818 static void wb_stop(sc)
1819 struct wb_softc *sc;
1824 ifp = &sc->arpcom.ac_if;
1827 untimeout(wb_tick, sc, sc->wb_stat_ch);
1829 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1830 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1831 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1832 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1835 * Free data in the RX lists.
1837 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1838 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1839 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1840 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1843 bzero((char *)&sc->wb_ldata->wb_rx_list,
1844 sizeof(sc->wb_ldata->wb_rx_list));
1847 * Free the TX list buffers.
1849 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1850 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1851 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1852 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1856 bzero((char *)&sc->wb_ldata->wb_tx_list,
1857 sizeof(sc->wb_ldata->wb_tx_list));
1859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1865 * Stop all chip I/O so that the kernel's probe routines don't
1866 * get confused by errant DMAs when rebooting.
1868 static void wb_shutdown(dev)
1871 struct wb_softc *sc;
1873 sc = device_get_softc(dev);