2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: src/sys/dev/ath/ath_hal/ah_internal.h,v 1.2.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
19 #ifndef _ATH_AH_INTERAL_H_
20 #define _ATH_AH_INTERAL_H_
22 * Atheros Device Hardware Access Layer (HAL).
24 * Internal definitions.
27 #define AH_MIN(a,b) ((a)<(b)?(a):(b))
28 #define AH_MAX(a,b) ((a)>(b)?(a):(b))
31 #define NBBY 8 /* number of bits/byte */
35 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
38 #define howmany(x, y) (((x)+((y)-1))/(y))
42 #define offsetof(type, field) ((size_t)(&((type *)0)->field))
46 uint16_t start; /* first register */
47 uint16_t end; /* ending register or zero */
51 * Transmit power scale factor.
53 * NB: This is not public because we want to discourage the use of
54 * scaling; folks should use the tx power limit interface.
57 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
58 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
59 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
60 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
61 HAL_TP_SCALE_MIN = 4, /* min, but still on */
65 HAL_CAP_RADAR = 0, /* Radar capability */
66 HAL_CAP_AR = 1, /* AR capability */
70 * Each chip or class of chips registers to offer support.
74 const char *(*probe)(uint16_t vendorid, uint16_t devid);
75 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
76 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error);
79 #define AH_CHIP(_name, _probe, _attach) \
80 static struct ath_hal_chip name##_chip = { \
85 OS_DATA_SET(ah_chips, name##_chip)
89 * Each RF backend registers to offer support; this is mostly
90 * used by multi-chip 5212 solutions. Single-chip solutions
91 * have a fixed idea about which RF to use.
95 HAL_BOOL (*probe)(struct ath_hal *ah);
96 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
99 #define AH_RF(_name, _probe, _attach) \
100 static struct ath_hal_rf _name##_rf = { \
101 .name = __STRING(_name), \
105 OS_DATA_SET(ah_rfs, _name##_rf)
108 struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
111 * Internal form of a HAL_CHANNEL. Note that the structure
112 * must be defined such that you can cast references to a
113 * HAL_CHANNEL so don't shuffle the first two members.
116 uint32_t channelFlags;
117 uint16_t channel; /* NB: must be first for casting */
119 int8_t maxRegTxPower;
121 int8_t minTxPower; /* as above... */
123 HAL_BOOL bssSendHere;
126 uint8_t calValid; /* bitmask of cal types */
129 int16_t rawNoiseFloor;
130 int16_t noiseFloorAdjust;
132 uint32_t regDmnFlags; /* Flags for channel use in reg */
133 uint32_t conformanceTestLimit; /* conformance test limit from reg domain */
134 uint16_t mainSpur; /* cached spur value for this cahnnel */
135 } HAL_CHANNEL_INTERNAL;
138 uint32_t halChanSpreadSupport : 1,
139 halSleepAfterBeaconBroken : 1,
140 halCompressSupport : 1,
142 halFastFramesSupport : 1,
143 halChapTuningSupport : 1,
144 halTurboGSupport : 1,
145 halTurboPrimeSupport : 1,
146 halMicAesCcmSupport : 1,
147 halMicCkipSupport : 1,
148 halMicTkipSupport : 1,
149 halTkipMicTxRxKeySupport : 1,
150 halCipherAesCcmSupport : 1,
151 halCipherCkipSupport : 1,
152 halCipherTkipSupport : 1,
155 halBssIdMaskSupport : 1,
156 halMcastKeySrchSupport : 1,
157 halTsfAddSupport : 1,
159 halChanQuarterRate : 1,
161 halRfSilentSupport : 1,
162 halHwPhyCounterSupport : 1,
164 halWowMatchPatternExact : 1,
165 halAutoSleepSupport : 1,
166 halFastCCSupport : 1,
167 halBtCoexSupport : 1;
168 uint32_t halRxStbcSupport : 1,
169 halTxStbcSupport : 1,
172 halRifsRxSupport : 1,
173 halRifsTxSupport : 1,
174 halExtChanDfsSupport : 1,
175 halForcePpmSupport : 1,
176 halEnhancedPmSupport : 1,
177 halMbssidAggrSupport : 1;
178 uint32_t halWirelessModes;
179 uint16_t halTotalQueues;
180 uint16_t halKeyCacheSize;
181 uint16_t halLow5GhzChan, halHigh5GhzChan;
182 uint16_t halLow2GhzChan, halHigh2GhzChan;
183 int halTstampPrecision;
185 uint8_t halTxChainMask;
186 uint8_t halRxChainMask;
187 uint8_t halNumGpioPins;
188 uint8_t halNumAntCfg2GHz;
189 uint8_t halNumAntCfg5GHz;
193 * The ``private area'' follows immediately after the ``public area''
194 * in the data structure returned by ath_hal_attach. Private data are
195 * used by device-independent code such as the regulatory domain support.
196 * In general, code within the HAL should never depend on data in the
197 * public area. Instead any public data needed internally should be
200 * When declaring a device-specific ath_hal data structure this structure
201 * is assumed to at the front; e.g.
203 * struct ath_hal_5212 {
204 * struct ath_hal_private ah_priv;
208 * It might be better to manage the method pointers in this structure
209 * using an indirect pointer to a read-only data structure but this would
210 * disallow class-style method overriding.
212 struct ath_hal_private {
213 struct ath_hal h; /* public area */
215 /* NB: all methods go first to simplify initialization */
216 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
217 uint16_t channelFlags,
218 uint16_t *lowChannel, uint16_t *highChannel);
219 u_int (*ah_getWirelessModes)(struct ath_hal*);
220 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
222 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
224 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
225 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
226 uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
227 HAL_BOOL (*ah_gpioSet)(struct ath_hal *,
228 uint32_t gpio, uint32_t val);
229 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
230 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
231 HAL_CHANNEL *, uint32_t);
232 int16_t (*ah_getNfAdjust)(struct ath_hal *,
233 const HAL_CHANNEL_INTERNAL*);
234 void (*ah_getNoiseFloor)(struct ath_hal *,
237 void *ah_eeprom; /* opaque EEPROM state */
238 uint16_t ah_eeversion; /* EEPROM version */
239 void (*ah_eepromDetach)(struct ath_hal *);
240 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
241 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int);
242 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
243 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
244 const void *args, uint32_t argsize,
245 void **result, uint32_t *resultsize);
248 * Device revision information.
250 uint16_t ah_devid; /* PCI device ID */
251 uint16_t ah_subvendorid; /* PCI subvendor ID */
252 uint32_t ah_macVersion; /* MAC version id */
253 uint16_t ah_macRev; /* MAC revision */
254 uint16_t ah_phyRev; /* PHY revision */
255 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
256 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
259 HAL_OPMODE ah_opmode; /* operating mode from reset */
260 HAL_CAPABILITIES ah_caps; /* device capabilities */
261 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
262 int16_t ah_powerLimit; /* tx power cap */
263 uint16_t ah_maxPowerLevel; /* calculated max tx power */
264 u_int ah_tpScale; /* tx power scale factor */
265 uint32_t ah_11nCompat; /* 11n compat controls */
268 * State for regulatory domain handling.
270 HAL_REG_DOMAIN ah_currentRD; /* Current regulatory domain */
271 HAL_CTRY_CODE ah_countryCode; /* current country code */
272 HAL_CHANNEL_INTERNAL ah_channels[256]; /* calculated channel list */
273 u_int ah_nchan; /* valid channels in list */
274 HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */
276 uint8_t ah_coverageClass; /* coverage class */
277 HAL_BOOL ah_regdomainUpdate; /* regdomain is updated? */
279 * RF Silent handling; setup according to the EEPROM.
281 uint16_t ah_rfsilent; /* GPIO pin + polarity */
282 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
284 * Diagnostic support for discriminating HIUERR reports.
286 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
287 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
290 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
292 #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
293 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
294 #define ath_hal_getWirelessModes(_ah) \
295 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
296 #define ath_hal_eepromRead(_ah, _off, _data) \
297 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
298 #define ath_hal_eepromWrite(_ah, _off, _data) \
299 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
300 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
301 AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio)
302 #define ath_hal_gpioCfgInput(_ah, _gpio) \
303 AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio)
304 #define ath_hal_gpioGet(_ah, _gpio) \
305 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio)
306 #define ath_hal_gpioSet(_ah, _gpio, _val) \
307 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val)
308 #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
309 AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
310 #define ath_hal_getpowerlimits(_ah, _chans, _nchan) \
311 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan)
312 #define ath_hal_getNfAdjust(_ah, _c) \
313 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
314 #define ath_hal_getNoiseFloor(_ah, _nfArray) \
315 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
317 #define ath_hal_eepromDetach(_ah) \
318 AH_PRIVATE(_ah)->ah_eepromDetach(_ah)
319 #define ath_hal_eepromGet(_ah, _param, _val) \
320 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
321 #define ath_hal_eepromSet(_ah, _param, _val) \
322 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
323 #define ath_hal_eepromGetFlag(_ah, _param) \
324 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
325 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \
326 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
327 #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
328 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
330 #if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_)
332 * Stuff that would naturally come from _ieee80211.h
334 #define IEEE80211_ADDR_LEN 6
336 #define IEEE80211_WEP_KEYLEN 5 /* 40bit */
337 #define IEEE80211_WEP_IVLEN 3 /* 24bit */
338 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
339 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
341 #define IEEE80211_CRC_LEN 4
343 #define IEEE80211_MTU 1500
344 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
345 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
348 IEEE80211_T_DS, /* direct sequence spread spectrum */
349 IEEE80211_T_FH, /* frequency hopping */
350 IEEE80211_T_OFDM, /* frequency division multiplexing */
351 IEEE80211_T_TURBO, /* high rate DS */
352 IEEE80211_T_HT, /* HT - full GI */
354 #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */
355 #endif /* _NET_IF_IEEE80211_H_ */
357 /* NB: these are defined privately until XR support is announced */
359 ATHEROS_T_XR = IEEE80211_T_HT+1, /* extended range */
362 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
365 #define INIT_CWMIN 15
366 #define INIT_CWMIN_11B 31
367 #define INIT_CWMAX 1023
368 #define INIT_SH_RETRY 10
369 #define INIT_LG_RETRY 10
370 #define INIT_SSH_RETRY 32
371 #define INIT_SLG_RETRY 32
374 uint32_t tqi_ver; /* HAL TXQ verson */
375 HAL_TX_QUEUE tqi_type; /* hw queue type*/
376 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
377 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
378 uint32_t tqi_priority;
379 uint32_t tqi_aifs; /* aifs */
380 uint32_t tqi_cwmin; /* cwMin */
381 uint32_t tqi_cwmax; /* cwMax */
382 uint16_t tqi_shretry; /* frame short retry limit */
383 uint16_t tqi_lgretry; /* frame long retry limit */
384 uint32_t tqi_cbrPeriod;
385 uint32_t tqi_cbrOverflowLimit;
386 uint32_t tqi_burstTime;
387 uint32_t tqi_readyTime;
388 uint32_t tqi_physCompBuf;
389 uint32_t tqi_intFlags; /* flags for internal use */
392 extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
393 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
394 extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
395 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
398 HAL_ANI_PRESENT, /* is ANI support present */
399 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */
400 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */
401 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */
402 HAL_ANI_FIRSTEP_LEVEL, /* set level */
403 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */
404 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
405 HAL_ANI_PHYERR_RESET, /* reset phy error stats */
408 #define HAL_SPUR_VAL_MASK 0x3FFF
409 #define HAL_SPUR_CHAN_WIDTH 87
410 #define HAL_BIN_WIDTH_BASE_100HZ 3125
411 #define HAL_BIN_WIDTH_TURBO_100HZ 6250
412 #define HAL_MAX_BINS_ALLOWED 28
416 * T = 5GHZ|OFDM|TURBO
418 * IS_CHAN_A(T) will return TRUE. This is probably
419 * not the default behavior we want. We should migrate to a better mask --
420 * perhaps CHANNEL_ALL.
422 * For now, IS_CHAN_G() masks itself with CHANNEL_108G.
426 #define IS_CHAN_A(_c) (((_c)->channelFlags & CHANNEL_A) == CHANNEL_A)
427 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
428 #define IS_CHAN_G(_c) (((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G)
429 #define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G)
430 #define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T)
431 #define IS_CHAN_PUREG(_c) \
432 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
434 #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0)
435 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
436 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
437 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
438 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
439 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
440 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
441 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
443 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
445 #define CHANNEL_HT40 (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
446 #define CHANNEL_HT (CHANNEL_HT20 | CHANNEL_HT40)
447 #define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT) != 0)
448 #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20)
449 #define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0)
452 * Deduce if the host cpu has big- or litt-endian byte order.
454 static __inline__ int
462 return (u.c[0] == 0);
465 /* unalligned little endian access */
466 #define LE_READ_2(p) \
468 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
469 #define LE_READ_4(p) \
471 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
472 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
475 * Register manipulation macros that expect bit field defines
476 * to follow the convention that an _S suffix is appended for
477 * a shift count, while the field mask has no suffix.
479 #define SM(_v, _f) (((_v) << _f##_S) & (_f))
480 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
481 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
482 OS_REG_WRITE(_a, _r, \
483 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
484 #define OS_REG_SET_BIT(_a, _r, _f) \
485 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
486 #define OS_REG_CLR_BIT(_a, _r, _f) \
487 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
490 * Regulatory domain support.
494 * Return the max allowed antenna gain based on the current
497 extern u_int ath_hal_getantennareduction(struct ath_hal *,
498 HAL_CHANNEL *, u_int twiceGain);
500 * Return the test group for the specific channel based on
501 * the current regulator domain.
503 extern u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *);
505 * Return whether or not a noise floor check is required
506 * based on the current regulatory domain for the specified
509 extern u_int ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *);
512 * Map a public channel definition to the corresponding
513 * internal data structure. This implicitly specifies
514 * whether or not the specified channel is ok to use
515 * based on the current regulatory domain constraints.
517 extern HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
518 const HAL_CHANNEL *);
520 /* system-configurable parameters */
521 extern int ath_hal_dma_beacon_response_time; /* in TU's */
522 extern int ath_hal_sw_beacon_response_time; /* in TU's */
523 extern int ath_hal_additional_swba_backoff; /* in TU's */
525 /* wait for the register contents to have the specified value */
526 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
527 uint32_t mask, uint32_t val);
529 /* return the first n bits in val reversed */
530 extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
532 /* printf interfaces */
533 extern void ath_hal_printf(struct ath_hal *, const char*, ...)
535 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
537 extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
539 /* allocate and free memory */
540 extern void *ath_hal_malloc(size_t);
541 extern void ath_hal_free(void *);
543 /* common debugging interfaces */
545 #include "ah_debug.h"
546 extern int ath_hal_debug;
547 extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
550 #define HALDEBUG(_ah, __m, _fmt, ...)
551 #endif /* AH_DEBUG */
554 * Register logging definitions shared with ardecode.
556 #include "ah_decode.h"
559 * Common assertion interface. Note: it is a bad idea to generate
560 * an assertion failure for any recoverable event. Instead catch
561 * the violation and, if possible, fix it up or recover from it; either
562 * with an error return value or a diagnostic messages. System software
563 * does not panic unless the situation is hopeless.
566 extern void ath_hal_assert_failed(const char* filename,
567 int lineno, const char* msg);
569 #define HALASSERT(_x) do { \
571 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
575 #define HALASSERT(_x)
576 #endif /* AH_ASSERT */
579 * Convert between microseconds and core system clocks.
581 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
582 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
585 * Generic get/set capability support. Each chip overrides
586 * this routine to support chip-specific capabilities.
588 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
589 HAL_CAPABILITY_TYPE type, uint32_t capability,
591 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
592 HAL_CAPABILITY_TYPE type, uint32_t capability,
593 uint32_t setting, HAL_STATUS *status);
596 * Diagnostic interface. This is an open-ended interface that
597 * is opaque to applications. Diagnostic programs use this to
598 * retrieve internal data structures, etc. There is no guarantee
599 * that calling conventions for calls other than HAL_DIAG_REVS
600 * are stable between HAL releases; a diagnostic application must
601 * use the HAL revision information to deal with ABI/API differences.
603 * NB: do not renumber these, certain codes are publicly used.
606 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */
607 HAL_DIAG_EEPROM = 1, /* EEPROM contents */
608 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */
609 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */
610 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */
611 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */
612 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */
613 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */
614 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */
615 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */
616 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */
617 HAL_DIAG_PCDAC = 11, /* PCDAC table */
618 HAL_DIAG_TXRATES = 12, /* Transmit rate table */
619 HAL_DIAG_REGS = 13, /* Registers */
620 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */
621 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */
622 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */
623 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */
624 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */
625 /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */
626 HAL_DIAG_REGREAD = 24, /* Reg reads */
627 HAL_DIAG_REGWRITE = 25, /* Reg writes */
628 HAL_DIAG_GET_REGBASE = 26, /* Get register base */
629 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */
630 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */
631 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */
632 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */
633 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */
634 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */
638 HAL_BB_HANG_DFS = 0x0001,
639 HAL_BB_HANG_RIFS = 0x0002,
640 HAL_BB_HANG_RX_CLEAR = 0x0004,
641 HAL_BB_HANG_UNKNOWN = 0x0080,
643 HAL_MAC_HANG_SIG1 = 0x0100,
644 HAL_MAC_HANG_SIG2 = 0x0200,
645 HAL_MAC_HANG_UNKNOWN = 0x8000,
647 HAL_BB_HANGS = HAL_BB_HANG_DFS
649 | HAL_BB_HANG_RX_CLEAR
650 | HAL_BB_HANG_UNKNOWN,
651 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
653 | HAL_MAC_HANG_UNKNOWN,
657 * Device revision information.
660 uint16_t ah_devid; /* PCI device ID */
661 uint16_t ah_subvendorid; /* PCI subvendor ID */
662 uint32_t ah_macVersion; /* MAC version id */
663 uint16_t ah_macRev; /* MAC revision */
664 uint16_t ah_phyRev; /* PHY revision */
665 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
666 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
670 * Argument payload for HAL_DIAG_SETKEY.
673 HAL_KEYVAL dk_keyval;
674 uint16_t dk_keyix; /* key index */
675 uint8_t dk_mac[IEEE80211_ADDR_LEN];
676 int dk_xor; /* XOR key data */
680 * Argument payload for HAL_DIAG_EEWRITE.
683 uint16_t ee_off; /* eeprom offset */
684 uint16_t ee_data; /* write data */
689 u_int offset; /* reg offset */
690 uint32_t val; /* reg value */
694 * 11n compatibility tweaks.
696 #define HAL_DIAG_11N_SERVICES 0x00000003
697 #define HAL_DIAG_11N_SERVICES_S 0
698 #define HAL_DIAG_11N_TXSTOMP 0x0000000c
699 #define HAL_DIAG_11N_TXSTOMP_S 2
702 int maxNoiseImmunityLevel; /* [0..4] */
703 int totalSizeDesired[5];
708 int maxSpurImmunityLevel; /* [0..7] */
711 int maxFirstepLevel; /* [0..2] */
714 uint32_t ofdmTrigHigh;
715 uint32_t ofdmTrigLow;
721 int period; /* update listen period */
724 extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
725 const void *args, uint32_t argsize,
726 void **result, uint32_t *resultsize);
729 * Setup a h/w rate table for use.
731 extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
734 * Common routine for implementing getChanNoise api.
736 extern int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan);
739 * Initialization support.
742 const uint32_t *data;
746 #define HAL_INI_INIT(_ia, _data, _cols) do { \
747 (_ia)->data = (const uint32_t *)(_data); \
748 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
749 (_ia)->cols = (_cols); \
751 #define HAL_INI_VAL(_ia, _r, _c) \
752 ((_ia)->data[((_r)*(_ia)->cols) + (_c)])
755 * OS_DELAY() does a PIO READ on the PCI bus which allows
756 * other cards' DMA reads to complete in the middle of our reset.
758 #define DMA_YIELD(x) do { \
759 if ((++(x) % 64) == 0) \
763 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
765 for (r = 0; r < N(regArray); r++) { \
766 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
771 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
773 for (r = 0; r < N(regArray); r++) { \
774 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
779 extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
781 extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
783 extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
784 const uint32_t data[], int regWr);
786 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
787 #endif /* _ATH_AH_INTERAL_H_ */