3 * ===================================
4 * HARP | Host ATM Research Platform
5 * ===================================
8 * This Host ATM Research Platform ("HARP") file (the "Software") is
9 * made available by Network Computing Services, Inc. ("NetworkCS")
10 * "AS IS". NetworkCS does not provide maintenance, improvements or
11 * support of any kind.
13 * NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
14 * INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
15 * AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
16 * SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
17 * In no event shall NetworkCS be responsible for any damages, including
18 * but not limited to consequential damages, arising from or relating to
19 * any use of the Software or related support.
21 * Copyright 1994-1998 Network Computing Services, Inc.
23 * Copies of this Software may be made, however, the above copyright
24 * notice must be reproduced on all copies.
26 * @(#) $FreeBSD: src/sys/dev/hfa/fore_slave.h,v 1.2 1999/08/28 00:41:52 peter Exp $
31 * FORE Systems 200-Series Adapter Support
32 * ---------------------------------------
34 * Slave Interface definitions
42 * This file contains the (mostly hardware) definitions for each of the
43 * supported 200-series slave interfaces.
48 * Structure defining the supported FORE 200-series interfaces
51 char *fd_name; /* Device name (from PROM) */
52 Atm_device fd_devtyp; /* Device type */
54 typedef struct fore_device Fore_device;
62 #define MON960_BASE 0x400 /* Address offset of Mon960 */
63 #define AALI_BASE 0x4d40 /* Address offset of Aali */
65 typedef volatile unsigned int Fore_reg; /* Slave control register */
66 typedef volatile unsigned char Fore_mem; /* Slave memory */
70 * SBA-200E SBus Slave Interface
71 * -----------------------------
74 #define SBA200E_PROM_NAME "FORE,sba-200e"
77 * SBA-200E Host Control Register (HCR)
79 #define SBA200E_READ_BITS 0x1ff /* Valid read data bits */
80 #define SBA200E_WRITE_BITS 0x01f /* Valid write data bits */
81 #define SBA200E_STICKY_BITS 0x013 /* Sticky data bits */
84 #define SBA200E_SBUS_INTR_RD 0x100 /* State of SBus interrupt */
85 #define SBA200E_TEST_MODE 0x080 /* Device is in test-mode */
86 #define SBA200E_IFIFO_FULL 0x040 /* Input FIFO almost full (when 0) */
87 #define SBA200E_ESP_HOLD_RD 0x020 /* State of ESP bus hold */
88 #define SBA200E_SBUS_ENA_RD 0x010 /* State of SBus interrupt enable */
89 #define SBA200E_OFIFO_FULL 0x008 /* Output FIFO almost full */
90 #define SBA200E_SELFTEST_FAIL 0x004 /* i960 self-test failed (when 0) */
91 #define SBA200E_HOLD_LOCK_RD 0x002 /* State of i960 hold lock signal */
92 #define SBA200E_RESET_RD 0x001 /* State of board reset signal */
94 /* Write access - bit set (clear) */
95 #define SBA200E_SBUS_ENA 0x010 /* Enable (disable) SBus interrupts */
96 #define SBA200E_CLR_SBUS_INTR 0x008 /* Clear SBus interrupt */
97 #define SBA200E_I960_INTR 0x004 /* Issue interrupt to i960 */
98 #define SBA200E_HOLD_LOCK 0x002 /* Set (clear) i960 hold lock signal */
99 #define SBA200E_RESET 0x001 /* Set (clear) board reset signal */
101 #define SBA200E_HCR_INIT(hcr,bits) \
102 ((hcr) = (SBA200E_WRITE_BITS & (bits)))
103 #define SBA200E_HCR_SET(hcr,bits) \
104 ((hcr) = (((hcr) & SBA200E_STICKY_BITS) | (bits)))
105 #define SBA200E_HCR_CLR(hcr,bits) \
106 ((hcr) = ((hcr) & (SBA200E_STICKY_BITS ^ (bits))))
111 * SBA-200 SBus Slave Interface
112 * ----------------------------
115 #define SBA200_PROM_NAME "FORE,sba-200"
118 * SBA-200 Board Control Register (BCR)
120 /* Write access - bit set */
121 #define SBA200_CLR_SBUS_INTR 0x04 /* Clear SBus interrupt */
122 #define SBA200_RESET 0x01 /* Assert board reset signal */
124 /* Write access - bit clear */
125 #define SBA200_RESET_CLR 0x00 /* Clear board reset signal */
130 * PCA-200E PCI Bus Slave Interface
131 * --------------------------------
137 #define FORE_VENDOR_ID 0x1127
138 #define FORE_PCA200E_ID 0x0300
141 * PCA-200E PCI Configuration Space
143 #define PCA200E_PCI_MEMBASE 0x10 /* Memory base address */
144 #define PCA200E_PCI_MCTL 0x40 /* Master control */
147 * PCA-200E Address Space
149 #define PCA200E_RAM_SIZE 0x100000
150 #define PCA200E_HCR_OFFSET 0x100000
151 #define PCA200E_IMASK_OFFSET 0x100004
152 #define PCA200E_PSR_OFFSET 0x100008
153 #define PCA200E_MMAP_SIZE 0x10000c
156 * PCA-200E Master Control
158 #define PCA200E_MCTL_SWAP 0x4000 /* Convert Slave endianess */
161 * PCA-200E Host Control Register (HCR)
163 #define PCA200E_READ_BITS 0x0ff /* Valid read data bits */
164 #define PCA200E_WRITE_BITS 0x01f /* Valid write data bits */
165 #define PCA200E_STICKY_BITS 0x000 /* Sticky data bits */
168 #define PCA200E_TEST_MODE 0x080 /* Device is in test-mode */
169 #define PCA200E_IFIFO_FULL 0x040 /* Input FIFO almost full */
170 #define PCA200E_ESP_HOLD_RD 0x020 /* State of ESP hold bus */
171 #define PCA200E_OFIFO_FULL 0x010 /* Output FIFO almost full */
172 #define PCA200E_HOLD_ACK 0x008 /* State of Hold Ack */
173 #define PCA200E_SELFTEST_FAIL 0x004 /* i960 self-test failed */
174 #define PCA200E_HOLD_LOCK_RD 0x002 /* State of i960 hold lock signal */
175 #define PCA200E_RESET_BD 0x001 /* State of board reset signal */
178 #define PCA200E_CLR_HBUS_INT 0x010 /* Clear host bus interrupt */
179 #define PCA200E_I960_INTRA 0x008 /* Set slave interrupt A */
180 #define PCA200E_I960_INTRB 0x004 /* Set slave interrupt B */
181 #define PCA200E_HOLD_LOCK 0x002 /* Set (clear) i960 hold lock signal */
182 #define PCA200E_RESET 0x001 /* Set (clear) board reset signal */
184 #define PCA200E_HCR_INIT(hcr,bits) \
185 ((hcr) = (PCA200E_WRITE_BITS & (bits)))
186 #define PCA200E_HCR_SET(hcr,bits) \
188 #define PCA200E_HCR_CLR(hcr,bits) \
191 #endif /* _FORE_SLAVE_H */