sys/dev/disk/aic7xxx/aic79xx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      aic7901 and aic7902 SCSI controllers
   4  *
   5  * Copyright (c) 1994-2001 Justin T. Gibbs.
   6  * Copyright (c) 2000-2002 Adaptec Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16  *    substantially similar to the "NO WARRANTY" disclaimer below
  17  *    ("Disclaimer") and any redistribution must be conditioned upon
  18  *    including a substantially similar Disclaimer requirement for further
  19  *    binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39  * POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#75 $
  42  *
  43  * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.3.2.5 2003/06/10 03:26:07 gibbs Exp $
  44  */
  45
  46 #ifdef __linux__
  47 #include "aic79xx_osm.h"
  48 #include "aic79xx_inline.h"
  49 #else
  50 #include <dev/aic7xxx/aic79xx_osm.h>
  51 #include <dev/aic7xxx/aic79xx_inline.h>
  52 #endif
  53
  54 static __inline uint64_t
  55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  56 {
  57         uint64_t id;
  58
  59         id = subvendor
  60            | (subdevice << 16)
  61            | ((uint64_t)vendor << 32)
  62            | ((uint64_t)device << 48);
  63
  64         return (id);
  65 }
  66
  67 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  68 #define ID_ALL_IROC_MASK                0xFFFFFF7FFFFFFFFFull
  69 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  70 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  71 #define ID_9005_GENERIC_IROC_MASK       0xFFF0FF7F00000000ull
  72
  73 #define ID_AIC7901                      0x800F9005FFFF9005ull
  74 #define ID_AHA_29320A                   0x8000900500609005ull
  75 #define ID_AHA_29320ALP                 0x8017900500449005ull
  76
  77 #define ID_AIC7901A                     0x801E9005FFFF9005ull
  78 #define ID_AHA_29320                    0x8012900500429005ull
  79 #define ID_AHA_29320B                   0x8013900500439005ull
  80 #define ID_AHA_29320LP                  0x8014900500449005ull
  81
  82 #define ID_AIC7902                      0x801F9005FFFF9005ull
  83 #define ID_AIC7902_B                    0x801D9005FFFF9005ull
  84 #define ID_AHA_39320                    0x8010900500409005ull
  85 #define ID_AHA_39320_B                  0x8015900500409005ull
  86 #define ID_AHA_39320A                   0x8016900500409005ull
  87 #define ID_AHA_39320D                   0x8011900500419005ull
  88 #define ID_AHA_39320D_B                 0x801C900500419005ull
  89 #define ID_AHA_39320D_HP                0x8011900500AC0E11ull
  90 #define ID_AHA_39320D_B_HP              0x801C900500AC0E11ull
  91 #define ID_AIC7902_PCI_REV_A4           0x3
  92 #define ID_AIC7902_PCI_REV_B0           0x10
  93 #define SUBID_HP                        0x0E11
  94
  95 #define DEVID_9005_TYPE(id) ((id) & 0xF)
  96 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
  97 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
  98 #define         DEVID_9005_TYPE_IROC            0x8     /* Raid(0,1,10) Card */
  99 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 100
 101 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
 102
 103 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
 104
 105 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 106 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
 107 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 108
 109 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
 110
 111 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
 112
 113 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
 114 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 115 #define         SUBID_9005_SEEPTYPE_4K          0x1
 116
 117 static ahd_device_setup_t ahd_aic7901_setup;
 118 static ahd_device_setup_t ahd_aic7901A_setup;
 119 static ahd_device_setup_t ahd_aic7902_setup;
 120
 121 struct ahd_pci_identity ahd_pci_ident_table [] =
 122 {
 123         /* aic7901 based controllers */
 124         {
 125                 ID_AHA_29320A,
 126                 ID_ALL_MASK,
 127                 "Adaptec 29320A Ultra320 SCSI adapter",
 128                 ahd_aic7901_setup
 129         },
 130         {
 131                 ID_AHA_29320ALP,
 132                 ID_ALL_MASK,
 133                 "Adaptec 29320ALP Ultra320 SCSI adapter",
 134                 ahd_aic7901_setup
 135         },
 136         /* aic7901A based controllers */
 137         {
 138                 ID_AHA_29320,
 139                 ID_ALL_MASK,
 140                 "Adaptec 29320 Ultra320 SCSI adapter",
 141                 ahd_aic7901A_setup
 142         },
 143         {
 144                 ID_AHA_29320B,
 145                 ID_ALL_MASK,
 146                 "Adaptec 29320B Ultra320 SCSI adapter",
 147                 ahd_aic7901A_setup
 148         },
 149         {
 150                 ID_AHA_29320LP,
 151                 ID_ALL_MASK,
 152                 "Adaptec 29320LP Ultra320 SCSI adapter",
 153                 ahd_aic7901A_setup
 154         },
 155         /* aic7902 based controllers */
 156         {
 157                 ID_AHA_39320,
 158                 ID_ALL_MASK,
 159                 "Adaptec 39320 Ultra320 SCSI adapter",
 160                 ahd_aic7902_setup
 161         },
 162         {
 163                 ID_AHA_39320_B,
 164                 ID_ALL_MASK,
 165                 "Adaptec 39320 Ultra320 SCSI adapter",
 166                 ahd_aic7902_setup
 167         },
 168         {
 169                 ID_AHA_39320A,
 170                 ID_ALL_MASK,
 171                 "Adaptec 39320A Ultra320 SCSI adapter",
 172                 ahd_aic7902_setup
 173         },
 174         {
 175                 ID_AHA_39320D,
 176                 ID_ALL_MASK,
 177                 "Adaptec 39320D Ultra320 SCSI adapter",
 178                 ahd_aic7902_setup
 179         },
 180         {
 181                 ID_AHA_39320D_HP,
 182                 ID_ALL_MASK,
 183                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 184                 ahd_aic7902_setup
 185         },
 186         {
 187                 ID_AHA_39320D_B,
 188                 ID_ALL_MASK,
 189                 "Adaptec 39320D Ultra320 SCSI adapter",
 190                 ahd_aic7902_setup
 191         },
 192         {
 193                 ID_AHA_39320D_B_HP,
 194                 ID_ALL_MASK,
 195                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 196                 ahd_aic7902_setup
 197         },
 198         {
 199                 ID_AHA_29320,
 200                 ID_ALL_MASK,
 201                 "Adaptec 29320 Ultra320 SCSI adapter",
 202                 ahd_aic7902_setup
 203         },
 204         {
 205                 ID_AHA_29320B,
 206                 ID_ALL_MASK,
 207                 "Adaptec 29320B Ultra320 SCSI adapter",
 208                 ahd_aic7902_setup
 209         },
 210         /* Generic chip probes for devices we don't know 'exactly' */
 211         {
 212                 ID_AIC7901 & ID_DEV_VENDOR_MASK,
 213                 ID_DEV_VENDOR_MASK,
 214                 "Adaptec AIC7901 Ultra320 SCSI adapter",
 215                 ahd_aic7901_setup
 216         },
 217         {
 218                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
 219                 ID_DEV_VENDOR_MASK,
 220                 "Adaptec AIC7901A Ultra320 SCSI adapter",
 221                 ahd_aic7901A_setup
 222         },
 223         {
 224                 ID_AIC7902 & ID_9005_GENERIC_MASK,
 225                 ID_9005_GENERIC_MASK,
 226                 "Adaptec AIC7902 Ultra320 SCSI adapter",
 227                 ahd_aic7902_setup
 228         }
 229 };
 230
 231 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
 232
 233 #define DEVCONFIG               0x40
 234 #define         PCIXINITPAT     0x0000E000ul
 235 #define                 PCIXINIT_PCI33_66       0x0000E000ul
 236 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
 237 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
 238 #define                 PCIXINIT_PCIX100_133    0x00008000ul
 239 #define PCI_BUS_MODES_INDEX(devconfig)  \
 240         (((devconfig) & PCIXINITPAT) >> 13)
 241 static const char *pci_bus_modes[] =
 242 {
 243         "PCI bus mode unknown",
 244         "PCI bus mode unknown",
 245         "PCI bus mode unknown",
 246         "PCI bus mode unknown",
 247         "PCI-X 101-133Mhz",
 248         "PCI-X 67-100Mhz",
 249         "PCI-X 50-66Mhz",
 250         "PCI 33 or 66Mhz"
 251 };
 252
 253 #define         TESTMODE        0x00000800ul
 254 #define         IRDY_RST        0x00000200ul
 255 #define         FRAME_RST       0x00000100ul
 256 #define         PCI64BIT        0x00000080ul
 257 #define         MRDCEN          0x00000040ul
 258 #define         ENDIANSEL       0x00000020ul
 259 #define         MIXQWENDIANEN   0x00000008ul
 260 #define         DACEN           0x00000004ul
 261 #define         STPWLEVEL       0x00000002ul
 262 #define         QWENDIANSEL     0x00000001ul
 263
 264 #define DEVCONFIG1              0x44
 265 #define         PREQDIS         0x01
 266
 267 #define CSIZE_LATTIME           0x0c
 268 #define         CACHESIZE       0x000000fful
 269 #define         LATTIME         0x0000ff00ul
 270
 271 static int      ahd_check_extport(struct ahd_softc *ahd);
 272 static void     ahd_configure_termination(struct ahd_softc *ahd,
 273                                           u_int adapter_control);
 274 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
 275
 276 struct ahd_pci_identity *
 277 ahd_find_pci_device(ahd_dev_softc_t pci)
 278 {
 279         uint64_t  full_id;
 280         uint16_t  device;
 281         uint16_t  vendor;
 282         uint16_t  subdevice;
 283         uint16_t  subvendor;
 284         struct    ahd_pci_identity *entry;
 285         u_int     i;
 286
 287         vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 288         device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 289         subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 290         subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 291         full_id = ahd_compose_id(device,
 292                                  vendor,
 293                                  subdevice,
 294                                  subvendor);
 295
 296         for (i = 0; i < ahd_num_pci_devs; i++) {
 297                 entry = &ahd_pci_ident_table[i];
 298                 if (entry->full_id == (full_id & entry->id_mask)) {
 299                         /* Honor exclusion entries. */
 300                         if (entry->name == NULL)
 301                                 return (NULL);
 302                         return (entry);
 303                 }
 304         }
 305         return (NULL);
 306 }
 307
 308 int
 309 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
 310 {
 311         struct scb_data *shared_scb_data;
 312         u_long           l;
 313         u_int            command;
 314         uint32_t         devconfig;
 315         uint16_t         subvendor;
 316         int              error;
 317
 318         shared_scb_data = NULL;
 319         ahd->description = entry->name;
 320         /*
 321          * Record if this is an HP board.
 322          */
 323         subvendor = ahd_pci_read_config(ahd->dev_softc,
 324                                         PCIR_SUBVEND_0, /*bytes*/2);
 325         if (subvendor == SUBID_HP)
 326                 ahd->flags |= AHD_HP_BOARD;
 327
 328         error = entry->setup(ahd);
 329         if (error != 0)
 330                 return (error);
 331
 332         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 333         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 334                 ahd->chip |= AHD_PCI;
 335                 /* Disable PCIX workarounds when running in PCI mode. */
 336                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 337         } else {
 338                 ahd->chip |= AHD_PCIX;
 339         }
 340         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 341
 342         ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
 343
 344         error = ahd_pci_map_registers(ahd);
 345         if (error != 0)
 346                 return (error);
 347
 348         /*
 349          * If we need to support high memory, enable dual
 350          * address cycles.  This bit must be set to enable
 351          * high address bit generation even if we are on a
 352          * 64bit bus (PCI64BIT set in devconfig).
 353          */
 354         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
 355                 uint32_t devconfig;
 356
 357                 if (bootverbose)
 358                         printf("%s: Enabling 39Bit Addressing\n",
 359                                ahd_name(ahd));
 360                 devconfig = ahd_pci_read_config(ahd->dev_softc,
 361                                                 DEVCONFIG, /*bytes*/4);
 362                 devconfig |= DACEN;
 363                 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
 364                                      devconfig, /*bytes*/4);
 365         }
 366
 367         /* Ensure busmastering is enabled */
 368         command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 369         command |= PCIM_CMD_BUSMASTEREN;
 370         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 371
 372         error = ahd_softc_init(ahd);
 373         if (error != 0)
 374                 return (error);
 375
 376         ahd->bus_intr = ahd_pci_intr;
 377
 378         error = ahd_reset(ahd, /*reinit*/FALSE);
 379         if (error != 0)
 380                 return (ENXIO);
 381
 382         ahd->pci_cachesize =
 383             ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
 384                                 /*bytes*/1) & CACHESIZE;
 385         ahd->pci_cachesize *= 4;
 386
 387         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 388         /* See if we have a SEEPROM and perform auto-term */
 389         error = ahd_check_extport(ahd);
 390         if (error != 0)
 391                 return (error);
 392
 393         /* Core initialization */
 394         error = ahd_init(ahd);
 395         if (error != 0)
 396                 return (error);
 397
 398         /*
 399          * Allow interrupts now that we are completely setup.
 400          */
 401         error = ahd_pci_map_int(ahd);
 402         if (error != 0)
 403                 return (error);
 404
 405         ahd_list_lock(&l);
 406         /*
 407          * Link this softc in with all other ahd instances.
 408          */
 409         ahd_softc_insert(ahd);
 410         ahd_list_unlock(&l);
 411         return (0);
 412 }
 413
 414 /*
 415  * Perform some simple tests that should catch situations where
 416  * our registers are invalidly mapped.
 417  */
 418 int
 419 ahd_pci_test_register_access(struct ahd_softc *ahd)
 420 {
 421         uint32_t cmd;
 422         u_int    targpcistat;
 423         u_int    pci_status1;
 424         int      error;
 425         uint8_t  hcntrl;
 426
 427         error = EIO;
 428
 429         /*
 430          * Enable PCI error interrupt status, but suppress NMIs
 431          * generated by SERR raised due to target aborts.
 432          */
 433         cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 434         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 435                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
 436
 437         /*
 438          * First a simple test to see if any
 439          * registers can be read.  Reading
 440          * HCNTRL has no side effects and has
 441          * at least one bit that is guaranteed to
 442          * be zero so it is a good register to
 443          * use for this test.
 444          */
 445         hcntrl = ahd_inb(ahd, HCNTRL);
 446         if (hcntrl == 0xFF)
 447                 goto fail;
 448
 449         /*
 450          * Next create a situation where write combining
 451          * or read prefetching could be initiated by the
 452          * CPU or host bridge.  Our device does not support
 453          * either, so look for data corruption and/or flaged
 454          * PCI errors.
 455          */
 456         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
 457         while (ahd_is_paused(ahd) == 0)
 458                 ;
 459
 460         /* Clear any PCI errors that occurred before our driver attached. */
 461         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 462         targpcistat = ahd_inb(ahd, TARGPCISTAT);
 463         ahd_outb(ahd, TARGPCISTAT, targpcistat);
 464         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 465                                           PCIR_STATUS + 1, /*bytes*/1);
 466         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 467                              pci_status1, /*bytes*/1);
 468         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 469         ahd_outb(ahd, CLRINT, CLRPCIINT);
 470
 471         ahd_outb(ahd, SEQCTL0, PERRORDIS);
 472         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
 473         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
 474                 goto fail;
 475
 476         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 477                 u_int targpcistat;
 478
 479                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 480                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 481                 if ((targpcistat & STA) != 0)
 482                         goto fail;
 483         }
 484
 485         error = 0;
 486
 487 fail:
 488         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 489
 490                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 491                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 492
 493                 /* Silently clear any latched errors. */
 494                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
 495                 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 496                                                   PCIR_STATUS + 1, /*bytes*/1);
 497                 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 498                                      pci_status1, /*bytes*/1);
 499                 ahd_outb(ahd, CLRINT, CLRPCIINT);
 500         }
 501         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
 502         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 503         return (error);
 504 }
 505
 506 /*
 507  * Check the external port logic for a serial eeprom
 508  * and termination/cable detection contrls.
 509  */
 510 static int
 511 ahd_check_extport(struct ahd_softc *ahd)
 512 {
 513         struct  vpd_config vpd;
 514         struct  seeprom_config *sc;
 515         u_int   adapter_control;
 516         int     have_seeprom;
 517         int     error;
 518
 519         sc = ahd->seep_config;
 520         have_seeprom = ahd_acquire_seeprom(ahd);
 521         if (have_seeprom) {
 522                 u_int start_addr;
 523
 524                 /*
 525                  * Fetch VPD for this function and parse it.
 526                  */
 527                 if (bootverbose)
 528                         printf("%s: Reading VPD from SEEPROM...",
 529                                ahd_name(ahd));
 530
 531                 /* Address is always in units of 16bit words */
 532                 start_addr = ((2 * sizeof(*sc))
 533                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
 534
 535                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
 536                                          start_addr, sizeof(vpd)/2,
 537                                          /*bytestream*/TRUE);
 538                 if (error == 0)
 539                         error = ahd_parse_vpddata(ahd, &vpd);
 540                 if (bootverbose)
 541                         printf("%s: VPD parsing %s\n",
 542                                ahd_name(ahd),
 543                                error == 0 ? "successful" : "failed");
 544
 545                 if (bootverbose)
 546                         printf("%s: Reading SEEPROM...", ahd_name(ahd));
 547
 548                 /* Address is always in units of 16bit words */
 549                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
 550
 551                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
 552                                          start_addr, sizeof(*sc)/2,
 553                                          /*bytestream*/FALSE);
 554
 555                 if (error != 0) {
 556                         printf("Unable to read SEEPROM\n");
 557                         have_seeprom = 0;
 558                 } else {
 559                         have_seeprom = ahd_verify_cksum(sc);
 560
 561                         if (bootverbose) {
 562                                 if (have_seeprom == 0)
 563                                         printf ("checksum error\n");
 564                                 else
 565                                         printf ("done.\n");
 566                         }
 567                 }
 568                 ahd_release_seeprom(ahd);
 569         }
 570
 571         if (!have_seeprom) {
 572                 u_int     nvram_scb;
 573
 574                 /*
 575                  * Pull scratch ram settings and treat them as
 576                  * if they are the contents of an seeprom if
 577                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
 578                  * in SCB 0xFF.  We manually compose the data as 16bit
 579                  * values to avoid endian issues.
 580                  */
 581                 ahd_set_scbptr(ahd, 0xFF);
 582                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
 583                 if (nvram_scb != 0xFF
 584                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 585                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
 586                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 587                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
 588                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
 589                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
 590                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
 591                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
 592                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 593                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
 594                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 595                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
 596                         uint16_t *sc_data;
 597                         int       i;
 598
 599                         ahd_set_scbptr(ahd, nvram_scb);
 600                         sc_data = (uint16_t *)sc;
 601                         for (i = 0; i < 64; i += 2)
 602                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
 603                         have_seeprom = ahd_verify_cksum(sc);
 604                         if (have_seeprom)
 605                                 ahd->flags |= AHD_SCB_CONFIG_USED;
 606                 }
 607         }
 608
 609 #if AHD_DEBUG
 610         if (have_seeprom != 0
 611          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 612                 uint16_t *sc_data;
 613                 int       i;
 614
 615                 printf("%s: Seeprom Contents:", ahd_name(ahd));
 616                 sc_data = (uint16_t *)sc;
 617                 for (i = 0; i < (sizeof(*sc)); i += 2)
 618                         printf("\n\t0x%.4x", sc_data[i]);
 619                 printf("\n");
 620         }
 621 #endif
 622
 623         if (!have_seeprom) {
 624                 if (bootverbose)
 625                         printf("%s: No SEEPROM available.\n", ahd_name(ahd));
 626                 ahd->flags |= AHD_USEDEFAULTS;
 627                 error = ahd_default_config(ahd);
 628                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
 629                 free(ahd->seep_config, M_DEVBUF);
 630                 ahd->seep_config = NULL;
 631         } else {
 632                 error = ahd_parse_cfgdata(ahd, sc);
 633                 adapter_control = sc->adapter_control;
 634         }
 635         if (error != 0)
 636                 return (error);
 637
 638         ahd_configure_termination(ahd, adapter_control);
 639
 640         return (0);
 641 }
 642
 643 static void
 644 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
 645 {
 646         int      error;
 647         u_int    sxfrctl1;
 648         uint8_t  termctl;
 649         uint32_t devconfig;
 650
 651         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 652         devconfig &= ~STPWLEVEL;
 653         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
 654                 devconfig |= STPWLEVEL;
 655         if (bootverbose)
 656                 printf("%s: STPWLEVEL is %s\n",
 657                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
 658         ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 659
 660         /* Make sure current sensing is off. */
 661         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
 662                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
 663         }
 664
 665         /*
 666          * Read to sense.  Write to set.
 667          */
 668         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
 669         if ((adapter_control & CFAUTOTERM) == 0) {
 670                 if (bootverbose)
 671                         printf("%s: Manual Primary Termination\n",
 672                                ahd_name(ahd));
 673                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
 674                 if ((adapter_control & CFSTERM) != 0)
 675                         termctl |= FLX_TERMCTL_ENPRILOW;
 676                 if ((adapter_control & CFWSTERM) != 0)
 677                         termctl |= FLX_TERMCTL_ENPRIHIGH;
 678         } else if (error != 0) {
 679                 printf("%s: Primary Auto-Term Sensing failed! "
 680                        "Using Defaults.\n", ahd_name(ahd));
 681                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
 682         }
 683
 684         if ((adapter_control & CFSEAUTOTERM) == 0) {
 685                 if (bootverbose)
 686                         printf("%s: Manual Secondary Termination\n",
 687                                ahd_name(ahd));
 688                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
 689                 if ((adapter_control & CFSELOWTERM) != 0)
 690                         termctl |= FLX_TERMCTL_ENSECLOW;
 691                 if ((adapter_control & CFSEHIGHTERM) != 0)
 692                         termctl |= FLX_TERMCTL_ENSECHIGH;
 693         } else if (error != 0) {
 694                 printf("%s: Secondary Auto-Term Sensing failed! "
 695                        "Using Defaults.\n", ahd_name(ahd));
 696                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
 697         }
 698
 699         /*
 700          * Now set the termination based on what we found.
 701          */
 702         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
 703         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
 704                 ahd->flags |= AHD_TERM_ENB_A;
 705                 sxfrctl1 |= STPWEN;
 706         }
 707         /* Must set the latch once in order to be effective. */
 708         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
 709         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
 710
 711         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
 712         if (error != 0) {
 713                 printf("%s: Unable to set termination settings!\n",
 714                        ahd_name(ahd));
 715         } else if (bootverbose) {
 716                 printf("%s: Primary High byte termination %sabled\n",
 717                        ahd_name(ahd),
 718                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
 719
 720                 printf("%s: Primary Low byte termination %sabled\n",
 721                        ahd_name(ahd),
 722                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
 723
 724                 printf("%s: Secondary High byte termination %sabled\n",
 725                        ahd_name(ahd),
 726                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
 727
 728                 printf("%s: Secondary Low byte termination %sabled\n",
 729                        ahd_name(ahd),
 730                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
 731         }
 732         return;
 733 }
 734
 735 #define DPE     0x80
 736 #define SSE     0x40
 737 #define RMA     0x20
 738 #define RTA     0x10
 739 #define STA     0x08
 740 #define DPR     0x01
 741
 742 static const char *split_status_source[] =
 743 {
 744         "DFF0",
 745         "DFF1",
 746         "OVLY",
 747         "CMC",
 748 };
 749
 750 static const char *pci_status_source[] =
 751 {
 752         "DFF0",
 753         "DFF1",
 754         "SG",
 755         "CMC",
 756         "OVLY",
 757         "NONE",
 758         "MSI",
 759         "TARG"
 760 };
 761
 762 static const char *split_status_strings[] =
 763 {
 764         "%s: Received split response in %s.\n",
 765         "%s: Received split completion error message in %s\n",
 766         "%s: Receive overrun in %s\n",
 767         "%s: Count not complete in %s\n",
 768         "%s: Split completion data bucket in %s\n",
 769         "%s: Split completion address error in %s\n",
 770         "%s: Split completion byte count error in %s\n",
 771         "%s: Signaled Target-abort to early terminate a split in %s\n"
 772 };
 773
 774 static const char *pci_status_strings[] =
 775 {
 776         "%s: Data Parity Error has been reported via PERR# in %s\n",
 777         "%s: Target initial wait state error in %s\n",
 778         "%s: Split completion read data parity error in %s\n",
 779         "%s: Split completion address attribute parity error in %s\n",
 780         "%s: Received a Target Abort in %s\n",
 781         "%s: Received a Master Abort in %s\n",
 782         "%s: Signal System Error Detected in %s\n",
 783         "%s: Address or Write Phase Parity Error Detected in %s.\n"
 784 };
 785
 786 void
 787 ahd_pci_intr(struct ahd_softc *ahd)
 788 {
 789         uint8_t         pci_status[8];
 790         ahd_mode_state  saved_modes;
 791         u_int           pci_status1;
 792         u_int           intstat;
 793         u_int           i;
 794         u_int           reg;
 795
 796         intstat = ahd_inb(ahd, INTSTAT);
 797
 798         if ((intstat & SPLTINT) != 0)
 799                 ahd_pci_split_intr(ahd, intstat);
 800
 801         if ((intstat & PCIINT) == 0)
 802                 return;
 803
 804         printf("%s: PCI error Interrupt\n", ahd_name(ahd));
 805         saved_modes = ahd_save_modes(ahd);
 806         ahd_dump_card_state(ahd);
 807         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 808         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
 809
 810                 if (i == 5)
 811                         continue;
 812                 pci_status[i] = ahd_inb(ahd, reg);
 813                 /* Clear latched errors.  So our interrupt deasserts. */
 814                 ahd_outb(ahd, reg, pci_status[i]);
 815         }
 816
 817         for (i = 0; i < 8; i++) {
 818                 u_int bit;
 819
 820                 if (i == 5)
 821                         continue;
 822
 823                 for (bit = 0; bit < 8; bit++) {
 824
 825                         if ((pci_status[i] & (0x1 << bit)) != 0) {
 826                                 static const char *s;
 827
 828                                 s = pci_status_strings[bit];
 829                                 if (i == 7/*TARG*/ && bit == 3)
 830                                         s = "%s: Signaled Target Abort\n";
 831                                 printf(s, ahd_name(ahd), pci_status_source[i]);
 832                         }
 833                 }
 834         }
 835         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 836                                           PCIR_STATUS + 1, /*bytes*/1);
 837         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 838                              pci_status1, /*bytes*/1);
 839         ahd_restore_modes(ahd, saved_modes);
 840         ahd_outb(ahd, CLRINT, CLRPCIINT);
 841         ahd_unpause(ahd);
 842 }
 843
 844 static void
 845 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
 846 {
 847         uint8_t         split_status[4];
 848         uint8_t         split_status1[4];
 849         uint8_t         sg_split_status[2];
 850         uint8_t         sg_split_status1[2];
 851         ahd_mode_state  saved_modes;
 852         u_int           i;
 853         uint16_t        pcix_status;
 854
 855         /*
 856          * Check for splits in all modes.  Modes 0 and 1
 857          * additionally have SG engine splits to look at.
 858          */
 859         pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
 860                                           /*bytes*/2);
 861         printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
 862                ahd_name(ahd), pcix_status);
 863         saved_modes = ahd_save_modes(ahd);
 864         for (i = 0; i < 4; i++) {
 865                 ahd_set_modes(ahd, i, i);
 866
 867                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
 868                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
 869                 /* Clear latched errors.  So our interrupt deasserts. */
 870                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
 871                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
 872                 if (i > 1)
 873                         continue;
 874                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
 875                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
 876                 /* Clear latched errors.  So our interrupt deasserts. */
 877                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
 878                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
 879         }
 880
 881         for (i = 0; i < 4; i++) {
 882                 u_int bit;
 883
 884                 for (bit = 0; bit < 8; bit++) {
 885
 886                         if ((split_status[i] & (0x1 << bit)) != 0) {
 887                                 static const char *s;
 888
 889                                 s = split_status_strings[bit];
 890                                 printf(s, ahd_name(ahd),
 891                                        split_status_source[i]);
 892                         }
 893
 894                         if (i > 1)
 895                                 continue;
 896
 897                         if ((sg_split_status[i] & (0x1 << bit)) != 0) {
 898                                 static const char *s;
 899
 900                                 s = split_status_strings[bit];
 901                                 printf(s, ahd_name(ahd), "SG");
 902                         }
 903                 }
 904         }
 905         /*
 906          * Clear PCI-X status bits.
 907          */
 908         ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
 909                              pcix_status, /*bytes*/2);
 910         ahd_outb(ahd, CLRINT, CLRSPLTINT);
 911         ahd_restore_modes(ahd, saved_modes);
 912 }
 913
 914 static int
 915 ahd_aic7901_setup(struct ahd_softc *ahd)
 916 {
 917         int error;
 918
 919         error = ahd_aic7902_setup(ahd);
 920         if (error != 0)
 921                 return (error);
 922         ahd->chip = AHD_AIC7901;
 923         return (0);
 924 }
 925
 926 static int
 927 ahd_aic7901A_setup(struct ahd_softc *ahd)
 928 {
 929         int error;
 930
 931         error = ahd_aic7902_setup(ahd);
 932         if (error != 0)
 933                 return (error);
 934         ahd->chip = AHD_AIC7901A;
 935         return (0);
 936 }
 937
 938 static int
 939 ahd_aic7902_setup(struct ahd_softc *ahd)
 940 {
 941         ahd_dev_softc_t pci;
 942         u_int rev;
 943
 944         pci = ahd->dev_softc;
 945         rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
 946         if (rev < ID_AIC7902_PCI_REV_A4) {
 947                 printf("%s: Unable to attach to unsupported chip revision %d\n",
 948                        ahd_name(ahd), rev);
 949                 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
 950                 return (ENXIO);
 951         }
 952         ahd->channel = ahd_get_pci_function(pci) + 'A';
 953         ahd->chip = AHD_AIC7902;
 954         ahd->features = AHD_AIC7902_FE;
 955         if (rev < ID_AIC7902_PCI_REV_B0) {
 956                 /*
 957                  * Enable A series workarounds.
 958                  */
 959                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
 960                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
 961                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
 962                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
 963                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
 964                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
 965                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
 966                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
 967                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
 968                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
 969                           |  AHD_FAINT_LED_BUG;
 970
 971                 /*
 972                  * IO Cell paramter setup.
 973                  */
 974                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 975
 976                 if ((ahd->flags & AHD_HP_BOARD) == 0)
 977                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
 978         } else {
 979                 u_int devconfig1;
 980
 981                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
 982                               |  AHD_NEW_DFCNTRL_OPTS;
 983                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_ABORT_LQI_BUG
 984                           |  AHD_INTCOLLISION_BUG|AHD_EARLY_REQ_BUG;
 985
 986                 /*
 987                  * IO Cell paramter setup.
 988                  */
 989                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 990                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
 991                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
 992
 993                 /*
 994                  * Set the PREQDIS bit for H2B which disables some workaround
 995                  * that doesn't work on regular PCI busses.
 996                  * XXX - Find out exactly what this does from the hardware
 997                  *       folks!
 998                  */
 999                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1000                 ahd_pci_write_config(pci, DEVCONFIG1,
1001                                      devconfig1|PREQDIS, /*bytes*/1);
1002                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1003         }
1004
1005         return (0);
1006 }