sys/dev/disk/ct/ct.c

   1 /* $FreeBSD: src/sys/dev/ct/ct.c,v 1.4.2.1 2001/07/26 02:32:18 nyan Exp $ */
   2 /*      $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $       */
   3 /*      $NetBSD$        */
   4
   5 #define CT_DEBUG
   6 #define CT_IO_CONTROL_FLAGS     (CT_USE_CCSEQ | CT_FAST_INTR)
   7
   8 /*
   9  * [NetBSD for NEC PC-98 series]
  10  *  Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
  11  *      NetBSD/pc98 porting staff. All rights reserved.
  12  *
  13  *  Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
  14  *      Naofumi HONDA.  All rights reserved.
  15  *
  16  *  Redistribution and use in source and binary forms, with or without
  17  *  modification, are permitted provided that the following conditions
  18  *  are met:
  19  *  1. Redistributions of source code must retain the above copyright
  20  *     notice, this list of conditions and the following disclaimer.
  21  *  2. Redistributions in binary form must reproduce the above copyright
  22  *     notice, this list of conditions and the following disclaimer in the
  23  *     documentation and/or other materials provided with the distribution.
  24  *  3. The name of the author may not be used to endorse or promote products
  25  *     derived from this software without specific prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  29  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  30  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  31  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  32  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  33  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  36  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 #include "opt_ddb.h"
  41
  42 #include <sys/param.h>
  43 #include <sys/systm.h>
  44 #include <sys/kernel.h>
  45 #if defined(__FreeBSD__) && __FreeBSD_version > 500001
  46 #include <sys/bio.h>
  47 #endif  /* __ FreeBSD__ */
  48 #include <sys/buf.h>
  49 #include <sys/queue.h>
  50 #include <sys/malloc.h>
  51 #include <sys/errno.h>
  52
  53 #ifdef __NetBSD__
  54 #include <sys/device.h>
  55
  56 #include <machine/bus.h>
  57 #include <machine/intr.h>
  58
  59 #include <dev/scsipi/scsi_all.h>
  60 #include <dev/scsipi/scsipi_all.h>
  61 #include <dev/scsipi/scsiconf.h>
  62 #include <dev/scsipi/scsi_disk.h>
  63
  64 #include <machine/dvcfg.h>
  65 #include <machine/physio_proc.h>
  66
  67 #include <i386/Cbus/dev/scsi_low.h>
  68
  69 #include <dev/ic/wd33c93reg.h>
  70 #include <i386/Cbus/dev/ct/ctvar.h>
  71 #include <i386/Cbus/dev/ct/ct_machdep.h>
  72 #endif /* __NetBSD__ */
  73
  74 #ifdef __FreeBSD__
  75 #include <machine/clock.h>
  76 #include <machine/bus.h>
  77 #include <machine/dvcfg.h>
  78 #include <machine/physio_proc.h>
  79
  80 #include <cam/scsi/scsi_low.h>
  81
  82 #include <dev/ic/wd33c93reg.h>
  83 #include <dev/ct/ctvar.h>
  84 #include <dev/ct/ct_machdep.h>
  85 #endif /* __FreeBSD__ */
  86
  87 #define CT_NTARGETS             8
  88 #define CT_NLUNS                8
  89 #define CT_RESET_DEFAULT        2000
  90 #define CT_DELAY_MAX            (2 * 1000 * 1000)
  91 #define CT_DELAY_INTERVAL       (1)
  92
  93 /***************************************************
  94  * DEBUG
  95  ***************************************************/
  96 #ifdef  CT_DEBUG
  97 int ct_debug;
  98 #endif  /* CT_DEBUG */
  99
 100 /***************************************************
 101  * IO control
 102  ***************************************************/
 103 #define CT_USE_CCSEQ    0x0100
 104 #define CT_FAST_INTR    0x0200
 105
 106 u_int ct_io_control = CT_IO_CONTROL_FLAGS;
 107
 108 /***************************************************
 109  * default data
 110  ***************************************************/
 111 u_int8_t cthw_cmdlevel[256] = {
 112 /*   0  1   2   3   4   5   6   7   8   9   A   B   C   E   D   F */
 113 /*0*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,1  ,0  ,1  ,0  ,0  ,0  ,0  ,0  ,
 114 /*1*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 115 /*2*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,1  ,0  ,1  ,0  ,0  ,0  ,0  ,0  ,
 116 /*3*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 117 /*4*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 118 /*5*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 119 /*6*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 120 /*7*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 121 /*8*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 122 /*9*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 123 /*A*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 124 /*B*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 125 /*C*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 126 /*D*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 127 /*E*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 128 /*F*/0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,0  ,
 129 };
 130
 131 #if     0
 132 /* default synch data table */
 133 /*  A  10    6.6   5.0   4.0   3.3   2.8   2.5   2.0  M/s */
 134 /*  X  100   150   200   250   300   350   400   500  ns  */
 135 static struct ct_synch_data ct_synch_data_FSCSI[] = {
 136         {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30},
 137         {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0}
 138 };
 139
 140 static struct ct_synch_data ct_synch_data_SCSI[] = {
 141         {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0}
 142 };
 143 #endif
 144 /***************************************************
 145  * DEVICE STRUCTURE
 146  ***************************************************/
 147 extern struct cfdriver ct_cd;
 148
 149 /*****************************************************************
 150  * Interface functions
 151  *****************************************************************/
 152 static int ct_xfer __P((struct ct_softc *, u_int8_t *, int, int, u_int *));
 153 static void ct_io_xfer __P((struct ct_softc *));
 154 static int ct_reselected __P((struct ct_softc *, u_int8_t));
 155 static void ct_phase_error __P((struct ct_softc *, u_int8_t));
 156 static int ct_start_selection __P((struct ct_softc *, struct slccb *));
 157 static int ct_msg __P((struct ct_softc *, struct targ_info *, u_int));
 158 static int ct_world_start __P((struct ct_softc *, int));
 159 static __inline void cthw_phase_bypass __P((struct ct_softc *, u_int8_t));
 160 static int cthw_chip_reset __P((struct ct_bus_access_handle *, int *, int, int));
 161 static void cthw_bus_reset __P((struct ct_softc *));
 162 static int ct_ccb_nexus_establish __P((struct ct_softc *));
 163 static int ct_lun_nexus_establish __P((struct ct_softc *));
 164 static int ct_target_nexus_establish __P((struct ct_softc *, int, int));
 165 static void cthw_attention __P((struct ct_softc *));
 166 static int ct_targ_init __P((struct ct_softc *, struct targ_info *, int));
 167 static int ct_unbusy __P((struct ct_softc *));
 168 static void ct_attention __P((struct ct_softc *));
 169 static struct ct_synch_data *ct_make_synch_table __P((struct ct_softc *));
 170 static int ct_catch_intr __P((struct ct_softc *));
 171
 172 struct scsi_low_funcs ct_funcs = {
 173         SC_LOW_INIT_T ct_world_start,
 174         SC_LOW_BUSRST_T cthw_bus_reset,
 175         SC_LOW_TARG_INIT_T ct_targ_init,
 176         SC_LOW_LUN_INIT_T NULL,
 177
 178         SC_LOW_SELECT_T ct_start_selection,
 179         SC_LOW_NEXUS_T ct_lun_nexus_establish,
 180         SC_LOW_NEXUS_T ct_ccb_nexus_establish,
 181
 182         SC_LOW_ATTEN_T cthw_attention,
 183         SC_LOW_MSG_T ct_msg,
 184
 185         SC_LOW_TIMEOUT_T NULL,
 186         SC_LOW_POLL_T ctintr,
 187
 188         NULL,   /* SC_LOW_POWER_T cthw_power, */
 189 };
 190
 191 /**************************************************
 192  * HW functions
 193  **************************************************/
 194 static __inline void
 195 cthw_phase_bypass(ct, ph)
 196         struct ct_softc *ct;
 197         u_int8_t ph;
 198 {
 199         struct ct_bus_access_handle *chp = &ct->sc_ch;
 200
 201         ct_cr_write_1(chp, wd3s_cph, ph);
 202         ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR);
 203 }
 204
 205 static void
 206 cthw_bus_reset(ct)
 207         struct ct_softc *ct;
 208 {
 209
 210         /*
 211          * wd33c93 does not have bus reset function.
 212          */
 213         if (ct->ct_bus_reset != NULL)
 214                 ((*ct->ct_bus_reset) (ct));
 215 }
 216
 217 static int
 218 cthw_chip_reset(chp, chiprevp, chipclk, hostid)
 219         struct ct_bus_access_handle *chp;
 220         int *chiprevp;
 221         int chipclk, hostid;
 222 {
 223 #define CT_SELTIMEOUT_20MHz_REGV        (0x80)
 224         u_int8_t aux, regv;
 225         u_int seltout;
 226         int wc;
 227
 228         /* issue abort cmd */
 229         ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT);
 230         SCSI_LOW_DELAY(1000);   /* 1ms wait */
 231         (void) ct_stat_read_1(chp);
 232         (void) ct_cr_read_1(chp, wd3s_stat);
 233
 234         /* setup chip registers */
 235         regv = 0;
 236         seltout = CT_SELTIMEOUT_20MHz_REGV;
 237         switch (chipclk)
 238         {
 239         case 8:
 240         case 10:
 241                 seltout = (seltout * chipclk) / 20;
 242                 regv = IDR_FS_8_10;
 243                 break;
 244
 245         case 12:
 246         case 15:
 247                 seltout = (seltout * chipclk) / 20;
 248                 regv = IDR_FS_12_15;
 249                 break;
 250
 251         case 16:
 252         case 20:
 253                 seltout = (seltout * chipclk) / 20;
 254                 regv = IDR_FS_16_20;
 255                 break;
 256
 257         default:
 258                 panic("ct: illegal chip clk rate\n");
 259                 break;
 260         }
 261
 262         regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF;
 263         ct_cr_write_1(chp, wd3s_oid, regv);
 264
 265         ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
 266         for (wc = CT_RESET_DEFAULT; wc > 0; wc --)
 267         {
 268                 aux = ct_stat_read_1(chp);
 269                 if (aux != 0xff && (aux & STR_INT))
 270                 {
 271                         regv = ct_cr_read_1(chp, wd3s_stat);
 272                         if (regv == BSR_RESET || regv == BSR_AFM_RESET)
 273                                 break;
 274
 275                         ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
 276                 }
 277                 SCSI_LOW_DELAY(1);
 278         }
 279         if (wc == 0)
 280                 return ENXIO;
 281
 282         ct_cr_write_1(chp, wd3s_tout, seltout);
 283         ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL);
 284         ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT);
 285         ct_cr_write_1(chp, wd3s_synch, 0);
 286         if (chiprevp != NULL)
 287         {
 288                 *chiprevp = CT_WD33C93;
 289                 if (regv == BSR_RESET)
 290                         goto out;
 291
 292                 *chiprevp = CT_WD33C93_A;
 293                 ct_cr_write_1(chp, wd3s_qtag, 0xaa);
 294                 if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa)
 295                 {
 296                         ct_cr_write_1(chp, wd3s_qtag, 0x0);
 297                         goto out;
 298                 }
 299                 ct_cr_write_1(chp, wd3s_qtag, 0x55);
 300                 if (ct_cr_read_1(chp, wd3s_qtag) != 0x55)
 301                 {
 302                         ct_cr_write_1(chp, wd3s_qtag, 0x0);
 303                         goto out;
 304                 }
 305                 ct_cr_write_1(chp, wd3s_qtag, 0x0);
 306                 *chiprevp = CT_WD33C93_B;
 307         }
 308
 309 out:
 310         (void) ct_stat_read_1(chp);
 311         (void) ct_cr_read_1(chp, wd3s_stat);
 312         return 0;
 313 }
 314
 315 static struct ct_synch_data *
 316 ct_make_synch_table(ct)
 317         struct ct_softc *ct;
 318 {
 319         struct ct_synch_data *sdtp, *sdp;
 320         u_int base, i, period;
 321
 322         sdtp = sdp = &ct->sc_default_sdt[0];
 323
 324         if ((ct->sc_chipclk % 5) == 0)
 325                 base = 1000 / (5 * 2);  /* 5 MHz type */
 326         else
 327                 base = 1000 / (4 * 2);  /* 4 MHz type */
 328
 329         if (ct->sc_chiprev >= CT_WD33C93_B)
 330         {
 331                 /* fast scsi */
 332                 for (i = 2; i < 8; i ++, sdp ++)
 333                 {
 334                         period = (base * i) / 2;
 335                         if (period >= 200)      /* 5 MHz */
 336                                 break;
 337                         sdp->cs_period = period / 4;
 338                         sdp->cs_syncr = (i * 0x10) | 0x80;
 339                 }
 340         }
 341
 342         for (i = 2; i < 8; i ++, sdp ++)
 343         {
 344                 period = (base * i);
 345                 if (period > 500)               /* 2 MHz */
 346                         break;
 347                 sdp->cs_period = period / 4;
 348                 sdp->cs_syncr = (i * 0x10);
 349         }
 350
 351         sdp->cs_period = 0;
 352         sdp->cs_syncr = 0;
 353         return sdtp;
 354 }
 355
 356 /**************************************************
 357  * Attach & Probe
 358  **************************************************/
 359 int
 360 ctprobesubr(chp, dvcfg, hsid, chipclk, chiprevp)
 361         struct ct_bus_access_handle *chp;
 362         u_int dvcfg, chipclk;
 363         int hsid;
 364         int *chiprevp;
 365 {
 366
 367 #if     0
 368         if ((ct_stat_read_1(chp) & STR_BSY) != 0)
 369                 return 0;
 370 #endif
 371         if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0)
 372                 return 0;
 373         return 1;
 374 }
 375
 376 int
 377 ctprint(aux, name)
 378         void *aux;
 379         const char *name;
 380 {
 381
 382         if (name != NULL)
 383                 printf("%s: scsibus ", name);
 384         return UNCONF;
 385 }
 386
 387 void
 388 ctattachsubr(ct)
 389         struct ct_softc *ct;
 390 {
 391         struct scsi_low_softc *slp = &ct->sc_sclow;
 392
 393         ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
 394         slp->sl_funcs = &ct_funcs;
 395         slp->sl_flags |= HW_READ_PADDING;
 396         (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS,
 397                                sizeof(struct ct_targ_info), 0);
 398 }
 399
 400 /**************************************************
 401  * SCSI LOW interface functions
 402  **************************************************/
 403 static void
 404 cthw_attention(ct)
 405         struct ct_softc *ct;
 406 {
 407         struct ct_bus_access_handle *chp = &ct->sc_ch;
 408
 409         ct->sc_atten = 1;
 410         if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0)
 411                 return;
 412
 413         ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN);
 414         SCSI_LOW_DELAY(10);
 415         if ((ct_stat_read_1(chp) & STR_LCI) == 0)
 416                 ct->sc_atten = 0;
 417         ct_unbusy(ct);
 418         return;
 419 }
 420
 421 static void
 422 ct_attention(ct)
 423         struct ct_softc *ct;
 424 {
 425         struct scsi_low_softc *slp = &ct->sc_sclow;
 426
 427         if (slp->sl_atten == 0)
 428         {
 429                 ct_unbusy(ct);
 430                 scsi_low_attention(slp);
 431         }
 432         else if (ct->sc_atten != 0)
 433         {
 434                 ct_unbusy(ct);
 435                 cthw_attention(ct);
 436         }
 437 }
 438
 439 static int
 440 ct_targ_init(ct, ti, action)
 441         struct ct_softc *ct;
 442         struct targ_info *ti;
 443         int action;
 444 {
 445         struct ct_targ_info *cti = (void *) ti;
 446
 447         if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
 448         {
 449                 if (ct->sc_sdp == NULL)
 450                 {
 451                         ct->sc_sdp = ct_make_synch_table(ct);
 452                 }
 453
 454                 switch (ct->sc_chiprev)
 455                 {
 456                 default:
 457                         ti->ti_maxsynch.offset = 5;
 458                         break;
 459
 460                 case CT_WD33C93_A:
 461                 case CT_AM33C93_A:
 462                         ti->ti_maxsynch.offset = 12;
 463                         break;
 464
 465                 case CT_WD33C93_B:
 466                 case CT_WD33C93_C:
 467                         ti->ti_maxsynch.offset = 12;
 468                         break;
 469                 }
 470
 471                 ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period;
 472                 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
 473                 cti->cti_syncreg = 0;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int
 480 ct_world_start(ct, fdone)
 481         struct ct_softc *ct;
 482         int fdone;
 483 {
 484         struct scsi_low_softc *slp = &ct->sc_sclow;
 485         struct ct_bus_access_handle *chp = &ct->sc_ch;
 486
 487         if (ct->sc_sdp == NULL)
 488         {
 489                 ct->sc_sdp = ct_make_synch_table(ct);
 490         }
 491
 492         if (slp->sl_cfgflags & CFG_NOPARITY)
 493                 ct->sc_creg = CR_DEFAULT;
 494         else
 495                 ct->sc_creg = CR_DEFAULT_HP;
 496
 497         if (ct->sc_dma & CT_DMA_DMASTART)
 498                 (*ct->ct_dma_xfer_stop) (ct);
 499         if (ct->sc_dma & CT_DMA_PIOSTART)
 500                 (*ct->ct_pio_xfer_stop) (ct);
 501         ct->sc_dma = 0;
 502         ct->sc_atten = 0;
 503
 504         cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
 505         scsi_low_bus_reset(slp);
 506         cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
 507
 508         SOFT_INTR_REQUIRED(slp);
 509         return 0;
 510 }
 511
 512 static int
 513 ct_start_selection(ct, cb)
 514         struct ct_softc *ct;
 515         struct slccb *cb;
 516 {
 517         struct scsi_low_softc *slp = &ct->sc_sclow;
 518         struct ct_bus_access_handle *chp = &ct->sc_ch;
 519
 520         struct targ_info *ti = slp->sl_Tnexus;
 521         struct lun_info *li = slp->sl_Lnexus;
 522         int s, satok;
 523         u_int8_t cmd;
 524
 525         ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
 526         ct->sc_atten = 0;
 527         satok = 0;
 528
 529         if (scsi_low_is_disconnect_ok(cb) != 0)
 530         {
 531                 if (ct->sc_chiprev >= CT_WD33C93_A)
 532                         satok = 1;
 533                 else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0)
 534                         satok = 1;
 535         }
 536
 537         if (satok != 0 &&
 538             scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0)
 539         {
 540                 cmd = WD3S_SELECT_ATN_TFR;
 541                 ct->sc_satgo = CT_SAT_GOING;
 542         }
 543         else
 544         {
 545                 cmd = WD3S_SELECT_ATN;
 546                 ct->sc_satgo = 0;
 547         }
 548
 549         if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0)
 550                 return SCSI_LOW_START_FAIL;
 551
 552         if ((ct->sc_satgo & CT_SAT_GOING) != 0)
 553         {
 554                 (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT);
 555                 scsi_low_cmd(slp, ti);
 556                 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
 557                 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
 558         }
 559         else
 560         {
 561                 /* anyway attention assert */
 562                 SCSI_LOW_ASSERT_ATN(slp);
 563         }
 564
 565         ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction);
 566
 567         s = splhigh();
 568         if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0)
 569         {
 570                 /* XXX:
 571                  * Reload a lun again here.
 572                  */
 573                 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
 574                 ct_cr_write_1(chp, wd3s_cmd, cmd);
 575                 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
 576                 {
 577                         splx(s);
 578                         SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
 579                         return SCSI_LOW_START_OK;
 580                 }
 581         }
 582         splx(s);
 583         return SCSI_LOW_START_FAIL;
 584 }
 585
 586 static int
 587 ct_msg(ct, ti, msg)
 588         struct ct_softc *ct;
 589         struct targ_info *ti;
 590         u_int msg;
 591 {
 592         struct ct_bus_access_handle *chp = &ct->sc_ch;
 593         struct ct_targ_info *cti = (void *) ti;
 594         struct ct_synch_data *csp = ct->sc_sdp;
 595         u_int offset, period;
 596         int error;
 597
 598         if ((msg & SCSI_LOW_MSG_WIDE) != 0)
 599         {
 600                 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
 601                 {
 602                         ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
 603                         return EINVAL;
 604                 }
 605                 return 0;
 606         }
 607
 608         if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
 609                 return 0;
 610
 611         offset = ti->ti_maxsynch.offset;
 612         period = ti->ti_maxsynch.period;
 613         for ( ; csp->cs_period != 0; csp ++)
 614         {
 615                 if (period == csp->cs_period)
 616                         break;
 617         }
 618
 619         if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0)
 620         {
 621                 ti->ti_maxsynch.period = 0;
 622                 ti->ti_maxsynch.offset = 0;
 623                 cti->cti_syncreg = 0;
 624                 error = EINVAL;
 625         }
 626         else
 627         {
 628                 cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr);
 629                 error = 0;
 630         }
 631
 632         if (ct->ct_synch_setup != 0)
 633                 (*ct->ct_synch_setup) (ct, ti);
 634         ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
 635         return error;
 636 }
 637
 638 /*************************************************
 639  * <DATA PHASE>
 640  *************************************************/
 641 static int
 642 ct_xfer(ct, data, len, direction, statp)
 643         struct ct_softc *ct;
 644         u_int8_t *data;
 645         int len, direction;
 646         u_int *statp;
 647 {
 648         struct ct_bus_access_handle *chp = &ct->sc_ch;
 649         int wc;
 650         register u_int8_t aux;
 651
 652         *statp = 0;
 653         if (len == 1)
 654         {
 655                 ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
 656         }
 657         else
 658         {
 659                 cthw_set_count(chp, len);
 660                 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
 661         }
 662
 663         aux = ct_stat_read_1(chp);
 664         if ((aux & STR_LCI) != 0)
 665         {
 666                 cthw_set_count(chp, 0);
 667                 return len;
 668         }
 669
 670         for (wc = 0; wc < ct->sc_tmaxcnt; wc ++)
 671         {
 672                 /* check data ready */
 673                 if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR))
 674                 {
 675                         if (direction == SCSI_LOW_READ)
 676                         {
 677                                 *data = ct_cr_read_1(chp, wd3s_data);
 678                                 if ((aux & STR_PE) != 0)
 679                                         *statp |= SCSI_LOW_DATA_PE;
 680                         }
 681                         else
 682                         {
 683                                 ct_cr_write_1(chp, wd3s_data, *data);
 684                         }
 685                         len --;
 686                         if (len <= 0)
 687                                 break;
 688                         data ++;
 689                 }
 690                 else
 691                 {
 692                         SCSI_LOW_DELAY(1);
 693                 }
 694
 695                 /* check phase miss */
 696                 aux = ct_stat_read_1(chp);
 697                 if ((aux & STR_INT) != 0)
 698                         break;
 699         }
 700         return len;
 701 }
 702
 703 #define CT_PADDING_BUF_SIZE 32
 704
 705 static void
 706 ct_io_xfer(ct)
 707         struct ct_softc *ct;
 708 {
 709         struct scsi_low_softc *slp = &ct->sc_sclow;
 710         struct ct_bus_access_handle *chp = &ct->sc_ch;
 711         struct sc_p *sp = &slp->sl_scp;
 712         u_int stat;
 713         int len;
 714         u_int8_t pbuf[CT_PADDING_BUF_SIZE];
 715
 716         /* polling mode */
 717         ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg);
 718
 719         if (sp->scp_datalen <= 0)
 720         {
 721                 slp->sl_error |= PDMAERR;
 722
 723                 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
 724                         SCSI_LOW_BZERO(pbuf, CT_PADDING_BUF_SIZE);
 725                 ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE,
 726                         sp->scp_direction, &stat);
 727         }
 728         else
 729         {
 730                 len = ct_xfer(ct, sp->scp_data, sp->scp_datalen,
 731                               sp->scp_direction, &stat);
 732                 sp->scp_data += (sp->scp_datalen - len);
 733                 sp->scp_datalen = len;
 734         }
 735 }
 736
 737 /**************************************************
 738  * <PHASE ERROR>
 739  **************************************************/
 740 struct ct_err {
 741         u_char  *pe_msg;
 742         u_int   pe_err;
 743         u_int   pe_errmsg;
 744         int     pe_done;
 745 };
 746
 747 struct ct_err ct_cmderr[] = {
 748 /*0*/   { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1},
 749 /*1*/   { "unexpected bus free", FATALIO, 0, 1},
 750 /*2*/   { NULL, SELTIMEOUTIO, 0, 1},
 751 /*3*/   { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
 752 /*4*/   { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
 753 /*5*/   { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1},
 754 /*6*/   { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0},
 755 /*7*/   { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
 756 };
 757
 758 static void
 759 ct_phase_error(ct, scsi_status)
 760         struct ct_softc *ct;
 761         u_int8_t scsi_status;
 762 {
 763         struct scsi_low_softc *slp = &ct->sc_sclow;
 764         struct targ_info *ti = slp->sl_Tnexus;
 765         struct ct_err *pep;
 766         u_int msg = 0;
 767
 768         if ((scsi_status & BSR_CM) == BSR_CMDERR &&
 769             (scsi_status & BSR_PHVALID) == 0)
 770         {
 771                 pep = &ct_cmderr[scsi_status & BSR_PM];
 772                 slp->sl_error |= pep->pe_err;
 773                 if ((pep->pe_err & PARITYERR) != 0)
 774                 {
 775                         if (ti->ti_phase == PH_MSGIN)
 776                                 msg = SCSI_LOW_MSG_PARITY;
 777                         else
 778                                 msg = SCSI_LOW_MSG_ERROR;
 779                 }
 780                 else
 781                         msg = pep->pe_errmsg;
 782
 783                 if (msg != 0)
 784                         scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1);
 785
 786                 if (pep->pe_msg != NULL)
 787                 {
 788                         printf("%s: phase error: %s",
 789                                 slp->sl_xname, pep->pe_msg);
 790                         scsi_low_print(slp, slp->sl_Tnexus);
 791                 }
 792
 793                 if (pep->pe_done != 0)
 794                         scsi_low_disconnected(slp, ti);
 795         }
 796         else
 797         {
 798                 slp->sl_error |= FATALIO;
 799                 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error");
 800         }
 801 }
 802
 803 /**************************************************
 804  * ### SCSI PHASE SEQUENCER ###
 805  **************************************************/
 806 static int
 807 ct_reselected(ct, scsi_status)
 808         struct ct_softc *ct;
 809         u_int8_t scsi_status;
 810 {
 811         struct scsi_low_softc *slp = &ct->sc_sclow;
 812         struct ct_bus_access_handle *chp = &ct->sc_ch;
 813         struct targ_info *ti;
 814         u_int sid;
 815         u_int8_t regv;
 816
 817         ct->sc_atten = 0;
 818         ct->sc_satgo &= ~CT_SAT_GOING;
 819         regv = ct_cr_read_1(chp, wd3s_sid);
 820         if ((regv & SIDR_VALID) == 0)
 821                 return EJUSTRETURN;
 822
 823         sid = regv & SIDR_IDM;
 824         if ((ti = scsi_low_reselected(slp, sid)) == NULL)
 825                 return EJUSTRETURN;
 826
 827         ct_target_nexus_establish(ct, 0, SCSI_LOW_READ);
 828         if (scsi_status != BSR_AFM_RESEL)
 829                 return EJUSTRETURN;
 830
 831         SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
 832         regv = ct_cr_read_1(chp, wd3s_data);
 833         if (scsi_low_msgin(slp, ti, (u_int) regv) == 0)
 834         {
 835                 if (scsi_low_is_msgout_continue(ti, 0) != 0)
 836                 {
 837                         /* XXX: scsi_low_attetion */
 838                         scsi_low_attention(slp);
 839                 }
 840         }
 841
 842         if (ct->sc_atten != 0)
 843         {
 844                 ct_attention(ct);
 845         }
 846
 847         ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
 848         return EJUSTRETURN;
 849 }
 850
 851 static int
 852 ct_target_nexus_establish(ct, lun, dir)
 853         struct ct_softc *ct;
 854         int lun, dir;
 855 {
 856         struct scsi_low_softc *slp = &ct->sc_sclow;
 857         struct ct_bus_access_handle *chp = &ct->sc_ch;
 858         struct targ_info *ti = slp->sl_Tnexus;
 859         struct ct_targ_info *cti = (void *) ti;
 860
 861         if (dir == SCSI_LOW_WRITE)
 862                 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
 863         else
 864                 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
 865         ct_cr_write_1(chp, wd3s_lun, lun);
 866         ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
 867         ct_cr_write_1(chp, wd3s_cph, 0);
 868         ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
 869         cthw_set_count(chp, 0);
 870         return 0;
 871 }
 872
 873 static int
 874 ct_lun_nexus_establish(ct)
 875         struct ct_softc *ct;
 876 {
 877         struct scsi_low_softc *slp = &ct->sc_sclow;
 878         struct ct_bus_access_handle *chp = &ct->sc_ch;
 879         struct lun_info *li = slp->sl_Lnexus;
 880
 881         ct_cr_write_1(chp, wd3s_lun, li->li_lun);
 882         return 0;
 883 }
 884
 885 static int
 886 ct_ccb_nexus_establish(ct)
 887         struct ct_softc *ct;
 888 {
 889         struct scsi_low_softc *slp = &ct->sc_sclow;
 890         struct ct_bus_access_handle *chp = &ct->sc_ch;
 891         struct lun_info *li = slp->sl_Lnexus;
 892         struct targ_info *ti = slp->sl_Tnexus;
 893         struct ct_targ_info *cti = (void *) ti;
 894         struct slccb *cb = slp->sl_Qnexus;
 895
 896         ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
 897
 898         if ((ct->sc_satgo & CT_SAT_GOING) != 0)
 899         {
 900                 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
 901                 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
 902         }
 903         if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
 904                 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
 905         else
 906                 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
 907         ct_cr_write_1(chp, wd3s_lun, li->li_lun);
 908         ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
 909         return 0;
 910 }
 911
 912 static int
 913 ct_unbusy(ct)
 914         struct ct_softc *ct;
 915 {
 916         struct scsi_low_softc *slp = &ct->sc_sclow;
 917         struct ct_bus_access_handle *chp = &ct->sc_ch;
 918         int wc;
 919         register u_int8_t regv;
 920
 921         for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
 922         {
 923                 regv = ct_stat_read_1(chp);
 924                 if ((regv & (STR_BSY | STR_CIP)) == 0)
 925                         return 0;
 926                 if (regv == (u_int8_t) -1)
 927                         return EIO;
 928
 929                 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
 930         }
 931
 932         printf("%s: unbusy timeout\n", slp->sl_xname);
 933         return EBUSY;
 934 }
 935
 936 static int
 937 ct_catch_intr(ct)
 938         struct ct_softc *ct;
 939 {
 940         struct ct_bus_access_handle *chp = &ct->sc_ch;
 941         int wc;
 942         register u_int8_t regv;
 943
 944         for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
 945         {
 946                 regv = ct_stat_read_1(chp);
 947                 if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT)
 948                         return 0;
 949
 950                 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
 951         }
 952         return EJUSTRETURN;
 953 }
 954
 955 int
 956 ctintr(arg)
 957         void *arg;
 958 {
 959         struct ct_softc *ct = arg;
 960         struct scsi_low_softc *slp = &ct->sc_sclow;
 961         struct ct_bus_access_handle *chp = &ct->sc_ch;
 962         struct targ_info *ti;
 963         struct physio_proc *pp;
 964         struct buf *bp;
 965         u_int derror, flags;
 966         int len, satgo, error;
 967         u_int8_t scsi_status, regv;
 968
 969 again:
 970         if (slp->sl_flags & HW_INACTIVE)
 971                 return 0;
 972
 973         /**************************************************
 974          * Get status & bus phase
 975          **************************************************/
 976         if ((ct_stat_read_1(chp) & STR_INT) == 0)
 977                 return 0;
 978
 979         scsi_status = ct_cr_read_1(chp, wd3s_stat);
 980         if (scsi_status == ((u_int8_t) -1))
 981                 return 1;
 982
 983         /**************************************************
 984          * Check reselection, or nexus
 985          **************************************************/
 986         if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL)
 987         {
 988                 if (ct_reselected(ct, scsi_status) == EJUSTRETURN)
 989                         return 1;
 990         }
 991
 992         if ((ti = slp->sl_Tnexus) == NULL)
 993                 return 1;
 994
 995         /**************************************************
 996          * Debug section
 997          **************************************************/
 998 #ifdef  CT_DEBUG
 999         if (ct_debug > 0)
1000         {
1001                 scsi_low_print(slp, NULL);
1002                 printf("%s: scsi_status 0x%x\n\n", slp->sl_xname,
1003                        (u_int) scsi_status);
1004 #ifdef  DDB
1005                 if (ct_debug > 1)
1006                         SCSI_LOW_DEBUGGER("ct");
1007 #endif  /* DDB */
1008         }
1009 #endif  /* CT_DEBUG */
1010
1011         /**************************************************
1012          * Internal scsi phase
1013          **************************************************/
1014         satgo = ct->sc_satgo;
1015         ct->sc_satgo &= ~CT_SAT_GOING;
1016
1017         switch (ti->ti_phase)
1018         {
1019         case PH_SELSTART:
1020                 if ((satgo & CT_SAT_GOING) == 0)
1021                 {
1022                         if (scsi_status != BSR_SELECTED)
1023                         {
1024                                 ct_phase_error(ct, scsi_status);
1025                                 return 1;
1026                         }
1027                         scsi_low_arbit_win(slp);
1028                         SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
1029                         return 1;
1030                 }
1031                 else
1032                 {
1033                         scsi_low_arbit_win(slp);
1034                         SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */
1035                 }
1036                 break;
1037
1038         case PH_RESEL:
1039                 if ((scsi_status & BSR_PHVALID) == 0 ||
1040                     (scsi_status & BSR_PM) != BSR_MSGIN)
1041                 {
1042                         scsi_low_restart(slp, SCSI_LOW_RESTART_HARD,
1043                                  "phase miss after reselect");
1044                         return 1;
1045                 }
1046                 break;
1047
1048         default:
1049                 if (slp->sl_flags & HW_PDMASTART)
1050                 {
1051                         slp->sl_flags &= ~HW_PDMASTART;
1052                         if (ct->sc_dma & CT_DMA_DMASTART)
1053                         {
1054                                 (*ct->ct_dma_xfer_stop) (ct);
1055                                 ct->sc_dma &= ~CT_DMA_DMASTART;
1056                         }
1057                         else if (ct->sc_dma & CT_DMA_PIOSTART)
1058                         {
1059                                 (*ct->ct_pio_xfer_stop) (ct);
1060                                 ct->sc_dma &= ~CT_DMA_PIOSTART;
1061                         }
1062                         else
1063                         {
1064                                 scsi_low_data_finish(slp);
1065                         }
1066                 }
1067                 break;
1068         }
1069
1070         /**************************************************
1071          * parse scsi phase
1072          **************************************************/
1073         if (scsi_status & BSR_PHVALID)
1074         {
1075                 /**************************************************
1076                  * Normal SCSI phase.
1077                  **************************************************/
1078                 if ((scsi_status & BSR_CM) == BSR_CMDABT)
1079                 {
1080                         ct_phase_error(ct, scsi_status);
1081                         return 1;
1082                 }
1083
1084                 switch (scsi_status & BSR_PM)
1085                 {
1086                 case BSR_DATAOUT:
1087                         SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1088                         if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
1089                         {
1090                                 ct_attention(ct);
1091                         }
1092                         goto common_data_phase;
1093
1094                 case BSR_DATAIN:
1095                         SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1096                         if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
1097                         {
1098                                 ct_attention(ct);
1099                         }
1100
1101 common_data_phase:
1102                         if (slp->sl_scp.scp_datalen > 0)
1103                         {
1104                                 slp->sl_flags |= HW_PDMASTART;
1105                                 if ((ct->sc_xmode & CT_XMODE_PIO) != 0)
1106                                 {
1107                                         pp = physio_proc_enter(bp);
1108                                         error = (*ct->ct_pio_xfer_start) (ct);
1109                                         physio_proc_leave(pp);
1110                                         if (error == 0)
1111                                         {
1112                                                 ct->sc_dma |= CT_DMA_PIOSTART;
1113                                                 return 1;
1114                                         }
1115                                 }
1116
1117                                 if ((ct->sc_xmode & CT_XMODE_DMA) != 0)
1118                                 {
1119                                         error = (*ct->ct_dma_xfer_start) (ct);
1120                                         if (error == 0)
1121                                         {
1122                                                 ct->sc_dma |= CT_DMA_DMASTART;
1123                                                 return 1;
1124                                         }
1125                                 }
1126                         }
1127                         else
1128                         {
1129                                 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
1130                                 {
1131                                         if (!(slp->sl_flags & HW_READ_PADDING))
1132                                         {
1133                                                 printf("%s: read padding required\n", slp->sl_xname);
1134                                                 return 1;
1135                                         }
1136                                 }
1137                                 else
1138                                 {
1139                                         if (!(slp->sl_flags & HW_WRITE_PADDING))
1140                                         {
1141                                                 printf("%s: write padding required\n", slp->sl_xname);
1142                                                 return 1;
1143                                         }
1144                                 }
1145                                 slp->sl_flags |= HW_PDMASTART;
1146                         }
1147
1148                         ct_io_xfer(ct);
1149                         return 1;
1150
1151                 case BSR_CMDOUT:
1152                         SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
1153                         if (scsi_low_cmd(slp, ti) != 0)
1154                         {
1155                                 ct_attention(ct);
1156                         }
1157
1158                         if (ct_xfer(ct, slp->sl_scp.scp_cmd,
1159                                     slp->sl_scp.scp_cmdlen,
1160                                     SCSI_LOW_WRITE, &derror) != 0)
1161                         {
1162                                 printf("%s: scsi cmd xfer short\n",
1163                                         slp->sl_xname);
1164                         }
1165                         return 1;
1166
1167                 case BSR_STATIN:
1168                         SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1169                         if ((ct_io_control & CT_USE_CCSEQ) != 0)
1170                         {
1171                                 if (scsi_low_is_msgout_continue(ti, 0) != 0 ||
1172                                     ct->sc_atten != 0)
1173                                 {
1174                                         ct_xfer(ct, &regv, 1, SCSI_LOW_READ,
1175                                                 &derror);
1176                                         scsi_low_statusin(slp, ti,
1177                                                           regv | derror);
1178                                 }
1179                                 else
1180                                 {
1181                                         ct->sc_satgo |= CT_SAT_GOING;
1182                                         cthw_set_count(chp, 0);
1183                                         cthw_phase_bypass(ct, 0x41);
1184                                 }
1185                         }
1186                         else
1187                         {
1188                                 ct_xfer(ct, &regv, 1, SCSI_LOW_READ, &derror);
1189                                 scsi_low_statusin(slp, ti, regv | derror);
1190                         }
1191                         return 1;
1192
1193                 case BSR_UNSPINFO0:
1194                 case BSR_UNSPINFO1:
1195                         printf("%s: illegal bus phase (0x%x)\n", slp->sl_xname,
1196                                 (u_int) scsi_status);
1197                         scsi_low_print(slp, ti);
1198                         return 1;
1199
1200                 case BSR_MSGOUT:
1201                         SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
1202                         flags = SCSI_LOW_MSGOUT_UNIFY;
1203                         if (ti->ti_ophase != ti->ti_phase)
1204                                 flags |= SCSI_LOW_MSGOUT_INIT;
1205                         len = scsi_low_msgout(slp, ti, flags);
1206
1207                         if (len > 1 && slp->sl_atten == 0)
1208                         {
1209                                 ct_attention(ct);
1210                         }
1211
1212                         if (ct_xfer(ct, ti->ti_msgoutstr, len,
1213                                     SCSI_LOW_WRITE, &derror) != 0)
1214                         {
1215                                 printf("%s: scsi msgout xfer short\n",
1216                                         slp->sl_xname);
1217                         }
1218                         SCSI_LOW_DEASSERT_ATN(slp);
1219                         ct->sc_atten = 0;
1220                         return 1;
1221
1222                 case BSR_MSGIN:/* msg in */
1223                         SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1224
1225                         ct_xfer(ct, &regv, 1, SCSI_LOW_READ, &derror);
1226                         if (scsi_low_msgin(slp, ti, regv | derror) == 0)
1227                         {
1228                                 if (scsi_low_is_msgout_continue(ti, 0) != 0)
1229                                 {
1230                                         /* XXX: scsi_low_attetion */
1231                                         scsi_low_attention(slp);
1232                                 }
1233                         }
1234
1235                         if ((ct_io_control & CT_FAST_INTR) != 0)
1236                         {
1237                                 if (ct_catch_intr(ct) == 0)
1238                                         goto again;
1239                         }
1240                         return 1;
1241                 }
1242         }
1243         else
1244         {
1245                 /**************************************************
1246                  * Special SCSI phase
1247                  **************************************************/
1248                 switch (scsi_status)
1249                 {
1250                 case BSR_SATSDP: /* SAT with save data pointer */
1251                         SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1252                         ct->sc_satgo |= CT_SAT_GOING;
1253                         scsi_low_msgin(slp, ti, MSG_SAVESP);
1254                         cthw_phase_bypass(ct, 0x41);
1255                         return 1;
1256
1257                 case BSR_SATFIN: /* SAT COMPLETE */
1258                         /*
1259                          * emulate statusin => msgin
1260                          */
1261                         SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1262                         scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun));
1263
1264                         SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1265                         scsi_low_msgin(slp, ti, MSG_COMP);
1266
1267                         scsi_low_disconnected(slp, ti);
1268                         return 1;
1269
1270                 case BSR_ACKREQ: /* negate ACK */
1271                         if (ct->sc_atten != 0)
1272                         {
1273                                 ct_attention(ct);
1274                         }
1275
1276                         ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
1277                         if ((ct_io_control & CT_FAST_INTR) != 0)
1278                         {
1279                                 /* XXX:
1280                                  * Should clear a pending interrupt and
1281                                  * sync with a next interrupt!
1282                                  */
1283                                 ct_catch_intr(ct);
1284                         }
1285                         return 1;
1286
1287                 case BSR_DISC: /* disconnect */
1288                         if (slp->sl_msgphase == MSGPH_NULL &&
1289                             (satgo & CT_SAT_GOING) != 0)
1290                         {
1291                                 /*
1292                                  * emulate disconnect msg
1293                                  */
1294                                 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1295                                 scsi_low_msgin(slp, ti, MSG_DISCON);
1296                         }
1297                         scsi_low_disconnected(slp, ti);
1298                         return 1;
1299
1300                 default:
1301                         break;
1302                 }
1303         }
1304
1305         ct_phase_error(ct, scsi_status);
1306         return 1;
1307 }