1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 * Gareth Hughes <gareth@valinux.com>
34 * $FreeBSD: src/sys/dev/drm/mga_state.c,v 1.6.2.1 2003/04/26 07:05:29 anholt Exp $
37 #include "dev/drm/mga.h"
38 #include "dev/drm/drmP.h"
39 #include "dev/drm/drm.h"
40 #include "dev/drm/mga_drm.h"
41 #include "dev/drm/mga_drv.h"
44 /* ================================================================
45 * DMA hardware state programming functions
48 static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
49 drm_clip_rect_t *box )
51 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
52 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
53 unsigned int pitch = dev_priv->front_pitch;
58 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
60 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
61 DMA_BLOCK( MGA_DWGCTL, ctx->dwgctl,
62 MGA_LEN + MGA_EXEC, 0x80000000,
63 MGA_DWGCTL, ctx->dwgctl,
64 MGA_LEN + MGA_EXEC, 0x80000000 );
66 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
67 MGA_CXBNDRY, (box->x2 << 16) | box->x1,
68 MGA_YTOP, box->y1 * pitch,
69 MGA_YBOT, box->y2 * pitch );
74 static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv )
76 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
77 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
82 DMA_BLOCK( MGA_DSTORG, ctx->dstorg,
83 MGA_MACCESS, ctx->maccess,
84 MGA_PLNWT, ctx->plnwt,
85 MGA_DWGCTL, ctx->dwgctl );
87 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl,
88 MGA_FOGCOL, ctx->fogcolor,
89 MGA_WFLAG, ctx->wflag,
90 MGA_ZORG, dev_priv->depth_offset );
92 DMA_BLOCK( MGA_FCOL, ctx->fcol,
93 MGA_DMAPAD, 0x00000000,
94 MGA_DMAPAD, 0x00000000,
95 MGA_DMAPAD, 0x00000000 );
100 static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv )
102 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
103 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
108 DMA_BLOCK( MGA_DSTORG, ctx->dstorg,
109 MGA_MACCESS, ctx->maccess,
110 MGA_PLNWT, ctx->plnwt,
111 MGA_DWGCTL, ctx->dwgctl );
113 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl,
114 MGA_FOGCOL, ctx->fogcolor,
115 MGA_WFLAG, ctx->wflag,
116 MGA_ZORG, dev_priv->depth_offset );
118 DMA_BLOCK( MGA_WFLAG1, ctx->wflag,
119 MGA_TDUALSTAGE0, ctx->tdualstage0,
120 MGA_TDUALSTAGE1, ctx->tdualstage1,
121 MGA_FCOL, ctx->fcol );
123 DMA_BLOCK( MGA_STENCIL, ctx->stencil,
124 MGA_STENCILCTL, ctx->stencilctl,
125 MGA_DMAPAD, 0x00000000,
126 MGA_DMAPAD, 0x00000000 );
131 static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
133 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
134 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
139 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2,
140 MGA_TEXCTL, tex->texctl,
141 MGA_TEXFILTER, tex->texfilter,
142 MGA_TEXBORDERCOL, tex->texbordercol );
144 DMA_BLOCK( MGA_TEXORG, tex->texorg,
145 MGA_TEXORG1, tex->texorg1,
146 MGA_TEXORG2, tex->texorg2,
147 MGA_TEXORG3, tex->texorg3 );
149 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
150 MGA_TEXWIDTH, tex->texwidth,
151 MGA_TEXHEIGHT, tex->texheight,
152 MGA_WR24, tex->texwidth );
154 DMA_BLOCK( MGA_WR34, tex->texheight,
155 MGA_TEXTRANS, 0x0000ffff,
156 MGA_TEXTRANSHIGH, 0x0000ffff,
157 MGA_DMAPAD, 0x00000000 );
162 static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
164 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
165 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
168 /* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
169 /* tex->texctl, tex->texctl2); */
173 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
174 MGA_TEXCTL, tex->texctl,
175 MGA_TEXFILTER, tex->texfilter,
176 MGA_TEXBORDERCOL, tex->texbordercol );
178 DMA_BLOCK( MGA_TEXORG, tex->texorg,
179 MGA_TEXORG1, tex->texorg1,
180 MGA_TEXORG2, tex->texorg2,
181 MGA_TEXORG3, tex->texorg3 );
183 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
184 MGA_TEXWIDTH, tex->texwidth,
185 MGA_TEXHEIGHT, tex->texheight,
186 MGA_WR49, 0x00000000 );
188 DMA_BLOCK( MGA_WR57, 0x00000000,
189 MGA_WR53, 0x00000000,
190 MGA_WR61, 0x00000000,
191 MGA_WR52, MGA_G400_WR_MAGIC );
193 DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC,
194 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
195 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
196 MGA_DMAPAD, 0x00000000 );
198 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
199 MGA_DMAPAD, 0x00000000,
200 MGA_TEXTRANS, 0x0000ffff,
201 MGA_TEXTRANSHIGH, 0x0000ffff );
206 static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
208 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
209 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
212 /* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
213 /* tex->texctl, tex->texctl2); */
217 DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 |
220 MGA_TEXCTL, tex->texctl,
221 MGA_TEXFILTER, tex->texfilter,
222 MGA_TEXBORDERCOL, tex->texbordercol );
224 DMA_BLOCK( MGA_TEXORG, tex->texorg,
225 MGA_TEXORG1, tex->texorg1,
226 MGA_TEXORG2, tex->texorg2,
227 MGA_TEXORG3, tex->texorg3 );
229 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
230 MGA_TEXWIDTH, tex->texwidth,
231 MGA_TEXHEIGHT, tex->texheight,
232 MGA_WR49, 0x00000000 );
234 DMA_BLOCK( MGA_WR57, 0x00000000,
235 MGA_WR53, 0x00000000,
236 MGA_WR61, 0x00000000,
237 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC );
239 DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
240 MGA_TEXTRANS, 0x0000ffff,
241 MGA_TEXTRANSHIGH, 0x0000ffff,
242 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC );
247 static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
249 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
250 unsigned int pipe = sarea_priv->warp_pipe;
255 DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND,
256 MGA_WVRTXSZ, 0x00000007,
257 MGA_WFLAG, 0x00000000,
258 MGA_WR24, 0x00000000 );
260 DMA_BLOCK( MGA_WR25, 0x00000100,
261 MGA_WR34, 0x00000000,
262 MGA_WR42, 0x0000ffff,
263 MGA_WR60, 0x0000ffff );
265 /* Padding required to to hardware bug.
267 DMA_BLOCK( MGA_DMAPAD, 0xffffffff,
268 MGA_DMAPAD, 0xffffffff,
269 MGA_DMAPAD, 0xffffffff,
270 MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
277 static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
279 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
280 unsigned int pipe = sarea_priv->warp_pipe;
283 /* printk("mga_g400_emit_pipe %x\n", pipe); */
287 DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND,
288 MGA_DMAPAD, 0x00000000,
289 MGA_DMAPAD, 0x00000000,
290 MGA_DMAPAD, 0x00000000 );
292 if ( pipe & MGA_T2 ) {
293 DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09,
294 MGA_DMAPAD, 0x00000000,
295 MGA_DMAPAD, 0x00000000,
296 MGA_DMAPAD, 0x00000000 );
298 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000,
299 MGA_WACCEPTSEQ, 0x00000000,
300 MGA_WACCEPTSEQ, 0x00000000,
301 MGA_WACCEPTSEQ, 0x1e000000 );
303 if ( dev_priv->warp_pipe & MGA_T2 ) {
304 /* Flush the WARP pipe */
305 DMA_BLOCK( MGA_YDST, 0x00000000,
306 MGA_FXLEFT, 0x00000000,
307 MGA_FXRIGHT, 0x00000001,
308 MGA_DWGCTL, MGA_DWGCTL_FLUSH );
310 DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001,
311 MGA_DWGSYNC, 0x00007000,
312 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
313 MGA_LEN + MGA_EXEC, 0x00000000 );
315 DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX |
317 MGA_LEN + MGA_EXEC, 0x00000000,
318 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
319 MGA_DMAPAD, 0x00000000 );
322 DMA_BLOCK( MGA_WVRTXSZ, 0x00001807,
323 MGA_DMAPAD, 0x00000000,
324 MGA_DMAPAD, 0x00000000,
325 MGA_DMAPAD, 0x00000000 );
327 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000,
328 MGA_WACCEPTSEQ, 0x00000000,
329 MGA_WACCEPTSEQ, 0x00000000,
330 MGA_WACCEPTSEQ, 0x18000000 );
333 DMA_BLOCK( MGA_WFLAG, 0x00000000,
334 MGA_WFLAG1, 0x00000000,
335 MGA_WR56, MGA_G400_WR56_MAGIC,
336 MGA_DMAPAD, 0x00000000 );
338 DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */
339 MGA_WR57, 0x00000000, /* tex0 */
340 MGA_WR53, 0x00000000, /* tex1 */
341 MGA_WR61, 0x00000000 ); /* tex1 */
343 DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
344 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
345 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
346 MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */
348 /* Padding required to to hardware bug */
349 DMA_BLOCK( MGA_DMAPAD, 0xffffffff,
350 MGA_DMAPAD, 0xffffffff,
351 MGA_DMAPAD, 0xffffffff,
352 MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
359 static void mga_g200_emit_state( drm_mga_private_t *dev_priv )
361 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
362 unsigned int dirty = sarea_priv->dirty;
364 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
365 mga_g200_emit_pipe( dev_priv );
366 dev_priv->warp_pipe = sarea_priv->warp_pipe;
369 if ( dirty & MGA_UPLOAD_CONTEXT ) {
370 mga_g200_emit_context( dev_priv );
371 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
374 if ( dirty & MGA_UPLOAD_TEX0 ) {
375 mga_g200_emit_tex0( dev_priv );
376 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
380 static void mga_g400_emit_state( drm_mga_private_t *dev_priv )
382 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
383 unsigned int dirty = sarea_priv->dirty;
384 int multitex = sarea_priv->warp_pipe & MGA_T2;
386 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
387 mga_g400_emit_pipe( dev_priv );
388 dev_priv->warp_pipe = sarea_priv->warp_pipe;
391 if ( dirty & MGA_UPLOAD_CONTEXT ) {
392 mga_g400_emit_context( dev_priv );
393 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
396 if ( dirty & MGA_UPLOAD_TEX0 ) {
397 mga_g400_emit_tex0( dev_priv );
398 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
401 if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) {
402 mga_g400_emit_tex1( dev_priv );
403 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
408 /* ================================================================
409 * SAREA state verification
412 /* Disallow all write destinations except the front and backbuffer.
414 static int mga_verify_context( drm_mga_private_t *dev_priv )
416 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
417 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
419 if ( ctx->dstorg != dev_priv->front_offset &&
420 ctx->dstorg != dev_priv->back_offset ) {
421 DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n",
422 ctx->dstorg, dev_priv->front_offset,
423 dev_priv->back_offset );
425 return DRM_ERR(EINVAL);
431 /* Disallow texture reads from PCI space.
433 static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
435 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
436 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
439 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
441 if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) {
442 DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n",
445 return DRM_ERR(EINVAL);
451 static int mga_verify_state( drm_mga_private_t *dev_priv )
453 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
454 unsigned int dirty = sarea_priv->dirty;
457 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
458 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
460 if ( dirty & MGA_UPLOAD_CONTEXT )
461 ret |= mga_verify_context( dev_priv );
463 if ( dirty & MGA_UPLOAD_TEX0 )
464 ret |= mga_verify_tex( dev_priv, 0 );
466 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
467 if ( dirty & MGA_UPLOAD_TEX1 )
468 ret |= mga_verify_tex( dev_priv, 1 );
470 if ( dirty & MGA_UPLOAD_PIPE )
471 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES );
473 if ( dirty & MGA_UPLOAD_PIPE )
474 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES );
480 static int mga_verify_iload( drm_mga_private_t *dev_priv,
481 unsigned int dstorg, unsigned int length )
483 if ( dstorg < dev_priv->texture_offset ||
484 dstorg + length > (dev_priv->texture_offset +
485 dev_priv->texture_size) ) {
486 DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg );
487 return DRM_ERR(EINVAL);
490 if ( length & MGA_ILOAD_MASK ) {
491 DRM_ERROR( "*** bad iload length: 0x%x\n",
492 length & MGA_ILOAD_MASK );
493 return DRM_ERR(EINVAL);
499 static int mga_verify_blit( drm_mga_private_t *dev_priv,
500 unsigned int srcorg, unsigned int dstorg )
502 if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
503 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) {
504 DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n",
506 return DRM_ERR(EINVAL);
512 /* ================================================================
516 static void mga_dma_dispatch_clear( drm_device_t *dev,
517 drm_mga_clear_t *clear )
519 drm_mga_private_t *dev_priv = dev->dev_private;
520 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
521 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
522 drm_clip_rect_t *pbox = sarea_priv->boxes;
523 int nbox = sarea_priv->nbox;
530 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
531 MGA_DMAPAD, 0x00000000,
532 MGA_DWGSYNC, 0x00007100,
533 MGA_DWGSYNC, 0x00007000 );
537 for ( i = 0 ; i < nbox ; i++ ) {
538 drm_clip_rect_t *box = &pbox[i];
539 u32 height = box->y2 - box->y1;
541 DRM_DEBUG( " from=%d,%d to=%d,%d\n",
542 box->x1, box->y1, box->x2, box->y2 );
544 if ( clear->flags & MGA_FRONT ) {
547 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
548 MGA_PLNWT, clear->color_mask,
549 MGA_YDSTLEN, (box->y1 << 16) | height,
550 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
552 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
553 MGA_FCOL, clear->clear_color,
554 MGA_DSTORG, dev_priv->front_offset,
555 MGA_DWGCTL + MGA_EXEC,
556 dev_priv->clear_cmd );
562 if ( clear->flags & MGA_BACK ) {
565 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
566 MGA_PLNWT, clear->color_mask,
567 MGA_YDSTLEN, (box->y1 << 16) | height,
568 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
570 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
571 MGA_FCOL, clear->clear_color,
572 MGA_DSTORG, dev_priv->back_offset,
573 MGA_DWGCTL + MGA_EXEC,
574 dev_priv->clear_cmd );
579 if ( clear->flags & MGA_DEPTH ) {
582 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
583 MGA_PLNWT, clear->depth_mask,
584 MGA_YDSTLEN, (box->y1 << 16) | height,
585 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
587 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
588 MGA_FCOL, clear->clear_depth,
589 MGA_DSTORG, dev_priv->depth_offset,
590 MGA_DWGCTL + MGA_EXEC,
591 dev_priv->clear_cmd );
600 /* Force reset of DWGCTL */
601 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
602 MGA_DMAPAD, 0x00000000,
603 MGA_PLNWT, ctx->plnwt,
604 MGA_DWGCTL, ctx->dwgctl );
611 static void mga_dma_dispatch_swap( drm_device_t *dev )
613 drm_mga_private_t *dev_priv = dev->dev_private;
614 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
615 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
616 drm_clip_rect_t *pbox = sarea_priv->boxes;
617 int nbox = sarea_priv->nbox;
622 sarea_priv->last_frame.head = dev_priv->prim.tail;
623 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
625 BEGIN_DMA( 4 + nbox );
627 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
628 MGA_DMAPAD, 0x00000000,
629 MGA_DWGSYNC, 0x00007100,
630 MGA_DWGSYNC, 0x00007000 );
632 DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset,
633 MGA_MACCESS, dev_priv->maccess,
634 MGA_SRCORG, dev_priv->back_offset,
635 MGA_AR5, dev_priv->front_pitch );
637 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
638 MGA_DMAPAD, 0x00000000,
639 MGA_PLNWT, 0xffffffff,
640 MGA_DWGCTL, MGA_DWGCTL_COPY );
642 for ( i = 0 ; i < nbox ; i++ ) {
643 drm_clip_rect_t *box = &pbox[i];
644 u32 height = box->y2 - box->y1;
645 u32 start = box->y1 * dev_priv->front_pitch;
647 DRM_DEBUG( " from=%d,%d to=%d,%d\n",
648 box->x1, box->y1, box->x2, box->y2 );
650 DMA_BLOCK( MGA_AR0, start + box->x2 - 1,
651 MGA_AR3, start + box->x1,
652 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
653 MGA_YDSTLEN + MGA_EXEC,
654 (box->y1 << 16) | height );
657 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
658 MGA_PLNWT, ctx->plnwt,
659 MGA_SRCORG, dev_priv->front_offset,
660 MGA_DWGCTL, ctx->dwgctl );
666 DRM_DEBUG( "%s... done.\n", __FUNCTION__ );
669 static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
671 drm_mga_private_t *dev_priv = dev->dev_private;
672 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
673 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
674 u32 address = (u32) buf->bus_address;
675 u32 length = (u32) buf->used;
678 DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used );
681 buf_priv->dispatched = 1;
683 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
686 if ( i < sarea_priv->nbox ) {
687 mga_emit_clip_rect( dev_priv,
688 &sarea_priv->boxes[i] );
693 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
694 MGA_DMAPAD, 0x00000000,
695 MGA_SECADDRESS, (address |
697 MGA_SECEND, ((address + length) |
701 } while ( ++i < sarea_priv->nbox );
704 if ( buf_priv->discard ) {
705 AGE_BUFFER( buf_priv );
708 buf_priv->dispatched = 0;
710 mga_freelist_put( dev, buf );
716 static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
717 unsigned int start, unsigned int end )
719 drm_mga_private_t *dev_priv = dev->dev_private;
720 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
721 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
722 u32 address = (u32) buf->bus_address;
725 DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end );
727 if ( start != end ) {
728 buf_priv->dispatched = 1;
730 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
733 if ( i < sarea_priv->nbox ) {
734 mga_emit_clip_rect( dev_priv,
735 &sarea_priv->boxes[i] );
740 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
741 MGA_DMAPAD, 0x00000000,
742 MGA_SETUPADDRESS, address + start,
743 MGA_SETUPEND, ((address + end) |
747 } while ( ++i < sarea_priv->nbox );
750 if ( buf_priv->discard ) {
751 AGE_BUFFER( buf_priv );
754 buf_priv->dispatched = 0;
756 mga_freelist_put( dev, buf );
762 /* This copies a 64 byte aligned agp region to the frambuffer with a
763 * standard blit, the ioctl needs to do checking.
765 static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
766 unsigned int dstorg, unsigned int length )
768 drm_mga_private_t *dev_priv = dev->dev_private;
769 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
770 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
771 u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
774 DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used );
780 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
781 MGA_DMAPAD, 0x00000000,
782 MGA_DWGSYNC, 0x00007100,
783 MGA_DWGSYNC, 0x00007000 );
785 DMA_BLOCK( MGA_DSTORG, dstorg,
786 MGA_MACCESS, 0x00000000,
790 DMA_BLOCK( MGA_PITCH, 64,
791 MGA_PLNWT, 0xffffffff,
792 MGA_DMAPAD, 0x00000000,
793 MGA_DWGCTL, MGA_DWGCTL_COPY );
795 DMA_BLOCK( MGA_AR0, 63,
797 MGA_FXBNDRY, (63 << 16) | 0,
798 MGA_YDSTLEN + MGA_EXEC, y2 );
800 DMA_BLOCK( MGA_PLNWT, ctx->plnwt,
801 MGA_SRCORG, dev_priv->front_offset,
802 MGA_PITCH, dev_priv->front_pitch,
803 MGA_DWGSYNC, 0x00007000 );
807 AGE_BUFFER( buf_priv );
811 buf_priv->dispatched = 0;
813 mga_freelist_put( dev, buf );
818 static void mga_dma_dispatch_blit( drm_device_t *dev,
819 drm_mga_blit_t *blit )
821 drm_mga_private_t *dev_priv = dev->dev_private;
822 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
823 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
824 drm_clip_rect_t *pbox = sarea_priv->boxes;
825 int nbox = sarea_priv->nbox;
830 BEGIN_DMA( 4 + nbox );
832 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
833 MGA_DMAPAD, 0x00000000,
834 MGA_DWGSYNC, 0x00007100,
835 MGA_DWGSYNC, 0x00007000 );
837 DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY,
838 MGA_PLNWT, blit->planemask,
839 MGA_SRCORG, blit->srcorg,
840 MGA_DSTORG, blit->dstorg );
842 DMA_BLOCK( MGA_SGN, scandir,
843 MGA_MACCESS, dev_priv->maccess,
844 MGA_AR5, blit->ydir * blit->src_pitch,
845 MGA_PITCH, blit->dst_pitch );
847 for ( i = 0 ; i < nbox ; i++ ) {
848 int srcx = pbox[i].x1 + blit->delta_sx;
849 int srcy = pbox[i].y1 + blit->delta_sy;
850 int dstx = pbox[i].x1 + blit->delta_dx;
851 int dsty = pbox[i].y1 + blit->delta_dy;
852 int h = pbox[i].y2 - pbox[i].y1;
853 int w = pbox[i].x2 - pbox[i].x1 - 1;
856 if ( blit->ydir == -1 ) {
857 srcy = blit->height - srcy - 1;
860 start = srcy * blit->src_pitch + srcx;
862 DMA_BLOCK( MGA_AR0, start + w,
864 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
865 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h );
868 /* Do something to flush AGP?
871 /* Force reset of DWGCTL */
872 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
873 MGA_PLNWT, ctx->plnwt,
874 MGA_PITCH, dev_priv->front_pitch,
875 MGA_DWGCTL, ctx->dwgctl );
881 /* ================================================================
885 int mga_dma_clear( DRM_IOCTL_ARGS )
888 drm_mga_private_t *dev_priv = dev->dev_private;
889 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
890 drm_mga_clear_t clear;
892 LOCK_TEST_WITH_RETURN( dev, filp );
894 DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t *)data, sizeof(clear) );
896 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
897 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
899 WRAP_TEST_WITH_RETURN( dev_priv );
901 mga_dma_dispatch_clear( dev, &clear );
903 /* Make sure we restore the 3D state next time.
905 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
910 int mga_dma_swap( DRM_IOCTL_ARGS )
913 drm_mga_private_t *dev_priv = dev->dev_private;
914 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
916 LOCK_TEST_WITH_RETURN( dev, filp );
918 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
919 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
921 WRAP_TEST_WITH_RETURN( dev_priv );
923 mga_dma_dispatch_swap( dev );
925 /* Make sure we restore the 3D state next time.
927 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
932 int mga_dma_vertex( DRM_IOCTL_ARGS )
935 drm_mga_private_t *dev_priv = dev->dev_private;
936 drm_device_dma_t *dma = dev->dma;
938 drm_mga_buf_priv_t *buf_priv;
939 drm_mga_vertex_t vertex;
941 LOCK_TEST_WITH_RETURN( dev, filp );
943 DRM_COPY_FROM_USER_IOCTL( vertex,
944 (drm_mga_vertex_t *)data,
947 if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL);
948 buf = dma->buflist[vertex.idx];
949 buf_priv = buf->dev_private;
951 buf->used = vertex.used;
952 buf_priv->discard = vertex.discard;
954 if ( !mga_verify_state( dev_priv ) ) {
955 if ( vertex.discard ) {
956 if ( buf_priv->dispatched == 1 )
957 AGE_BUFFER( buf_priv );
958 buf_priv->dispatched = 0;
959 mga_freelist_put( dev, buf );
961 return DRM_ERR(EINVAL);
964 WRAP_TEST_WITH_RETURN( dev_priv );
966 mga_dma_dispatch_vertex( dev, buf );
971 int mga_dma_indices( DRM_IOCTL_ARGS )
974 drm_mga_private_t *dev_priv = dev->dev_private;
975 drm_device_dma_t *dma = dev->dma;
977 drm_mga_buf_priv_t *buf_priv;
978 drm_mga_indices_t indices;
980 LOCK_TEST_WITH_RETURN( dev, filp );
982 DRM_COPY_FROM_USER_IOCTL( indices,
983 (drm_mga_indices_t *)data,
986 if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL);
988 buf = dma->buflist[indices.idx];
989 buf_priv = buf->dev_private;
991 buf_priv->discard = indices.discard;
993 if ( !mga_verify_state( dev_priv ) ) {
994 if ( indices.discard ) {
995 if ( buf_priv->dispatched == 1 )
996 AGE_BUFFER( buf_priv );
997 buf_priv->dispatched = 0;
998 mga_freelist_put( dev, buf );
1000 return DRM_ERR(EINVAL);
1003 WRAP_TEST_WITH_RETURN( dev_priv );
1005 mga_dma_dispatch_indices( dev, buf, indices.start, indices.end );
1010 int mga_dma_iload( DRM_IOCTL_ARGS )
1013 drm_device_dma_t *dma = dev->dma;
1014 drm_mga_private_t *dev_priv = dev->dev_private;
1016 drm_mga_buf_priv_t *buf_priv;
1017 drm_mga_iload_t iload;
1020 LOCK_TEST_WITH_RETURN( dev, filp );
1022 DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t *)data, sizeof(iload) );
1025 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {
1026 if ( MGA_DMA_DEBUG )
1027 DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ );
1028 return DRM_ERR(EBUSY);
1031 if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL);
1033 buf = dma->buflist[iload.idx];
1034 buf_priv = buf->dev_private;
1036 if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) {
1037 mga_freelist_put( dev, buf );
1038 return DRM_ERR(EINVAL);
1041 WRAP_TEST_WITH_RETURN( dev_priv );
1043 mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length );
1045 /* Make sure we restore the 3D state next time.
1047 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1052 int mga_dma_blit( DRM_IOCTL_ARGS )
1055 drm_mga_private_t *dev_priv = dev->dev_private;
1056 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1057 drm_mga_blit_t blit;
1060 LOCK_TEST_WITH_RETURN( dev, filp );
1062 DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t *)data, sizeof(blit) );
1064 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
1065 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1067 if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) )
1068 return DRM_ERR(EINVAL);
1070 WRAP_TEST_WITH_RETURN( dev_priv );
1072 mga_dma_dispatch_blit( dev, &blit );
1074 /* Make sure we restore the 3D state next time.
1076 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1081 int mga_getparam( DRM_IOCTL_ARGS )
1084 drm_mga_private_t *dev_priv = dev->dev_private;
1085 drm_mga_getparam_t param;
1089 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1090 return DRM_ERR(EINVAL);
1093 DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t *)data,
1096 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
1098 switch( param.param ) {
1099 case MGA_PARAM_IRQ_NR:
1103 return DRM_ERR(EINVAL);
1106 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
1107 DRM_ERROR( "copy_to_user\n" );
1108 return DRM_ERR(EFAULT);