1 /* $NetBSD: i82365var.h,v 1.8 1999/10/15 06:07:27 haya Exp $ */
2 /* $FreeBSD: src/sys/dev/pcic/i82365var.h,v 1.15.2.1 2000/05/23 03:57:02 imp Exp $ */
5 * Copyright (c) 1997 Marc Horowitz. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Marc Horowitz.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <dev/pccard/pccardreg.h>
35 #include <dev/pcic/i82365reg.h>
40 STAILQ_ENTRY(pcic_event) pe_q;
45 #define PCIC_EVENT_INSERTION 0
46 #define PCIC_EVENT_REMOVAL 1
49 struct pcic_softc *sc;
51 bus_space_tag_t ph_bus_t; /* I/O or MEM? I don't mind */
52 bus_space_handle_t ph_bus_h;
53 u_int8_t (* ph_read)(struct pcic_handle*, int);
54 void (* ph_write)(struct pcic_handle *, int, u_int8_t);
61 struct pccard_mem_handle mem[PCIC_MEM_WINS]; /* XXX BAD XXX */
63 struct pccard_io_handle io[PCIC_IO_WINS]; /* XXX BAD XXX */
67 struct proc *event_thread;
68 STAILQ_HEAD(, pcic_event) events;
71 #define PCIC_FLAG_SOCKETP 0x0001
72 #define PCIC_FLAG_CARDP 0x0002
74 #define PCIC_LASTSTATE_PRESENT 0x0002
75 #define PCIC_LASTSTATE_HALF 0x0001
76 #define PCIC_LASTSTATE_EMPTY 0x0000
78 #define C0SA PCIC_CHIP0_BASE+PCIC_SOCKETA_INDEX
79 #define C0SB PCIC_CHIP0_BASE+PCIC_SOCKETB_INDEX
80 #define C1SA PCIC_CHIP1_BASE+PCIC_SOCKETA_INDEX
81 #define C1SB PCIC_CHIP1_BASE+PCIC_SOCKETB_INDEX
84 * This is sort of arbitrary. It merely needs to be "enough". It can be
85 * overridden in the conf file, anyway.
88 #define PCIC_MEM_PAGES 4
89 #define PCIC_MEMSIZE PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE
97 bus_space_handle_t memh;
99 bus_space_handle_t ioh;
102 struct resource *irq_res;
104 struct resource *mem_res;
106 struct resource *port_res;
109 #define PCIC_MAX_MEM_PAGES (8 * sizeof(int))
111 /* used by memory window mapping functions */
115 * used by io window mapping functions. These can actually overlap
116 * with another pcic, since the underlying extent mapper will deal
117 * with individual allocations. This is here to deal with the fact
118 * that different busses have different real widths (different pc
119 * hardware seems to use 10 or 12 bits for the I/O bus).
127 struct pcic_handle handle[PCIC_NSLOTS];
131 int pcic_ident_ok(int);
132 int pcic_vendor(struct pcic_handle *);
133 char *pcic_vendor_to_string(int);
135 int pcic_attach(device_t dev);
139 static __inline int pcic_read(struct pcic_handle *, int);
142 struct pcic_handle *h;
146 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX,
148 return (bus_space_read_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA));
151 static __inline void pcic_write(struct pcic_handle *, int, int);
153 pcic_write(h, idx, data)
154 struct pcic_handle *h;
159 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX,
161 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA, (data));
164 #define pcic_read(h, idx) \
165 (*(h)->ph_read)((h), (idx))
167 #define pcic_write(h, idx, data) \
168 (*(h)->ph_write)((h), (idx), (data))
173 * bus/device/etc routines
175 int pcic_activate_resource(device_t dev, device_t child, int type, int rid,
177 struct resource *pcic_alloc_resource(device_t dev, device_t child, int type,
178 int *rid, u_long start, u_long end, u_long count, u_int flags);
179 int pcic_deactivate_resource(device_t dev, device_t child, int type, int rid,
181 int pcic_release_resource(device_t dev, device_t child, int type, int rid,
183 int pcic_setup_intr(device_t dev, device_t child, struct resource *irq,
184 int flags, driver_intr_t intr, void *arg, void **cookiep);
185 int pcic_teardown_intr(device_t dev, device_t child, struct resource *irq,
187 int pcic_suspend(device_t dev);
188 int pcic_resume(device_t dev);
189 int pcic_enable_socket(device_t dev, device_t child);
190 int pcic_disable_socket(device_t dev, device_t child);
191 int pcic_set_res_flags(device_t dev, device_t child, int type, int rid,
193 int pcic_set_memory_offset(device_t dev, device_t child, int rid,