2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * $FreeBSD: src/sys/i386/isa/if_le.c,v 1.56.2.4 2002/06/05 23:24:10 paul Exp $
28 * DEC EtherWORKS 2 Ethernet Controllers
29 * DEC EtherWORKS 3 Ethernet Controllers
31 * Written by Matt Thomas
32 * BPF support code stolen directly from if_ec.c
34 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
35 * DE2002, DE203, DE204, DE205, and DE422 cards.
42 #include <sys/param.h>
43 #include <sys/systm.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/malloc.h>
50 #include <net/ethernet.h>
52 #include <net/if_types.h>
53 #include <net/if_dl.h>
55 #include <netinet/in.h>
56 #include <netinet/if_ether.h>
59 #include <machine/clock.h>
61 #include <i386/isa/isa_device.h>
62 #include <i386/isa/icu.h>
69 /* Forward declarations */
70 typedef struct le_softc le_softc_t;
71 typedef struct le_board le_board_t;
73 typedef u_short le_mcbits_t;
74 #define LE_MC_NBPW_LOG2 4
75 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
77 #if !defined(LE_NOLEMAC)
79 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
81 * Start of DEC EtherWORKS III (LEMAC) dependent structures
84 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
86 static int lemac_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
88 struct le_lemac_info {
89 u_int lemac__lastpage; /* last 2K page */
90 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
91 u_int lemac__membase; /* Physical address of start of RAM */
92 u_int lemac__txctl; /* Transmit Control Byte */
93 u_int lemac__txmax; /* Maximum # of outstanding transmits */
94 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
95 /* local copy of multicast table */
96 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
97 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
98 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
99 #define lemac_memmode le_un.un_lemac.lemac__memmode
100 #define lemac_membase le_un.un_lemac.lemac__membase
101 #define lemac_txctl le_un.un_lemac.lemac__txctl
102 #define lemac_txmax le_un.un_lemac.lemac__txmax
103 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
104 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
105 #define lemac_prodname le_un.un_lemac.lemac__prodname
107 #endif /* !defined(LE_NOLEMAC) */
109 #if !defined(LE_NOLANCE)
111 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
113 * Start of DEC EtherWORKS II (LANCE) dependent structures
117 #include <i386/isa/ic/am7990.h>
123 static int depca_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
125 typedef struct lance_descinfo lance_descinfo_t;
126 typedef struct lance_ring lance_ring_t;
128 typedef unsigned lance_addr_t;
130 struct lance_descinfo {
131 caddr_t di_addr; /* address of descriptor */
132 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
133 unsigned di_buflen; /* size of buffer owned by descriptor */
134 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
138 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
139 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
140 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
141 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
142 unsigned ri_max; /* Size of Ring - 1 */
143 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
144 lance_addr_t ri_heap; /* Start of RAM for this ring */
145 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
146 lance_addr_t ri_outptr; /* Pointer to first output byte */
147 unsigned ri_outsize; /* Space remaining for output */
150 struct le_lance_info {
151 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
152 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
153 unsigned lance__csr3; /* Copy of CSR3 */
154 unsigned lance__rap; /* IO Port Offset of RAP */
155 unsigned lance__rdp; /* IO Port Offset of RDP */
156 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
157 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
158 unsigned lance__rxbufsize; /* Size of a receive buffer */
159 ln_initb_t lance__initb; /* local copy of LANCE initblock */
160 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
161 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
162 lance_ring_t lance__rxinfo; /* Receive ring information */
163 lance_ring_t lance__txinfo; /* Transmit ring information */
164 #define lance_csr1 le_un.un_lance.lance__csr1
165 #define lance_csr2 le_un.un_lance.lance__csr2
166 #define lance_csr3 le_un.un_lance.lance__csr3
167 #define lance_rap le_un.un_lance.lance__rap
168 #define lance_rdp le_un.un_lance.lance__rdp
169 #define lance_ramoffset le_un.un_lance.lance__ramoffset
170 #define lance_ramsize le_un.un_lance.lance__ramsize
171 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
172 #define lance_initb le_un.un_lance.lance__initb
173 #define lance_raminitb le_un.un_lance.lance__raminitb
174 #define lance_ramdesc le_un.un_lance.lance__ramdesc
175 #define lance_rxinfo le_un.un_lance.lance__rxinfo
176 #define lance_txinfo le_un.un_lance.lance__txinfo
178 #endif /* !defined(LE_NOLANCE) */
181 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
183 * Start of Common Code
187 static void (*le_intrvec[NLE])(le_softc_t *sc);
190 * Ethernet status, per interface.
193 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
194 void (*if_init) __P((void *));/* Interface init routine */
195 void (*if_reset) __P((le_softc_t *));/* Interface reset routine */
196 caddr_t le_membase; /* Starting memory address (virtual) */
197 unsigned le_iobase; /* Starting I/O base address */
198 unsigned le_irq; /* Interrupt Request Value */
199 unsigned le_flags; /* local copy of if_flags */
200 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
201 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
202 le_mcbits_t *le_mctbl; /* pointer to multicast table */
203 const char *le_prodname; /* product name DE20x-xx */
204 u_char le_hwaddr[6]; /* local copy of hwaddr */
206 #if !defined(LE_NOLEMAC)
207 struct le_lemac_info un_lemac; /* LEMAC specific information */
209 #if !defined(LE_NOLANCE)
210 struct le_lance_info un_lance; /* Am7990 specific information */
214 #define le_if le_ac.ac_if
217 static int le_probe(struct isa_device *dvp);
218 static int le_attach(struct isa_device *dvp);
219 static ointhand2_t le_intr;
220 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
221 static void le_input(le_softc_t *sc, caddr_t seg1, size_t total_len,
222 size_t len2, caddr_t seg2);
223 static void le_multi_filter(le_softc_t *sc);
224 static void le_multi_op(le_softc_t *sc, const u_char *mca, int oper_flg);
225 static int le_read_macaddr(le_softc_t *sc, int ioreg, int skippat);
227 #define LE_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
230 int (*bd_probe)(le_softc_t *sc, const le_board_t *bd, int *msize);
234 static le_softc_t le_softc[NLE];
236 static const le_board_t le_boards[] = {
237 #if !defined(LE_NOLEMAC)
238 { lemac_probe }, /* DE20[345] */
240 #if !defined(LE_NOLANCE)
241 { depca_probe }, /* DE{20[012],422} */
243 { NULL } /* Must Be Last! */
247 * This tells the autoconf code how to set us up.
249 struct isa_driver ledriver = {
250 le_probe, le_attach, "le",
253 static unsigned le_intrs[NLE];
255 #define LE_ADDREQUAL(a1, a2) \
256 (((u_short *)a1)[0] == ((u_short *)a2)[0] \
257 || ((u_short *)a1)[1] == ((u_short *)a2)[1] \
258 || ((u_short *)a1)[2] == ((u_short *)a2)[2])
259 #define LE_ADDRBRDCST(a1) \
260 (((u_short *)a1)[0] == 0xFFFFU \
261 || ((u_short *)a1)[1] == 0xFFFFU \
262 || ((u_short *)a1)[2] == 0xFFFFU)
264 #define LE_INL(sc, reg) \
266 __asm __volatile("inl %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
270 #define LE_OUTL(sc, reg, data) \
271 ({__asm __volatile("outl %0, %1"::"a" ((u_int)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
273 #define LE_INW(sc, reg) \
275 __asm __volatile("inw %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
279 #define LE_OUTW(sc, reg, data) \
280 ({__asm __volatile("outw %0, %1"::"a" ((u_short)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
282 #define LE_INB(sc, reg) \
284 __asm __volatile("inb %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
288 #define LE_OUTB(sc, reg, data) \
289 ({__asm __volatile("outb %0, %1"::"a" ((u_char)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
291 #define MEMCPY(to, from, len) bcopy(from, to, len)
292 #define MEMSET(where, what, howmuch) bzero(where, howmuch)
293 #define MEMCMP(l, r, len) bcmp(l, r, len)
298 struct isa_device *dvp)
300 le_softc_t *sc = &le_softc[dvp->id_unit];
301 const le_board_t *bd;
304 if (dvp->id_unit >= NLE) {
305 printf("%s%d not configured -- too many devices\n",
306 ledriver.name, dvp->id_unit);
310 sc->le_iobase = dvp->id_iobase;
311 sc->le_membase = (u_char *) dvp->id_maddr;
312 sc->le_irq = dvp->id_irq;
313 sc->le_if.if_name = ledriver.name;
314 sc->le_if.if_unit = dvp->id_unit;
317 * Find and Initialize board..
320 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
322 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
323 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
333 struct isa_device *dvp)
335 le_softc_t *sc = &le_softc[dvp->id_unit];
336 struct ifnet *ifp = &sc->le_if;
338 dvp->id_ointr = le_intr;
340 ifp->if_mtu = ETHERMTU;
341 printf("%s%d: %s ethernet address %6D\n",
342 ifp->if_name, ifp->if_unit,
344 sc->le_ac.ac_enaddr, ":");
346 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
347 ifp->if_output = ether_output;
348 ifp->if_ioctl = le_ioctl;
349 ifp->if_type = IFT_ETHER;
352 ifp->if_init = sc->if_init;
354 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
366 (*le_intrvec[unit])(&le_softc[unit]);
381 struct ether_header eh;
384 if (total_len - sizeof(eh) > ETHERMTU
385 || total_len - sizeof(eh) < ETHERMIN) {
386 sc->le_if.if_ierrors++;
389 MEMCPY(&eh, seg1, sizeof(eh));
391 seg1 += sizeof(eh); total_len -= sizeof(eh); len1 -= sizeof(eh);
393 MGETHDR(m, M_DONTWAIT, MT_DATA);
395 sc->le_if.if_ierrors++;
398 m->m_pkthdr.len = total_len;
399 m->m_pkthdr.rcvif = &sc->le_if;
400 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
401 MCLGET(m, M_DONTWAIT);
402 if ((m->m_flags & M_EXT) == 0) {
404 sc->le_if.if_ierrors++;
407 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
408 MGET(m->m_next, M_DONTWAIT, MT_DATA);
409 if (m->m_next == NULL) {
411 sc->le_if.if_ierrors++;
414 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
415 len1 = total_len = MHLEN - LE_XTRA;
416 MEMCPY(mtod(m->m_next, caddr_t), &seg1[MHLEN-LE_XTRA], m->m_next->m_len);
417 } else if (total_len + LE_XTRA > MHLEN) {
418 panic("le_input: pkt of unknown length");
420 m->m_data += LE_XTRA;
421 m->m_len = total_len;
422 MEMCPY(mtod(m, caddr_t), seg1, len1);
424 MEMCPY(mtod(m, caddr_t) + len1, seg2, total_len - len1);
425 ether_input(&sc->le_if, &eh, m);
434 le_softc_t *sc = ifp->if_softc;
437 if ((sc->le_flags & IFF_UP) == 0)
446 error = ether_ioctl(ifp, cmd, data);
457 * Update multicast listeners
473 * This is the standard method of reading the DEC Address ROMS.
474 * I don't understand it but it does work.
482 int cksum, rom_cksum;
485 int idx, idx2, found, octet;
486 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
489 for (idx = 0; idx < 32; idx++) {
490 octet = LE_INB(sc, ioreg);
492 if (octet == testpat[idx2]) {
493 if (++idx2 == sizeof testpat) {
507 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
508 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
510 cksum = *(u_short *) &sc->le_hwaddr[0];
512 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
513 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
515 if (cksum > 65535) cksum -= 65535;
516 cksum += *(u_short *) &sc->le_hwaddr[2];
517 if (cksum > 65535) cksum -= 65535;
519 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
520 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
522 if (cksum > 65535) cksum -= 65535;
523 cksum += *(u_short *) &sc->le_hwaddr[4];
524 if (cksum >= 65535) cksum -= 65535;
526 rom_cksum = LE_INB(sc, ioreg);
527 rom_cksum |= LE_INB(sc, ioreg) << 8;
529 if (cksum != rom_cksum)
538 struct ifmultiaddr *ifma;
540 MEMSET(sc->le_mctbl, 0, (sc->le_mcmask + 1) / 8);
542 if (sc->le_if.if_flags & IFF_ALLMULTI) {
543 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
546 sc->le_flags &= ~IFF_MULTICAST;
547 /* if (interface has had an address assigned) { */
548 le_multi_op(sc, etherbroadcastaddr, TRUE);
549 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
552 sc->le_flags |= IFF_MULTICAST;
554 for (ifma = sc->le_ac.ac_if.if_multiaddrs.lh_first; ifma;
555 ifma = ifma->ifma_link.le_next) {
556 if (ifma->ifma_addr->sa_family != AF_LINK)
559 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
560 sc->le_flags &= ~LE_BRDCSTONLY;
570 u_int idx, bit, data, crc = 0xFFFFFFFFUL;
573 for (data = *(__unaligned u_long *) mca, bit = 0; bit < 48; bit++, data >>=
575 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
577 for (idx = 0; idx < 6; idx++)
578 for (data = *mca++, bit = 0; bit < 8; bit++, data >>= 1)
579 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
582 * The following two line convert the N bit index into a longword index
583 * and a longword mask.
585 crc &= sc->le_mcmask;
586 bit = 1 << (crc & (LE_MC_NBPW -1));
587 idx = crc >> (LE_MC_NBPW_LOG2);
590 * Set or clear hash filter bit in our table.
593 sc->le_mctbl[idx] |= bit; /* Set Bit */
595 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
599 #if !defined(LE_NOLEMAC)
601 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
603 * Start of DEC EtherWORKS III (LEMAC) dependent code
607 #define LEMAC_INTR_ENABLE(sc) \
608 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
610 #define LEMAC_INTR_DISABLE(sc) \
611 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
613 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
614 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
615 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
617 static void lemac_init(void *xsc);
618 static void lemac_start(struct ifnet *ifp);
619 static void lemac_reset(le_softc_t *sc);
620 static void lemac_intr(le_softc_t *sc);
621 static void lemac_rne_intr(le_softc_t *sc);
622 static void lemac_tne_intr(le_softc_t *sc);
623 static void lemac_txd_intr(le_softc_t *sc, unsigned cs_value);
624 static void lemac_rxd_intr(le_softc_t *sc, unsigned cs_value);
625 static int lemac_read_eeprom(le_softc_t *sc);
626 static void lemac_init_adapmem(le_softc_t *sc);
628 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
630 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
631 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
632 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
633 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
634 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
637 * An IRQ mapping table. Less space than switch statement.
639 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
642 * Some tuning/monitoring variables.
644 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
645 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
647 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
648 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
649 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
650 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
656 const le_board_t *bd,
661 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
662 DELAY(LEMAC_EEP_DELAY);
665 * Read Ethernet address if card is present.
667 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
670 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
672 * Clear interrupts and set IRQ.
675 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
676 irq = lemac_irqs[portval >> 5];
677 LE_OUTB(sc, LEMAC_REG_IC, portval);
680 * Make sure settings match.
683 if (irq != sc->le_irq) {
684 printf("%s%d: lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
685 sc->le_if.if_name, sc->le_if.if_unit, sc->le_irq, irq);
690 * Try to reset the unit
692 sc->if_init = lemac_init;
693 sc->le_if.if_start = lemac_start;
694 sc->if_reset = lemac_reset;
695 sc->lemac_memmode = 2;
697 if ((sc->le_flags & IFF_UP) == 0)
701 * Check for correct memory base configuration.
703 if (vtophys(sc->le_membase) != sc->lemac_membase) {
704 printf("%s%d: lemac configuration error: expected iomem 0x%x actual 0x%x\n",
705 sc->le_if.if_name, sc->le_if.if_unit,
706 vtophys(sc->le_membase), sc->lemac_membase);
710 sc->le_prodname = sc->lemac_prodname;
711 sc->le_mctbl = sc->lemac_mctbl;
712 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
713 sc->lemac_txmax = lemac_deftxmax;
715 le_intrvec[sc->le_if.if_unit] = lemac_intr;
717 return LEMAC_IOSPACE;
721 * Do a hard reset of the board;
733 sc->le_flags &= IFF_UP;
734 sc->le_if.if_flags &= ~IFF_OACTIVE;
735 LEMAC_INTR_DISABLE(sc);
737 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
738 DELAY(LEMAC_EEP_DELAY);
740 /* Disable Interrupts */
741 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
744 * Read EEPROM information. NOTE - the placement of this function
745 * is important because functions hereafter may rely on information
746 * read from the EEPROM.
748 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
749 printf("%s%d: reset: EEPROM checksum failed (0x%x)\n",
750 sc->le_if.if_name, sc->le_if.if_unit, cksum);
755 * Force to 2K mode if not already configured.
758 portval = LE_INB(sc, LEMAC_REG_MBR);
759 if (!LEMAC_2K_MODE(portval)) {
760 if (LEMAC_64K_MODE(portval)) {
761 portval = (((portval * 2) & 0xF) << 4);
762 sc->lemac_memmode = 64;
763 } else if (LEMAC_32K_MODE(portval)) {
764 portval = ((portval & 0xF) << 4);
765 sc->lemac_memmode = 32;
767 LE_OUTB(sc, LEMAC_REG_MBR, portval);
769 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
772 * Initialize Free Memory Queue, Init mcast table with broadcast.
775 lemac_init_adapmem(sc);
776 sc->le_flags |= IFF_UP;
784 le_softc_t *sc = (le_softc_t *)xsc;
787 if ((sc->le_flags & IFF_UP) == 0)
793 * If the interface has the up flag
795 if (sc->le_if.if_flags & IFF_UP) {
796 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
797 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
798 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
799 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
800 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
801 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
802 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
803 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
805 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
807 if (sc->le_if.if_flags & IFF_PROMISC) {
808 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
810 LEMAC_INTR_DISABLE(sc);
812 LE_OUTB(sc, LEMAC_REG_MPN, 0);
813 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
814 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], lemac_allmulti_mctbl, sizeof(lemac_allmulti_mctbl));
816 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], sc->lemac_mctbl, sizeof(sc->lemac_mctbl));
818 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
821 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
823 LEMAC_INTR_ENABLE(sc);
824 sc->le_if.if_flags |= IFF_RUNNING;
826 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
828 LEMAC_INTR_DISABLE(sc);
829 sc->le_if.if_flags &= ~IFF_RUNNING;
835 * What to do upon receipt of an interrupt.
843 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
846 * Determine cause of interrupt. Receive events take
847 * priority over Transmit.
850 cs_value = LE_INB(sc, LEMAC_REG_CS);
853 * Check for Receive Queue not being empty.
854 * Check for Transmit Done Queue not being empty.
857 if (cs_value & LEMAC_CS_RNE)
859 if (cs_value & LEMAC_CS_TNE)
863 * Check for Transmitter Disabled.
864 * Check for Receiver Disabled.
867 if (cs_value & LEMAC_CS_TXD)
868 lemac_txd_intr(sc, cs_value);
869 if (cs_value & LEMAC_CS_RXD)
870 lemac_rxd_intr(sc, cs_value);
873 * Toggle LED and unmask interrupts.
876 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
877 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
884 int rxcount, rxlen, rxpg;
888 rxcount = LE_INB(sc, LEMAC_REG_RQC);
890 rxpg = LE_INB(sc, LEMAC_REG_RQ);
891 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
893 rxptr = sc->le_membase;
894 sc->le_if.if_ipackets++;
895 if (*rxptr & LEMAC_RX_OK) {
898 * Get receive length - subtract out checksum.
901 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
902 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
903 } else { /* end if (*rxptr & LEMAC_RX_OK) */
904 sc->le_if.if_ierrors++;
906 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
907 } /* end while (recv_count--) */
918 * Handle CS_RXD (Receiver disabled) here.
920 * Check Free Memory Queue Count. If not equal to zero
921 * then just turn Receiver back on. If it is equal to
922 * zero then check to see if transmitter is disabled.
923 * Process transmit TXD loop once more. If all else
924 * fails then do software init (0xC0 to EEPROM Init)
925 * and rebuild Free Memory Queue.
931 * Re-enable Receiver.
934 cs_value &= ~LEMAC_CS_RXD;
935 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
937 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
940 if (cs_value & LEMAC_CS_TXD)
941 lemac_txd_intr(sc, cs_value);
943 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
946 printf("%s%d: fatal RXD error, attempting recovery\n",
947 sc->le_if.if_name, sc->le_if.if_unit);
950 if (sc->le_flags & IFF_UP) {
956 * Error during initializion. Mark card as disabled.
958 printf("%s%d: recovery failed -- board disabled\n",
959 sc->le_if.if_name, sc->le_if.if_unit);
967 le_softc_t *sc = (le_softc_t *) ifp;
968 struct ifqueue *ifq = &ifp->if_snd;
970 if ((ifp->if_flags & IFF_RUNNING) == 0)
973 LEMAC_INTR_DISABLE(sc);
975 while (ifq->ifq_head != NULL) {
980 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
981 ifp->if_flags |= IFF_OACTIVE;
985 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
987 * Check for good transmit page.
989 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
991 ifp->if_flags |= IFF_OACTIVE;
996 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
999 * The first four bytes of each transmit buffer are for
1000 * control information. The first byte is the control
1001 * byte, then the length (why not word aligned?), then
1002 * the off to the buffer.
1005 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
1006 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
1007 *(u_int *) sc->le_membase = txhdr;
1010 * Copy the packet to the board
1013 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
1015 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
1017 if (sc->le_if.if_bpf)
1018 bpf_mtap(&sc->le_if, m);
1020 m_freem(m); /* free the mbuf */
1022 LEMAC_INTR_ENABLE(sc);
1029 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
1033 txsts = LE_INB(sc, LEMAC_REG_TDQ);
1034 sc->le_if.if_opackets++; /* another one done */
1035 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
1036 sc->le_if.if_collisions++;
1038 sc->le_if.if_flags &= ~IFF_OACTIVE;
1039 lemac_start(&sc->le_if);
1048 * Read transmit status, remove transmit buffer from
1049 * transmit queue and place on free memory queue,
1050 * then reset transmitter.
1051 * Increment appropriate counters.
1055 sc->le_if.if_oerrors++;
1056 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
1057 sc->le_if.if_collisions++;
1058 sc->le_if.if_flags &= ~IFF_OACTIVE;
1060 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
1061 /* Get Page number and write it back out */
1063 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
1064 /* Turn back on transmitter */
1072 int word_off, cksum;
1077 ep = sc->lemac_eeprom;
1078 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
1079 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
1080 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
1082 DELAY(LEMAC_EEP_DELAY);
1084 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
1085 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
1089 * Set up Transmit Control Byte for use later during transmit.
1092 sc->lemac_txctl |= LEMAC_TX_FLAGS;
1094 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
1095 sc->lemac_txctl &= ~LEMAC_TX_SQE;
1097 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
1098 sc->lemac_txctl |= LEMAC_TX_LAB;
1100 MEMCPY(sc->lemac_prodname, &sc->lemac_eeprom[LEMAC_EEP_PRDNM], LEMAC_EEP_PRDNMSZ);
1101 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1112 conf = LE_INB(sc, LEMAC_REG_CNF);
1114 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1115 sc->lemac_lastpage = 63;
1116 conf &= ~LEMAC_CNF_DRAM;
1118 sc->lemac_lastpage = 127;
1119 conf |= LEMAC_CNF_DRAM;
1122 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1124 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1125 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1129 #endif /* !defined(LE_NOLEMAC) */
1131 #if !defined(LE_NOLANCE)
1133 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1135 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1138 static void depca_intr(le_softc_t *sc);
1139 static int lance_init_adapmem(le_softc_t *sc);
1140 static int lance_init_ring(le_softc_t *sc, ln_ring_t *rp, lance_ring_t *ri,
1141 unsigned ndescs, unsigned bufoffset,
1142 unsigned descoffset);
1143 static void lance_init(void *xsc);
1144 static void lance_reset(le_softc_t *sc);
1145 static void lance_intr(le_softc_t *sc);
1146 static int lance_rx_intr(le_softc_t *sc);
1147 static void lance_start(struct ifnet *ifp);
1148 static int lance_tx_intr(le_softc_t *sc);
1150 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1151 #define LN_TXDESC_RATIO 2048
1152 #define LN_DESC_MAX 128
1156 unsigned lance_rx_misses;
1157 unsigned lance_rx_badcrc;
1158 unsigned lance_rx_badalign;
1159 unsigned lance_rx_badframe;
1160 unsigned lance_rx_buferror;
1161 unsigned lance_tx_deferred;
1162 unsigned lance_tx_single_collisions;
1163 unsigned lance_tx_multiple_collisions;
1164 unsigned lance_tx_excessive_collisions;
1165 unsigned lance_tx_late_collisions;
1167 unsigned lance_memory_errors;
1168 unsigned lance_inits;
1169 unsigned lance_tx_intrs;
1170 unsigned lance_tx_nospc[2];
1171 unsigned lance_tx_drains[2];
1172 unsigned lance_tx_orphaned;
1173 unsigned lance_tx_adoptions;
1174 unsigned lance_tx_emptied;
1175 unsigned lance_tx_deftxint;
1176 unsigned lance_tx_buferror;
1177 unsigned lance_high_txoutptr;
1178 unsigned lance_low_txheapsize;
1179 unsigned lance_low_txfree;
1180 unsigned lance_tx_intr_hidescs;
1181 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1183 unsigned lance_rx_intrs;
1184 unsigned lance_rx_badsop;
1185 unsigned lance_rx_contig;
1186 unsigned lance_rx_noncontig;
1187 unsigned lance_rx_intr_hidescs;
1188 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1189 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1192 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1193 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1194 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1197 #define LN_STAT(stat) 0
1198 #define LN_MINSTAT(stat, val) 0
1199 #define LN_MAXSTAT(stat, val) 0
1202 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1203 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1205 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1206 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1209 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1210 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1212 #define LN_SETFLAG(sc, vaddr, val) \
1213 (((volatile u_char *) vaddr)[3] = (val))
1215 #define LN_PUTDESC(sc, desc, vaddr) \
1216 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1217 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1218 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1221 * Only get the descriptor flags and length/status. All else
1224 #define LN_GETDESC(sc, desc, vaddr) \
1225 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1226 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1230 * These definitions are specific to the DEC "DEPCA-style" NICs.
1231 * (DEPCA, DE10x, DE20[012], DE422)
1234 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1235 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1236 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1237 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1238 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1240 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1241 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1242 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1243 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1244 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1245 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1246 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1247 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1248 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1250 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1251 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1253 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1255 #define DEPCA_REG_EISAID 0x80
1256 #define DEPCA_EISAID_MASK 0xf0ffffff
1257 #define DEPCA_EISAID_DE422 0x2042A310
1261 DEPCA_DE100, DEPCA_DE101,
1263 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1268 static const char *depca_signatures[] = {
1272 "DE200", "DE201", "DE202",
1280 const le_board_t *bd,
1283 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1286 * Find out how memory we are dealing with. Adjust
1287 * the ID string offset approriately if we are at
1288 * 32K. Make sure the ROM is enabled.
1290 nicsr = DEPCA_RDNICSR(sc);
1291 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1293 if (nicsr & DEPCA_NICSR_32KRAM) {
1295 * Make we are going to read the upper
1296 * 32K so we do read the ROM.
1298 sc->lance_ramsize = 32 * 1024;
1299 nicsr &= ~DEPCA_NICSR_LOW32K;
1300 sc->lance_ramoffset = 32 * 1024;
1301 idstr_offset -= sc->lance_ramsize;
1303 sc->lance_ramsize = 64 * 1024;
1304 sc->lance_ramoffset = 0;
1306 DEPCA_WRNICSR(sc, nicsr);
1308 sc->le_prodname = NULL;
1309 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1310 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1311 sc->le_prodname = depca_signatures[idx];
1316 if (sc->le_prodname == NULL) {
1318 * Try to get the EISA device if it's a DE422.
1320 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1321 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1322 == DEPCA_EISAID_DE422) {
1323 sc->le_prodname = "DE422";
1328 if (idx == DEPCA_CLASSIC)
1329 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1332 * Try to read the address ROM.
1333 * Stop the LANCE, reset the Address ROM Counter (AAC),
1334 * read the NICSR to "clock" in the reset, and then
1335 * re-enable the Address ROM Counter. Now read the
1338 sc->lance_rdp = DEPCA_REG_RDP;
1339 sc->lance_rap = DEPCA_REG_RAP;
1340 sc->lance_csr3 = LN_CSR3_ALE;
1341 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1342 sc->le_mcmask = LN_MC_MASK;
1343 LN_SELCSR(sc, LN_CSR0);
1344 LN_WRCSR(sc, LN_CSR0_STOP);
1346 if (idx < DEPCA_DE200) {
1347 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1348 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1351 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1354 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
1356 * Renable shared RAM.
1358 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1360 le_intrvec[sc->le_if.if_unit] = depca_intr;
1361 if (!lance_init_adapmem(sc))
1364 sc->if_reset = lance_reset;
1365 sc->if_init = lance_init;
1366 sc->le_if.if_start = lance_start;
1367 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1370 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1371 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1372 *msize = sc->lance_ramsize;
1373 return DEPCA_IOSPACE;
1380 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1385 * Here's as good a place to describe our paritioning of the
1386 * LANCE shared RAM space. (NOTE: this driver does not yet support
1387 * the concept of a LANCE being able to DMA).
1389 * First is the 24 (00:23) bytes for LANCE Initialization Block
1390 * Next are the recieve descriptors. The number is calculated from
1391 * how many LN_BUFSIZE buffers we can allocate (this number must
1392 * be a power of 2). Next are the transmit descriptors. The amount
1393 * of transmit descriptors is derived from the size of the RAM
1394 * divided by 1K. Now come the receive buffers (one for each receive
1395 * descriptor). Finally is the transmit heap. (no fixed buffers are
1396 * allocated so as to make the most use of the limited space).
1402 lance_addr_t rxbufoffset;
1403 lance_addr_t rxdescoffset, txdescoffset;
1404 unsigned rxdescs, txdescs;
1407 * First calculate how many descriptors we heap.
1408 * Note this assumes the ramsize is a power of two.
1410 sc->lance_rxbufsize = LN_BUFSIZE;
1412 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1415 if (rxdescs > LN_DESC_MAX) {
1416 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1417 rxdescs = LN_DESC_MAX;
1419 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1420 if (txdescs > LN_DESC_MAX)
1421 txdescs = LN_DESC_MAX;
1424 * Now calculate where everything goes in memory
1426 rxdescoffset = sizeof(ln_initb_t);
1427 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1428 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1430 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1432 * Remember these for debugging.
1434 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1435 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1438 * Initialize the rings.
1440 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1441 rxdescs, rxbufoffset, rxdescoffset))
1443 sc->lance_rxinfo.ri_heap = rxbufoffset;
1444 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1446 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1447 txdescs, 0, txdescoffset))
1449 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1450 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1453 * Set CSR1 and CSR2 to the address of the init block (which
1454 * for us is always 0.
1456 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1457 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1467 lance_addr_t bufoffset,
1468 lance_addr_t descoffset)
1470 lance_descinfo_t *di;
1473 * Initialize the ring pointer in the LANCE InitBlock
1475 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1476 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1477 rp->r_log2_size = ffs(ndescs) - 1;
1480 * Allocate the ring entry descriptors and initialize
1481 * our ring information data structure. All these are
1482 * our copies and do not live in the LANCE RAM.
1484 ri->ri_first = (lance_descinfo_t *) malloc(ndescs * sizeof(*di), M_DEVBUF, M_NOWAIT);
1485 if (ri->ri_first == NULL) {
1486 printf("lance_init_ring: malloc(%d) failed\n", ndescs * sizeof(*di));
1489 ri->ri_free = ri->ri_max = ndescs;
1490 ri->ri_last = ri->ri_first + ri->ri_max;
1491 for (di = ri->ri_first; di < ri->ri_last; di++) {
1492 di->di_addr = sc->le_membase + descoffset;
1495 di->di_bufaddr = bufoffset;
1496 di->di_buflen = sc->lance_rxbufsize;
1497 bufoffset += sc->lance_rxbufsize;
1499 descoffset += sizeof(ln_desc_t);
1509 printf("%s%d: %s: nicsr=%04x",
1510 sc->le_if.if_name, sc->le_if.if_unit,
1511 id, DEPCA_RDNICSR(sc));
1512 LN_SELCSR(sc, LN_CSR0); printf(" csr0=%04x", LN_RDCSR(sc));
1513 LN_SELCSR(sc, LN_CSR1); printf(" csr1=%04x", LN_RDCSR(sc));
1514 LN_SELCSR(sc, LN_CSR2); printf(" csr2=%04x", LN_RDCSR(sc));
1515 LN_SELCSR(sc, LN_CSR3); printf(" csr3=%04x\n", LN_RDCSR(sc));
1516 LN_SELCSR(sc, LN_CSR0);
1523 register int cnt, csr;
1525 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1527 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1528 LN_WRCSR(sc, LN_CSR0_STOP);
1531 sc->le_flags &= ~IFF_UP;
1532 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1534 le_multi_filter(sc); /* initialize the multicast table */
1535 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1536 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1537 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1538 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1539 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1541 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1542 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1543 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1544 if (sc->le_if.if_flags & IFF_PROMISC) {
1545 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1547 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1550 * We force the init block to be at the start
1551 * of the LANCE's RAM buffer.
1553 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1554 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1555 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1556 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1558 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1561 * clear INITDONE and INIT the chip
1563 LN_SELCSR(sc, LN_CSR0);
1564 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1569 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1574 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1575 lance_dumpcsrs(sc, "lance_reset: reset failure");
1577 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1578 sc->le_if.if_flags |= IFF_UP;
1579 sc->le_flags |= IFF_UP;
1587 le_softc_t *sc = (le_softc_t *)xsc;
1589 lance_descinfo_t *di;
1593 if (sc->le_if.if_flags & IFF_RUNNING) {
1597 * If we were running, requeue any pending transmits.
1599 ri = &sc->lance_txinfo;
1600 di = ri->ri_nextout;
1601 while (ri->ri_free < ri->ri_max) {
1602 if (--di == ri->ri_first)
1603 di = ri->ri_nextout - 1;
1604 if (di->di_mbuf == NULL)
1606 IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
1615 * Reset the transmit ring. Make sure we own all the buffers.
1616 * Also reset the transmit heap.
1618 sc->le_if.if_flags &= ~IFF_OACTIVE;
1619 ri = &sc->lance_txinfo;
1620 for (di = ri->ri_first; di < ri->ri_last; di++) {
1621 if (di->di_mbuf != NULL) {
1622 m_freem(di->di_mbuf);
1626 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1627 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1629 LN_PUTDESC(sc, &desc, di->di_addr);
1631 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1632 ri->ri_free = ri->ri_max;
1633 ri->ri_outptr = ri->ri_heap;
1634 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1636 ri = &sc->lance_rxinfo;
1637 desc.d_flag = LN_DFLAG_OWNER;
1638 desc.d_buflen = 0 - sc->lance_rxbufsize;
1639 for (di = ri->ri_first; di < ri->ri_last; di++) {
1640 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1641 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1642 LN_PUTDESC(sc, &desc, di->di_addr);
1644 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1645 ri->ri_outptr = ri->ri_heap;
1646 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1649 if (sc->le_if.if_flags & IFF_UP) {
1650 sc->le_if.if_flags |= IFF_RUNNING;
1651 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1652 /* lance_dumpcsrs(sc, "lance_init: up"); */
1653 lance_start(&sc->le_if);
1655 /* lance_dumpcsrs(sc, "lance_init: down"); */
1656 sc->le_if.if_flags &= ~IFF_RUNNING;
1666 oldcsr = LN_RDCSR(sc);
1667 oldcsr &= ~LN_CSR0_ENABINTR;
1668 LN_WRCSR(sc, oldcsr);
1669 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1671 if (oldcsr & LN_CSR0_ERRSUM) {
1672 if (oldcsr & LN_CSR0_MISS) {
1674 * LN_CSR0_MISS is signaled when the LANCE receiver
1675 * loses a packet because it doesn't own a receive
1676 * descriptor. Rev. D LANCE chips, which are no
1677 * longer used, require a chip reset as described
1680 LN_STAT(rx_misses++);
1682 if (oldcsr & LN_CSR0_MEMERROR) {
1683 LN_STAT(memory_errors++);
1684 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1691 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1696 if (oldcsr & LN_CSR0_TXINT) {
1697 if (lance_tx_intr(sc))
1698 lance_start(&sc->le_if);
1701 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1702 printf("%s%d: lance_intr: stray interrupt\n",
1703 sc->le_if.if_name, sc->le_if.if_unit);
1710 lance_ring_t *ri = &sc->lance_rxinfo;
1711 lance_descinfo_t *eop;
1713 int ndescs, total_len, rxdescs;
1715 LN_STAT(rx_intrs++);
1717 for (rxdescs = 0;;) {
1719 * Now to try to find the end of this packet chain.
1721 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1723 * If we don't own this descriptor, the packet ain't
1724 * all here so return because we are done.
1726 LN_GETDESC(sc, &desc, eop->di_addr);
1727 if (desc.d_flag & LN_DFLAG_OWNER)
1730 * In case we have missed a packet and gotten the
1731 * LANCE confused, make sure we are pointing at the
1732 * start of a packet. If we aren't, something is really
1733 * strange so reinit the LANCE.
1735 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1736 LN_STAT(rx_buferror++);
1739 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1740 LN_STAT(rx_badsop++);
1743 if (desc.d_flag & LN_DFLAG_EOP)
1745 if (++eop == ri->ri_last)
1749 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1750 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1752 * Valid Packet -- If the SOP is less than or equal to the EOP
1753 * or the length is less than the receive buffer size, then the
1754 * packet is contiguous in memory and can be copied in one shot.
1755 * Otherwise we need to copy two segments to get the entire
1758 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1759 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1760 total_len, total_len, NULL);
1761 LN_STAT(rx_contig++);
1763 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1765 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1766 sc->le_membase + ri->ri_first->di_bufaddr);
1767 LN_STAT(rx_noncontig++);
1771 * If the packet is bad, increment the
1774 sc->le_if.if_ierrors++;
1775 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1776 LN_STAT(rx_badcrc++);
1777 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1778 LN_STAT(rx_badalign++);
1779 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1780 LN_STAT(rx_badframe++);
1782 sc->le_if.if_ipackets++;
1783 LN_STAT(rx_ndescs[ndescs-1]++);
1785 while (ndescs-- > 0) {
1786 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1787 if (++ri->ri_nextin == ri->ri_last)
1788 ri->ri_nextin = ri->ri_first;
1791 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1792 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1801 le_softc_t *sc = (le_softc_t *) ifp;
1802 struct ifqueue *ifq = &ifp->if_snd;
1803 lance_ring_t *ri = &sc->lance_txinfo;
1804 lance_descinfo_t *di;
1807 struct mbuf *m, *m0;
1810 if ((ifp->if_flags & IFF_RUNNING) == 0)
1819 * Make the packet meets the minimum size for Ethernet.
1820 * The slop is so that we also use an even number of longwards.
1822 len = ETHERMIN + sizeof(struct ether_header);
1823 if (m->m_pkthdr.len > len)
1824 len = m->m_pkthdr.len;
1826 slop = (8 - len) & 3;
1828 * If there are no free ring entries (there must be always
1829 * one owned by the host), or there's not enough space for
1830 * this packet, or this packet would wrap around the end
1831 * of LANCE RAM then wait for the transmits to empty for
1832 * space and ring entries to become available.
1834 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1836 * Try to see if we can free up anything off the transit ring.
1838 if (lance_tx_intr(sc) > 0) {
1839 LN_STAT(tx_drains[0]++);
1843 LN_STAT(tx_nospc[0]++);
1847 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1849 * Since the packet won't fit in the end of the transmit
1850 * heap, see if there is space at the beginning of the transmit
1851 * heap. If not, try again when there is space.
1853 LN_STAT(tx_orphaned++);
1854 slop += ri->ri_heapend - ri->ri_outptr;
1855 if (len + slop > ri->ri_outsize) {
1856 LN_STAT(tx_nospc[1]++);
1860 * Point to the beginning of the heap
1862 ri->ri_outptr = ri->ri_heap;
1863 LN_STAT(tx_adoptions++);
1867 * Initialize the descriptor (saving the buffer address,
1868 * buffer length, and mbuf) and write the packet out
1871 di = ri->ri_nextout;
1872 di->di_bufaddr = ri->ri_outptr;
1873 di->di_buflen = len + slop;
1875 bp = sc->le_membase + di->di_bufaddr;
1876 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1877 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1881 * Zero out the remainder if needed (< ETHERMIN).
1883 if (m->m_pkthdr.len < len)
1884 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1887 * Finally, copy out the descriptor and tell the
1888 * LANCE to transmit!.
1890 desc.d_buflen = 0 - len;
1891 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1892 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1893 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1894 LN_PUTDESC(sc, &desc, di->di_addr);
1895 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1898 * Do our bookkeeping with our transmit heap.
1899 * (if we wrap, point back to the beginning).
1901 ri->ri_outptr += di->di_buflen;
1902 ri->ri_outsize -= di->di_buflen;
1903 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1904 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1906 if (ri->ri_outptr == ri->ri_heapend)
1907 ri->ri_outptr = ri->ri_heap;
1910 if (++ri->ri_nextout == ri->ri_last)
1911 ri->ri_nextout = ri->ri_first;
1912 LN_MINSTAT(low_txfree, ri->ri_free);
1915 ifp->if_flags |= IFF_OACTIVE;
1924 lance_ring_t *ri = &sc->lance_txinfo;
1927 LN_STAT(tx_intrs++);
1928 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1931 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1932 if (desc.d_flag & LN_DFLAG_OWNER)
1935 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1936 sc->le_if.if_collisions++;
1937 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1938 LN_STAT(tx_deferred++);
1939 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1940 LN_STAT(tx_single_collisions++);
1941 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1942 LN_STAT(tx_multiple_collisions++);
1944 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1945 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1946 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1947 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1949 LN_STAT(tx_excessive_collisions++);
1950 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1952 printf("%s%d: lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1953 sc->le_if.if_name, sc->le_if.if_unit,
1954 tdr, (tdr*99)/1000, (tdr*117)/1000);
1957 if (desc.d_status & LN_DSTS_TxBUFERROR)
1958 LN_STAT(tx_buferror++);
1959 sc->le_if.if_oerrors++;
1960 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1964 LN_STAT(tx_late_collisions++);
1968 m_freem(ri->ri_nextin->di_mbuf);
1969 ri->ri_nextin->di_mbuf = NULL;
1970 sc->le_if.if_opackets++;
1972 ri->ri_outsize += ri->ri_nextin->di_buflen;
1973 if (++ri->ri_nextin == ri->ri_last)
1974 ri->ri_nextin = ri->ri_first;
1975 sc->le_if.if_flags &= ~IFF_OACTIVE;
1978 if (ri->ri_free == ri->ri_max)
1979 LN_STAT(tx_emptied++);
1980 /* LN_STAT(tx_intr_descs[xmits]++); */
1981 LN_MAXSTAT(tx_intr_hidescs, xmits);
1984 #endif /* !defined(LE_NOLANCE) */