1 /* $FreeBSD: src/sys/dev/mii/miidevs.h,v 1.4.2.12 2003/05/13 21:21:33 ps Exp $ */
4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
9 /*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/
12 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
13 * All rights reserved.
15 * This code is derived from software contributed to The NetBSD Foundation
16 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
17 * NASA Ames Research Center.
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20 * modification, are permitted provided that the following conditions
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29 * This product includes software developed by the NetBSD
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45 * POSSIBILITY OF SUCH DAMAGE.
49 * List of known MII OUIs.
50 * For a complete list see http://standards.ieee.org/regauth/oui/
52 * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped
53 * to the 16 bits available in the id registers. The MII_OUI() macro
54 * in "mii.h" reflects the most obvious way. If a vendor uses a
55 * different mapping, an "xx" prefixed OUI is defined here which is
56 * mangled accordingly to compensate.
59 #define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
60 #define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
61 #define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
62 #define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
63 #define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
64 #define MII_OUI_INTEL 0x00aa00 /* Intel */
65 #define MII_OUI_JATO 0x00e083 /* Jato Technologies */
66 #define MII_OUI_LEVEL1 0x00207b /* Level 1 */
67 #define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
68 #define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
69 #define MII_OUI_REALTEK 0x000020 /* RealTek Semicondctor */
70 #define MII_OUI_SEEQ 0x00a07d /* Seeq */
71 #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
72 #define MII_OUI_TDK 0x00c039 /* TDK */
73 #define MII_OUI_TI 0x080028 /* Texas Instruments */
74 #define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
75 #define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
77 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */
78 #define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
80 /* Intel 82553 A/B steppings */
81 #define MII_OUI_xxINTEL 0x00f800 /* Intel */
83 /* some vendors have the bits swapped within bytes
84 (ie, ordered as on the wire) */
85 #define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */
86 #define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
87 #define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */
88 #define MII_OUI_xxSEEQ 0x0005be /* Seeq */
89 #define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */
90 #define MII_OUI_xxTI 0x100014 /* Texas Instruments */
91 #define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */
93 /* Level 1 is completely different - from right to left.
94 (Two bits get lost in the third OUI byte.) */
95 #define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */
97 /* Don't know what's going on here. */
98 #define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */
102 * List of known models. Grouped by oui.
105 /* Altima Communications PHYs */
106 #define MII_MODEL_xxALTIMA_AC101 0x0021
107 #define MII_STR_xxALTIMA_AC101 "AC101 10/100 media interface"
109 /* Advanced Micro Devices PHYs */
110 #define MII_MODEL_xxAMD_79C873 0x0000
111 #define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface"
112 #define MII_MODEL_AMD_79c973phy 0x0036
113 #define MII_STR_AMD_79c973phy "Am79c973 internal PHY"
114 #define MII_MODEL_AMD_79c978 0x0039
115 #define MII_STR_AMD_79c978 "Am79c978 HomePNA PHY"
117 /* Broadcom Corp. PHYs. */
118 #define MII_MODEL_BROADCOM_3c905Cphy 0x0017
119 #define MII_STR_BROADCOM_3c905Cphy "3c905C 10/100 internal PHY"
120 #define MII_MODEL_xxBROADCOM_BCM5400 0x0004
121 #define MII_STR_xxBROADCOM_BCM5400 "Broadcom 1000baseTX PHY"
122 #define MII_MODEL_xxBROADCOM_BCM5401 0x0005
123 #define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseTX PHY"
124 #define MII_MODEL_xxBROADCOM_BCM5411 0x0007
125 #define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseTX PHY"
126 #define MII_MODEL_xxBROADCOM_BCM5701 0x0011
127 #define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseTX PHY"
128 #define MII_MODEL_xxBROADCOM_BCM5703 0x0016
129 #define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseTX PHY"
130 #define MII_MODEL_xxBROADCOM_BCM5704 0x0019
131 #define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseTX PHY"
133 /* Davicom Semiconductor PHYs */
134 #define MII_MODEL_xxDAVICOM_DM9101 0x0000
135 #define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 media interface"
137 /* Integrated Circuit Systems PHYs */
138 #define MII_MODEL_xxICS_1890 0x0002
139 #define MII_STR_xxICS_1890 "ICS1890 10/100 media interface"
142 #define MII_MODEL_xxINTEL_I82553AB 0x0000
143 #define MII_STR_xxINTEL_I82553AB "i83553 10/100 media interface"
144 #define MII_MODEL_INTEL_I82555 0x0015
145 #define MII_STR_INTEL_I82555 "i82555 10/100 media interface"
146 #define MII_MODEL_INTEL_I82562EM 0x0032
147 #define MII_STR_INTEL_I82562EM "i82562EM 10/100 media interface"
148 #define MII_MODEL_INTEL_I82562ET 0x0033
149 #define MII_STR_INTEL_I82562ET "i82562ET 10/100 media interface"
150 #define MII_MODEL_INTEL_I82553C 0x0035
151 #define MII_STR_INTEL_I82553C "i82553 10/100 media interface"
153 /* Jato Technologies PHYs */
154 #define MII_MODEL_JATO_BASEX 0x0000
155 #define MII_STR_JATO_BASEX "Jato 1000baseX media interface"
158 #define MII_MODEL_xxLEVEL1_LXT970 0x0000
159 #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
161 /* National Semiconductor PHYs */
162 #define MII_MODEL_NATSEMI_DP83840 0x0000
163 #define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface"
164 #define MII_MODEL_NATSEMI_DP83843 0x0001
165 #define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface"
166 #define MII_MODEL_NATSEMI_DP83891 0x0005
167 #define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 media interface"
168 #define MII_MODEL_NATSEMI_DP83861 0x0006
169 #define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 media interface"
171 /* Quality Semiconductor PHYs */
172 #define MII_MODEL_QUALSEMI_QS6612 0x0000
173 #define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface"
175 /* RealTek Semiconductor PHYs */
176 #define MII_MODEL_REALTEK_RTL8201L 0x0020
177 #define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 media interface"
180 #define MII_MODEL_xxSEEQ_80220 0x0003
181 #define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface"
182 #define MII_MODEL_xxSEEQ_84220 0x0004
183 #define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface"
185 /* Silicon Integrated Systems PHYs */
186 #define MII_MODEL_xxSIS_900 0x0000
187 #define MII_STR_xxSIS_900 "SiS 900 10/100 media interface"
190 #define MII_MODEL_TDK_78Q2120 0x0014
191 #define MII_STR_TDK_78Q2120 "TDK 78Q2120 media interface"
193 /* Texas Instruments PHYs */
194 #define MII_MODEL_xxTI_TLAN10T 0x0001
195 #define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface"
196 #define MII_MODEL_xxTI_100VGPMI 0x0002
197 #define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
199 /* XaQti Corp. PHYs. */
200 #define MII_MODEL_XAQTI_XMACII 0x0000
201 #define MII_STR_XAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
203 /* Marvell Semiconductor PHYs */
204 #define MII_MODEL_MARVELL_E1000 0x0000
205 #define MII_STR_MARVELL_E1000 "Marvell Semiconductor 88E1000* gigabit PHY"