sys/dev/netif/sr/if_sr.c

   1 /*
   2  * Copyright (c) 1996 - 2001 John Hay.
   3  * Copyright (c) 1996 SDL Communications, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the author nor the names of any co-contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
  31  */
  32
  33 /*
  34  * Programming assumptions and other issues.
  35  *
  36  * Only a 16K window will be used.
  37  *
  38  * The descriptors of a DMA channel will fit in a 16K memory window.
  39  *
  40  * The buffers of a transmit DMA channel will fit in a 16K memory window.
  41  *
  42  * When interface is going up, handshaking is set and it is only cleared
  43  * when the interface is down'ed.
  44  *
  45  * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
  46  * internal/external clock, etc.....
  47  *
  48  */
  49
  50 #include "opt_netgraph.h"
  51 #ifdef NETGRAPH
  52 #include <dev/sr/if_sr.h>
  53 #endif  /* NETGRAPH */
  54
  55 #include <sys/param.h>
  56 #include <sys/systm.h>
  57 #include <sys/kernel.h>
  58 #include <sys/malloc.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/sockio.h>
  61 #include <sys/socket.h>
  62 #include <sys/bus.h>
  63 #include <machine/bus.h>
  64 #include <machine/resource.h>
  65 #include <machine/bus_pio.h>
  66 #include <machine/bus_memio.h>
  67 #include <sys/rman.h>
  68
  69 #include <net/if.h>
  70 #ifdef NETGRAPH
  71 #include <sys/syslog.h>
  72 #else /* NETGRAPH */
  73 #include <net/if_sppp.h>
  74
  75 #include <net/bpf.h>
  76 #endif  /* NETGRAPH */
  77
  78 #include <machine/md_var.h>
  79
  80 #include <dev/ic/hd64570.h>
  81 #include <dev/sr/if_srregs.h>
  82
  83 #ifdef NETGRAPH
  84 #include <netgraph/ng_message.h>
  85 #include <netgraph/netgraph.h>
  86 #endif /* NETGRAPH */
  87 /* #define USE_MODEMCK */
  88
  89 #ifndef BUGGY
  90 #define BUGGY           0
  91 #endif
  92
  93 #ifndef NETGRAPH
  94 #define PPP_HEADER_LEN  4
  95 #endif /* NETGRAPH */
  96
  97 static int      next_sc_unit = 0;
  98 #ifndef NETGRAPH
  99 #ifdef USE_MODEMCK
 100 static int      sr_watcher = 0;
 101 #endif
 102 #endif /* NETGRAPH */
 103
 104 /*
 105  * Define the software interface for the card... There is one for
 106  * every channel (port).
 107  */
 108 struct sr_softc {
 109 #ifndef NETGRAPH
 110         struct  sppp ifsppp;    /* PPP service w/in system */
 111 #endif /* NETGRAPH */
 112         struct  sr_hardc *hc;   /* card-level information */
 113
 114         int     unit;           /* With regard to all sr devices */
 115         int     subunit;        /* With regard to this card */
 116
 117         struct  buf_block {
 118                 u_int   txdesc; /* DPRAM offset */
 119                 u_int   txstart;/* DPRAM offset */
 120                 u_int   txend;  /* DPRAM offset */
 121                 u_int   txtail; /* # of 1st free gran */
 122                 u_int   txmax;  /* # of free grans */
 123                 u_int   txeda;  /* err descr addr */
 124         } block[SR_TX_BLOCKS];
 125
 126         char    xmit_busy;      /* Transmitter is busy */
 127         char    txb_inuse;      /* # of tx grans in use */
 128         u_int   txb_new;        /* ndx to new buffer */
 129         u_int   txb_next_tx;    /* ndx to next gran rdy tx */
 130
 131         u_int   rxdesc;         /* DPRAM offset */
 132         u_int   rxstart;        /* DPRAM offset */
 133         u_int   rxend;          /* DPRAM offset */
 134         u_int   rxhind;         /* ndx to the hd of rx bufrs */
 135         u_int   rxmax;          /* # of avail grans */
 136
 137         u_int   clk_cfg;        /* Clock configuration */
 138
 139         int     scachan;        /* channel # on card */
 140 #ifdef NETGRAPH
 141         int     running;        /* something is attached so we are running */
 142         int     dcd;            /* do we have dcd? */
 143         /* ---netgraph bits --- */
 144         char            nodename[NG_NODELEN + 1]; /* store our node name */
 145         int             datahooks;      /* number of data hooks attached */
 146         node_p          node;           /* netgraph node */
 147         hook_p          hook;           /* data hook */
 148         hook_p          debug_hook;
 149         struct ifqueue  xmitq_hipri;    /* hi-priority transmit queue */
 150         struct ifqueue  xmitq;          /* transmit queue */
 151         int             flags;          /* state */
 152 #define SCF_RUNNING     0x01            /* board is active */
 153 #define SCF_OACTIVE     0x02            /* output is active */
 154         int             out_dog;        /* watchdog cycles output count-down */
 155 #if ( __FreeBSD__ >= 3 )
 156         struct callout_handle handle;   /* timeout(9) handle */
 157 #endif
 158         u_long          inbytes, outbytes;      /* stats */
 159         u_long          lastinbytes, lastoutbytes; /* a second ago */
 160         u_long          inrate, outrate;        /* highest rate seen */
 161         u_long          inlast;         /* last input N secs ago */
 162         u_long          out_deficit;    /* output since last input */
 163         u_long          oerrors, ierrors[6];
 164         u_long          opackets, ipackets;
 165 #endif /* NETGRAPH */
 166 };
 167
 168 #ifdef NETGRAPH
 169 #define DOG_HOLDOFF     6       /* dog holds off for 6 secs */
 170 #define QUITE_A_WHILE   300     /* 5 MINUTES */
 171 #define LOTS_OF_PACKETS 100
 172 #endif /* NETGRAPH */
 173
 174 /*
 175  * Baud Rate table for Sync Mode.
 176  * Each entry consists of 3 elements:
 177  * Baud Rate (x100) , TMC, BR
 178  *
 179  * Baud Rate = FCLK / TMC / 2^BR
 180  * Baud table for Crystal freq. of 9.8304 Mhz
 181  */
 182 #ifdef N2_TEST_SPEED
 183 struct rate_line {
 184         int     target;         /* target rate/100 */
 185         int     tmc_reg;        /* TMC register value */
 186         int     br_reg;         /* BR (BaudRateClk) selector */
 187 } n2_rates[] = {
 188         /* Baudx100     TMC             BR */
 189         { 3,            128,            8 },
 190         { 6,            128,            7 },
 191         { 12,           128,            6 },
 192         { 24,           128,            5 },
 193         { 48,           128,            4 },
 194         { 96,           128,            3 },
 195         { 192,          128,            2 },
 196         { 384,          128,            1 },
 197         { 560,          88,             1 },
 198         { 640,          77,             1 },
 199         { 1280,         38,             1 },
 200         { 2560,         19,             1 },
 201         { 5120,         10,             1 },
 202         { 10000,        5,              1 },
 203         { 15000,        3,              1 },
 204         { 25000,        2,              1 },
 205         { 50000,        1,              1 },
 206         { 0,            0,              0 }
 207 };
 208
 209 int     sr_test_speed[] = {
 210         N2_TEST_SPEED,
 211         N2_TEST_SPEED
 212 };
 213
 214 int     etc0vals[] = {
 215         SR_MCR_ETC0,            /* ISA channel 0 */
 216         SR_MCR_ETC1,            /* ISA channel 1 */
 217         SR_FECR_ETC0,           /* PCI channel 0 */
 218         SR_FECR_ETC1            /* PCI channel 1 */
 219 };
 220 #endif
 221
 222 devclass_t sr_devclass;
 223 #ifndef NETGRAPH
 224 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
 225 #else
 226 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
 227 #endif
 228
 229 static void     srintr(void *arg);
 230 static void     sr_xmit(struct sr_softc *sc);
 231 #ifndef NETGRAPH
 232 static void     srstart(struct ifnet *ifp);
 233 static int      srioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
 234 static void     srwatchdog(struct ifnet *ifp);
 235 #else
 236 static void     srstart(struct sr_softc *sc);
 237 static void     srwatchdog(struct sr_softc *sc);
 238 #endif /* NETGRAPH */
 239 static int      sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
 240 static void     sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
 241 static void     sr_eat_packet(struct sr_softc *sc, int single);
 242 static void     sr_get_packets(struct sr_softc *sc);
 243
 244 static void     sr_up(struct sr_softc *sc);
 245 static void     sr_down(struct sr_softc *sc);
 246 static void     src_init(struct sr_hardc *hc);
 247 static void     sr_init_sca(struct sr_hardc *hc);
 248 static void     sr_init_msci(struct sr_softc *sc);
 249 static void     sr_init_rx_dmac(struct sr_softc *sc);
 250 static void     sr_init_tx_dmac(struct sr_softc *sc);
 251 static void     sr_dmac_intr(struct sr_hardc *hc, u_char isr);
 252 static void     sr_msci_intr(struct sr_hardc *hc, u_char isr);
 253 static void     sr_timer_intr(struct sr_hardc *hc, u_char isr);
 254 #ifndef NETGRAPH
 255 #ifdef USE_MODEMCK
 256 static void     sr_modemck(void *x);
 257 #endif
 258 #else
 259 static void     sr_modemck(struct sr_softc *x);
 260 #endif /* NETGRAPH */
 261
 262 #ifdef NETGRAPH
 263 static  void    ngsr_watchdog_frame(void * arg);
 264 static  void    ngsr_init(void* ignored);
 265
 266 static ng_constructor_t ngsr_constructor;
 267 static ng_rcvmsg_t      ngsr_rcvmsg;
 268 static ng_shutdown_t    ngsr_rmnode;
 269 static ng_newhook_t     ngsr_newhook;
 270 /*static ng_findhook_t  ngsr_findhook; */
 271 static ng_connect_t     ngsr_connect;
 272 static ng_rcvdata_t     ngsr_rcvdata;
 273 static ng_disconnect_t  ngsr_disconnect;
 274
 275 static struct ng_type typestruct = {
 276         NG_VERSION,
 277         NG_SR_NODE_TYPE,
 278         NULL,
 279         ngsr_constructor,
 280         ngsr_rcvmsg,
 281         ngsr_rmnode,
 282         ngsr_newhook,
 283         NULL,
 284         ngsr_connect,
 285         ngsr_rcvdata,
 286         ngsr_rcvdata,
 287         ngsr_disconnect,
 288         NULL
 289 };
 290
 291 static int      ngsr_done_init = 0;
 292 #endif /* NETGRAPH */
 293
 294 /*
 295  * Register the ports on the adapter.
 296  * Fill in the info for each port.
 297 #ifndef NETGRAPH
 298  * Attach each port to sppp and bpf.
 299 #endif
 300  */
 301 int
 302 sr_attach(device_t device)
 303 {
 304         int intf_sw, pndx;
 305         u_int32_t flags;
 306         u_int fecr, *fecrp;
 307         struct sr_hardc *hc;
 308         struct sr_softc *sc;
 309 #ifndef NETGRAPH
 310         struct ifnet *ifp;
 311 #endif /* NETGRAPH */
 312         int unit;               /* index: channel w/in card */
 313
 314         hc = (struct sr_hardc *)device_get_softc(device);
 315         MALLOC(sc, struct sr_softc *,
 316                 hc->numports * sizeof(struct sr_softc),
 317                 M_DEVBUF, M_WAITOK | M_ZERO);
 318         if (sc == NULL)
 319                 goto errexit;
 320         hc->sc = sc;
 321
 322         /*
 323          * Get the TX clock direction and configuration. The default is a
 324          * single external clock which is used by RX and TX.
 325          */
 326         switch(hc->cardtype) {
 327         case SR_CRD_N2:
 328                 flags = device_get_flags(device);
 329 #ifdef N2_TEST_SPEED
 330                 if (sr_test_speed[0] > 0)
 331                         hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 332                 else
 333 #endif
 334                 if (flags & SR_FLAGS_0_CLK_MSK)
 335                         hc->sc[0].clk_cfg =
 336                             (flags & SR_FLAGS_0_CLK_MSK)
 337                             >> SR_FLAGS_CLK_SHFT;
 338
 339                 if (hc->numports == 2)
 340 #ifdef N2_TEST_SPEED
 341                         if (sr_test_speed[1] > 0)
 342                                 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 343                         else
 344 #endif
 345                         if (flags & SR_FLAGS_1_CLK_MSK)
 346                                 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
 347                                     >> (SR_FLAGS_CLK_SHFT +
 348                                     SR_FLAGS_CLK_CHAN_SHFT);
 349                 break;
 350         case SR_CRD_N2PCI:
 351                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
 352                 fecr = *fecrp;
 353                 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
 354                         switch (pndx) {
 355                         case 1:
 356                                 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
 357                                 break;
 358                         case 0:
 359                         default:
 360                                 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
 361                         }
 362
 363 #ifdef N2_TEST_SPEED
 364                         if (sr_test_speed[pndx] > 0)
 365                                 sc->clk_cfg = SR_FLAGS_INT_CLK;
 366                         else
 367 #endif
 368                                 switch (intf_sw) {
 369                                 default:
 370                                 case SR_FE_ID_RS232:
 371                                 case SR_FE_ID_HSSI:
 372                                 case SR_FE_ID_RS422:
 373                                 case SR_FE_ID_TEST:
 374                                         break;
 375
 376                                 case SR_FE_ID_V35:
 377                                         sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
 378                                         break;
 379
 380                                 case SR_FE_ID_X21:
 381                                         sc->clk_cfg = SR_FLAGS_EXT_CLK;
 382                                         break;
 383                                 }
 384                 }
 385                 sc = hc->sc;
 386                 break;
 387         }
 388
 389         /*
 390          * Report Card configuration information before we start configuring
 391          * each channel on the card...
 392          */
 393         printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
 394                hc->cunit, hc->memsize / 1024, hc->mempages,
 395                (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
 396
 397         src_init(hc);
 398         sr_init_sca(hc);
 399
 400         if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
 401             INTR_TYPE_NET, srintr, hc, &hc->intr_cookie) != 0)
 402                 goto errexit;
 403
 404         /*
 405          * Now configure each port on the card.
 406          */
 407         for (unit = 0; unit < hc->numports; sc++, unit++) {
 408                 sc->hc = hc;
 409                 sc->subunit = unit;
 410                 sc->unit = next_sc_unit;
 411                 next_sc_unit++;
 412                 sc->scachan = unit % NCHAN;
 413
 414                 sr_init_rx_dmac(sc);
 415                 sr_init_tx_dmac(sc);
 416                 sr_init_msci(sc);
 417
 418                 printf("sr%d: Adapter %d, port %d.\n",
 419                        sc->unit, hc->cunit, sc->subunit);
 420
 421 #ifndef NETGRAPH
 422                 ifp = &sc->ifsppp.pp_if;
 423                 ifp->if_softc = sc;
 424                 ifp->if_unit = sc->unit;
 425                 ifp->if_name = "sr";
 426                 ifp->if_mtu = PP_MTU;
 427                 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
 428                 ifp->if_ioctl = srioctl;
 429                 ifp->if_start = srstart;
 430                 ifp->if_watchdog = srwatchdog;
 431
 432                 sc->ifsppp.pp_flags = PP_KEEPALIVE;
 433                 sppp_attach((struct ifnet *)&sc->ifsppp);
 434                 if_attach(ifp);
 435
 436                 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
 437 #else   /* NETGRAPH */
 438                 /*
 439                  * we have found a node, make sure our 'type' is availabe.
 440                  */
 441                 if (ngsr_done_init == 0) ngsr_init(NULL);
 442                 if (ng_make_node_common(&typestruct, &sc->node) != 0)
 443                         goto errexit;
 444                 sc->node->private = sc;
 445                 callout_handle_init(&sc->handle);
 446                 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
 447                 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
 448                 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
 449                 if (ng_name_node(sc->node, sc->nodename)) {
 450                         ng_rmnode(sc->node);
 451                         ng_unref(sc->node);
 452                         return (0);
 453                 }
 454                 sc->running = 0;
 455 #endif  /* NETGRAPH */
 456         }
 457
 458         if (hc->mempages)
 459                 SRC_SET_OFF(hc->iobase);
 460
 461         return (0);
 462
 463 errexit:
 464         sr_deallocate_resources(device);
 465         return (ENXIO);
 466 }
 467
 468 int
 469 sr_detach(device_t device)
 470 {
 471         device_t parent = device_get_parent(device);
 472         struct sr_hardc *hc = device_get_softc(device);
 473
 474         if (hc->intr_cookie != NULL) {
 475                 if (BUS_TEARDOWN_INTR(parent, device,
 476                         hc->res_irq, hc->intr_cookie) != 0) {
 477                                 printf("intr teardown failed.. continuing\n");
 478                 }
 479                 hc->intr_cookie = NULL;
 480         }
 481
 482         /* XXX Stop the DMA. */
 483
 484         /*
 485          * deallocate any system resources we may have
 486          * allocated on behalf of this driver.
 487          */
 488         FREE(hc->sc, M_DEVBUF);
 489         hc->sc = NULL;
 490         hc->mem_start = NULL;
 491         return (sr_deallocate_resources(device));
 492 }
 493
 494 int
 495 sr_allocate_ioport(device_t device, int rid, u_long size)
 496 {
 497         struct sr_hardc *hc = device_get_softc(device);
 498
 499         hc->rid_ioport = rid;
 500         hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
 501                         &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
 502         if (hc->res_ioport == NULL) {
 503                 goto errexit;
 504         }
 505         return (0);
 506
 507 errexit:
 508         sr_deallocate_resources(device);
 509         return (ENXIO);
 510 }
 511
 512 int
 513 sr_allocate_irq(device_t device, int rid, u_long size)
 514 {
 515         struct sr_hardc *hc = device_get_softc(device);
 516
 517         hc->rid_irq = rid;
 518         hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ,
 519                         &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE);
 520         if (hc->res_irq == NULL) {
 521                 goto errexit;
 522         }
 523         return (0);
 524
 525 errexit:
 526         sr_deallocate_resources(device);
 527         return (ENXIO);
 528 }
 529
 530 int
 531 sr_allocate_memory(device_t device, int rid, u_long size)
 532 {
 533         struct sr_hardc *hc = device_get_softc(device);
 534
 535         hc->rid_memory = rid;
 536         hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 537                         &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
 538         if (hc->res_memory == NULL) {
 539                 goto errexit;
 540         }
 541         return (0);
 542
 543 errexit:
 544         sr_deallocate_resources(device);
 545         return (ENXIO);
 546 }
 547
 548 int
 549 sr_allocate_plx_memory(device_t device, int rid, u_long size)
 550 {
 551         struct sr_hardc *hc = device_get_softc(device);
 552
 553         hc->rid_plx_memory = rid;
 554         hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 555                         &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
 556         if (hc->res_plx_memory == NULL) {
 557                 goto errexit;
 558         }
 559         return (0);
 560
 561 errexit:
 562         sr_deallocate_resources(device);
 563         return (ENXIO);
 564 }
 565
 566 int
 567 sr_deallocate_resources(device_t device)
 568 {
 569         struct sr_hardc *hc = device_get_softc(device);
 570
 571         if (hc->res_irq != 0) {
 572                 bus_deactivate_resource(device, SYS_RES_IRQ,
 573                         hc->rid_irq, hc->res_irq);
 574                 bus_release_resource(device, SYS_RES_IRQ,
 575                         hc->rid_irq, hc->res_irq);
 576                 hc->res_irq = 0;
 577         }
 578         if (hc->res_ioport != 0) {
 579                 bus_deactivate_resource(device, SYS_RES_IOPORT,
 580                         hc->rid_ioport, hc->res_ioport);
 581                 bus_release_resource(device, SYS_RES_IOPORT,
 582                         hc->rid_ioport, hc->res_ioport);
 583                 hc->res_ioport = 0;
 584         }
 585         if (hc->res_memory != 0) {
 586                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 587                         hc->rid_memory, hc->res_memory);
 588                 bus_release_resource(device, SYS_RES_MEMORY,
 589                         hc->rid_memory, hc->res_memory);
 590                 hc->res_memory = 0;
 591         }
 592         if (hc->res_plx_memory != 0) {
 593                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 594                         hc->rid_plx_memory, hc->res_plx_memory);
 595                 bus_release_resource(device, SYS_RES_MEMORY,
 596                         hc->rid_plx_memory, hc->res_plx_memory);
 597                 hc->res_plx_memory = 0;
 598         }
 599         return (0);
 600 }
 601
 602 /*
 603  * N2 Interrupt Service Routine
 604  *
 605  * First figure out which SCA gave the interrupt.
 606  * Process it.
 607  * See if there is other interrupts pending.
 608  * Repeat until there no interrupts remain.
 609  */
 610 static void
 611 srintr(void *arg)
 612 {
 613         struct sr_hardc *hc = (struct sr_hardc *)arg;
 614         sca_regs *sca = hc->sca;        /* MSCI register tree */
 615         u_char  isr0, isr1, isr2;       /* interrupt statii captured */
 616
 617 #if BUGGY > 1
 618         printf("sr: srintr_hc(hc=%08x)\n", hc);
 619 #endif
 620
 621         /*
 622          * Since multiple interfaces may share this interrupt, we must loop
 623          * until no interrupts are still pending service.
 624          */
 625         while (1) {
 626                 /*
 627                  * Read all three interrupt status registers from the N2
 628                  * card...
 629                  */
 630                 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
 631                 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
 632                 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
 633
 634                 /*
 635                  * If all three registers returned 0, we've finished
 636                  * processing interrupts from this device, so we can quit
 637                  * this loop...
 638                  */
 639                 if ((isr0 | isr1 | isr2) == 0)
 640                         break;
 641
 642 #if BUGGY > 2
 643                 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
 644 #ifndef NETGRAPH
 645                         unit, isr0, isr1, isr2);
 646 #else
 647                         hc->cunit, isr0, isr1, isr2);
 648 #endif /* NETGRAPH */
 649 #endif
 650
 651                 /*
 652                  * Now we can dispatch the interrupts. Since we don't expect
 653                  * either MSCI or timer interrupts, we'll test for DMA
 654                  * interrupts first...
 655                  */
 656                 if (isr1)       /* DMA-initiated interrupt */
 657                         sr_dmac_intr(hc, isr1);
 658
 659                 if (isr0)       /* serial part IRQ? */
 660                         sr_msci_intr(hc, isr0);
 661
 662                 if (isr2)       /* timer-initiated interrupt */
 663                         sr_timer_intr(hc, isr2);
 664         }
 665 }
 666
 667 /*
 668  * This will only start the transmitter. It is assumed that the data
 669  * is already there.
 670  * It is normally called from srstart() or sr_dmac_intr().
 671  */
 672 static void
 673 sr_xmit(struct sr_softc *sc)
 674 {
 675         u_short cda_value;      /* starting descriptor */
 676         u_short eda_value;      /* ending descriptor */
 677         struct sr_hardc *hc;
 678 #ifndef NETGRAPH
 679         struct ifnet *ifp;      /* O/S Network Services */
 680 #endif /* NETGRAPH */
 681         dmac_channel *dmac;     /* DMA channel registers */
 682
 683 #if BUGGY > 0
 684         printf("sr: sr_xmit( sc=%08x)\n", sc);
 685 #endif
 686
 687         hc = sc->hc;
 688 #ifndef NETGRAPH
 689         ifp = &sc->ifsppp.pp_if;
 690 #endif /* NETGRAPH */
 691         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
 692
 693         /*
 694          * Get the starting and ending addresses of the chain to be
 695          * transmitted and pass these on to the DMA engine on-chip.
 696          */
 697         cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
 698         cda_value &= 0x00ffff;
 699         eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
 700         eda_value &= 0x00ffff;
 701
 702         SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
 703         SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
 704
 705         /*
 706          * Now we'll let the DMA status register know about this change
 707          */
 708         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
 709
 710         sc->xmit_busy = 1;      /* mark transmitter busy */
 711
 712 #if BUGGY > 2
 713         printf("sr%d: XMIT  cda=%04x, eda=%4x, rcda=%08lx\n",
 714                sc->unit, cda_value, eda_value,
 715                sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
 716 #endif
 717
 718         sc->txb_next_tx++;      /* update next transmit seq# */
 719
 720         if (sc->txb_next_tx == SR_TX_BLOCKS)    /* handle wrap... */
 721                 sc->txb_next_tx = 0;
 722
 723 #ifndef NETGRAPH
 724         /*
 725          * Finally, we'll set a timout (which will start srwatchdog())
 726          * within the O/S network services layer...
 727          */
 728         ifp->if_timer = 2;      /* Value in seconds. */
 729 #else
 730         /*
 731          * Don't time out for a while.
 732          */
 733         sc->out_dog = DOG_HOLDOFF;      /* give ourself some breathing space*/
 734 #endif /* NETGRAPH */
 735 }
 736
 737 /*
 738  * This function will be called from the upper level when a user add a
 739  * packet to be send, and from the interrupt handler after a finished
 740  * transmit.
 741  *
 742  * NOTE: it should run at spl_imp().
 743  *
 744  * This function only place the data in the oncard buffers. It does not
 745  * start the transmition. sr_xmit() does that.
 746  *
 747  * Transmitter idle state is indicated by the IFF_OACTIVE flag.
 748  * The function that clears that should ensure that the transmitter
 749  * and its DMA is in a "good" idle state.
 750  */
 751 #ifndef NETGRAPH
 752 static void
 753 srstart(struct ifnet *ifp)
 754 {
 755         struct sr_softc *sc;    /* channel control structure */
 756 #else
 757 static void
 758 srstart(struct sr_softc *sc)
 759 {
 760 #endif /* NETGRAPH */
 761         struct sr_hardc *hc;    /* card control/config block */
 762         int len;                /* total length of a packet */
 763         int pkts;               /* packets placed in DPRAM */
 764         int tlen;               /* working length of pkt */
 765         u_int i;
 766         struct mbuf *mtx;       /* message buffer from O/S */
 767         u_char *txdata;         /* buffer address in DPRAM */
 768         sca_descriptor *txdesc; /* working descriptor pointr */
 769         struct buf_block *blkp;
 770
 771 #ifndef NETGRAPH
 772 #if BUGGY > 0
 773         printf("sr: srstart( ifp=%08x)\n", ifp);
 774 #endif
 775         sc = ifp->if_softc;
 776         if ((ifp->if_flags & IFF_RUNNING) == 0)
 777                 return;
 778 #endif /* NETGRAPH */
 779         hc = sc->hc;
 780         /*
 781          * It is OK to set the memory window outside the loop because all tx
 782          * buffers and descriptors are assumed to be in the same 16K window.
 783          */
 784         if (hc->mempages) {
 785                 SRC_SET_ON(hc->iobase);
 786                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
 787         }
 788
 789         /*
 790          * Loop to place packets into DPRAM.
 791          *
 792          * We stay in this loop until there is nothing in
 793          * the TX queue left or the tx buffers are full.
 794          */
 795 top_srstart:
 796
 797         /*
 798          * See if we have space for more packets.
 799          */
 800         if (sc->txb_inuse == SR_TX_BLOCKS) {    /* out of space? */
 801 #ifndef NETGRAPH
 802                 ifp->if_flags |= IFF_OACTIVE;   /* yes, mark active */
 803 #else
 804                 /*ifp->if_flags |= IFF_OACTIVE;*/       /* yes, mark active */
 805 #endif /* NETGRAPH */
 806
 807                 if (hc->mempages)
 808                         SRC_SET_OFF(hc->iobase);
 809
 810 #if BUGGY > 9
 811                 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
 812                        sc->unit, sc->txb_inuse);
 813 #endif
 814                 return;
 815         }
 816         /*
 817          * OK, the card can take more traffic.  Let's see if there's any
 818          * pending from the system...
 819          *
 820          * NOTE:
 821          * The architecture of the networking interface doesn't
 822          * actually call us like 'write()', providing an address.  We get
 823          * started, a lot like a disk strategy routine, and we actually call
 824          * back out to the system to get traffic to send...
 825          *
 826          * NOTE:
 827          * If we were gonna run through another layer, we would use a
 828          * dispatch table to select the service we're getting a packet
 829          * from...
 830          */
 831 #ifndef NETGRAPH
 832         mtx = sppp_dequeue(ifp);
 833 #else /* NETGRAPH */
 834         IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 835         if (mtx == NULL) {
 836                 IF_DEQUEUE(&sc->xmitq, mtx);
 837         }
 838 #endif /* NETGRAPH */
 839         if (!mtx) {
 840                 if (hc->mempages)
 841                         SRC_SET_OFF(hc->iobase);
 842                 return;
 843         }
 844         /*
 845          * OK, we got a packet from the network services of the O/S. Now we
 846          * can move it into the DPRAM (under control of the descriptors) and
 847          * fire it off...
 848          */
 849         pkts = 0;
 850         i = 0;                  /* counts # of granules used */
 851
 852         blkp = &sc->block[sc->txb_new]; /* address of free granule */
 853         txdesc = (sca_descriptor *)
 854             (hc->mem_start + (blkp->txdesc & hc->winmsk));
 855
 856         txdata = (u_char *)(hc->mem_start
 857                             + (blkp->txstart & hc->winmsk));
 858
 859         /*
 860          * Now we'll try to install as many packets as possible into the
 861          * card's DP RAM buffers.
 862          */
 863         for (;;) {              /* perform actual copy of packet */
 864                 len = mtx->m_pkthdr.len;        /* length of message */
 865
 866 #if BUGGY > 1
 867                 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
 868                            sc->unit, mtx, len);
 869 #endif
 870
 871 #ifndef NETGRAPH
 872                 if (ifp->if_bpf)
 873                         bpf_mtap(ifp, mtx);
 874 #else   /* NETGRAPH */
 875                 sc->outbytes += len;
 876 #endif  /* NETGRAPH */
 877
 878                 /*
 879                  * We can perform a straight copy because the tranmit
 880                  * buffers won't wrap.
 881                  */
 882                 m_copydata(mtx, 0, len, txdata);
 883
 884                 /*
 885                  * Now we know how big the message is gonna be.  We must now
 886                  * construct the descriptors to drive this message out...
 887                  */
 888                 tlen = len;
 889                 while (tlen > SR_BUF_SIZ) {     /* loop for full granules */
 890                         txdesc->stat = 0;       /* reset bits */
 891                         txdesc->len = SR_BUF_SIZ;       /* size of granule */
 892                         tlen -= SR_BUF_SIZ;
 893
 894                         txdesc++;       /* move to next dscr */
 895                         txdata += SR_BUF_SIZ;   /* adjust data addr */
 896                         i++;
 897                 }
 898
 899                 /*
 900                  * This section handles the setting of the final piece of a
 901                  * message.
 902                  */
 903                 txdesc->stat = SCA_DESC_EOM;
 904                 txdesc->len = tlen;
 905                 pkts++;
 906
 907                 /*
 908                  * prepare for subsequent packets (if any)
 909                  */
 910                 txdesc++;
 911                 txdata += SR_BUF_SIZ;   /* next mem granule */
 912                 i++;            /* count of granules */
 913
 914                 /*
 915                  * OK, we've now placed the message into the DPRAM where it
 916                  * can be transmitted.  We'll now release the message memory
 917                  * and update the statistics...
 918                  */
 919                 m_freem(mtx);
 920 #ifndef NETGRAPH
 921                 ++sc->ifsppp.pp_if.if_opackets;
 922 #else   /* NETGRAPH */
 923                 sc->opackets++;
 924 #endif /* NETGRAPH */
 925
 926                 /*
 927                  * Check if we have space for another packet. XXX This is
 928                  * hardcoded.  A packet can't be larger than 3 buffers (3 x
 929                  * 512).
 930                  */
 931                 if ((i + 3) >= blkp->txmax) {   /* enough remains? */
 932 #if BUGGY > 9
 933                         printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
 934                                sc->unit, i, pkts);
 935 #endif
 936                         break;
 937                 }
 938                 /*
 939                  * We'll pull the next message to be sent (if any)
 940                  */
 941 #ifndef NETGRAPH
 942                 mtx = sppp_dequeue(ifp);
 943 #else /* NETGRAPH */
 944                 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 945                 if (mtx == NULL) {
 946                         IF_DEQUEUE(&sc->xmitq, mtx);
 947                 }
 948 #endif /* NETGRAPH */
 949                 if (!mtx) {     /* no message?  We're done! */
 950 #if BUGGY > 9
 951                         printf("sr%d.srstart: pending=0, pkts=%d\n",
 952                                sc->unit, pkts);
 953 #endif
 954                         break;
 955                 }
 956         }
 957
 958         blkp->txtail = i;       /* record next free granule */
 959
 960         /*
 961          * Mark the last descriptor, so that the SCA know where to stop.
 962          */
 963         txdesc--;               /* back up to last descriptor in list */
 964         txdesc->stat |= SCA_DESC_EOT;   /* mark as end of list */
 965
 966         /*
 967          * Now we'll reset the transmit granule's descriptor address so we
 968          * can record this in the structure and fire it off w/ the DMA
 969          * processor of the serial chip...
 970          */
 971         txdesc = (sca_descriptor *)blkp->txdesc;
 972         blkp->txeda = (u_short)((u_int)&txdesc[i]);
 973
 974         sc->txb_inuse++;        /* update inuse status */
 975         sc->txb_new++;          /* new traffic wuz added */
 976
 977         if (sc->txb_new == SR_TX_BLOCKS)
 978                 sc->txb_new = 0;
 979
 980         /*
 981          * If the tranmitter wasn't marked as "busy" we will force it to be
 982          * started...
 983          */
 984         if (sc->xmit_busy == 0) {
 985                 sr_xmit(sc);
 986 #if BUGGY > 9
 987                 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
 988 #endif
 989         }
 990         goto top_srstart;
 991 }
 992
 993 #ifndef NETGRAPH
 994 /*
 995  * Handle ioctl's at the device level, though we *will* call up
 996  * a layer...
 997  */
 998 #if BUGGY > 2
 999 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
1000 #endif
1001
1002 static int
1003 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1004 {
1005         int s, error, was_up, should_be_up;
1006         struct sr_softc *sc = ifp->if_softc;
1007
1008 #if BUGGY > 0
1009         printf("sr%d: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1010                ifp->if_unit, ifp, cmd, data);
1011 #endif
1012
1013         was_up = ifp->if_flags & IFF_RUNNING;
1014
1015         error = sppp_ioctl(ifp, cmd, data);
1016
1017 #if BUGGY > 1
1018         printf("sr%d: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1019               ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1020 #endif
1021
1022         if (error)
1023                 return error;
1024
1025         if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1026 #if BUGGY > 2
1027                 if (bug_splats[sc->unit]++ < 2) {
1028                         printf("sr(%d).if_addrlist = %08x\n",
1029                                sc->unit, ifp->if_addrlist);
1030                         printf("sr(%d).if_bpf = %08x\n",
1031                                sc->unit, ifp->if_bpf);
1032                         printf("sr(%d).if_init = %08x\n",
1033                                sc->unit, ifp->if_init);
1034                         printf("sr(%d).if_output = %08x\n",
1035                                sc->unit, ifp->if_output);
1036                         printf("sr(%d).if_start = %08x\n",
1037                                sc->unit, ifp->if_start);
1038                         printf("sr(%d).if_done = %08x\n",
1039                                sc->unit, ifp->if_done);
1040                         printf("sr(%d).if_ioctl = %08x\n",
1041                                sc->unit, ifp->if_ioctl);
1042                         printf("sr(%d).if_reset = %08x\n",
1043                                sc->unit, ifp->if_reset);
1044                         printf("sr(%d).if_watchdog = %08x\n",
1045                                sc->unit, ifp->if_watchdog);
1046                 }
1047 #endif
1048                 return 0;
1049         }
1050
1051         s = splimp();
1052         should_be_up = ifp->if_flags & IFF_RUNNING;
1053
1054         if (!was_up && should_be_up) {
1055                 /*
1056                  * Interface should be up -- start it.
1057                  */
1058                 sr_up(sc);
1059                 srstart(ifp);
1060
1061                 /*
1062                  * XXX Clear the IFF_UP flag so that the link will only go
1063                  * up after sppp lcp and ipcp negotiation.
1064                  */
1065                 /* ifp->if_flags &= ~IFF_UP; */
1066         } else if (was_up && !should_be_up) {
1067                 /*
1068                  * Interface should be down -- stop it.
1069                  */
1070                 sr_down(sc);
1071                 sppp_flush(ifp);
1072         }
1073         splx(s);
1074         return 0;
1075 }
1076 #endif /* NETGRAPH */
1077
1078 /*
1079  * This is to catch lost tx interrupts.
1080  */
1081 static void
1082 #ifndef NETGRAPH
1083 srwatchdog(struct ifnet *ifp)
1084 #else
1085 srwatchdog(struct sr_softc *sc)
1086 #endif /* NETGRAPH */
1087 {
1088         int     got_st0, got_st1, got_st3, got_dsr;
1089 #ifndef NETGRAPH
1090         struct sr_softc *sc = ifp->if_softc;
1091 #endif /* NETGRAPH */
1092         struct sr_hardc *hc = sc->hc;
1093         msci_channel *msci = &hc->sca->msci[sc->scachan];
1094         dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1095
1096 #if BUGGY > 0
1097 #ifndef NETGRAPH
1098         printf("srwatchdog(unit=%d)\n", unit);
1099 #else
1100         printf("srwatchdog(unit=%d)\n", sc->unit);
1101 #endif /* NETGRAPH */
1102 #endif
1103
1104 #ifndef NETGRAPH
1105         if (!(ifp->if_flags & IFF_RUNNING))
1106                 return;
1107
1108         ifp->if_oerrors++;      /* update output error count */
1109 #else   /* NETGRAPH */
1110         sc->oerrors++;  /* update output error count */
1111 #endif /* NETGRAPH */
1112
1113         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1114         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1115         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1116         got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1117
1118 #ifndef NETGRAPH
1119 #if     0
1120         if (ifp->if_flags & IFF_DEBUG)
1121 #endif
1122                 printf("sr%d: transmit failed, "
1123 #else   /* NETGRAPH */
1124         printf("sr%d: transmit failed, "
1125 #endif /* NETGRAPH */
1126                        "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1127                        sc->unit,
1128                        got_st0, got_st1, got_st3, got_dsr);
1129
1130         if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1131                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1132                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1133                 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1134         }
1135         sc->xmit_busy = 0;
1136 #ifndef NETGRAPH
1137         ifp->if_flags &= ~IFF_OACTIVE;
1138 #else
1139         /*ifp->if_flags &= ~IFF_OACTIVE; */
1140 #endif /* NETGRAPH */
1141
1142         if (sc->txb_inuse && --sc->txb_inuse)
1143                 sr_xmit(sc);
1144
1145 #ifndef NETGRAPH
1146         srstart(ifp);   /* restart transmitter */
1147 #else
1148         srstart(sc);    /* restart transmitter */
1149 #endif /* NETGRAPH */
1150 }
1151
1152 static void
1153 sr_up(struct sr_softc *sc)
1154 {
1155         u_int *fecrp;
1156         struct sr_hardc *hc = sc->hc;
1157         sca_regs *sca = hc->sca;
1158         msci_channel *msci = &sca->msci[sc->scachan];
1159
1160 #if BUGGY > 0
1161         printf("sr_up(sc=%08x)\n", sc);
1162 #endif
1163
1164         /*
1165          * Enable transmitter and receiver. Raise DTR and RTS. Enable
1166          * interrupts.
1167          *
1168          * XXX What about using AUTO mode in msci->md0 ???
1169          */
1170         SRC_PUT8(hc->sca_base, msci->ctl,
1171                  SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1172
1173         if (sc->scachan == 0)
1174                 switch (hc->cardtype) {
1175                 case SR_CRD_N2:
1176                         outb(hc->iobase + SR_MCR,
1177                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1178                         break;
1179                 case SR_CRD_N2PCI:
1180                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1181                         *fecrp &= ~SR_FECR_DTR0;
1182                         break;
1183                 }
1184         else
1185                 switch (hc->cardtype) {
1186                 case SR_CRD_N2:
1187                         outb(hc->iobase + SR_MCR,
1188                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1189                         break;
1190                 case SR_CRD_N2PCI:
1191                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1192                         *fecrp &= ~SR_FECR_DTR1;
1193                         break;
1194                 }
1195
1196         if (sc->scachan == 0) {
1197                 SRC_PUT8(hc->sca_base, sca->ier0,
1198                          SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1199                 SRC_PUT8(hc->sca_base, sca->ier1,
1200                          SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1201         } else {
1202                 SRC_PUT8(hc->sca_base, sca->ier0,
1203                          SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1204                 SRC_PUT8(hc->sca_base, sca->ier1,
1205                          SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1206         }
1207
1208         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1209         inb(hc->iobase);        /* XXX slow it down a bit. */
1210         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1211
1212 #ifndef NETGRAPH
1213 #ifdef USE_MODEMCK
1214         if (sr_watcher == 0)
1215                 sr_modemck(NULL);
1216 #endif
1217 #else   /* NETGRAPH */
1218         untimeout(ngsr_watchdog_frame, sc, sc->handle);
1219         sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
1220         sc->running = 1;
1221 #endif /* NETGRAPH */
1222 }
1223
1224 static void
1225 sr_down(struct sr_softc *sc)
1226 {
1227         u_int *fecrp;
1228         struct sr_hardc *hc = sc->hc;
1229         sca_regs *sca = hc->sca;
1230         msci_channel *msci = &sca->msci[sc->scachan];
1231
1232 #if BUGGY > 0
1233         printf("sr_down(sc=%08x)\n", sc);
1234 #endif
1235 #ifdef NETGRAPH
1236         untimeout(ngsr_watchdog_frame, sc, sc->handle);
1237         sc->running = 0;
1238 #endif /* NETGRAPH */
1239
1240         /*
1241          * Disable transmitter and receiver. Lower DTR and RTS. Disable
1242          * interrupts.
1243          */
1244         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1245         inb(hc->iobase);        /* XXX slow it down a bit. */
1246         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1247
1248         SRC_PUT8(hc->sca_base, msci->ctl,
1249                  SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1250
1251         if (sc->scachan == 0)
1252                 switch (hc->cardtype) {
1253                 case SR_CRD_N2:
1254                         outb(hc->iobase + SR_MCR,
1255                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1256                         break;
1257                 case SR_CRD_N2PCI:
1258                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1259                         *fecrp |= SR_FECR_DTR0;
1260                         break;
1261                 }
1262         else
1263                 switch (hc->cardtype) {
1264                 case SR_CRD_N2:
1265                         outb(hc->iobase + SR_MCR,
1266                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1267                         break;
1268                 case SR_CRD_N2PCI:
1269                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1270                         *fecrp |= SR_FECR_DTR1;
1271                         break;
1272                 }
1273
1274         if (sc->scachan == 0) {
1275                 SRC_PUT8(hc->sca_base, sca->ier0,
1276                          SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1277                 SRC_PUT8(hc->sca_base, sca->ier1,
1278                          SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1279         } else {
1280                 SRC_PUT8(hc->sca_base, sca->ier0,
1281                          SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1282                 SRC_PUT8(hc->sca_base, sca->ier1,
1283                          SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1284         }
1285 }
1286
1287 /*
1288  * Initialize the card, allocate memory for the sr_softc structures
1289  * and fill in the pointers.
1290  */
1291 static void
1292 src_init(struct sr_hardc *hc)
1293 {
1294         struct sr_softc *sc = hc->sc;
1295         int x;
1296         u_int chanmem;
1297         u_int bufmem;
1298         u_int next;
1299         u_int descneeded;
1300
1301 #if BUGGY > 0
1302         printf("src_init(hc=%08x)\n", hc);
1303 #endif
1304
1305         chanmem = hc->memsize / hc->numports;
1306         next = 0;
1307
1308         for (x = 0; x < hc->numports; x++, sc++) {
1309                 int blk;
1310
1311                 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1312                         sc->block[blk].txdesc = next;
1313                         bufmem = (16 * 1024) / SR_TX_BLOCKS;
1314                         descneeded = bufmem / SR_BUF_SIZ;
1315
1316                         sc->block[blk].txstart = sc->block[blk].txdesc
1317                             + ((((descneeded * sizeof(sca_descriptor))
1318                                  / SR_BUF_SIZ) + 1)
1319                                * SR_BUF_SIZ);
1320
1321                         sc->block[blk].txend = next + bufmem;
1322                         sc->block[blk].txmax =
1323                             (sc->block[blk].txend - sc->block[blk].txstart)
1324                             / SR_BUF_SIZ;
1325                         next += bufmem;
1326
1327 #if BUGGY > 2
1328                         printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1329                                sc->unit, blk,
1330                                sc->block[blk].txdesc, sc->block[blk].txstart);
1331 #endif
1332                 }
1333
1334                 sc->rxdesc = next;
1335                 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1336                 descneeded = bufmem / SR_BUF_SIZ;
1337                 sc->rxstart = sc->rxdesc +
1338                     ((((descneeded * sizeof(sca_descriptor)) /
1339                        SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1340                 sc->rxend = next + bufmem;
1341                 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1342                 next += bufmem;
1343         }
1344 }
1345
1346 /*
1347  * The things done here are channel independent.
1348  *
1349  * Configure the sca waitstates.
1350  * Configure the global interrupt registers.
1351  * Enable master dma enable.
1352  */
1353 static void
1354 sr_init_sca(struct sr_hardc *hc)
1355 {
1356         sca_regs *sca = hc->sca;
1357
1358 #if BUGGY > 0
1359         printf("sr_init_sca(hc=%08x)\n", hc);
1360 #endif
1361
1362         /*
1363          * Do the wait registers. Set everything to 0 wait states.
1364          */
1365         SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1366         SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1367         SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1368         SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1369         SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1370
1371         /*
1372          * Configure the interrupt registers. Most are cleared until the
1373          * interface is configured.
1374          */
1375         SRC_PUT8(hc->sca_base, sca->ier0, 0x00);        /* MSCI interrupts. */
1376         SRC_PUT8(hc->sca_base, sca->ier1, 0x00);        /* DMAC interrupts */
1377         SRC_PUT8(hc->sca_base, sca->ier2, 0x00);        /* TIMER interrupts. */
1378         SRC_PUT8(hc->sca_base, sca->itcr, 0x00);        /* Use ivr and no intr
1379                                                          * ack */
1380         SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1381         SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1382
1383         /*
1384          * Configure the timers. XXX Later
1385          */
1386
1387         /*
1388          * Set the DMA channel priority to rotate between all four channels.
1389          *
1390          * Enable all dma channels.
1391          */
1392         SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1393         SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1394 }
1395
1396 /*
1397  * Configure the msci
1398  *
1399  * NOTE: The serial port configuration is hardcoded at the moment.
1400  */
1401 static void
1402 sr_init_msci(struct sr_softc *sc)
1403 {
1404         int portndx;            /* on-board port number */
1405         u_int mcr_v;            /* contents of modem control */
1406         u_int *fecrp;           /* pointer for PCI's MCR i/o */
1407         struct sr_hardc *hc = sc->hc;
1408         msci_channel *msci = &hc->sca->msci[sc->scachan];
1409 #ifdef N2_TEST_SPEED
1410         int br_v;               /* contents for BR divisor */
1411         int etcndx;             /* index into ETC table */
1412         int fifo_v, gotspeed;   /* final tabled speed found */
1413         int tmc_v;              /* timer control register */
1414         int wanted;             /* speed (bitrate) wanted... */
1415         struct rate_line *rtp;
1416 #endif
1417
1418         portndx = sc->scachan;
1419
1420 #if BUGGY > 0
1421         printf("sr: sr_init_msci( sc=%08x)\n", sc);
1422 #endif
1423
1424         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1425         SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1426                  SCA_MD0_CRC_CCITT |
1427                  SCA_MD0_CRC_ENABLE |
1428                  SCA_MD0_MODE_HDLC);
1429         SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1430         SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1431
1432         /*
1433          * According to the manual I should give a reset after changing the
1434          * mode registers.
1435          */
1436         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1437         SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1438                  SCA_CTL_UDRNC |
1439                  SCA_CTL_RTS);
1440
1441         /*
1442          * XXX Later we will have to support different clock settings.
1443          */
1444         switch (sc->clk_cfg) {
1445         default:
1446 #if BUGGY > 0
1447                 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1448                        portndx, sc->clk_cfg);
1449 #endif
1450                 /* FALLTHROUGH */
1451         case SR_FLAGS_EXT_CLK:
1452                 /*
1453                  * For now all interfaces are programmed to use the RX clock
1454                  * for the TX clock.
1455                  */
1456
1457 #if BUGGY > 0
1458                 printf("sr%d: External Clock Selected.\n", portndx);
1459 #endif
1460
1461                 SRC_PUT8(hc->sca_base, msci->rxs,
1462                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1463                 SRC_PUT8(hc->sca_base, msci->txs,
1464                          SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1465                 break;
1466
1467         case SR_FLAGS_EXT_SEP_CLK:
1468 #if BUGGY > 0
1469                 printf("sr%d: Split Clocking Selected.\n", portndx);
1470 #endif
1471
1472                 SRC_PUT8(hc->sca_base, msci->rxs,
1473                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1474                 SRC_PUT8(hc->sca_base, msci->txs,
1475                          SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1476                 break;
1477
1478         case SR_FLAGS_INT_CLK:
1479 #if BUGGY > 0
1480                 printf("sr%d: Internal Clocking selected.\n", portndx);
1481 #endif
1482
1483                 /*
1484                  * XXX I do need some code to set the baud rate here!
1485                  */
1486 #ifdef N2_TEST_SPEED
1487                 switch (hc->cardtype) {
1488                 case SR_CRD_N2PCI:
1489                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1490                         mcr_v = *fecrp;
1491                         etcndx = 2;
1492                         break;
1493                 case SR_CRD_N2:
1494                 default:
1495                         mcr_v = inb(hc->iobase + SR_MCR);
1496                         etcndx = 0;
1497                 }
1498
1499                 fifo_v = 0x10;  /* stolen from Linux version */
1500
1501                 /*
1502                  * search for appropriate speed in table, don't calc it:
1503                  */
1504                 wanted = sr_test_speed[portndx];
1505                 rtp = &n2_rates[0];     /* point to first table item */
1506
1507                 while ((rtp->target > 0)        /* search table for speed */
1508                        &&(rtp->target != wanted))
1509                         rtp++;
1510
1511                 /*
1512                  * We've searched the table for a matching speed.  If we've
1513                  * found the correct rate line, we'll get the pre-calc'd
1514                  * values for the TMC and baud rate divisor for subsequent
1515                  * use...
1516                  */
1517                 if (rtp->target > 0) {  /* use table-provided values */
1518                         gotspeed = wanted;
1519                         tmc_v = rtp->tmc_reg;
1520                         br_v = rtp->br_reg;
1521                 } else {        /* otherwise assume 1MBit comm rate */
1522                         gotspeed = 10000;
1523                         tmc_v = 5;
1524                         br_v = 1;
1525                 }
1526
1527                 /*
1528                  * Now we mask in the enable clock output for the MCR:
1529                  */
1530                 mcr_v |= etc0vals[etcndx + portndx];
1531
1532                 /*
1533                  * Now we'll program the registers with these speed- related
1534                  * contents...
1535                  */
1536                 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1537                 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1538                 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1539                 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1540
1541                 switch (hc->cardtype) {
1542                 case SR_CRD_N2PCI:
1543                         *fecrp = mcr_v;
1544                         break;
1545                 case SR_CRD_N2:
1546                 default:
1547                         outb(hc->iobase + SR_MCR, mcr_v);
1548                 }
1549
1550 #if BUGGY > 0
1551                 if (wanted != gotspeed)
1552                         printf("sr%d: Speed wanted=%d, found=%d\n",
1553                                wanted, gotspeed);
1554
1555                 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1556                        portndx, gotspeed, tmc_v, br_v);
1557 #endif
1558 #else
1559                 SRC_PUT8(hc->sca_base, msci->rxs,
1560                          SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1561                 SRC_PUT8(hc->sca_base, msci->txs,
1562                          SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1563
1564                 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1565
1566                 if (portndx == 0)
1567                         switch (hc->cardtype) {
1568                         case SR_CRD_N2PCI:
1569                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1570                                 *fecrp |= SR_FECR_ETC0;
1571                                 break;
1572                         case SR_CRD_N2:
1573                         default:
1574                                 mcr_v = inb(hc->iobase + SR_MCR);
1575                                 mcr_v |= SR_MCR_ETC0;
1576                                 outb(hc->iobase + SR_MCR, mcr_v);
1577                         }
1578                 else
1579                         switch (hc->cardtype) {
1580                         case SR_CRD_N2:
1581                                 mcr_v = inb(hc->iobase + SR_MCR);
1582                                 mcr_v |= SR_MCR_ETC1;
1583                                 outb(hc->iobase + SR_MCR, mcr_v);
1584                                 break;
1585                         case SR_CRD_N2PCI:
1586                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1587                                 *fecrp |= SR_FECR_ETC1;
1588                                 break;
1589                         }
1590 #endif
1591         }
1592
1593         /*
1594          * XXX Disable all interrupts for now. I think if you are using the
1595          * dmac you don't use these interrupts.
1596          */
1597         SRC_PUT8(hc->sca_base, msci->ie0, 0);
1598         SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1599         SRC_PUT8(hc->sca_base, msci->ie2, 0);
1600         SRC_PUT8(hc->sca_base, msci->fie, 0);
1601
1602         SRC_PUT8(hc->sca_base, msci->sa0, 0);
1603         SRC_PUT8(hc->sca_base, msci->sa1, 0);
1604
1605         SRC_PUT8(hc->sca_base, msci->idl, 0x7E);        /* set flags value */
1606
1607         SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1608         SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1609         SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1610 }
1611
1612 /*
1613  * Configure the rx dma controller.
1614  */
1615 static void
1616 sr_init_rx_dmac(struct sr_softc *sc)
1617 {
1618         struct sr_hardc *hc;
1619         dmac_channel *dmac;
1620         sca_descriptor *rxd;
1621         u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1622
1623 #if BUGGY > 0
1624         printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1625 #endif
1626
1627         hc = sc->hc;
1628         dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1629
1630         if (hc->mempages)
1631                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1632
1633         /*
1634          * This phase initializes the contents of the descriptor table
1635          * needed to construct a circular buffer...
1636          */
1637         rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1638         rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1639
1640         for (rxbuf = sc->rxstart;
1641              rxbuf < sc->rxend;
1642              rxbuf += SR_BUF_SIZ, rxd++) {
1643                 /*
1644                  * construct the circular chain...
1645                  */
1646                 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1647                 rxd->cp = (u_short)(rxda & 0xffff);
1648
1649                 /*
1650                  * set the on-card buffer address...
1651                  */
1652                 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1653                 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1654
1655                 rxd->len = 0;   /* bytes resident w/in granule */
1656                 rxd->stat = 0xff;       /* The sca write here when finished */
1657         }
1658
1659         /*
1660          * heal the chain so that the last entry points to the first...
1661          */
1662         rxd--;
1663         rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1664
1665         /*
1666          * reset the reception handler's index...
1667          */
1668         sc->rxhind = 0;
1669
1670         /*
1671          * We'll now configure the receiver's DMA logic...
1672          */
1673         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA transfer */
1674         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1675
1676         /* XXX maybe also SCA_DMR_CNTE */
1677         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1678         SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1679
1680         cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1681         sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1682
1683         SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1684         SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1685
1686         rxd = (sca_descriptor *)sc->rxstart;
1687
1688         SRC_PUT16(hc->sca_base, dmac->eda,
1689                   (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1690
1691         SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1692
1693
1694         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);  /* Enable DMA */
1695 }
1696
1697 /*
1698  * Configure the TX DMA descriptors.
1699  * Initialize the needed values and chain the descriptors.
1700  */
1701 static void
1702 sr_init_tx_dmac(struct sr_softc *sc)
1703 {
1704         int blk;
1705         u_int txbuf, txda, txda_d;
1706         struct sr_hardc *hc;
1707         sca_descriptor *txd;
1708         dmac_channel *dmac;
1709         struct buf_block *blkp;
1710         u_int x;
1711         u_int sarb_v;
1712
1713 #if BUGGY > 0
1714         printf("sr_init_tx_dmac(sc=%08x)\n", sc);
1715 #endif
1716
1717         hc = sc->hc;
1718         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1719
1720         if (hc->mempages)
1721                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1722
1723         /*
1724          * Initialize the array of descriptors for transmission
1725          */
1726         for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1727                 blkp = &sc->block[blk];
1728                 txd = (sca_descriptor *)(hc->mem_start
1729                                          + (blkp->txdesc & hc->winmsk));
1730                 txda_d = (u_int) hc->mem_start
1731                     - (blkp->txdesc & ~hc->winmsk);
1732
1733                 x = 0;
1734                 txbuf = blkp->txstart;
1735                 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1736                         txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1737                         txd->cp = (u_short)(txda & 0xffff);
1738
1739                         txd->bp = (u_short)((txbuf + hc->mem_pstart)
1740                                             & 0xffff);
1741                         txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1742                                             & 0xff);
1743                         txd->len = 0;
1744                         txd->stat = 0;
1745                         x++;
1746                 }
1747
1748                 txd--;
1749                 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1750                                     & 0xffff);
1751
1752                 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1753         }
1754
1755         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA */
1756         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1757         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1758         SRC_PUT8(hc->sca_base, dmac->dir,
1759                  SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1760
1761         sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1762         sarb_v &= 0x00ff;
1763
1764         SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1765 }
1766
1767 /*
1768  * Look through the descriptors to see if there is a complete packet
1769  * available. Stop if we get to where the sca is busy.
1770  *
1771  * Return the length and status of the packet.
1772  * Return nonzero if there is a packet available.
1773  *
1774  * NOTE:
1775  * It seems that we get the interrupt a bit early. The updateing of
1776  * descriptor values is not always completed when this is called.
1777  */
1778 static int
1779 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1780 {
1781         int granules;   /* count of granules in pkt */
1782         int wki, wko;
1783         struct sr_hardc *hc;
1784         sca_descriptor *rxdesc; /* current descriptor */
1785         sca_descriptor *endp;   /* ending descriptor */
1786         sca_descriptor *cda;    /* starting descriptor */
1787
1788         hc = sc->hc;            /* get card's information */
1789
1790         /*
1791          * set up starting descriptor by pulling that info from the DMA half
1792          * of the HD chip...
1793          */
1794         wki = DMAC_RXCH(sc->scachan);
1795         wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1796
1797         cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1798
1799 #if BUGGY > 1
1800         printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1801                wki, wko, cda);
1802 #endif
1803
1804         /*
1805          * open the appropriate memory window and set our expectations...
1806          */
1807         if (hc->mempages) {
1808                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1809                 SRC_SET_ON(hc->iobase);
1810         }
1811         rxdesc = (sca_descriptor *)
1812             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1813         endp = rxdesc;
1814         rxdesc = &rxdesc[sc->rxhind];
1815         endp = &endp[sc->rxmax];
1816
1817         *len = 0;               /* reset result total length */
1818         granules = 0;           /* reset count of granules */
1819
1820         /*
1821          * This loop will scan descriptors, but it *will* puke up if we wrap
1822          * around to our starting point...
1823          */
1824         while (rxdesc != cda) {
1825                 *len += rxdesc->len;    /* increment result length */
1826                 granules++;
1827
1828                 /*
1829                  * If we hit a valid packet's completion we'll know we've
1830                  * got a live one, and that we can deliver the packet.
1831                  * Since we're only allowed to report a packet available,
1832                  * somebody else does that...
1833                  */
1834                 if (rxdesc->stat & SCA_DESC_EOM) {      /* End Of Message */
1835                         *rxstat = rxdesc->stat; /* return closing */
1836 #if BUGGY > 0
1837                         printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1838                                sc->unit, *len, *rxstat, granules);
1839 #endif
1840                         return 1;       /* indicate success */
1841                 }
1842                 /*
1843                  * OK, this packet take up multiple granules.  Move on to
1844                  * the next descriptor so we can consider it...
1845                  */
1846                 rxdesc++;
1847
1848                 if (rxdesc == endp)     /* recognize & act on wrap point */
1849                         rxdesc = (sca_descriptor *)
1850                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1851         }
1852
1853         /*
1854          * Nothing found in the DPRAM.  Let the caller know...
1855          */
1856         *len = 0;
1857         *rxstat = 0;
1858
1859         return 0;
1860 }
1861
1862 /*
1863  * Copy a packet from the on card memory into a provided mbuf.
1864  * Take into account that buffers wrap and that a packet may
1865  * be larger than a buffer.
1866  */
1867 static void
1868 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1869 {
1870         struct sr_hardc *hc;
1871         sca_descriptor *rxdesc;
1872         u_int rxdata;
1873         u_int rxmax;
1874         u_int off = 0;
1875         u_int tlen;
1876
1877 #if BUGGY > 0
1878         printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1879                m, sc, len);
1880 #endif
1881
1882         hc = sc->hc;
1883
1884         rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1885         rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1886
1887         rxdesc = (sca_descriptor *)
1888             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1889         rxdesc = &rxdesc[sc->rxhind];
1890
1891         /*
1892          * Using the count of bytes in the received packet, we decrement it
1893          * for each granule (controller by an SCA descriptor) to control the
1894          * looping...
1895          */
1896         while (len) {
1897                 /*
1898                  * tlen gets the length of *this* granule... ...which is
1899                  * then copied to the target buffer.
1900                  */
1901                 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1902
1903                 if (hc->mempages)
1904                         SRC_SET_MEM(hc->iobase, rxdata);
1905
1906                 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1907                       mtod(m, caddr_t) +off,
1908                       tlen);
1909
1910                 off += tlen;
1911                 len -= tlen;
1912
1913                 /*
1914                  * now, return to the descriptor's window in DPRAM and reset
1915                  * the descriptor we've just suctioned...
1916                  */
1917                 if (hc->mempages)
1918                         SRC_SET_MEM(hc->iobase, sc->rxdesc);
1919
1920                 rxdesc->len = 0;
1921                 rxdesc->stat = 0xff;
1922
1923                 /*
1924                  * Move on to the next granule.  If we've any remaining
1925                  * bytes to process we'll just continue in our loop...
1926                  */
1927                 rxdata += SR_BUF_SIZ;
1928                 rxdesc++;
1929
1930                 if (rxdata == rxmax) {  /* handle the wrap point */
1931                         rxdata = sc->rxstart;
1932                         rxdesc = (sca_descriptor *)
1933                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1934                 }
1935         }
1936 }
1937
1938 /*
1939  * If single is set, just eat a packet. Otherwise eat everything up to
1940  * where cda points. Update pointers to point to the next packet.
1941  *
1942  * This handles "flushing" of a packet as received...
1943  *
1944  * If the "single" parameter is zero, all pending reeceive traffic will
1945  * be flushed out of existence.  A non-zero value will only drop the
1946  * *next* (currently) pending packet...
1947  */
1948 static void
1949 sr_eat_packet(struct sr_softc *sc, int single)
1950 {
1951         struct sr_hardc *hc;
1952         sca_descriptor *rxdesc; /* current descriptor being eval'd */
1953         sca_descriptor *endp;   /* last descriptor in chain */
1954         sca_descriptor *cda;    /* current start point */
1955         u_int loopcnt = 0;      /* count of packets flushed ??? */
1956         u_char stat;            /* captured status byte from descr */
1957
1958         hc = sc->hc;
1959         cda = (sca_descriptor *)(hc->mem_start +
1960                                  (SRC_GET16(hc->sca_base,
1961                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1962                                   hc->winmsk));
1963
1964         /*
1965          * loop until desc->stat == (0xff || EOM) Clear the status and
1966          * length in the descriptor. Increment the descriptor.
1967          */
1968         if (hc->mempages)
1969                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1970
1971         rxdesc = (sca_descriptor *)
1972             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1973         endp = rxdesc;
1974         rxdesc = &rxdesc[sc->rxhind];
1975         endp = &endp[sc->rxmax];
1976
1977         /*
1978          * allow loop, but abort it if we wrap completely...
1979          */
1980         while (rxdesc != cda) {
1981                 loopcnt++;
1982
1983                 if (loopcnt > sc->rxmax) {
1984                         printf("sr%d: eat pkt %d loop, cda %x, "
1985                                "rxdesc %x, stat %x.\n",
1986                                sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1987                                rxdesc->stat);
1988                         break;
1989                 }
1990                 stat = rxdesc->stat;
1991
1992                 rxdesc->len = 0;
1993                 rxdesc->stat = 0xff;
1994
1995                 rxdesc++;
1996                 sc->rxhind++;
1997
1998                 if (rxdesc == endp) {
1999                         rxdesc = (sca_descriptor *)
2000                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
2001                         sc->rxhind = 0;
2002                 }
2003                 if (single && (stat == SCA_DESC_EOM))
2004                         break;
2005         }
2006
2007         /*
2008          * Update the eda to the previous descriptor.
2009          */
2010         rxdesc = (sca_descriptor *)sc->rxdesc;
2011         rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2012
2013         SRC_PUT16(hc->sca_base,
2014                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2015                   (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2016 }
2017
2018 /*
2019  * While there is packets available in the rx buffer, read them out
2020  * into mbufs and ship them off.
2021  */
2022 static void
2023 sr_get_packets(struct sr_softc *sc)
2024 {
2025         u_char rxstat;          /* acquired status byte */
2026         int i;
2027         int pkts;               /* count of packets found */
2028         int rxndx;              /* rcv buffer index */
2029         int tries;              /* settling time counter */
2030         u_int len;              /* length of pending packet */
2031         struct sr_hardc *hc;    /* card-level information */
2032         sca_descriptor *rxdesc; /* descriptor in memory */
2033 #ifndef NETGRAPH
2034         struct ifnet *ifp;      /* network intf ctl table */
2035 #endif /* NETGRAPH */
2036         struct mbuf *m = NULL;  /* message buffer */
2037
2038 #if BUGGY > 0
2039         printf("sr_get_packets(sc=%08x)\n", sc);
2040 #endif
2041
2042         hc = sc->hc;
2043 #ifndef NETGRAPH
2044         ifp = &sc->ifsppp.pp_if;
2045 #endif /* NETGRAPH */
2046
2047         if (hc->mempages) {
2048                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2049                 SRC_SET_ON(hc->iobase); /* enable shared memory */
2050         }
2051         pkts = 0;               /* reset count of found packets */
2052
2053         /*
2054          * for each complete packet in the receiving pool, process each
2055          * packet...
2056          */
2057         while (sr_packet_avail(sc, &len, &rxstat)) {    /* packet pending? */
2058                 /*
2059                  * I have seen situations where we got the interrupt but the
2060                  * status value wasn't deposited.  This code should allow
2061                  * the status byte's value to settle...
2062                  */
2063
2064                 tries = 5;
2065
2066                 while ((rxstat == 0x00ff)
2067                        && --tries)
2068                         sr_packet_avail(sc, &len, &rxstat);
2069
2070 #if BUGGY > 1
2071                 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2072                        len, rxstat);
2073 #endif
2074
2075                 pkts++;
2076 #ifdef NETGRAPH
2077                 sc->inbytes += len;
2078                 sc->inlast = 0;
2079 #endif /* NETGRAPH */
2080
2081                 /*
2082                  * OK, we've settled the incoming message status. We can now
2083                  * process it...
2084                  */
2085                 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2086 #if BUGGY > 1
2087                         printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2088                                sc->unit, rxstat, len);
2089 #endif
2090
2091                         MGETHDR(m, M_DONTWAIT, MT_DATA);
2092                         if (m == NULL) {
2093                                 /*
2094                                  * eat (flush) packet if get mbuf fail!!
2095                                  */
2096                                 sr_eat_packet(sc, 1);
2097                                 continue;
2098                         }
2099                         /*
2100                          * construct control information for pass-off
2101                          */
2102 #ifndef NETGRAPH
2103                         m->m_pkthdr.rcvif = ifp;
2104 #else
2105                         m->m_pkthdr.rcvif = NULL;
2106 #endif /* NETGRAPH */
2107                         m->m_pkthdr.len = m->m_len = len;
2108                         if (len > MHLEN) {
2109                                 MCLGET(m, M_DONTWAIT);
2110                                 if ((m->m_flags & M_EXT) == 0) {
2111                                         /*
2112                                          * We couldn't get a big enough
2113                                          * message packet, so we'll send the
2114                                          * packet to /dev/null...
2115                                          */
2116                                         m_freem(m);
2117                                         sr_eat_packet(sc, 1);
2118                                         continue;
2119                                 }
2120                         }
2121                         /*
2122                          * OK, we've got a good message buffer.  Now we can
2123                          * copy the received message into it
2124                          */
2125                         sr_copy_rxbuf(m, sc, len);      /* copy from DPRAM */
2126
2127 #ifndef NETGRAPH
2128                         if (ifp->if_bpf)
2129                                 bpf_mtap(ifp, m);
2130
2131 #if BUGGY > 3
2132                         {
2133                                 u_char *bp;
2134
2135                                 bp = (u_char *)m;
2136                                 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2137                                        sc->unit,
2138                                        bp[0], bp[1], bp[2],
2139                                        bp[4], bp[5], bp[6]);
2140                         }
2141 #endif
2142                         sppp_input(ifp, m);
2143                         ifp->if_ipackets++;
2144
2145 #else   /* NETGRAPH */
2146 #if BUGGY > 3
2147                         {
2148                                 u_char *bp;
2149
2150                                 bp = mtod(m,u_char *);
2151                                 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2152                                        sc->unit,
2153                                        bp[0], bp[1], bp[2],
2154                                        bp[4], bp[5], bp[6]);
2155                                 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2156                                        bp[6], bp[7], bp[8],
2157                                        bp[9], bp[10], bp[11]);
2158                         }
2159 #endif
2160                         ng_queue_data(sc->hook, m, NULL);
2161                         sc->ipackets++;
2162 #endif /* NETGRAPH */
2163                         /*
2164                          * Update the eda to the previous descriptor.
2165                          */
2166                         i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2167                         sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2168
2169                         rxdesc = (sca_descriptor *)sc->rxdesc;
2170                         rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2171                         rxdesc = &rxdesc[rxndx];
2172
2173                         SRC_PUT16(hc->sca_base,
2174                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2175                                   (u_short)((u_int)(rxdesc + hc->mem_pstart)
2176                                              & 0xffff));
2177
2178                 } else {
2179                         int got_st3, got_cda, got_eda;
2180                         int tries = 5;
2181
2182                         while ((rxstat == 0xff) && --tries)
2183                                 sr_packet_avail(sc, &len, &rxstat);
2184
2185                         /*
2186                          * It look like we get an interrupt early
2187                          * sometimes and then the status is not
2188                          * filled in yet.
2189                          */
2190                         if (tries && (tries != 5))
2191                                 continue;
2192
2193                         /*
2194                          * This chunk of code handles the error packets.
2195                          * We'll log them for posterity...
2196                          */
2197                         sr_eat_packet(sc, 1);
2198
2199 #ifndef NETGRAPH
2200                         ifp->if_ierrors++;
2201 #else
2202                         sc->ierrors[0]++;
2203 #endif /* NETGRAPH */
2204
2205                         got_st3 = SRC_GET8(hc->sca_base,
2206                                   hc->sca->msci[sc->scachan].st3);
2207                         got_cda = SRC_GET16(hc->sca_base,
2208                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2209                         got_eda = SRC_GET16(hc->sca_base,
2210                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2211
2212 #if BUGGY > 0
2213                         printf("sr%d: Receive error chan %d, "
2214                                "stat %02x, msci st3 %02x,"
2215                                "rxhind %d, cda %04x, eda %04x.\n",
2216                                sc->unit, sc->scachan, rxstat,
2217                                got_st3, sc->rxhind, got_cda, got_eda);
2218 #endif
2219                 }
2220         }
2221
2222 #if BUGGY > 0
2223         printf("sr%d: sr_get_packets() found %d packet(s)\n",
2224                sc->unit, pkts);
2225 #endif
2226
2227         if (hc->mempages)
2228                 SRC_SET_OFF(hc->iobase);
2229 }
2230
2231 /*
2232  * All DMA interrupts come here.
2233  *
2234  * Each channel has two interrupts.
2235  * Interrupt A for errors and Interrupt B for normal stuff like end
2236  * of transmit or receive dmas.
2237  */
2238 static void
2239 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2240 {
2241         u_char dsr;             /* contents of DMA Stat Reg */
2242         u_char dotxstart;       /* enables for tranmit part */
2243         int mch;                /* channel being processed */
2244         struct sr_softc *sc;    /* channel's softc structure */
2245         sca_regs *sca = hc->sca;
2246         dmac_channel *dmac;     /* dma structure of chip */
2247
2248 #if BUGGY > 0
2249         printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2250 #endif
2251
2252         mch = 0;                /* assume chan0 on card */
2253         dotxstart = isr1;       /* copy for xmitter starts */
2254
2255         /*
2256          * Shortcut if there is no interrupts for dma channel 0 or 1.
2257          * Skip processing for channel 0 if no incoming hit
2258          */
2259         if ((isr1 & 0x0F) == 0) {
2260                 mch = 1;
2261                 isr1 >>= 4;
2262         }
2263         do {
2264                 sc = &hc->sc[mch];
2265
2266                 /*
2267                  * Transmit channel - DMA Status Register Evaluation
2268                  */
2269                 if (isr1 & 0x0C) {
2270                         dmac = &sca->dmac[DMAC_TXCH(mch)];
2271
2272                         /*
2273                          * get the DMA Status Register contents and write
2274                          * back to reset interrupt...
2275                          */
2276                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2277                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2278
2279                         /*
2280                          * Check for (& process) a Counter overflow
2281                          */
2282                         if (dsr & SCA_DSR_COF) {
2283                                 printf("sr%d: TX DMA Counter overflow, "
2284                                        "txpacket no %lu.\n",
2285 #ifndef NETGRAPH
2286                                        sc->unit, sc->ifsppp.pp_if.if_opackets);
2287                                 sc->ifsppp.pp_if.if_oerrors++;
2288 #else
2289                                        sc->unit, sc->opackets);
2290                                 sc->oerrors++;
2291 #endif /* NETGRAPH */
2292                         }
2293                         /*
2294                          * Check for (& process) a Buffer overflow
2295                          */
2296                         if (dsr & SCA_DSR_BOF) {
2297                                 printf("sr%d: TX DMA Buffer overflow, "
2298                                        "txpacket no %lu, dsr %02x, "
2299                                        "cda %04x, eda %04x.\n",
2300 #ifndef NETGRAPH
2301                                        sc->unit, sc->ifsppp.pp_if.if_opackets,
2302 #else
2303                                        sc->unit, sc->opackets,
2304 #endif /* NETGRAPH */
2305                                        dsr,
2306                                        SRC_GET16(hc->sca_base, dmac->cda),
2307                                        SRC_GET16(hc->sca_base, dmac->eda));
2308 #ifndef NETGRAPH
2309                                 sc->ifsppp.pp_if.if_oerrors++;
2310 #else
2311                                 sc->oerrors++;
2312 #endif /* NETGRAPH */
2313                         }
2314                         /*
2315                          * Check for (& process) an End of Transfer (OK)
2316                          */
2317                         if (dsr & SCA_DSR_EOT) {
2318                                 /*
2319                                  * This should be the most common case.
2320                                  *
2321                                  * Clear the IFF_OACTIVE flag.
2322                                  *
2323                                  * Call srstart to start a new transmit if
2324                                  * there is data to transmit.
2325                                  */
2326 #if BUGGY > 0
2327                                 printf("sr%d: TX Completed OK\n", sc->unit);
2328 #endif
2329                                 sc->xmit_busy = 0;
2330 #ifndef NETGRAPH
2331                                 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2332                                 sc->ifsppp.pp_if.if_timer = 0;
2333 #else
2334                                 /* XXX may need to mark tx inactive? */
2335                                 sc->out_deficit++;
2336                                 sc->out_dog = DOG_HOLDOFF;
2337 #endif /* NETGRAPH */
2338
2339                                 if (sc->txb_inuse && --sc->txb_inuse)
2340                                         sr_xmit(sc);
2341                         }
2342                 }
2343                 /*
2344                  * Receive channel processing of DMA Status Register
2345                  */
2346                 if (isr1 & 0x03) {
2347                         dmac = &sca->dmac[DMAC_RXCH(mch)];
2348
2349                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2350                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2351
2352                         /*
2353                          * End of frame processing (MSG OK?)
2354                          */
2355                         if (dsr & SCA_DSR_EOM) {
2356 #if BUGGY > 0
2357                                 int tt, ind;
2358
2359 #ifndef NETGRAPH
2360                                 tt = sc->ifsppp.pp_if.if_ipackets;
2361 #else   /* NETGRAPH */
2362                                 tt = sc->ipackets;
2363 #endif /* NETGRAPH */
2364                                 ind = sc->rxhind;
2365 #endif
2366
2367                                 sr_get_packets(sc);
2368 #if BUGGY > 0
2369 #ifndef NETGRAPH
2370                                 if (tt == sc->ifsppp.pp_if.if_ipackets)
2371 #else   /* NETGRAPH */
2372                                 if (tt == sc->ipackets)
2373 #endif /* NETGRAPH */
2374                                 {
2375                                         sca_descriptor *rxdesc;
2376                                         int i;
2377
2378                                         printf("SR: RXINTR isr1 %x, dsr %x, "
2379                                                "no data %d pkts, orxind %d.\n",
2380                                                dotxstart, dsr, tt, ind);
2381                                         printf("SR: rxdesc %x, rxstart %x, "
2382                                                "rxend %x, rxhind %d, "
2383                                                "rxmax %d.\n",
2384                                                sc->rxdesc, sc->rxstart,
2385                                                sc->rxend, sc->rxhind,
2386                                                sc->rxmax);
2387                                         printf("SR: cda %x, eda %x.\n",
2388                                             SRC_GET16(hc->sca_base, dmac->cda),
2389                                             SRC_GET16(hc->sca_base, dmac->eda));
2390
2391                                         if (hc->mempages) {
2392                                                 SRC_SET_ON(hc->iobase);
2393                                                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2394                                         }
2395                                         rxdesc = (sca_descriptor *)
2396                                                  (hc->mem_start +
2397                                                   (sc->rxdesc & hc->winmsk));
2398                                         rxdesc = &rxdesc[sc->rxhind];
2399
2400                                         for (i = 0; i < 3; i++, rxdesc++)
2401                                                 printf("SR: rxdesc->stat %x, "
2402                                                        "len %d.\n",
2403                                                        rxdesc->stat,
2404                                                        rxdesc->len);
2405
2406                                         if (hc->mempages)
2407                                                 SRC_SET_OFF(hc->iobase);
2408                                 }
2409 #endif /* BUGGY */
2410                         }
2411                         /*
2412                          * Check for Counter overflow
2413                          */
2414                         if (dsr & SCA_DSR_COF) {
2415                                 printf("sr%d: RX DMA Counter overflow, "
2416                                        "rxpkts %lu.\n",
2417 #ifndef NETGRAPH
2418                                        sc->unit, sc->ifsppp.pp_if.if_ipackets);
2419                                 sc->ifsppp.pp_if.if_ierrors++;
2420 #else   /* NETGRAPH */
2421                                        sc->unit, sc->ipackets);
2422                                 sc->ierrors[1]++;
2423 #endif /* NETGRAPH */
2424                         }
2425                         /*
2426                          * Check for Buffer overflow
2427                          */
2428                         if (dsr & SCA_DSR_BOF) {
2429                                 printf("sr%d: RX DMA Buffer overflow, "
2430                                        "rxpkts %lu, rxind %d, "
2431                                        "cda %x, eda %x, dsr %x.\n",
2432 #ifndef NETGRAPH
2433                                        sc->unit, sc->ifsppp.pp_if.if_ipackets,
2434 #else   /* NETGRAPH */
2435                                        sc->unit, sc->ipackets,
2436 #endif /* NETGRAPH */
2437                                        sc->rxhind,
2438                                        SRC_GET16(hc->sca_base, dmac->cda),
2439                                        SRC_GET16(hc->sca_base, dmac->eda),
2440                                        dsr);
2441
2442                                 /*
2443                                  * Make sure we eat as many as possible.
2444                                  * Then get the system running again.
2445                                  */
2446                                 if (hc->mempages)
2447                                         SRC_SET_ON(hc->iobase);
2448
2449                                 sr_eat_packet(sc, 0);
2450 #ifndef NETGRAPH
2451                                 sc->ifsppp.pp_if.if_ierrors++;
2452 #else   /* NETGRAPH */
2453                                 sc->ierrors[2]++;
2454 #endif /* NETGRAPH */
2455
2456                                 SRC_PUT8(hc->sca_base,
2457                                          sca->msci[mch].cmd,
2458                                          SCA_CMD_RXMSGREJ);
2459
2460                                 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2461
2462 #if BUGGY > 0
2463                                 printf("sr%d: RX DMA Buffer overflow, "
2464                                        "rxpkts %lu, rxind %d, "
2465                                        "cda %x, eda %x, dsr %x. After\n",
2466                                        sc->unit,
2467 #ifndef NETGRAPH
2468                                        sc->ipackets,
2469 #else   /* NETGRAPH */
2470                                        sc->ifsppp.pp_if.if_ipackets,
2471 #endif /* NETGRAPH */
2472                                        sc->rxhind,
2473                                        SRC_GET16(hc->sca_base, dmac->cda),
2474                                        SRC_GET16(hc->sca_base, dmac->eda),
2475                                        SRC_GET8(hc->sca_base, dmac->dsr));
2476 #endif
2477
2478                                 if (hc->mempages)
2479                                         SRC_SET_OFF(hc->iobase);
2480                         }
2481                         /*
2482                          * End of Transfer
2483                          */
2484                         if (dsr & SCA_DSR_EOT) {
2485                                 /*
2486                                  * If this happen, it means that we are
2487                                  * receiving faster than what the processor
2488                                  * can handle.
2489                                  *
2490                                  * XXX We should enable the dma again.
2491                                  */
2492                                 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2493                                        sc->unit,
2494 #ifndef NETGRAPH
2495                                        sc->ifsppp.pp_if.if_ipackets);
2496                                 sc->ifsppp.pp_if.if_ierrors++;
2497 #else
2498                                        sc->ipackets);
2499                                 sc->ierrors[3]++;
2500 #endif /* NETGRAPH */
2501                         }
2502                 }
2503                 isr1 >>= 4;     /* process next half of ISR */
2504                 mch++;          /* and move to next channel */
2505         } while ((mch < NCHAN) && isr1);        /* loop for each chn */
2506
2507         /*
2508          * Now that we have done all the urgent things, see if we can fill
2509          * the transmit buffers.
2510          */
2511         for (mch = 0; mch < NCHAN; mch++) {
2512                 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2513                         sc = &hc->sc[mch];
2514 #ifndef NETGRAPH
2515                         srstart(&sc->ifsppp.pp_if);
2516 #else
2517                         srstart(sc);
2518 #endif /* NETGRAPH */
2519                 }
2520                 dotxstart >>= 4;/* shift for next channel */
2521         }
2522 }
2523 #ifndef NETGRAPH
2524 #ifdef USE_MODEMCK
2525 /*
2526  * Perform timeout on an FR channel
2527  *
2528  * Establish a periodic check of open N2 ports;  If
2529  * a port is open/active, its DCD state is checked
2530  * and a loss of DCD is recognized (and eventually
2531  * processed).
2532  */
2533 static void
2534 sr_modemck(void *arg)
2535 {
2536         u_int s;
2537         int card;               /* card index in table */
2538         int cards;              /* card list index */
2539         int mch;                /* channel on card */
2540         u_char dcd_v;           /* Data Carrier Detect */
2541         u_char got_st0;         /* contents of ST0 */
2542         u_char got_st1;         /* contents of ST1 */
2543         u_char got_st2;         /* contents of ST2 */
2544         u_char got_st3;         /* contents of ST3 */
2545         struct sr_hardc *hc;    /* card's configuration */
2546         struct sr_hardc *Card[16];/* up to 16 cards in system */
2547         struct sr_softc *sc;    /* channel's softc structure */
2548         struct ifnet *ifp;      /* interface control table */
2549         msci_channel *msci;     /* regs specific to channel */
2550
2551         s = splimp();
2552
2553 #if     0
2554         if (sr_opens == 0) {    /* count of "up" channels */
2555                 sr_watcher = 0; /* indicate no watcher */
2556                 splx(s);
2557                 return;
2558         }
2559 #endif
2560
2561         sr_watcher = 1;         /* mark that we're online */
2562
2563         /*
2564          * Now we'll need a list of cards to process.  Since we can handle
2565          * both ISA and PCI cards (and I didn't think of making this logic
2566          * global YET) we'll generate a single table of card table
2567          * addresses.
2568          */
2569         cards = 0;
2570
2571         for (card = 0; card < NSR; card++) {
2572                 hc = &sr_hardc[card];
2573
2574                 if (hc->sc == (void *)0)
2575                         continue;
2576
2577                 Card[cards++] = hc;
2578         }
2579
2580         hc = sr_hardc_pci;
2581
2582         while (hc) {
2583                 Card[cards++] = hc;
2584                 hc = hc->next;
2585         }
2586
2587         /*
2588          * OK, we've got work we can do.  Let's do it... (Please note that
2589          * this code _only_ deals w/ ISA cards)
2590          */
2591         for (card = 0; card < cards; card++) {
2592                 hc = Card[card];/* get card table */
2593
2594                 for (mch = 0; mch < hc->numports; mch++) {
2595                         sc = &hc->sc[mch];
2596
2597                         ifp = &sc->ifsppp.pp_if;
2598
2599                         /*
2600                          * if this channel isn't "up", skip it
2601                          */
2602                         if ((ifp->if_flags & IFF_UP) == 0)
2603                                 continue;
2604
2605                         /*
2606                          * OK, now we can go looking at this channel's
2607                          * actual register contents...
2608                          */
2609                         msci = &hc->sca->msci[sc->scachan];
2610
2611                         /*
2612                          * OK, now we'll look into the actual status of this
2613                          * channel...
2614                          *
2615                          * I suck in more registers than strictly needed
2616                          */
2617                         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2618                         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2619                         got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2620                         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2621
2622                         /*
2623                          * We want to see if the DCD signal is up (DCD is
2624                          * true if zero)
2625                          */
2626                         dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2627
2628                         if (dcd_v == 0)
2629                                 printf("sr%d: DCD lost\n", sc->unit);
2630                 }
2631         }
2632
2633         /*
2634          * OK, now set up for the next modem signal checking pass...
2635          */
2636         timeout(sr_modemck, NULL, hz);
2637
2638         splx(s);
2639 }
2640 #endif
2641 #else   /* NETGRAPH */
2642 /*
2643  * If a port is open/active, it's DCD state is checked
2644  * and a loss of DCD is recognized (and eventually processed?).
2645  */
2646 static void
2647 sr_modemck(struct sr_softc *sc )
2648 {
2649         u_int s;
2650         u_char got_st3;                 /* contents of ST3 */
2651         struct sr_hardc *hc = sc->hc;   /* card's configuration */
2652         msci_channel *msci;             /* regs specific to channel */
2653
2654         s = splimp();
2655
2656
2657         if (sc->running == 0)
2658                 return;
2659         /*
2660          * OK, now we can go looking at this channel's register contents...
2661          */
2662         msci = &hc->sca->msci[sc->scachan];
2663         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2664
2665         /*
2666          * We want to see if the DCD signal is up (DCD is true if zero)
2667          */
2668         sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2669         splx(s);
2670 }
2671
2672 #endif  /* NETGRAPH */
2673 static void
2674 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2675 {
2676         printf("src%d: SRINTR: MSCI\n", hc->cunit);
2677 }
2678
2679 static void
2680 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2681 {
2682         printf("src%d: SRINTR: TIMER\n", hc->cunit);
2683 }
2684
2685 #ifdef  NETGRAPH
2686 /*****************************************
2687  * Device timeout/watchdog routine.
2688  * called once per second.
2689  * checks to see that if activity was expected, that it hapenned.
2690  * At present we only look to see if expected output was completed.
2691  */
2692 static void
2693 ngsr_watchdog_frame(void * arg)
2694 {
2695         struct sr_softc * sc = arg;
2696         int s;
2697         int     speed;
2698
2699         if (sc->running == 0)
2700                 return; /* if we are not running let timeouts die */
2701         /*
2702          * calculate the apparent throughputs
2703          *  XXX a real hack
2704          */
2705         s = splimp();
2706         speed = sc->inbytes - sc->lastinbytes;
2707         sc->lastinbytes = sc->inbytes;
2708         if ( sc->inrate < speed )
2709                 sc->inrate = speed;
2710         speed = sc->outbytes - sc->lastoutbytes;
2711         sc->lastoutbytes = sc->outbytes;
2712         if ( sc->outrate < speed )
2713                 sc->outrate = speed;
2714         sc->inlast++;
2715         splx(s);
2716
2717         if ((sc->inlast > QUITE_A_WHILE)
2718         && (sc->out_deficit > LOTS_OF_PACKETS)) {
2719                 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2720                 s = splimp();
2721                 sr_down(sc);
2722                 sr_up(sc);
2723                 sc->inlast = sc->out_deficit = 0;
2724                 splx(s);
2725         } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2726                 if (sc->out_dog == 0) {
2727                         log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2728                                         sc->unit);
2729                         s = splimp();
2730                         srwatchdog(sc);
2731 #if 0
2732                         sr_down(sc);
2733                         sr_up(sc);
2734 #endif
2735                         splx(s);
2736                         sc->inlast = sc->out_deficit = 0;
2737                 } else {
2738                         sc->out_dog--;
2739                 }
2740         }
2741         sr_modemck(sc);         /* update the DCD status */
2742         sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
2743 }
2744
2745 /***********************************************************************
2746  * This section contains the methods for the Netgraph interface
2747  ***********************************************************************/
2748 /*
2749  * It is not possible or allowable to create a node of this type.
2750  * If the hardware exists, it will already have created it.
2751  */
2752 static  int
2753 ngsr_constructor(node_p *nodep)
2754 {
2755         return (EINVAL);
2756 }
2757
2758 /*
2759  * give our ok for a hook to be added...
2760  * If we are not running this should kick the device into life.
2761  * The hook's private info points to our stash of info about that
2762  * channel.
2763  */
2764 static int
2765 ngsr_newhook(node_p node, hook_p hook, const char *name)
2766 {
2767         struct sr_softc *       sc = node->private;
2768
2769         /*
2770          * check if it's our friend the debug hook
2771          */
2772         if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2773                 hook->private = NULL; /* paranoid */
2774                 sc->debug_hook = hook;
2775                 return (0);
2776         }
2777
2778         /*
2779          * Check for raw mode hook.
2780          */
2781         if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2782                 return (EINVAL);
2783         }
2784         hook->private = sc;
2785         sc->hook = hook;
2786         sc->datahooks++;
2787         sr_up(sc);
2788         return (0);
2789 }
2790
2791 /*
2792  * incoming messages.
2793  * Just respond to the generic TEXT_STATUS message
2794  */
2795 static  int
2796 ngsr_rcvmsg(node_p node,
2797         struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2798 {
2799         struct sr_softc *       sc;
2800         int error = 0;
2801
2802         sc = node->private;
2803         switch (msg->header.typecookie) {
2804             case        NG_SR_COOKIE:
2805                 error = EINVAL;
2806                 break;
2807             case        NGM_GENERIC_COOKIE:
2808                 switch(msg->header.cmd) {
2809                     case NGM_TEXT_STATUS: {
2810                             char        *arg;
2811                             int pos = 0;
2812                             int resplen = sizeof(struct ng_mesg) + 512;
2813                             MALLOC(*resp, struct ng_mesg *, resplen,
2814                                         M_NETGRAPH, M_NOWAIT | M_ZERO);
2815                             if (*resp == NULL) {
2816                                 error = ENOMEM;
2817                                 break;
2818                             }
2819                             arg = (*resp)->data;
2820
2821                             /*
2822                              * Put in the throughput information.
2823                              */
2824                             pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2825                             "highest rate seen: %ld B/S in, %ld B/S out\n",
2826                             sc->inbytes, sc->outbytes,
2827                             sc->inrate, sc->outrate);
2828                             pos += sprintf(arg + pos,
2829                                 "%ld output errors\n",
2830                                 sc->oerrors);
2831                             pos += sprintf(arg + pos,
2832                                 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2833                                 sc->ierrors[0],
2834                                 sc->ierrors[1],
2835                                 sc->ierrors[2],
2836                                 sc->ierrors[3],
2837                                 sc->ierrors[4],
2838                                 sc->ierrors[5]);
2839
2840                             (*resp)->header.version = NG_VERSION;
2841                             (*resp)->header.arglen = strlen(arg) + 1;
2842                             (*resp)->header.token = msg->header.token;
2843                             (*resp)->header.typecookie = NG_SR_COOKIE;
2844                             (*resp)->header.cmd = msg->header.cmd;
2845                             strncpy((*resp)->header.cmdstr, "status",
2846                                         NG_CMDSTRLEN);
2847                         }
2848                         break;
2849                     default:
2850                         error = EINVAL;
2851                         break;
2852                     }
2853                 break;
2854             default:
2855                 error = EINVAL;
2856                 break;
2857         }
2858         free(msg, M_NETGRAPH);
2859         return (error);
2860 }
2861
2862 /*
2863  * get data from another node and transmit it to the correct channel
2864  */
2865 static  int
2866 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2867 {
2868         int s;
2869         int error = 0;
2870         struct sr_softc * sc = hook->node->private;
2871         struct ifqueue  *xmitq_p;
2872
2873         /*
2874          * data doesn't come in from just anywhere (e.g control hook)
2875          */
2876         if ( hook->private == NULL) {
2877                 error = ENETDOWN;
2878                 goto bad;
2879         }
2880
2881         /*
2882          * Now queue the data for when it can be sent
2883          */
2884         if (meta && meta->priority > 0) {
2885                 xmitq_p = (&sc->xmitq_hipri);
2886         } else {
2887                 xmitq_p = (&sc->xmitq);
2888         }
2889         s = splimp();
2890         if (IF_QFULL(xmitq_p)) {
2891                 IF_DROP(xmitq_p);
2892                 splx(s);
2893                 error = ENOBUFS;
2894                 goto bad;
2895         }
2896         IF_ENQUEUE(xmitq_p, m);
2897         srstart(sc);
2898         splx(s);
2899         return (0);
2900
2901 bad:
2902         /*
2903          * It was an error case.
2904          * check if we need to free the mbuf, and then return the error
2905          */
2906         NG_FREE_DATA(m, meta);
2907         return (error);
2908 }
2909
2910 /*
2911  * do local shutdown processing..
2912  * this node will refuse to go away, unless the hardware says to..
2913  * don't unref the node, or remove our name. just clear our links up.
2914  */
2915 static  int
2916 ngsr_rmnode(node_p node)
2917 {
2918         struct sr_softc * sc = node->private;
2919
2920         sr_down(sc);
2921         ng_cutlinks(node);
2922         node->flags &= ~NG_INVALID; /* bounce back to life */
2923         return (0);
2924 }
2925
2926 /* already linked */
2927 static  int
2928 ngsr_connect(hook_p hook)
2929 {
2930         /* be really amiable and just say "YUP that's OK by me! " */
2931         return (0);
2932 }
2933
2934 /*
2935  * notify on hook disconnection (destruction)
2936  *
2937  * Invalidate the private data associated with this dlci.
2938  * For this type, removal of the last link resets tries to destroy the node.
2939  * As the device still exists, the shutdown method will not actually
2940  * destroy the node, but reset the device and leave it 'fresh' :)
2941  *
2942  * The node removal code will remove all references except that owned by the
2943  * driver.
2944  */
2945 static  int
2946 ngsr_disconnect(hook_p hook)
2947 {
2948         struct sr_softc * sc = hook->node->private;
2949         int     s;
2950         /*
2951          * If it's the data hook, then free resources etc.
2952          */
2953         if (hook->private) {
2954                 s = splimp();
2955                 sc->datahooks--;
2956                 if (sc->datahooks == 0)
2957                         sr_down(sc);
2958                 splx(s);
2959         } else {
2960                 sc->debug_hook = NULL;
2961         }
2962         return (0);
2963 }
2964
2965 /*
2966  * called during bootup
2967  * or LKM loading to put this type into the list of known modules
2968  */
2969 static void
2970 ngsr_init(void *ignored)
2971 {
2972         if (ng_newtype(&typestruct))
2973                 printf("ngsr install failed\n");
2974         ngsr_done_init = 1;
2975 }
2976 #endif /* NETGRAPH */
2977
2978 /*
2979  ********************************* END ************************************
2980  */