2 * Copyright (c) 1996, 2000 Gary Jennejohn. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 *---------------------------------------------------------------------------
33 * $FreeBSD: src/sys/i4b/layer1/isic/i4b_hscx.h,v 1.2.2.1 2001/08/10 14:08:38 obrien Exp $
35 * last edit-date: [Wed Jan 24 09:09:51 2001]
37 *---------------------------------------------------------------------------*/
43 HSCX_VA1, /* 82525 A1 */
44 HSCX_UNKN1, /* unknown 1 */
45 HSCX_VA2, /* 82525 A2 */
46 HSCX_UNKN3, /* unknown 3 */
47 HSCX_VA3, /* 82525 A3 */
48 HSCX_V21, /* 82525 2.1 */
49 HSCX_UNKN /* unknown version */
52 #define HSCX_CH_A 0 /* channel A */
53 #define HSCX_CH_B 1 /* channel B */
55 #define HSCX_FIFO_LEN 32 /* 32 bytes FIFO on chip */
58 * definitions of registers and bits for the HSCX ISDN chip.
61 typedef struct hscx_reg {
63 /* 32 byte deep FIFO always first */
65 unsigned char hscx_fifo [HSCX_FIFO_LEN];
67 /* most registers can be read/written, but have different names */
68 /* so define a union with read/write names to make that clear */
72 unsigned char hscx_ista;
73 unsigned char hscx_star;
74 unsigned char hscx_mode;
75 unsigned char hscx_timr;
76 unsigned char hscx_exir;
77 unsigned char hscx_rbcl;
78 unsigned char dummy_26;
79 unsigned char hscx_rsta;
80 unsigned char hscx_ral1;
81 unsigned char hscx_rhcr;
82 unsigned char dummy_2a;
83 unsigned char dummy_2b;
84 unsigned char hscx_ccr2;
85 unsigned char hscx_rbch;
86 unsigned char hscx_vstr;
87 unsigned char hscx_ccr;
88 unsigned char dummy_30;
89 unsigned char dummy_31;
90 unsigned char dummy_32;
91 unsigned char dummy_33;
94 unsigned char hscx_mask;
95 unsigned char hscx_cmdr;
96 unsigned char hscx_mode;
97 unsigned char hscx_timr;
98 unsigned char hscx_xad1;
99 unsigned char hscx_xad2;
100 unsigned char hscx_rah1;
101 unsigned char hscx_rah2;
102 unsigned char hscx_ral1;
103 unsigned char hscx_ral2;
104 unsigned char hscx_xbcl;
105 unsigned char hscx_bgr;
106 unsigned char hscx_ccr2;
107 unsigned char hscx_xbch;
108 unsigned char hscx_rlcr;
109 unsigned char hscx_ccr1;
110 unsigned char hscx_tsax;
111 unsigned char hscx_tsar;
112 unsigned char hscx_xccr;
113 unsigned char hscx_rccr;
118 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
120 /* HSCX read registers */
122 #define h_ista hscx_rw.hscx_r.hscx_ista
123 #define H_ISTA REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ista)
124 #define h_star hscx_rw.hscx_r.hscx_star
125 #define H_STAR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_star)
126 #define h_mode hscx_rw.hscx_r.hscx_mode
127 #define H_MODE REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_mode)
128 #define h_timr hscx_rw.hscx_r.hscx_timr
129 #define H_TIMR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_timr)
130 #define h_exir hscx_rw.hscx_r.hscx_exir
131 #define H_EXIR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_exir)
132 #define h_rbcl hscx_rw.hscx_r.hscx_rbcl
133 #define H_RBCL REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rbcl)
134 #define h_rsta hscx_rw.hscx_r.hscx_rsta
135 #define H_RSTA REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rsta)
136 #define h_ral1 hscx_rw.hscx_r.hscx_ral1
137 #define H_RAL1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ral1)
138 #define h_rhcr hscx_rw.hscx_r.hscx_rhcr
139 #define H_RHCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rhcr)
140 #define h_ccr2 hscx_rw.hscx_r.hscx_ccr2
141 #define H_CCR2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ccr2)
142 #define h_rbch hscx_rw.hscx_r.hscx_rbch
143 #define H_RBCH REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rbch)
144 #define h_vstr hscx_rw.hscx_r.hscx_vstr
145 #define H_VSTR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_vstr)
146 #define h_ccr hscx_rw.hscx_r.hscx_ccr
147 #define H_CCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ccr)
149 /* HSCX write registers - for hscx_mode, hscx_timr, hscx_ral1, hscx_ccr2 */
150 /* see read registers */
152 #define h_mask hscx_rw.hscx_w.hscx_mask
153 #define H_MASK REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_mask)
154 #define h_cmdr hscx_rw.hscx_w.hscx_cmdr
155 #define H_CMDR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_cmdr)
156 #define h_xad1 hscx_rw.hscx_w.hscx_xad1
157 #define H_XAD1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xad1)
158 #define h_xad2 hscx_rw.hscx_w.hscx_xad2
159 #define H_XAD2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xad2)
160 #define h_rah1 hscx_rw.hscx_w.hscx_rah1
161 #define H_RAH1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rah1)
162 #define h_rah2 hscx_rw.hscx_w.hscx_rah2
163 #define H_RAH2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rah2)
164 #define h_ral2 hscx_rw.hscx_w.hscx_ral2
165 #define H_RAL2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_ral2)
166 #define h_xbcl hscx_rw.hscx_w.hscx_xbcl
167 #define H_XBCL REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xbcl)
168 #define h_bgr hscx_rw.hscx_w.hscx_bgr
169 #define H_BGR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_bgr)
170 #define h_xbch hscx_rw.hscx_w.hscx_xbch
171 #define H_XBCH REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xbch)
172 #define h_rlcr hscx_rw.hscx_w.hscx_rlcr
173 #define H_RLCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rlcr)
174 #define h_ccr1 hscx_rw.hscx_w.hscx_ccr1
175 #define H_CCR1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_ccr1)
176 #define h_tsax hscx_rw.hscx_w.hscx_tsax
177 #define H_TSAX REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_tsax)
178 #define h_tsar hscx_rw.hscx_w.hscx_tsar
179 #define H_TSAR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_tsar)
180 #define h_xccr hscx_rw.hscx_w.hscx_xccr
181 #define H_XCCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xccr)
182 #define h_rccr hscx_rw.hscx_w.hscx_rccr
183 #define H_RCCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rccr)
185 #define HSCX_ISTA_RME 0x80
186 #define HSCX_ISTA_RPF 0x40
187 #define HSCX_ISTA_RSC 0x20
188 #define HSCX_ISTA_XPR 0x10
189 #define HSCX_ISTA_TIN 0x08
190 #define HSCX_ISTA_ICA 0x04
191 #define HSCX_ISTA_EXA 0x02
192 #define HSCX_ISTA_EXB 0x01
194 #define HSCX_MASK_RME 0x80
195 #define HSCX_MASK_RPF 0x40
196 #define HSCX_MASK_RSC 0x20
197 #define HSCX_MASK_XPR 0x10
198 #define HSCX_MASK_TIN 0x08
199 #define HSCX_MASK_ICA 0x04
200 #define HSCX_MASK_EXA 0x02
201 #define HSCX_MASK_EXB 0x01
203 #define HSCX_EXIR_XMR 0x80
204 #define HSCX_EXIR_XDU 0x40
205 #define HSCX_EXIR_PCE 0x20
206 #define HSCX_EXIR_RFO 0x10
207 #define HSCX_EXIR_CSC 0x08
208 #define HSCX_EXIR_RFS 0x04
210 /* the other bits are always 0 */
212 #define HSCX_STAR_XDOV 0x80
213 #define HSCX_STAR_XFW 0x40
214 #define HSCX_STAR_XRNR 0x20
215 #define HSCX_STAR_RRNR 0x10
216 #define HSCX_STAR_RLI 0x08
217 #define HSCX_STAR_CEC 0x04
218 #define HSCX_STAR_CTS 0x02
219 #define HSCX_STAR_WFA 0x01
221 #define HSCX_CMDR_RMC 0x80
222 #define HSCX_CMDR_RHR 0x40
223 /* also known as XREP in transparent mode */
224 #define HSCX_CMDR_RNR 0x20
225 #define HSCX_CMDR_STI 0x10
226 #define HSCX_CMDR_XTF 0x08
227 #define HSCX_CMDR_XIF 0x04
228 #define HSCX_CMDR_XME 0x02
229 #define HSCX_CMDR_XRES 0x01
231 #define HSCX_MODE_MDS1 0x80
232 #define HSCX_MODE_MDS0 0x40
233 #define HSCX_MODE_ADM 0x20
234 #define HSCX_MODE_TMD 0x10
235 #define HSCX_MODE_RAC 0x08
236 #define HSCX_MODE_RTS 0x04
237 #define HSCX_MODE_TRS 0x02
238 #define HSCX_MODE_TLP 0x01
240 #define HSCX_RSTA_VFR 0x80
241 #define HSCX_RSTA_RDO 0x40
242 #define HSCX_RSTA_CRC 0x20
243 #define HSCX_RSTA_RAB 0x10
244 #define HSCX_RSTA_HA1 0x08
245 #define HSCX_RSTA_HA0 0x04
246 #define HSCX_RSTA_CR 0x02
247 #define HSCX_RSTA_LA 0x01
249 #define HSCX_RSTA_MASK 0xf0 /* the interesting ones */
251 /* only used in DMA mode */
252 #define HSCX_XBCH_DMA 0x80
253 #define HSCX_XBCH_NRM 0x40
254 #define HSCX_XBCH_CAS 0x20
255 #define HSCX_XBCH_XC 0x10
256 /* the rest are bits 11 thru 8 of the byte count */
258 #define HSCX_RBCH_DMA 0x80
259 #define HSCX_RBCH_NRM 0x40
260 #define HSCX_RBCH_CAS 0x20
261 #define HSCX_RBCH_OV 0x10
262 /* the rest are bits 11 thru 8 of the byte count */
264 #define HSCX_VSTR_CD 0x80
265 /* bits 6 thru 4 are 0 */
266 /* bits 3 thru 0 are the version number */
268 #define HSCX_RLCR_RC 0x80
269 /* the rest of the bits are used to set the received length */
271 #define HSCX_CCR1_PU 0x80
272 /* bits 6 and 5 are SC1 SC0 */
273 #define HSCX_CCR1_ODS 0x10
274 #define HSCX_CCR1_ITF 0x08
275 #define HSCX_CCR1_CM2 0x04
276 #define HSCX_CCR1_CM1 0x02
277 #define HSCX_CCR1_CM0 0x01
279 /* for clock mode 5 */
280 #define HSCX_CCR2_SOC2 0x80
281 #define HSCX_CCR2_SOC1 0x40
282 #define HSCX_CCR2_XCS0 0x20
283 #define HSCX_CCR2_RCS0 0x10
284 #define HSCX_CCR2_TIO 0x08
285 #define HSCX_CCR2_CIE 0x04
286 #define HSCX_CCR2_RIE 0x02
287 #define HSCX_CCR2_DIV 0x01
289 /* bits 7 thru 2 are TSNX */
290 #define HSCX_TSAX_XCS2 0x02
291 #define HSCX_TSAX_XCS1 0x01
293 /* bits 7 thru 2 are TSNR */
294 #define HSCX_TSAR_RCS2 0x02
295 #define HSCX_TSAR_RCS1 0x01
297 #endif /* I4B_HSCX_H_ */