2 * Copyright (c) 2000, 2001 Sergio Prallon. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 *---------------------------------------------------------------------------
33 * i4b_itjc_pci.c: NetJet-S hardware driver
34 * ----------------------------------------
36 * $FreeBSD: src/sys/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.1.2.1 2001/08/10 14:08:39 obrien Exp $
38 * last edit-date: [Thu Jan 11 11:29:38 2001]
40 *---------------------------------------------------------------------------*/
48 #include <sys/param.h>
49 #include <sys/kernel.h>
50 #include <sys/systm.h>
53 #include <machine/clock.h>
54 #include <machine/bus_pio.h>
55 #include <machine/bus.h>
56 #include <machine/resource.h>
60 #include <pci/pcireg.h>
61 #include <pci/pcivar.h>
63 #include <sys/socket.h>
66 #include <machine/i4b_debug.h>
67 #include <machine/i4b_ioctl.h>
68 #include <machine/i4b_trace.h>
70 #include <i4b/include/i4b_global.h>
71 #include <i4b/include/i4b_mbuf.h>
73 #include <i4b/layer1/i4b_l1.h>
75 #include <i4b/layer1/itjc/i4b_hdlc.h> /* XXXXXXXXXXXXXXXXXXXXXXXX */
77 #include <i4b/layer1/isic/i4b_isic.h>
78 #include <i4b/layer1/isic/i4b_isac.h>
80 #include <i4b/layer1/itjc/i4b_itjc_ext.h>
82 #define PCI_TJNET_VID (0xe159)
83 #define PCI_TJ300_DID (0x0001)
90 static int itjc_probe(device_t dev);
91 static int itjc_attach(device_t dev);
92 static void itjc_shutdown(device_t dev);
93 static void itjc_intr(void *xsc);
94 static int itjc_dma_start(struct l1_softc *sc);
95 static void itjc_dma_stop(struct l1_softc *sc);
96 static void itjc_isac_intr(struct l1_softc *sc);
97 static void itjc_init_linktab(struct l1_softc *sc);
98 static void itjc_bchannel_setup(int unit, int h_chan, int bprot,
100 static void itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp);
104 * Shorter names to bus resource manager routines.
107 #define itjc_bus_setup(sc) \
108 bus_space_handle_t h = \
109 rman_get_bushandle((sc)->sc_resources.io_base[0]); \
110 bus_space_tag_t t = \
111 rman_get_bustag((sc)->sc_resources.io_base[0]);
113 #define itjc_read_1(port) (bus_space_read_1(t, h, (port)))
114 #define itjc_read_4(port) (bus_space_read_4(t, h, (port)))
115 #define itjc_write_1(port, data) (bus_space_write_1(t, h, (port), (data)))
116 #define itjc_write_4(port, data) (bus_space_write_4(t, h, (port), (data)))
117 #define itjc_read_multi_1(port, buf, size) \
118 (bus_space_read_multi_1(t, h, (port), (buf), (size)))
119 #define itjc_write_multi_1(port, buf, size) \
120 (bus_space_write_multi_1(t, h, (port), (buf), (size)))
123 /*---------------------------------------------------------------------------*
124 * Glue data to register ourselves as a PCI device driver.
125 *---------------------------------------------------------------------------*/
127 static device_method_t itjc_pci_methods[] =
129 /* Device interface */
130 DEVMETHOD(device_probe, itjc_probe),
131 DEVMETHOD(device_attach, itjc_attach),
132 DEVMETHOD(device_shutdown, itjc_shutdown),
135 DEVMETHOD(bus_print_child, bus_generic_print_child),
136 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
141 static driver_t itjc_pci_driver =
145 sizeof(struct l1_softc)
148 static devclass_t itjc_pci_devclass;
150 DRIVER_MODULE(netjet, pci, itjc_pci_driver, itjc_pci_devclass, 0, 0);
153 * Jump table for multiplex routines.
156 struct i4b_l1mux_func itjc_l1mux_func =
160 itjc_mph_command_req,
162 itjc_ph_activate_req,
165 struct l1_softc *itjc_scp[ITJC_MAXUNIT];
168 /*---------------------------------------------------------------------------*
169 * Tiger300/320 PCI ASIC registers.
170 *---------------------------------------------------------------------------*/
173 * Register offsets from i/o base.
177 TIGER_RESET_PIB_CL_TIME = 0x00,
178 TIGER_DMA_OPER = 0x01,
179 TIGER_AUX_PORT_CNTL = 0x02,
180 TIGER_AUX_PORT_DATA = 0x03,
181 TIGER_INT0_MASK = 0x04,
182 TIGER_INT1_MASK = 0x05,
183 TIGER_INT0_STATUS = 0x06,
184 TIGER_INT1_STATUS = 0x07,
185 TIGER_DMA_WR_START_ADDR = 0x08,
186 TIGER_DMA_WR_INT_ADDR = 0x0C,
187 TIGER_DMA_WR_END_ADDR = 0x10,
188 TIGER_DMA_WR_CURR_ADDR = 0x14,
189 TIGER_DMA_RD_START_ADDR = 0x18,
190 TIGER_DMA_RD_INT_ADDR = 0x1C,
191 TIGER_DMA_RD_END_ADDR = 0x20,
192 TIGER_DMA_RD_CURR_ADDR = 0x24,
193 TIGER_PULSE_COUNTER = 0x28,
197 * Bits on the above registers.
202 /* Reset and PIB Cycle Timing */
204 TIGER_DMA_OP_MODE_MASK = 0x80,
205 TIGER_SELF_ADDR_DMA = 0x00, /* Wrap around ending addr */
206 TIGER_NORMAL_DMA = 0x80, /* Stop at ending addr */
208 TIGER_DMA_INT_MODE_MASK = 0x40,
209 TIGER_DONT_LATCH_DMA_INT= 0x00, /* Bits on int0 status will be
210 set only while curr addr
211 equals int or end addr */
212 TIGER_LATCH_DMA_INT = 0x40, /* Bits on int0 status remain
213 set until cleared by CPU */
215 TIGER_PIB_CYCLE_TIMING_MASK = 0x30,
216 TIGER_PIB_3_CYCLES = 0x00,
217 TIGER_PIB_5_CYCLES = 0x01,
218 TIGER_PIB_12_CYCLES = 0x10,
220 TIGER_RESET_MASK = 0x0F,
221 TIGER_RESET_PULSE_COUNT = 0x08,
222 TIGER_RESET_SERIAL_PORT = 0x04,
223 TIGER_RESET_DMA_LOGIC = 0x02,
224 TIGER_RESET_EXTERNAL = 0x01,
225 TIGER_RESET_ALL = 0x0F,
228 TIGER_DMA_RESTART_MASK = 0x02,
229 TIGER_HOLD_DMA = 0x00,
230 TIGER_RESTART_DMA = 0x00,
232 TIGER_DMA_ENABLE_MASK = 0x01,
233 TIGER_ENABLE_DMA = 0x01,
234 TIGER_DISABLE_DMA = 0x00,
236 /* AUX Port Control & Data plus Interrupt 1 Mask & Status */
237 TIGER_AUX_7_MASK = 0x80,
238 TIGER_AUX_6_MASK = 0x40,
239 TIGER_AUX_5_MASK = 0x20,
240 TIGER_AUX_4_MASK = 0x10,
241 TIGER_ISAC_INT_MASK = 0x10,
242 TIGER_AUX_3_MASK = 0x08,
243 TIGER_AUX_2_MASK = 0x04,
244 TIGER_AUX_1_MASK = 0x02,
245 TIGER_AUX_0_MASK = 0x01,
247 /* AUX Port Control */
248 TIGER_AUX_7_IS_INPUT = 0x00,
249 TIGER_AUX_7_IS_OUTPUT = 0x80,
250 TIGER_AUX_6_IS_INPUT = 0x00,
251 TIGER_AUX_6_IS_OUTPUT = 0x40,
252 TIGER_AUX_5_IS_INPUT = 0x00,
253 TIGER_AUX_5_IS_OUTPUT = 0x20,
254 TIGER_AUX_4_IS_INPUT = 0x00,
255 TIGER_AUX_4_IS_OUTPUT = 0x10,
256 TIGER_AUX_3_IS_INPUT = 0x00,
257 TIGER_AUX_3_IS_OUTPUT = 0x80,
258 TIGER_AUX_2_IS_INPUT = 0x00,
259 TIGER_AUX_2_IS_OUTPUT = 0x40,
260 TIGER_AUX_1_IS_INPUT = 0x00,
261 TIGER_AUX_1_IS_OUTPUT = 0x20,
262 TIGER_AUX_0_IS_INPUT = 0x00,
263 TIGER_AUX_0_IS_OUTPUT = 0x10,
264 TIGER_AUX_NJ_DEFAULT = 0xEF, /* All but ISAC int is output */
266 /* Interrupt 0 Mask & Status */
267 TIGER_PCI_TARGET_ABORT_INT_MASK = 0x20,
268 TIGER_NO_TGT_ABORT_INT = 0x00,
269 TIGER_TARGET_ABORT_INT = 0x20,
270 TIGER_PCI_MASTER_ABORT_INT_MASK = 0x10,
271 TIGER_NO_MST_ABORT_INT = 0x00,
272 TIGER_MASTER_ABORT_INT = 0x10,
273 TIGER_DMA_RD_END_INT_MASK = 0x08,
274 TIGER_NO_RD_END_INT = 0x00,
275 TIGER_RD_END_INT = 0x08,
276 TIGER_DMA_RD_INT_INT_MASK = 0x04,
277 TIGER_NO_RD_INT_INT = 0x00,
278 TIGER_RD_INT_INT = 0x04,
279 TIGER_DMA_WR_END_INT_MASK = 0x02,
280 TIGER_NO_WR_END_INT = 0x00,
281 TIGER_WR_END_INT = 0x02,
282 TIGER_DMA_WR_INT_INT_MASK = 0x01,
283 TIGER_NO_WR_INT_INT = 0x00,
284 TIGER_WR_INT_INT = 0x01,
286 /* Interrupt 1 Mask & Status */
287 TIGER_NO_AUX_7_INT = 0x00,
288 TIGER_AUX_7_INT = 0x80,
289 TIGER_NO_AUX_6_INT = 0x00,
290 TIGER_AUX_6_INT = 0x40,
291 TIGER_NO_AUX_5_INT = 0x00,
292 TIGER_AUX_5_INT = 0x20,
293 TIGER_NO_AUX_4_INT = 0x00,
294 TIGER_AUX_4_INT = 0x10,
295 TIGER_NO_ISAC_INT = 0x00,
296 TIGER_ISAC_INT = 0x10,
297 TIGER_NO_AUX_3_INT = 0x00,
298 TIGER_AUX_3_INT = 0x08,
299 TIGER_NO_AUX_2_INT = 0x00,
300 TIGER_AUX_2_INT = 0x04,
301 TIGER_NO_AUX_1_INT = 0x00,
302 TIGER_AUX_1_INT = 0x02,
303 TIGER_NO_AUX_0_INT = 0x00,
304 TIGER_AUX_0_INT = 0x01
308 * Peripheral Interface Bus definitions. This is an ISA like bus
309 * created by the Tiger ASIC to keep ISA chips like the ISAC happy
310 * on a PCI environment.
312 * Since the PIB only supplies 4 addressing lines, the 2 higher bits
313 * (A4 & A5) of the ISAC register addresses are wired on the 2 lower
314 * AUX lines. Another restriction is that all I/O to the PIB (8bit
315 * wide) is mapped on the PCI side as 32bit data. So the PCI address
316 * of a given ISAC register has to be multiplied by 4 before being
317 * added to the PIB base offset.
319 enum tiger_pib_regs_defs
321 /* Offset from the I/O base to the ISAC registers. */
323 PIB_LO_ADDR_MASK = 0x0F,
324 PIB_HI_ADDR_MASK = 0x30,
325 PIB_LO_ADDR_SHIFT = 2, /* Align on dword boundary */
326 PIB_HI_ADDR_SHIFT = 4 /* Right shift to AUX_1 & AUX_0 */
330 #define itjc_set_pib_addr_msb(a) \
332 itjc_write_1(TIGER_AUX_PORT_DATA, \
333 ((a) & PIB_HI_ADDR_MASK) >> PIB_HI_ADDR_SHIFT) \
336 #define itjc_pib_2_pci(a) \
338 (((a) & PIB_LO_ADDR_MASK) << PIB_LO_ADDR_SHIFT) + PIB_OFFSET \
341 #define itjc_get_dma_offset(ctx,reg) \
343 (u_int16_t)((bus_addr_t)itjc_read_4((reg)) - (ctx)->bus_addr) \
348 * IOM-2 serial channel 0 DMA data ring buffers.
350 * The Tiger300/320 ASIC do not nothing more than transfer via DMA the
351 * first 32 bits of every IOM-2 frame on the serial interface to the
352 * ISAC. So we have no framing/deframing facilities like we would have
353 * with an HSCX, having to do the job with CPU cycles. On the plus side
354 * we are able to specify large rings which can limit the occurrence of
360 ITJC_RING_SLOT_WORDS = 64,
361 ITJC_RING_WORDS = 3 * ITJC_RING_SLOT_WORDS,
362 ITJC_RING_SLOT_BYTES = 4 * ITJC_RING_SLOT_WORDS,
363 ITJC_RING_BYTES = 4 * ITJC_RING_WORDS,
364 ITJC_DMA_POOL_WORDS = 2 * ITJC_RING_WORDS,
365 ITJC_DMA_POOL_BYTES = 4 * ITJC_DMA_POOL_WORDS
368 #define itjc_ring_add(x, d) (((x) + 4 * (d)) % ITJC_RING_BYTES)
369 #define itjc_ring_sub(x, d) (((x) + ITJC_RING_BYTES - 4 * (d)) \
378 HSCX_CH_A = 0, /* For compatibility reasons. */
384 ITJC_TEL_SILENCE_BYTE = 0x00,
385 ITJC_HDLC_FLAG_BYTE = 0x7E,
386 ITJC_HDLC_ABORT_BYTE = 0xFF
390 * Hardware DMA control block (one per card).
394 ITJC_DS_LOAD_FAILED = -1,
414 dma_context [ ITJC_MAXUNIT ];
417 * B-channel DMA control blocks (4 per card -- 1 RX & 1 TX per channel).
443 u_int8_t hdlc_blevel;
445 dma_rx_state_t state;
453 u_int16_t next_write;
455 u_int16_t hdlc_blevel;
458 u_int16_t next_frame;
461 dma_tx_state_t state;
466 dma_rx_context [ ITJC_MAXUNIT ] [ 2 ];
469 dma_tx_context [ ITJC_MAXUNIT ] [ 2 ];
472 * Used by the mbuf handling functions.
483 /*---------------------------------------------------------------------------*
484 * itjc_map_callback - get DMA bus address from resource mgr.
485 *---------------------------------------------------------------------------*/
487 itjc_map_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
489 dma_context_t *ctx = (dma_context_t *)arg;
494 ctx->state = ITJC_DS_LOAD_FAILED;
498 ctx->bus_addr = segs->ds_addr;
499 ctx->state = ITJC_DS_STOPPED;
503 /*---------------------------------------------------------------------------*
504 * itjc_dma_start - Complete DMA setup & start the Tiger DMA engine.
505 *---------------------------------------------------------------------------*/
507 itjc_dma_start(struct l1_softc *sc)
509 int unit = sc->sc_unit;
510 dma_context_t *ctx = &dma_context[unit];
511 dma_rx_context_t *rxc = &dma_rx_context[unit][0];
512 dma_tx_context_t *txc = &dma_tx_context[unit][0];
520 /* See if it is already running. */
522 if (ctx->state == ITJC_DS_RUNNING)
525 if (ctx->state == ITJC_DS_LOAD_FAILED)
527 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA map loading "
528 "failed (error=%d).\n", unit, ctx->error);
532 if (ctx->state != ITJC_DS_STOPPED)
534 NDBGL1(L1_ERROR, "itjc%d: dma_start: Unexpected DMA "
535 "state (%d).\n", unit, ctx->state);
540 * Initialize the DMA control structures (hardware & B-channel).
544 txc->ring = ctx->pool + TIGER_CH_A;
545 rxc->ring = ctx->pool + TIGER_CH_A + ITJC_RING_BYTES;
548 rxc->bus_addr = ba + ITJC_RING_BYTES;
552 txc->ring = ctx->pool + TIGER_CH_B;
553 rxc->ring = ctx->pool + TIGER_CH_B + ITJC_RING_BYTES;
556 rxc->bus_addr = ba + ITJC_RING_BYTES;
559 * Fill the DMA ring buffers with IOM-2 channel 0 frames made of
560 * idle/abort sequences for the B & D channels and NOP for IOM-2
561 * cmd/ind, monitor handshake & data.
563 pool_end = (u_int32_t *)ctx->pool + ITJC_DMA_POOL_WORDS;
564 for (ip = (u_int32_t *)ctx->pool; ip < pool_end; ++ip)
568 * Program the Tiger DMA gears.
571 itjc_write_4(TIGER_DMA_WR_START_ADDR, ba);
572 itjc_write_4(TIGER_DMA_WR_INT_ADDR, ba + ITJC_RING_SLOT_BYTES - 4);
573 itjc_write_4(TIGER_DMA_WR_END_ADDR, ba + ITJC_RING_BYTES - 4);
575 ba += ITJC_RING_BYTES;
577 itjc_write_4(TIGER_DMA_RD_START_ADDR, ba);
578 itjc_write_4(TIGER_DMA_RD_INT_ADDR, ba + ITJC_RING_SLOT_BYTES * 2 - 4);
579 itjc_write_4(TIGER_DMA_RD_END_ADDR, ba + ITJC_RING_BYTES - 4);
581 itjc_write_1(TIGER_INT0_MASK,
582 TIGER_WR_END_INT | TIGER_WR_INT_INT | TIGER_RD_INT_INT);
584 itjc_write_1(TIGER_DMA_OPER, TIGER_ENABLE_DMA);
587 * See if it really started.
589 ba = itjc_read_4(TIGER_DMA_RD_CURR_ADDR);
590 for (i = 0; i < 10; ++i)
592 DELAY(SEC_DELAY/1000);
593 if (ba != itjc_read_4(TIGER_DMA_RD_CURR_ADDR))
595 ctx->state = ITJC_DS_RUNNING;
600 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA start failed.\n ", unit);
605 /*---------------------------------------------------------------------------*
606 * itjc_dma_stop - Stop the Tiger DMA engine.
607 *---------------------------------------------------------------------------*/
609 itjc_dma_stop(struct l1_softc *sc)
611 dma_context_t *ctx = &dma_context[sc->sc_unit];
615 /* Only stop the DMA if it is running. */
617 if (ctx->state != ITJC_DS_RUNNING)
620 itjc_write_1(TIGER_DMA_OPER, TIGER_DISABLE_DMA);
621 DELAY(SEC_DELAY/1000);
623 ctx->state = ITJC_DS_STOPPED;
627 /*---------------------------------------------------------------------------*
628 * itjc_bchannel_dma_setup - The DMA side of itjc_bchannel_setup.
629 *---------------------------------------------------------------------------*/
631 itjc_bchannel_dma_setup(struct l1_softc *sc, int h_chan, int activate)
633 dma_rx_context_t *rxc = &dma_rx_context[sc->sc_unit][h_chan];
634 dma_tx_context_t *txc = &dma_tx_context[sc->sc_unit][h_chan];
636 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
649 * Get the DMA engine going if it's not running already.
653 rxc->hdlc_len = rxc->hdlc_tmp = rxc->hdlc_crc = 0;
654 rxc->hdlc_ib = rxc->hdlc_blevel = rxc->hdlc_flag = 0;
656 txc->hdlc_tmp = txc->hdlc_blevel = txc->hdlc_crc = 0;
661 if (chan->bprot == BPROT_NONE)
662 fill_byte = ITJC_TEL_SILENCE_BYTE;
664 fill_byte = ITJC_HDLC_ABORT_BYTE;
666 ring_end = rxc->ring + ITJC_RING_BYTES;
667 for (cp = rxc->ring; cp < ring_end; cp += 4)
670 ring_end = txc->ring + ITJC_RING_BYTES;
671 for (cp = txc->ring; cp < ring_end; cp += 4)
675 itjc_get_dma_offset(rxc, TIGER_DMA_RD_CURR_ADDR);
677 txc->next_frame = txc->next_write =
678 itjc_get_dma_offset(txc, TIGER_DMA_WR_CURR_ADDR);
680 rxc->state = ITJC_RS_ACTIVE;
681 txc->state = ITJC_TS_AFTER_XDU;
685 dma_rx_context_t *rxc2;
687 txc->state = ITJC_TS_IDLE;
688 rxc->state = ITJC_RS_IDLE;
690 rxc2 = &dma_rx_context[sc->sc_unit][0];
692 if (rxc2->state == ITJC_RS_IDLE
693 && rxc2[1].state == ITJC_RS_IDLE)
701 /*---------------------------------------------------------------------------*
702 * Mbuf & if_queues management routines.
703 *---------------------------------------------------------------------------*/
706 itjc_get_rx_mbuf(l1_bchan_state_t *chan, u_int8_t **dst_end_p,
709 struct mbuf *mbuf = chan->in_mbuf;
711 if (mbuf == NULL && which == ITJC_MB_NEW)
713 if ((mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
714 panic("itjc_get_rx_mbuf: cannot allocate mbuf!");
716 chan->in_mbuf = mbuf;
717 chan->in_cbptr = (u_int8_t *)mbuf->m_data;
721 if (dst_end_p != NULL)
724 *dst_end_p = (u_int8_t *)(mbuf->m_data)
730 return chan->in_cbptr;
735 itjc_save_rx_mbuf(l1_bchan_state_t *chan, u_int8_t * dst)
737 struct mbuf *mbuf = chan->in_mbuf;
739 if (dst != NULL && mbuf != NULL)
741 chan->in_cbptr = dst;
742 chan->in_len = dst - (u_int8_t *)mbuf->m_data;
744 else if (dst == NULL && mbuf == NULL)
746 chan->in_cbptr = NULL;
750 panic("itjc_save_rx_mbuf: stale pointer dst=%p mbuf=%p "
751 "in_cbptr=%p in_len=%d", dst, mbuf,
752 chan->in_cbptr, chan->in_len);
757 itjc_free_rx_mbuf(l1_bchan_state_t *chan)
759 struct mbuf *mbuf = chan->in_mbuf;
764 chan->in_mbuf = NULL;
765 chan->in_cbptr = NULL;
771 itjc_put_rx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan, u_int16_t len)
774 struct mbuf *mbuf = chan->in_mbuf;
775 u_int8_t *data = mbuf->m_data;
778 mbuf->m_pkthdr.len = mbuf->m_len = len;
780 if (sc->sc_trace & TRACE_B_RX)
782 hdr.unit = L0ITJCUNIT(sc->sc_unit);
783 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
785 hdr.count = ++sc->sc_trace_bcount;
787 i4b_l1_trace_ind(&hdr, len, data);
790 if (chan->bprot == BPROT_NONE)
792 activity = ! i4b_l1_bchan_tel_silence(data, len);
794 /* move rx'd data to rx queue */
796 if (! _IF_QFULL(&chan->rx_queue))
798 IF_ENQUEUE(&chan->rx_queue, mbuf);
809 chan->rxcount += len;
811 (*chan->isic_drvr_linktab->bch_rx_data_ready)
812 (chan->isic_drvr_linktab->unit);
816 (*chan->isic_drvr_linktab->bch_activity)
817 (chan->isic_drvr_linktab->unit, ACT_RX);
819 chan->in_mbuf = NULL;
820 chan->in_cbptr = NULL;
825 #define itjc_free_tx_mbufs(chan) \
827 i4b_Bfreembuf((chan)->out_mbuf_head); \
828 (chan)->out_mbuf_cur = (chan)->out_mbuf_head = NULL; \
829 (chan)->out_mbuf_cur_ptr = NULL; \
830 (chan)->out_mbuf_cur_len = 0; \
835 itjc_get_tx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan,
836 u_int8_t **src_p, which_mb_t which)
839 struct mbuf *mbuf = chan->out_mbuf_cur;
840 u_int8_t activity = 1;
849 *src_p = chan->out_mbuf_cur_ptr;
850 return chan->out_mbuf_cur_len;
858 chan->txcount += mbuf->m_len;
866 chan->out_mbuf_cur_ptr = *src_p = NULL;
867 chan->out_mbuf_cur_len = 0;
869 if (chan->out_mbuf_head != NULL)
871 i4b_Bfreembuf(chan->out_mbuf_head);
872 chan->out_mbuf_head = NULL;
879 chan->txcount += mbuf->m_len;
882 if (chan->out_mbuf_head != NULL)
883 i4b_Bfreembuf(chan->out_mbuf_head);
885 IF_DEQUEUE(&chan->tx_queue, mbuf);
889 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
890 chan->out_mbuf_cur_ptr = *src_p = NULL;
891 chan->out_mbuf_cur_len = 0;
893 chan->state &= ~(HSCX_TX_ACTIVE);
895 (*chan->isic_drvr_linktab->bch_tx_queue_empty)
896 (chan->isic_drvr_linktab->unit);
901 chan->out_mbuf_head = mbuf;
904 chan->out_mbuf_cur = mbuf;
905 chan->out_mbuf_cur_ptr = data = mbuf->m_data;
906 chan->out_mbuf_cur_len = len = mbuf->m_len;
908 chan->state |= HSCX_TX_ACTIVE;
910 if (sc->sc_trace & TRACE_B_TX)
912 hdr.unit = L0ITJCUNIT(sc->sc_unit);
913 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
915 hdr.count = ++sc->sc_trace_bcount;
917 i4b_l1_trace_ind(&hdr, len, data);
920 if (chan->bprot == BPROT_NONE)
921 activity = ! i4b_l1_bchan_tel_silence(data, len);
924 (*chan->isic_drvr_linktab->bch_activity)
925 (chan->isic_drvr_linktab->unit, ACT_TX);
932 #define itjc_save_tx_mbuf(chan, src, dst) \
934 (chan)->out_mbuf_cur != NULL ? \
936 (chan)->out_mbuf_cur_ptr = (src), \
937 (chan)->out_mbuf_cur_len = (len) \
944 /*---------------------------------------------------------------------------*
945 * B-channel interrupt service routines.
946 *---------------------------------------------------------------------------*/
949 * Since the Tiger ASIC doesn't produce a XMIT underflow indication,
950 * we need to deduce it ourselves. This is somewhat tricky because we
951 * are dealing with modulo m arithmetic. The idea here is to have a
952 * "XDU zone" ahead of the writing pointer sized 1/3 of total ring
953 * length (a ring slot). If the hardware DMA pointer is found there we
954 * consider that a XDU has occurred. To complete the scheme, we never
955 * let the ring have more than 2 slots of (unsent) data and adjust the
956 * interrupt registers to cause an interrupt at every slot.
959 itjc_xdu(struct l1_softc *sc, l1_bchan_state_t *chan, dma_tx_context_t *ctx,
960 u_int16_t *dst_p, u_int16_t *dst_end_p, u_int8_t tx_restart)
975 * Since the hardware is running, be conservative and assume
976 * the pointer location has a `fuzy' error factor.
978 dma = itjc_get_dma_offset(ctx, TIGER_DMA_WR_CURR_ADDR);
980 dma_h = itjc_ring_add(dma, 1);
982 dst_end = itjc_ring_sub(dma_l, ITJC_RING_SLOT_WORDS);
984 if (ctx->state != ITJC_TS_ACTIVE)
986 xdu = (ctx->state == ITJC_TS_AFTER_XDU);
987 dst = itjc_ring_add(dma_h, 4);
992 * Check for xmit underruns.
994 xdu_l = dst = ctx->next_write;
995 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
998 xdu = (xdu_l <= dma_l && dma_l < xdu_h)
999 || (xdu_l <= dma_h && dma_h < xdu_h);
1001 xdu = (xdu_l <= dma_l || dma_l < xdu_h)
1002 || (xdu_l <= dma_h || dma_h < xdu_h);
1006 ctx->state = ITJC_TS_AFTER_XDU;
1008 dst = itjc_ring_add(dma_h, 4);
1010 else if (tx_restart)
1013 * See if we still can restart from immediately
1014 * after the last frame sent. It's a XDU test but
1015 * using the real data end on the comparsions. We
1016 * don't consider XDU an error here because we were
1017 * just trying to avoid send a filling gap between
1018 * frames. If it's already sent no harm is done.
1020 xdu_l = dst = ctx->next_frame;
1021 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1024 xdu = (xdu_l <= dma_l && dma_l < xdu_h)
1025 || (xdu_l <= dma_h && dma_h < xdu_h);
1027 xdu = (xdu_l <= dma_l || dma_l < xdu_h)
1028 || (xdu_l <= dma_h || dma_h < xdu_h);
1031 dst = itjc_ring_add(dma_h, 4);
1040 if (dst_end_p != NULL)
1041 *dst_end_p = dst_end;
1043 ctx->next_write = dst_end;
1049 #define itjc_rotate_hdlc_flag(blevel) \
1050 ((u_int8_t)(0x7E7E >> (8 - (u_int8_t)((blevel) >> 8))))
1054 itjc_dma_rx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1055 dma_rx_context_t *ctx)
1074 if (ctx->state == ITJC_RS_IDLE)
1078 dma = itjc_get_dma_offset(ctx, TIGER_DMA_RD_CURR_ADDR);
1079 dma = itjc_ring_sub(dma, 1);
1080 src = ctx->next_read;
1082 if (chan->bprot == BPROT_NONE)
1084 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_CURR);
1089 dst = itjc_get_rx_mbuf(chan, &dst_end,
1093 src = itjc_ring_add(src, 1);
1097 itjc_put_rx_mbuf(sc, chan, BCH_MAX_DATALEN);
1098 dst = dst_end = NULL;
1101 ctx->next_read = src;
1102 itjc_save_rx_mbuf(chan, dst);
1106 blevel = ctx->hdlc_blevel;
1107 flag = ctx->hdlc_flag;
1108 len = ctx->hdlc_len;
1109 tmp = ctx->hdlc_tmp;
1110 crc = ctx->hdlc_crc;
1113 dst = itjc_get_rx_mbuf(chan, NULL, ITJC_MB_CURR);
1117 HDLC_DECODE(*dst++, len, tmp, tmp2, blevel, ib, crc, flag,
1120 src = itjc_ring_add(src, 1);
1124 panic("itjc_dma_rx_intr: nfrcmd with "
1125 "valid current frame");
1127 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_NEW);
1128 len = dst_end - dst;
1131 len = BCH_MAX_DATALEN - len;
1133 if ((!len) || (len > BCH_MAX_DATALEN))
1136 * NOTE: frames without any data, only crc
1137 * field, should be silently discared.
1139 NDBGL1(L1_S_MSG, "itjc_dma_rx_intr: "
1140 "bad frame (len=%d, unit=%d)",
1143 itjc_free_rx_mbuf(chan);
1151 "CRC (crc=0x%04x, len=%d, unit=%d)",
1152 crc, len, sc->sc_unit);
1154 itjc_free_rx_mbuf(chan);
1159 itjc_put_rx_mbuf(sc, chan, len);
1166 NDBGL1(L1_S_ERR, "Read Abort (unit=%d)", sc->sc_unit);
1168 itjc_free_rx_mbuf(chan);
1173 NDBGL1(L1_S_ERR, "RDO (unit=%d) dma=%d src=%d",
1174 sc->sc_unit, dma, src);
1176 itjc_free_rx_mbuf(chan);
1184 itjc_save_rx_mbuf(chan, dst);
1186 ctx->next_read = src;
1187 ctx->hdlc_blevel= blevel;
1188 ctx->hdlc_flag = flag;
1189 ctx->hdlc_len = len;
1190 ctx->hdlc_tmp = tmp;
1191 ctx->hdlc_crc = crc;
1197 * The HDLC side of itjc_dma_tx_intr. We made a separate function
1198 * to improve readability and (perhaps) help the compiler with
1199 * register allocation.
1202 itjc_hdlc_encode(struct l1_softc *sc, l1_bchan_state_t *chan,
1203 dma_tx_context_t * ctx)
1212 u_int16_t saved_len,
1226 saved_len = len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1228 filled = ctx->filled;
1229 flag = ctx->hdlc_flag;
1231 if (src == NULL && flag == 2 && filled >= ITJC_RING_WORDS)
1234 tx_restart = (flag == 2 && src != NULL);
1235 xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, tx_restart);
1240 crc = ctx->hdlc_crc;
1241 tmp = ctx->hdlc_tmp;
1242 blevel = ctx->hdlc_blevel;
1248 NDBGL1(L1_H_XFRERR, "XDU");
1252 * Abort the current frame and
1253 * prepare for a full restart.
1255 itjc_free_tx_mbufs(chan);
1256 saved_len = len = filled = 0;
1257 flag = (u_int8_t)-2;
1259 else if (filled < ITJC_RING_SLOT_WORDS)
1262 * A little garbage may have been retransmitted.
1263 * Send an abort before any new data.
1266 flag = (u_int8_t)-2;
1273 while (dst != dst_end)
1276 *src++, len, tmp, tmp2, blevel, ib, crc, flag,
1278 if ((len = saved_len) == 0)
1279 len = itjc_get_tx_mbuf(sc, chan, &src,
1284 ctx->next_frame = dst;
1286 flag_byte = itjc_rotate_hdlc_flag(blevel);
1288 for (dst_end1 = itjc_ring_sub(dst_end, 1);
1290 dst = itjc_ring_add(dst, 1))
1292 ring[dst] = flag_byte;
1299 ctx->state = ITJC_TS_ACTIVE;
1303 len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1306 ring[dst] = (u_int8_t)tmp;
1307 dst = itjc_ring_add(dst, 1);
1312 ctx->hdlc_blevel = blevel;
1313 ctx->hdlc_flag = flag;
1314 ctx->hdlc_tmp = tmp;
1315 ctx->hdlc_crc = crc;
1318 ctx->filled = filled;
1319 ctx->next_write = dst;
1321 itjc_save_tx_mbuf(chan, src, len);
1326 itjc_dma_tx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1327 dma_tx_context_t * ctx)
1340 if (ctx->state == ITJC_TS_IDLE)
1343 if (chan->bprot != BPROT_NONE)
1345 itjc_hdlc_encode(sc, chan, ctx);
1350 filled = ctx->filled;
1352 len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1354 if (len == 0 && filled >= ITJC_RING_WORDS)
1357 xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, len != 0);
1359 if (xdu && filled < ITJC_RING_WORDS)
1361 NDBGL1(L1_H_XFRERR, "XDU");
1369 ctx->state = ITJC_TS_ACTIVE;
1371 data_end = src + len;
1372 while (dst != dst_end)
1374 ring[dst] = *src++; --len;
1376 dst = itjc_ring_add(dst, 1);
1378 if (src >= data_end)
1380 len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1382 len = itjc_get_tx_mbuf(sc, chan,
1390 data_end = src + len;
1394 itjc_save_tx_mbuf(chan, src, len);
1399 ctx->next_frame = dst;
1401 for (; dst != dst_end; dst = itjc_ring_add(dst, 1))
1403 ring[dst] = ITJC_TEL_SILENCE_BYTE;
1407 ctx->next_write = dst;
1408 ctx->filled = filled;
1414 /*---------------------------------------------------------------------------*
1415 * NetJet fifo read/write routines.
1416 *---------------------------------------------------------------------------*/
1419 itjc_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1423 if (what != ISIC_WHAT_ISAC)
1424 panic("itjc_write_fifo: Trying to read from HSCX fifo.\n");
1426 itjc_set_pib_addr_msb(0);
1427 itjc_read_multi_1(PIB_OFFSET, buf, size);
1432 itjc_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1436 if (what != ISIC_WHAT_ISAC)
1437 panic("itjc_write_fifo: Trying to write to HSCX fifo.\n");
1439 itjc_set_pib_addr_msb(0);
1440 itjc_write_multi_1(PIB_OFFSET, buf, size);
1444 /*---------------------------------------------------------------------------*
1445 * Read an ISAC register.
1446 *---------------------------------------------------------------------------*/
1448 itjc_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
1452 if (what != ISIC_WHAT_ISAC)
1454 panic("itjc_read_reg: what(%d) != ISIC_WHAT_ISAC\n",
1459 itjc_set_pib_addr_msb(offs);
1460 return itjc_read_1(itjc_pib_2_pci(offs));
1464 /*---------------------------------------------------------------------------*
1465 * Write an ISAC register.
1466 *---------------------------------------------------------------------------*/
1468 itjc_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
1472 if (what != ISIC_WHAT_ISAC)
1474 panic("itjc_write_reg: what(%d) != ISIC_WHAT_ISAC\n",
1479 itjc_set_pib_addr_msb(offs);
1480 itjc_write_1(itjc_pib_2_pci(offs), data);
1484 /*---------------------------------------------------------------------------*
1485 * itjc_probe - probe for a card.
1486 *---------------------------------------------------------------------------*/
1487 static int itjc_probe(device_t dev)
1489 u_int16_t vid = pci_get_vendor(dev),
1490 did = pci_get_device(dev);
1492 if ((vid == PCI_TJNET_VID) && (did == PCI_TJ300_DID))
1494 device_set_desc(dev, "NetJet-S");
1502 /*---------------------------------------------------------------------------*
1503 * itjc_attach - attach a (previously probed) card.
1504 *---------------------------------------------------------------------------*/
1506 itjc_attach(device_t dev)
1508 bus_space_handle_t h;
1511 struct l1_softc *sc = device_get_softc(dev);
1513 u_int16_t vid = pci_get_vendor(dev),
1514 did = pci_get_device(dev);
1516 int unit = device_get_unit(dev),
1523 dma_context_t *ctx = &dma_context[unit];
1525 bzero(sc, sizeof(struct l1_softc));
1527 /* Probably not really required. */
1528 if (unit > ITJC_MAXUNIT)
1530 printf("itjc%d: Error, unit > ITJC_MAXUNIT!\n", unit);
1535 if (!(vid == PCI_TJNET_VID && did == PCI_TJ300_DID))
1537 printf("itjc%d: unknown device (%04X,%04X)!\n", unit, vid, did);
1541 itjc_scp[unit] = sc;
1543 sc->sc_resources.io_rid[0] = PCIR_MAPS+0;
1544 sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
1545 &sc->sc_resources.io_rid[0], 0, ~0, 1, RF_ACTIVE);
1547 if (sc->sc_resources.io_base[0] == NULL)
1549 printf("itjc%d: couldn't map IO port\n", unit);
1554 h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1555 t = rman_get_bustag(sc->sc_resources.io_base[0]);
1559 /* Allocate interrupt. */
1560 sc->sc_resources.irq_rid = 0;
1561 sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
1562 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
1564 if (sc->sc_resources.irq == NULL)
1566 printf("itjc%d: couldn't map interrupt\n", unit);
1573 error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
1574 itjc_intr, sc, &ih);
1578 printf("itjc%d: couldn't set up irq handler\n", unit);
1584 * Reset the ASIC & the ISAC.
1586 itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1588 DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1590 itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1591 TIGER_SELF_ADDR_DMA | TIGER_PIB_3_CYCLES);
1593 DELAY(SEC_DELAY/100); /* ... and more 10 to recover. */
1596 * First part of DMA initialization. Create & map the memory
1597 * pool that will be used to bear the rx & tx ring buffers.
1599 ctx->state = ITJC_DS_LOADING;
1601 error = bus_dma_tag_create(
1605 BUS_SPACE_MAXADDR_32BIT, /* lowaddr*/
1606 BUS_SPACE_MAXADDR, /* highaddr*/
1608 NULL, /* filterarg*/
1609 ITJC_DMA_POOL_BYTES, /* maxsize*/
1611 ITJC_DMA_POOL_BYTES, /* maxsegsz*/
1612 BUS_DMA_ALLOCNOW | BUS_DMAMEM_NOSYNC, /* flags*/
1617 printf("itjc%d: couldn't create bus DMA tag.\n", unit);
1623 error = bus_dmamem_alloc(
1624 ctx->tag, /* DMA tag */
1625 (void **)&ctx->pool, /* KV addr of the allocated memory */
1626 BUS_DMA_NOWAIT | BUS_DMAMEM_NOSYNC, /* flags */
1627 &ctx->map); /* KV <-> PCI map */
1633 * Load the KV <-> PCI map so the device sees the same
1634 * memory segment as pointed by pool. Note: since the
1635 * load may happen assyncronously (completion indicated by
1636 * the execution of the callback function) we have to
1637 * delay the initialization of the DMA engine to a moment we
1638 * actually have the proper bus addresses to feed the Tiger
1639 * and our DMA control blocks. This will be done in
1640 * itjc_bchannel_setup via a call to itjc_dma_start.
1643 ctx->tag, /* DMA tag */
1644 ctx->map, /* DMA map */
1645 ctx->pool, /* KV addr of buffer */
1646 ITJC_DMA_POOL_BYTES, /* buffer size */
1647 itjc_map_callback, /* this receive the bus addr/error */
1648 ctx, /* callback aux arg */
1654 * Setup the AUX port so we can talk to the ISAC.
1656 itjc_write_1(TIGER_AUX_PORT_CNTL, TIGER_AUX_NJ_DEFAULT);
1657 itjc_write_1(TIGER_INT1_MASK, TIGER_ISAC_INT);
1660 * From now on, almost like a `normal' ISIC driver.
1665 ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
1667 HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
1668 HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
1670 /* setup access routines */
1672 sc->clearirq = NULL;
1673 sc->readreg = itjc_read_reg;
1674 sc->writereg = itjc_write_reg;
1676 sc->readfifo = itjc_read_fifo;
1677 sc->writefifo = itjc_write_fifo;
1679 /* setup card type */
1681 sc->sc_cardtyp = CARD_TYPEP_NETJET_S;
1683 /* setup IOM bus type */
1685 sc->sc_bustyp = BUS_TYPE_IOM2;
1687 /* set up some other miscellaneous things */
1689 sc->sc_bfifolen = 2 * ITJC_RING_SLOT_WORDS;
1691 printf("itjc%d: ISAC 2186 Version 1.1 (IOM-2)\n", unit);
1696 /* init the "HSCX" */
1697 itjc_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
1699 itjc_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
1701 /* can't use the normal B-Channel stuff */
1702 itjc_init_linktab(sc);
1704 /* set trace level */
1706 sc->sc_trace = TRACE_OFF;
1708 sc->sc_state = ISAC_IDLE;
1717 sc->sc_freeflag = 0;
1719 sc->sc_obuf2 = NULL;
1720 sc->sc_freeflag2 = 0;
1722 #if defined(__FreeBSD__) && __FreeBSD__ >=3
1723 callout_handle_init(&sc->sc_T3_callout);
1724 callout_handle_init(&sc->sc_T4_callout);
1727 /* init higher protocol layers */
1729 i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_ATTACH,
1730 sc->sc_cardtyp, &itjc_l1mux_func);
1736 switch (res_init_level)
1739 bus_dmamap_unload(ctx->tag, ctx->map);
1743 bus_dmamem_free(ctx->tag, ctx->pool, ctx->map);
1744 bus_dmamap_destroy(ctx->tag, ctx->map);
1748 bus_dma_tag_destroy(ctx->tag);
1752 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
1756 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+0,
1757 sc->sc_resources.io_base[0]);
1763 itjc_scp[unit] = NULL;
1770 /*---------------------------------------------------------------------------*
1771 * itjc_intr - main interrupt service routine.
1772 *---------------------------------------------------------------------------*/
1774 itjc_intr(void *xsc)
1776 struct l1_softc *sc = xsc;
1777 l1_bchan_state_t *chan = &sc->sc_chan[0];
1778 dma_context_t *dma = &dma_context[sc->sc_unit];
1779 dma_rx_context_t *rxc = &dma_rx_context[sc->sc_unit][0];
1780 dma_tx_context_t *txc = &dma_tx_context[sc->sc_unit][0];
1784 /* Honor interrupts from successfully configured cards only. */
1785 if (dma->state < ITJC_DS_STOPPED)
1788 /* First, we check the ISAC... */
1789 if (! (itjc_read_1(TIGER_AUX_PORT_DATA) & TIGER_ISAC_INT_MASK))
1791 itjc_write_1(TIGER_INT1_STATUS, TIGER_ISAC_INT);
1792 NDBGL1(L1_H_IRQ, "ISAC");
1796 /* ... after what we always have a look at the DMA rings. */
1798 NDBGL1(L1_H_IRQ, "Tiger");
1800 itjc_read_1(TIGER_INT0_STATUS);
1801 itjc_write_1(TIGER_INT0_STATUS, TIGER_TARGET_ABORT_INT
1802 | TIGER_MASTER_ABORT_INT | TIGER_RD_END_INT
1803 | TIGER_RD_INT_INT | TIGER_WR_END_INT | TIGER_WR_INT_INT);
1805 itjc_dma_rx_intr(sc, chan, rxc);
1806 itjc_dma_tx_intr(sc, chan, txc);
1808 ++chan; ++rxc; ++txc;
1810 itjc_dma_rx_intr(sc, chan, rxc);
1811 itjc_dma_tx_intr(sc, chan, txc);
1815 /*---------------------------------------------------------------------------*
1816 * itjc_bchannel_setup - (Re)initialize and start/stop a Bchannel.
1817 *---------------------------------------------------------------------------*/
1819 itjc_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1822 struct l1_softc *sc = itjc_scp[unit];
1824 struct l1_softc *sc = isic_find_sc(unit);
1826 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1829 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1830 unit, h_chan, activate ? "activate" : "deactivate");
1833 * If we are deactivating the channel, we have to stop
1834 * the DMA before we reset the channel control structures.
1837 itjc_bchannel_dma_setup(sc, h_chan, activate);
1841 chan->state = HSCX_IDLE;
1843 chan->unit = sc->sc_unit; /* unit number */
1844 chan->channel = h_chan; /* B channel */
1845 chan->bprot = bprot; /* B channel protocol */
1849 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1851 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1853 chan->rxcount = 0; /* reset rx counter */
1855 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1857 chan->in_mbuf = NULL; /* reset mbuf ptr */
1858 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1859 chan->in_len = 0; /* reset mbuf data len */
1861 /* transmitter part */
1863 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1865 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1867 chan->txcount = 0; /* reset tx counter */
1869 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1871 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1872 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1873 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1874 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1877 * Only setup & start the DMA after all other channel
1878 * control structures are in place.
1881 itjc_bchannel_dma_setup(sc, h_chan, activate);
1887 /*---------------------------------------------------------------------------*
1888 * itjc_bchannel_start - Signal us we have more data to send.
1889 *---------------------------------------------------------------------------*/
1891 itjc_bchannel_start(int unit, int h_chan)
1895 * I disabled this routine because it was causing crashes when
1896 * this driver was used with the ISP (kernel SPPP) protocol driver.
1897 * The scenario is reproductible:
1898 * Use the -link1 (dial on demand) ifconfig option.
1899 * Start an interactive TCP connection to somewhere.
1900 * Wait until the PPP connection times out and is dropped.
1901 * Try to send something on the TCP connection.
1902 * The machine will print some garbage and halt or reboot
1903 * (no panic messages).
1905 * I've nailed down the problem to the fact that this routine
1906 * was being called before the B channel had been setup again.
1908 * For now, I don't have a good solution other than this one.
1909 * But, don't despair. The impact of it is unnoticeable.
1913 struct l1_softc *sc = itjc_scp[unit];
1915 struct l1_softc *sc = isic_find_sc(unit);
1917 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1921 dma_tx_context_t *txc = &dma_tx_context[unit][h_chan];
1923 if (chan->state & HSCX_TX_ACTIVE)
1929 itjc_dma_tx_intr(sc, chan, txc);
1936 /*---------------------------------------------------------------------------*
1937 * itjc_shutdown - Stop the driver and reset the card.
1938 *---------------------------------------------------------------------------*/
1940 itjc_shutdown(device_t dev)
1942 struct l1_softc *sc = device_get_softc(dev);
1947 * Stop the DMA the nice and easy way.
1949 itjc_bchannel_setup(sc->sc_unit, 0, BPROT_NONE, 0);
1950 itjc_bchannel_setup(sc->sc_unit, 1, BPROT_NONE, 0);
1955 itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1957 DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1959 itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1960 TIGER_SELF_ADDR_DMA | TIGER_LATCH_DMA_INT | TIGER_PIB_3_CYCLES);
1962 DELAY(SEC_DELAY/100); /* ... and more 10 to recover */
1966 /*---------------------------------------------------------------------------*
1967 * itjc_ret_linktab - Return the address of itjc drivers linktab.
1968 *---------------------------------------------------------------------------*/
1970 itjc_ret_linktab(int unit, int channel)
1973 struct l1_softc *sc = itjc_scp[unit];
1975 struct l1_softc *sc = isic_find_sc(unit);
1977 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1979 return(&chan->isic_isdn_linktab);
1982 /*---------------------------------------------------------------------------*
1983 * itjc_set_linktab - Set the driver linktab in the b channel softc.
1984 *---------------------------------------------------------------------------*/
1986 itjc_set_linktab(int unit, int channel, drvr_link_t *dlt)
1989 struct l1_softc *sc = itjc_scp[unit];
1991 struct l1_softc *sc = isic_find_sc(unit);
1993 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1995 chan->isic_drvr_linktab = dlt;
1999 /*---------------------------------------------------------------------------*
2000 * itjc_init_linktab - Initialize our local linktab.
2001 *---------------------------------------------------------------------------*/
2003 itjc_init_linktab(struct l1_softc *sc)
2005 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
2006 isdn_link_t *lt = &chan->isic_isdn_linktab;
2008 /* make sure the hardware driver is known to layer 4 */
2009 /* avoid overwriting if already set */
2010 if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
2012 ctrl_types[CTRL_PASSIVE].set_linktab = itjc_set_linktab;
2013 ctrl_types[CTRL_PASSIVE].get_linktab = itjc_ret_linktab;
2017 lt->unit = sc->sc_unit;
2018 lt->channel = HSCX_CH_A;
2019 lt->bch_config = itjc_bchannel_setup;
2020 lt->bch_tx_start = itjc_bchannel_start;
2021 lt->bch_stat = itjc_bchannel_stat;
2022 lt->tx_queue = &chan->tx_queue;
2024 /* used by non-HDLC data transfers, i.e. telephony drivers */
2025 lt->rx_queue = &chan->rx_queue;
2027 /* used by HDLC data transfers, i.e. ipr and isp drivers */
2028 lt->rx_mbuf = &chan->in_mbuf;
2030 chan = &sc->sc_chan[HSCX_CH_B];
2031 lt = &chan->isic_isdn_linktab;
2033 lt->unit = sc->sc_unit;
2034 lt->channel = HSCX_CH_B;
2035 lt->bch_config = itjc_bchannel_setup;
2036 lt->bch_tx_start = itjc_bchannel_start;
2037 lt->bch_stat = itjc_bchannel_stat;
2038 lt->tx_queue = &chan->tx_queue;
2040 /* used by non-HDLC data transfers, i.e. telephony drivers */
2041 lt->rx_queue = &chan->rx_queue;
2043 /* used by HDLC data transfers, i.e. ipr and isp drivers */
2044 lt->rx_mbuf = &chan->in_mbuf;
2048 /*---------------------------------------------------------------------------*
2049 * itjc_bchannel_stat - Collect link statistics for a given B channel.
2050 *---------------------------------------------------------------------------*/
2052 itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
2055 struct l1_softc *sc = itjc_scp[unit];
2057 struct l1_softc *sc = isic_find_sc(unit);
2059 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
2064 bsp->outbytes = chan->txcount;
2065 bsp->inbytes = chan->rxcount;
2074 /*---------------------------------------------------------------------------*
2075 * Netjet - ISAC interrupt routine.
2076 *---------------------------------------------------------------------------*/
2078 itjc_isac_intr(struct l1_softc *sc)
2080 register u_char irq_stat;
2084 /* get isac irq status */
2085 irq_stat = ISAC_READ(I_ISTA);
2088 itjc_isac_irq(sc, irq_stat); /* isac handler */
2092 ISAC_WRITE(I_MASK, 0xff);
2096 ISAC_WRITE(I_MASK, ISAC_IMASK);
2100 /*---------------------------------------------------------------------------*
2101 * itjc_recover - Try to recover from ISAC irq lockup.
2102 *---------------------------------------------------------------------------*/
2104 itjc_recover(struct l1_softc *sc)
2108 /* get isac irq status */
2110 byte = ISAC_READ(I_ISTA);
2112 NDBGL1(L1_ERROR, " ISAC: ISTA = 0x%x", byte);
2114 if(byte & ISAC_ISTA_EXI)
2115 NDBGL1(L1_ERROR, " ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
2117 if(byte & ISAC_ISTA_CISQ)
2119 byte = ISAC_READ(I_CIRR);
2121 NDBGL1(L1_ERROR, " ISAC: CISQ = 0x%x", byte);
2123 if(byte & ISAC_CIRR_SQC)
2124 NDBGL1(L1_ERROR, " ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
2127 NDBGL1(L1_ERROR, " ISAC: IMASK = 0x%x", ISAC_IMASK);
2129 ISAC_WRITE(I_MASK, 0xff);
2131 ISAC_WRITE(I_MASK, ISAC_IMASK);
2134 #endif /* NITJC > 0 */