Initial import from FreeBSD RELENG_4:
[dragonfly.git] / sys / net / i4b / layer1 / itjc / i4b_itjc_pci.c
1 /*
2  *   Copyright (c) 2000, 2001 Sergio Prallon. All rights reserved.
3  *
4  *   Redistribution and use in source and binary forms, with or without
5  *   modification, are permitted provided that the following conditions
6  *   are met:
7  *
8  *   1. Redistributions of source code must retain the above copyright
9  *      notice, this list of conditions and the following disclaimer.
10  *   2. Redistributions in binary form must reproduce the above copyright
11  *      notice, this list of conditions and the following disclaimer in the
12  *      documentation and/or other materials provided with the distribution.
13  *   3. Neither the name of the author nor the names of any co-contributors
14  *      may be used to endorse or promote products derived from this software
15  *      without specific prior written permission.
16  *   4. Altered versions must be plainly marked as such, and must not be
17  *      misrepresented as being the original software and/or documentation.
18  *   
19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  *   SUCH DAMAGE.
30  *
31  *---------------------------------------------------------------------------
32  *
33  *      i4b_itjc_pci.c: NetJet-S hardware driver
34  *      ----------------------------------------
35  *
36  * $FreeBSD: src/sys/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.1.2.1 2001/08/10 14:08:39 obrien Exp $
37  *
38  *      last edit-date: [Thu Jan 11 11:29:38 2001]
39  *
40  *---------------------------------------------------------------------------*/
41
42 #include "itjc.h"
43 #include "opt_i4b.h"
44 #include "pci.h"
45
46 #if (NITJC > 0)
47
48 #include <sys/param.h>
49 #include <sys/kernel.h>
50 #include <sys/systm.h>
51 #include <sys/mbuf.h>
52
53 #include <machine/clock.h>
54 #include <machine/bus_pio.h>
55 #include <machine/bus.h>
56 #include <machine/resource.h>
57 #include <sys/bus.h>
58 #include <sys/rman.h>
59
60 #include <pci/pcireg.h>
61 #include <pci/pcivar.h>
62
63 #include <sys/socket.h>
64 #include <net/if.h>
65
66 #include <machine/i4b_debug.h>
67 #include <machine/i4b_ioctl.h>
68 #include <machine/i4b_trace.h>
69
70 #include <i4b/include/i4b_global.h>
71 #include <i4b/include/i4b_mbuf.h>
72
73 #include <i4b/layer1/i4b_l1.h>
74
75 #include <i4b/layer1/itjc/i4b_hdlc.h>   /* XXXXXXXXXXXXXXXXXXXXXXXX */
76
77 #include <i4b/layer1/isic/i4b_isic.h>
78 #include <i4b/layer1/isic/i4b_isac.h>
79
80 #include <i4b/layer1/itjc/i4b_itjc_ext.h>
81
82 #define PCI_TJNET_VID (0xe159)
83 #define PCI_TJ300_DID (0x0001)
84
85
86 /*
87  * Function prototypes
88  */
89
90 static int  itjc_probe(device_t dev);
91 static int  itjc_attach(device_t dev);
92 static void itjc_shutdown(device_t dev);
93 static void itjc_intr(void *xsc);
94 static int  itjc_dma_start(struct l1_softc *sc);
95 static void itjc_dma_stop(struct l1_softc *sc);
96 static void itjc_isac_intr(struct l1_softc *sc);
97 static void itjc_init_linktab(struct l1_softc *sc);
98 static void itjc_bchannel_setup(int unit, int h_chan, int bprot, 
99         int activate);
100 static void itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp);
101
102
103 /*
104  * Shorter names to bus resource manager routines.
105  */
106
107 #define itjc_bus_setup(sc)                                              \
108         bus_space_handle_t h =                                          \
109                 rman_get_bushandle((sc)->sc_resources.io_base[0]);      \
110         bus_space_tag_t    t =                                          \
111                 rman_get_bustag((sc)->sc_resources.io_base[0]);
112
113 #define itjc_read_1(port)       (bus_space_read_1(t, h, (port)))
114 #define itjc_read_4(port)       (bus_space_read_4(t, h, (port)))
115 #define itjc_write_1(port, data) (bus_space_write_1(t, h, (port), (data)))
116 #define itjc_write_4(port, data) (bus_space_write_4(t, h, (port), (data)))
117 #define itjc_read_multi_1(port, buf, size)                              \
118         (bus_space_read_multi_1(t, h, (port), (buf), (size)))
119 #define itjc_write_multi_1(port, buf, size)                             \
120         (bus_space_write_multi_1(t, h, (port), (buf), (size)))
121
122
123 /*---------------------------------------------------------------------------*
124  *      Glue data to register ourselves as a PCI device driver.
125  *---------------------------------------------------------------------------*/
126
127 static device_method_t itjc_pci_methods[] =
128 {
129         /* Device interface */
130         DEVMETHOD(device_probe,         itjc_probe),
131         DEVMETHOD(device_attach,        itjc_attach),
132         DEVMETHOD(device_shutdown,      itjc_shutdown),
133
134         /* bus interface */
135         DEVMETHOD(bus_print_child,      bus_generic_print_child),
136         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
137
138         { 0, 0 }
139 };
140
141 static driver_t itjc_pci_driver =
142 {
143         "itjc",
144         itjc_pci_methods,
145         sizeof(struct l1_softc)
146 };
147
148 static devclass_t itjc_pci_devclass;
149
150 DRIVER_MODULE(netjet, pci, itjc_pci_driver, itjc_pci_devclass, 0, 0);
151
152 /*
153  * Jump table for multiplex routines.
154  */
155
156 struct i4b_l1mux_func itjc_l1mux_func =
157 {
158         itjc_ret_linktab,
159         itjc_set_linktab,
160         itjc_mph_command_req,
161         itjc_ph_data_req,
162         itjc_ph_activate_req,
163 };
164
165 struct l1_softc *itjc_scp[ITJC_MAXUNIT];
166
167
168 /*---------------------------------------------------------------------------*
169  *      Tiger300/320 PCI ASIC registers.
170  *---------------------------------------------------------------------------*/
171
172 /*
173  *      Register offsets from i/o base.
174  */
175 enum tiger_regs
176 {
177         TIGER_RESET_PIB_CL_TIME = 0x00,
178         TIGER_DMA_OPER          = 0x01,
179         TIGER_AUX_PORT_CNTL     = 0x02,
180         TIGER_AUX_PORT_DATA     = 0x03,
181         TIGER_INT0_MASK         = 0x04,
182         TIGER_INT1_MASK         = 0x05,
183         TIGER_INT0_STATUS       = 0x06,
184         TIGER_INT1_STATUS       = 0x07,
185         TIGER_DMA_WR_START_ADDR = 0x08,
186         TIGER_DMA_WR_INT_ADDR   = 0x0C,
187         TIGER_DMA_WR_END_ADDR   = 0x10,
188         TIGER_DMA_WR_CURR_ADDR  = 0x14,
189         TIGER_DMA_RD_START_ADDR = 0x18,
190         TIGER_DMA_RD_INT_ADDR   = 0x1C,
191         TIGER_DMA_RD_END_ADDR   = 0x20,
192         TIGER_DMA_RD_CURR_ADDR  = 0x24,
193         TIGER_PULSE_COUNTER     = 0x28,
194 };
195
196 /*
197  * Bits on the above registers.
198  */
199
200 enum tiger_reg_bits
201 {
202 /* Reset and PIB Cycle Timing */
203
204         TIGER_DMA_OP_MODE_MASK          = 0x80,
205                 TIGER_SELF_ADDR_DMA     = 0x00, /* Wrap around ending addr */
206                 TIGER_NORMAL_DMA        = 0x80, /* Stop at ending addr */
207
208         TIGER_DMA_INT_MODE_MASK         = 0x40,
209                 TIGER_DONT_LATCH_DMA_INT= 0x00, /* Bits on int0 status will be
210                                                    set only while curr addr
211                                                    equals int or end addr */
212                 TIGER_LATCH_DMA_INT     = 0x40, /* Bits on int0 status remain
213                                                    set until cleared by CPU */
214
215         TIGER_PIB_CYCLE_TIMING_MASK     = 0x30,
216                 TIGER_PIB_3_CYCLES      = 0x00,
217                 TIGER_PIB_5_CYCLES      = 0x01,
218                 TIGER_PIB_12_CYCLES     = 0x10,
219
220         TIGER_RESET_MASK                = 0x0F,
221                 TIGER_RESET_PULSE_COUNT = 0x08,
222                 TIGER_RESET_SERIAL_PORT = 0x04,
223                 TIGER_RESET_DMA_LOGIC   = 0x02,
224                 TIGER_RESET_EXTERNAL    = 0x01,
225                 TIGER_RESET_ALL         = 0x0F,
226         
227 /* DMA Operation */
228         TIGER_DMA_RESTART_MASK          = 0x02,
229                 TIGER_HOLD_DMA          = 0x00,
230                 TIGER_RESTART_DMA       = 0x00,
231
232         TIGER_DMA_ENABLE_MASK           = 0x01,
233                 TIGER_ENABLE_DMA        = 0x01,
234                 TIGER_DISABLE_DMA       = 0x00,
235
236 /* AUX Port Control & Data plus Interrupt 1 Mask & Status  */
237         TIGER_AUX_7_MASK                = 0x80,
238         TIGER_AUX_6_MASK                = 0x40,
239         TIGER_AUX_5_MASK                = 0x20,
240         TIGER_AUX_4_MASK                = 0x10,
241         TIGER_ISAC_INT_MASK             = 0x10,
242         TIGER_AUX_3_MASK                = 0x08,
243         TIGER_AUX_2_MASK                = 0x04,
244         TIGER_AUX_1_MASK                = 0x02,
245         TIGER_AUX_0_MASK                = 0x01,
246
247 /* AUX Port Control */
248                 TIGER_AUX_7_IS_INPUT    = 0x00,
249                 TIGER_AUX_7_IS_OUTPUT   = 0x80,
250                 TIGER_AUX_6_IS_INPUT    = 0x00,
251                 TIGER_AUX_6_IS_OUTPUT   = 0x40,
252                 TIGER_AUX_5_IS_INPUT    = 0x00,
253                 TIGER_AUX_5_IS_OUTPUT   = 0x20,
254                 TIGER_AUX_4_IS_INPUT    = 0x00,
255                 TIGER_AUX_4_IS_OUTPUT   = 0x10,
256                 TIGER_AUX_3_IS_INPUT    = 0x00,
257                 TIGER_AUX_3_IS_OUTPUT   = 0x80,
258                 TIGER_AUX_2_IS_INPUT    = 0x00,
259                 TIGER_AUX_2_IS_OUTPUT   = 0x40,
260                 TIGER_AUX_1_IS_INPUT    = 0x00,
261                 TIGER_AUX_1_IS_OUTPUT   = 0x20,
262                 TIGER_AUX_0_IS_INPUT    = 0x00,
263                 TIGER_AUX_0_IS_OUTPUT   = 0x10,
264                 TIGER_AUX_NJ_DEFAULT    = 0xEF, /* All but ISAC int is output */
265
266 /* Interrupt 0 Mask & Status */
267         TIGER_PCI_TARGET_ABORT_INT_MASK = 0x20,
268                 TIGER_NO_TGT_ABORT_INT  = 0x00,
269                 TIGER_TARGET_ABORT_INT  = 0x20,
270         TIGER_PCI_MASTER_ABORT_INT_MASK = 0x10,
271                 TIGER_NO_MST_ABORT_INT  = 0x00,
272                 TIGER_MASTER_ABORT_INT  = 0x10,
273         TIGER_DMA_RD_END_INT_MASK       = 0x08,
274                 TIGER_NO_RD_END_INT     = 0x00,
275                 TIGER_RD_END_INT        = 0x08,
276         TIGER_DMA_RD_INT_INT_MASK       = 0x04,
277                 TIGER_NO_RD_INT_INT     = 0x00,
278                 TIGER_RD_INT_INT        = 0x04,
279         TIGER_DMA_WR_END_INT_MASK       = 0x02,
280                 TIGER_NO_WR_END_INT     = 0x00,
281                 TIGER_WR_END_INT        = 0x02,
282         TIGER_DMA_WR_INT_INT_MASK       = 0x01,
283                 TIGER_NO_WR_INT_INT     = 0x00,
284                 TIGER_WR_INT_INT        = 0x01,
285
286 /* Interrupt 1 Mask & Status */
287                 TIGER_NO_AUX_7_INT      = 0x00,
288                 TIGER_AUX_7_INT         = 0x80,
289                 TIGER_NO_AUX_6_INT      = 0x00,
290                 TIGER_AUX_6_INT         = 0x40,
291                 TIGER_NO_AUX_5_INT      = 0x00,
292                 TIGER_AUX_5_INT         = 0x20,
293                 TIGER_NO_AUX_4_INT      = 0x00,
294                 TIGER_AUX_4_INT         = 0x10,
295                 TIGER_NO_ISAC_INT       = 0x00,
296                 TIGER_ISAC_INT          = 0x10,
297                 TIGER_NO_AUX_3_INT      = 0x00,
298                 TIGER_AUX_3_INT         = 0x08,
299                 TIGER_NO_AUX_2_INT      = 0x00,
300                 TIGER_AUX_2_INT         = 0x04,
301                 TIGER_NO_AUX_1_INT      = 0x00,
302                 TIGER_AUX_1_INT         = 0x02,
303                 TIGER_NO_AUX_0_INT      = 0x00,
304                 TIGER_AUX_0_INT         = 0x01
305 };
306
307 /*
308  * Peripheral Interface Bus definitions. This is an ISA like bus
309  * created by the Tiger ASIC to keep ISA chips like the ISAC happy
310  * on a PCI environment.
311  *
312  * Since the PIB only supplies 4 addressing lines, the 2 higher bits
313  * (A4 & A5) of the ISAC register addresses are wired on the 2 lower
314  * AUX lines. Another restriction is that all I/O to the PIB (8bit
315  * wide) is mapped on the PCI side as 32bit data. So the PCI address
316  * of a given ISAC register has to be multiplied by 4 before being
317  * added to the PIB base offset.
318  */
319 enum tiger_pib_regs_defs
320 {
321         /* Offset from the I/O base to the ISAC registers. */
322         PIB_OFFSET              = 0xC0,
323         PIB_LO_ADDR_MASK        = 0x0F,         
324         PIB_HI_ADDR_MASK        = 0x30,
325         PIB_LO_ADDR_SHIFT       = 2,    /* Align on dword boundary */
326         PIB_HI_ADDR_SHIFT       = 4     /* Right shift to AUX_1 & AUX_0 */
327 };
328
329
330 #define itjc_set_pib_addr_msb(a)                                        \
331 (                                                                       \
332         itjc_write_1(TIGER_AUX_PORT_DATA,                               \
333                 ((a) & PIB_HI_ADDR_MASK) >> PIB_HI_ADDR_SHIFT)          \
334 )
335
336 #define itjc_pib_2_pci(a)                                               \
337 (                                                                       \
338         (((a) & PIB_LO_ADDR_MASK) << PIB_LO_ADDR_SHIFT) + PIB_OFFSET    \
339 )
340
341 #define itjc_get_dma_offset(ctx,reg)                                    \
342 (                                                                       \
343         (u_int16_t)((bus_addr_t)itjc_read_4((reg)) - (ctx)->bus_addr)   \
344 )
345
346
347 /*
348  * IOM-2 serial channel 0 DMA data ring buffers.
349  *
350  * The Tiger300/320 ASIC do not nothing more than transfer via DMA the
351  * first 32 bits of every IOM-2 frame on the serial interface to the
352  * ISAC. So we have no framing/deframing facilities like we would have
353  * with an HSCX, having to do the job with CPU cycles. On the plus side
354  * we are able to specify large rings which can limit the occurrence of
355  * over/underruns.
356  */
357
358 enum
359 {
360         ITJC_RING_SLOT_WORDS    = 64,
361         ITJC_RING_WORDS         = 3 * ITJC_RING_SLOT_WORDS,
362         ITJC_RING_SLOT_BYTES    = 4 * ITJC_RING_SLOT_WORDS,
363         ITJC_RING_BYTES         = 4 * ITJC_RING_WORDS,
364         ITJC_DMA_POOL_WORDS     = 2 * ITJC_RING_WORDS,
365         ITJC_DMA_POOL_BYTES     = 4 * ITJC_DMA_POOL_WORDS
366 };
367
368 #define itjc_ring_add(x, d)     (((x) + 4 * (d)) % ITJC_RING_BYTES)
369 #define itjc_ring_sub(x, d)     (((x) + ITJC_RING_BYTES - 4 * (d))      \
370                                         % ITJC_RING_BYTES)
371
372
373 enum
374 {
375         TIGER_CH_A              = 0,
376         TIGER_CH_B              = 1,
377
378         HSCX_CH_A               = 0,    /* For compatibility reasons. */
379         HSCX_CH_B               = 1,
380 };
381
382 enum
383 {
384         ITJC_TEL_SILENCE_BYTE   = 0x00,
385         ITJC_HDLC_FLAG_BYTE     = 0x7E,
386         ITJC_HDLC_ABORT_BYTE    = 0xFF
387 };
388
389 /*
390  * Hardware DMA control block (one per card).
391  */
392 typedef enum
393 {
394         ITJC_DS_LOAD_FAILED     = -1,
395         ITJC_DS_FREE            =  0,
396         ITJC_DS_LOADING,
397         ITJC_DS_STOPPED,
398         ITJC_DS_RUNNING
399 }
400         dma_state_t;
401
402 typedef struct
403 {
404         dma_state_t     state;
405         u_int8_t        *pool;
406         bus_addr_t      bus_addr;
407         bus_dma_tag_t   tag;
408         bus_dmamap_t    map;
409         int             error;
410 }
411         dma_context_t;
412
413 dma_context_t
414         dma_context     [ ITJC_MAXUNIT ];
415
416 /*
417  * B-channel DMA control blocks (4 per card -- 1 RX & 1 TX per channel).
418  */
419 typedef enum
420 {
421         ITJC_RS_IDLE    = 0,
422         ITJC_RS_ACTIVE
423 }
424         dma_rx_state_t;
425
426 typedef enum
427 {
428         ITJC_TS_IDLE    = 0,
429         ITJC_TS_ACTIVE,
430         ITJC_TS_AFTER_XDU
431 }
432         dma_tx_state_t;
433
434 typedef struct
435 {
436         u_int8_t        *ring;
437         bus_addr_t      bus_addr;
438         u_int16_t       next_read;
439         u_int16_t       hdlc_len;
440         u_int16_t       hdlc_tmp;
441         u_int16_t       hdlc_crc;
442         u_int16_t       hdlc_ib;
443         u_int8_t        hdlc_blevel;
444         u_int8_t        hdlc_flag;
445         dma_rx_state_t  state;
446 }
447         dma_rx_context_t;
448
449 typedef struct
450 {
451         u_int8_t        *ring;
452         bus_addr_t      bus_addr;
453         u_int16_t       next_write;
454         u_int32_t       hdlc_tmp;
455         u_int16_t       hdlc_blevel;
456         u_int16_t       hdlc_crc;
457         u_int16_t       hdlc_ib;
458         u_int16_t       next_frame;
459         u_int16_t       filled;
460         u_int8_t        hdlc_flag;
461         dma_tx_state_t  state;
462 }
463         dma_tx_context_t;
464
465 dma_rx_context_t
466         dma_rx_context  [ ITJC_MAXUNIT ] [ 2 ];
467
468 dma_tx_context_t
469         dma_tx_context  [ ITJC_MAXUNIT ] [ 2 ];
470
471 /*
472  * Used by the mbuf handling functions.
473  */
474 typedef enum
475 {
476         ITJC_MB_CURR = 0,
477         ITJC_MB_NEXT = 1,
478         ITJC_MB_NEW  = 2
479 }
480         which_mb_t;
481
482
483 /*---------------------------------------------------------------------------*
484  *      itjc_map_callback - get DMA bus address from resource mgr.
485  *---------------------------------------------------------------------------*/
486 static void
487 itjc_map_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
488 {
489         dma_context_t           *ctx = (dma_context_t *)arg;
490
491         if (error)
492         {
493                 ctx->error = error;
494                 ctx->state = ITJC_DS_LOAD_FAILED;
495                 return;
496         }
497
498         ctx->bus_addr = segs->ds_addr;
499         ctx->state = ITJC_DS_STOPPED;
500 }
501
502
503 /*---------------------------------------------------------------------------*
504  *      itjc_dma_start - Complete DMA setup & start the Tiger DMA engine.
505  *---------------------------------------------------------------------------*/
506 static int
507 itjc_dma_start(struct l1_softc *sc)
508 {
509         int                     unit    = sc->sc_unit;
510         dma_context_t           *ctx    = &dma_context[unit];
511         dma_rx_context_t        *rxc    = &dma_rx_context[unit][0];
512         dma_tx_context_t        *txc    = &dma_tx_context[unit][0];
513         bus_addr_t              ba;
514         u_int8_t                i;
515         u_int32_t               *pool_end,
516                                 *ip;
517
518         itjc_bus_setup(sc);
519
520         /* See if it is already running. */
521
522         if (ctx->state == ITJC_DS_RUNNING)
523                 return 0;
524
525         if (ctx->state == ITJC_DS_LOAD_FAILED)
526         {
527                 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA map loading "
528                         "failed (error=%d).\n", unit, ctx->error);
529                 return 1;
530         }
531
532         if (ctx->state != ITJC_DS_STOPPED)
533         {
534                 NDBGL1(L1_ERROR, "itjc%d: dma_start: Unexpected DMA "
535                         "state (%d).\n", unit, ctx->state);
536                 return 1;
537         }
538
539         /*
540          * Initialize the DMA control structures (hardware & B-channel).
541          */
542         ba = ctx->bus_addr;
543
544         txc->ring = ctx->pool + TIGER_CH_A;
545         rxc->ring = ctx->pool + TIGER_CH_A + ITJC_RING_BYTES;
546
547         txc->bus_addr = ba;
548         rxc->bus_addr = ba + ITJC_RING_BYTES;
549
550         ++rxc; ++txc;
551
552         txc->ring = ctx->pool + TIGER_CH_B;
553         rxc->ring = ctx->pool + TIGER_CH_B + ITJC_RING_BYTES;
554
555         txc->bus_addr = ba;
556         rxc->bus_addr = ba + ITJC_RING_BYTES;
557
558         /*
559          * Fill the DMA ring buffers with IOM-2 channel 0 frames made of
560          * idle/abort sequences for the B & D channels and NOP for IOM-2
561          * cmd/ind, monitor handshake & data.
562          */
563         pool_end = (u_int32_t *)ctx->pool + ITJC_DMA_POOL_WORDS;
564         for (ip = (u_int32_t *)ctx->pool; ip < pool_end; ++ip)
565                 *ip = 0xFFFFFFFF;
566
567         /*
568          * Program the Tiger DMA gears.
569          */
570
571         itjc_write_4(TIGER_DMA_WR_START_ADDR, ba);
572         itjc_write_4(TIGER_DMA_WR_INT_ADDR, ba + ITJC_RING_SLOT_BYTES - 4);
573         itjc_write_4(TIGER_DMA_WR_END_ADDR, ba + ITJC_RING_BYTES - 4);
574
575         ba += ITJC_RING_BYTES;
576
577         itjc_write_4(TIGER_DMA_RD_START_ADDR, ba);
578         itjc_write_4(TIGER_DMA_RD_INT_ADDR, ba + ITJC_RING_SLOT_BYTES * 2 - 4);
579         itjc_write_4(TIGER_DMA_RD_END_ADDR, ba + ITJC_RING_BYTES - 4);
580
581         itjc_write_1(TIGER_INT0_MASK, 
582                 TIGER_WR_END_INT | TIGER_WR_INT_INT | TIGER_RD_INT_INT);
583
584         itjc_write_1(TIGER_DMA_OPER, TIGER_ENABLE_DMA);
585
586         /*
587          * See if it really started.
588          */
589         ba = itjc_read_4(TIGER_DMA_RD_CURR_ADDR);
590         for (i = 0; i < 10; ++i)
591         {
592                 DELAY(SEC_DELAY/1000);
593                 if (ba != itjc_read_4(TIGER_DMA_RD_CURR_ADDR))
594                 {
595                         ctx->state = ITJC_DS_RUNNING;
596                         return 0;
597                 }
598         }
599
600         NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA start failed.\n ", unit);
601         return 1;
602 }
603
604
605 /*---------------------------------------------------------------------------*
606  *      itjc_dma_stop - Stop the Tiger DMA engine.
607  *---------------------------------------------------------------------------*/
608 void
609 itjc_dma_stop(struct l1_softc *sc)
610 {
611         dma_context_t           *ctx    = &dma_context[sc->sc_unit];
612
613         itjc_bus_setup(sc);
614
615         /* Only stop the DMA if it is running. */
616
617         if (ctx->state != ITJC_DS_RUNNING)
618                 return;
619
620         itjc_write_1(TIGER_DMA_OPER, TIGER_DISABLE_DMA);
621         DELAY(SEC_DELAY/1000);
622
623         ctx->state = ITJC_DS_STOPPED;
624 }
625
626
627 /*---------------------------------------------------------------------------*
628  *      itjc_bchannel_dma_setup - The DMA side of itjc_bchannel_setup.
629  *---------------------------------------------------------------------------*/
630 static void
631 itjc_bchannel_dma_setup(struct l1_softc *sc, int h_chan, int activate)
632 {
633         dma_rx_context_t        *rxc  = &dma_rx_context[sc->sc_unit][h_chan];
634         dma_tx_context_t        *txc  = &dma_tx_context[sc->sc_unit][h_chan];
635
636         l1_bchan_state_t        *chan = &sc->sc_chan[h_chan];
637
638         u_int8_t                fill_byte,
639                                 *ring_end,
640                                 *cp;
641
642         int                     s = SPLI4B();
643
644         itjc_bus_setup(sc);
645
646         if (activate)
647         {
648                 /*
649                  * Get the DMA engine going if it's not running already.
650                  */
651                 itjc_dma_start(sc);
652
653                 rxc->hdlc_len   = rxc->hdlc_tmp    = rxc->hdlc_crc  = 0;
654                 rxc->hdlc_ib    = rxc->hdlc_blevel = rxc->hdlc_flag = 0;
655
656                 txc->hdlc_tmp   = txc->hdlc_blevel = txc->hdlc_crc  = 0;
657                 txc->hdlc_ib    = 0;
658                 txc->hdlc_flag  = 2;
659                 txc->filled     = 0;
660
661                 if (chan->bprot == BPROT_NONE)
662                         fill_byte = ITJC_TEL_SILENCE_BYTE;
663                 else
664                         fill_byte = ITJC_HDLC_ABORT_BYTE;
665
666                 ring_end = rxc->ring + ITJC_RING_BYTES;
667                 for (cp = rxc->ring; cp < ring_end; cp += 4)
668                         *cp = fill_byte;
669
670                 ring_end = txc->ring + ITJC_RING_BYTES;
671                 for (cp = txc->ring; cp < ring_end; cp += 4)
672                         *cp = fill_byte;
673
674                 rxc->next_read  =
675                         itjc_get_dma_offset(rxc, TIGER_DMA_RD_CURR_ADDR);
676
677                 txc->next_frame = txc->next_write =
678                         itjc_get_dma_offset(txc, TIGER_DMA_WR_CURR_ADDR);
679
680                 rxc->state      = ITJC_RS_ACTIVE;
681                 txc->state      = ITJC_TS_AFTER_XDU;
682         }
683         else
684         {
685                 dma_rx_context_t        *rxc2;
686
687                 txc->state      = ITJC_TS_IDLE;
688                 rxc->state      = ITJC_RS_IDLE;
689
690                 rxc2 = &dma_rx_context[sc->sc_unit][0];
691
692                 if (rxc2->state == ITJC_RS_IDLE 
693                 && rxc2[1].state == ITJC_RS_IDLE)
694                         itjc_dma_stop(sc);
695         }
696
697         splx(s);
698 }
699
700
701 /*---------------------------------------------------------------------------*
702  *      Mbuf & if_queues management routines.
703  *---------------------------------------------------------------------------*/
704
705 static u_int8_t *
706 itjc_get_rx_mbuf(l1_bchan_state_t *chan, u_int8_t **dst_end_p,
707 which_mb_t which)
708 {
709         struct mbuf     *mbuf = chan->in_mbuf;
710
711         if (mbuf == NULL && which == ITJC_MB_NEW)
712         {
713                 if ((mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
714                         panic("itjc_get_rx_mbuf: cannot allocate mbuf!");
715
716                 chan->in_mbuf  = mbuf;
717                 chan->in_cbptr = (u_int8_t *)mbuf->m_data;
718                 chan->in_len   = 0;
719         }
720
721         if (dst_end_p != NULL)
722         {
723                 if (mbuf != NULL)
724                         *dst_end_p = (u_int8_t *)(mbuf->m_data)
725                                 + BCH_MAX_DATALEN;
726                 else
727                         *dst_end_p = NULL;
728         }
729
730         return chan->in_cbptr;
731 }
732
733
734 static void
735 itjc_save_rx_mbuf(l1_bchan_state_t *chan, u_int8_t * dst)
736 {
737         struct mbuf     *mbuf = chan->in_mbuf;
738
739         if (dst != NULL && mbuf != NULL)
740         {
741                 chan->in_cbptr = dst;
742                 chan->in_len   = dst - (u_int8_t *)mbuf->m_data;
743         }
744         else if (dst == NULL && mbuf == NULL)
745         {
746                 chan->in_cbptr = NULL;
747                 chan->in_len   = 0;
748         }
749         else
750                 panic("itjc_save_rx_mbuf: stale pointer dst=%p mbuf=%p "
751                         "in_cbptr=%p in_len=%d", dst, mbuf, 
752                         chan->in_cbptr, chan->in_len);
753 }
754
755
756 static void
757 itjc_free_rx_mbuf(l1_bchan_state_t *chan)
758 {
759         struct mbuf     *mbuf = chan->in_mbuf;
760
761         if (mbuf != NULL)
762                 i4b_Bfreembuf(mbuf);
763
764         chan->in_mbuf  = NULL;
765         chan->in_cbptr = NULL;
766         chan->in_len   = 0;
767 }
768
769
770 static void
771 itjc_put_rx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan, u_int16_t len)
772 {
773         i4b_trace_hdr_t hdr;
774         struct mbuf     *mbuf    = chan->in_mbuf;
775         u_int8_t        *data    = mbuf->m_data;
776         int             activity = 1;
777
778         mbuf->m_pkthdr.len = mbuf->m_len = len;
779
780         if (sc->sc_trace & TRACE_B_RX)
781         {
782                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
783                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
784                 hdr.dir = FROM_NT;
785                 hdr.count = ++sc->sc_trace_bcount;
786                 MICROTIME(hdr.time);
787                 i4b_l1_trace_ind(&hdr, len, data);
788         }
789
790         if (chan->bprot == BPROT_NONE)
791         {
792                 activity = ! i4b_l1_bchan_tel_silence(data, len);
793                                 
794                 /* move rx'd data to rx queue */
795
796                 if (! _IF_QFULL(&chan->rx_queue))
797                 {
798                         IF_ENQUEUE(&chan->rx_queue, mbuf);
799                 }
800                 else
801                 {
802                         i4b_Bfreembuf(mbuf);
803                         len = 0;
804                 }
805         }
806
807         if (len != 0)
808         {
809                 chan->rxcount += len;
810
811                 (*chan->isic_drvr_linktab->bch_rx_data_ready)
812                         (chan->isic_drvr_linktab->unit);
813         }
814                                 
815         if (activity)
816                 (*chan->isic_drvr_linktab->bch_activity)
817                         (chan->isic_drvr_linktab->unit, ACT_RX);
818
819         chan->in_mbuf  = NULL;
820         chan->in_cbptr = NULL;
821         chan->in_len   = 0;
822 }
823
824
825 #define itjc_free_tx_mbufs(chan)                                        \
826 {                                                                       \
827         i4b_Bfreembuf((chan)->out_mbuf_head);                           \
828         (chan)->out_mbuf_cur = (chan)->out_mbuf_head = NULL;            \
829         (chan)->out_mbuf_cur_ptr = NULL;                                \
830         (chan)->out_mbuf_cur_len = 0;                                   \
831 }
832
833
834 static u_int16_t
835 itjc_get_tx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan,
836         u_int8_t **src_p, which_mb_t which)
837 {
838         i4b_trace_hdr_t hdr;
839         struct mbuf     *mbuf = chan->out_mbuf_cur;
840         u_int8_t        activity = 1;
841         u_int16_t       len;
842         void            *data;
843
844         switch (which)
845         {
846         case ITJC_MB_CURR:
847                 if (mbuf != NULL)
848                 {
849                         *src_p = chan->out_mbuf_cur_ptr;
850                         return   chan->out_mbuf_cur_len;
851                 }
852
853                 break;
854
855         case ITJC_MB_NEXT:
856                 if (mbuf != NULL)
857                 {
858                         chan->txcount += mbuf->m_len;
859
860                         mbuf = mbuf->m_next;
861
862                         if (mbuf != NULL)
863                                 goto new_mbuf;
864                 }
865
866                 chan->out_mbuf_cur_ptr = *src_p = NULL;
867                 chan->out_mbuf_cur_len = 0;
868
869                 if (chan->out_mbuf_head != NULL)
870                 {
871                         i4b_Bfreembuf(chan->out_mbuf_head);
872                         chan->out_mbuf_head = NULL;
873                 }
874
875                 return 0;
876
877         case ITJC_MB_NEW:
878                 if (mbuf != NULL)
879                         chan->txcount += mbuf->m_len;
880         }
881
882         if (chan->out_mbuf_head != NULL)
883                 i4b_Bfreembuf(chan->out_mbuf_head);
884
885         IF_DEQUEUE(&chan->tx_queue, mbuf);
886
887         if (mbuf == NULL)
888         {
889                 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
890                 chan->out_mbuf_cur_ptr = *src_p = NULL;
891                 chan->out_mbuf_cur_len = 0;
892
893                 chan->state &= ~(HSCX_TX_ACTIVE);
894
895                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)
896                         (chan->isic_drvr_linktab->unit);
897
898                 return 0;
899         }
900
901         chan->out_mbuf_head = mbuf;
902
903 new_mbuf:
904         chan->out_mbuf_cur      = mbuf;
905         chan->out_mbuf_cur_ptr  = data = mbuf->m_data;
906         chan->out_mbuf_cur_len  = len  = mbuf->m_len;
907
908         chan->state |= HSCX_TX_ACTIVE;
909
910         if (sc->sc_trace & TRACE_B_TX)
911         {
912                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
913                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
914                 hdr.dir = FROM_TE;
915                 hdr.count = ++sc->sc_trace_bcount;
916                 MICROTIME(hdr.time);
917                 i4b_l1_trace_ind(&hdr, len, data);
918         }
919
920         if (chan->bprot == BPROT_NONE)
921                 activity = ! i4b_l1_bchan_tel_silence(data, len);
922
923         if (activity)
924                 (*chan->isic_drvr_linktab->bch_activity)
925                         (chan->isic_drvr_linktab->unit, ACT_TX);
926
927         *src_p = data;
928         return len;
929 }
930
931
932 #define itjc_save_tx_mbuf(chan, src, dst)                               \
933 (                                                                       \
934         (chan)->out_mbuf_cur != NULL ?                                  \
935         (                                                               \
936                 (chan)->out_mbuf_cur_ptr = (src),                       \
937                 (chan)->out_mbuf_cur_len = (len)                        \
938         )                                                               \
939         :                                                               \
940                 0                                                       \
941 )
942
943
944 /*---------------------------------------------------------------------------*
945  *      B-channel interrupt service routines.
946  *---------------------------------------------------------------------------*/
947
948 /*
949  * Since the Tiger ASIC doesn't produce a XMIT underflow indication,
950  * we need to deduce it ourselves. This is somewhat tricky because we
951  * are dealing with modulo m arithmetic. The idea here is to have a
952  * "XDU zone" ahead of the writing pointer sized 1/3 of total ring
953  * length (a ring slot). If the hardware DMA pointer is found there we
954  * consider that a XDU has occurred. To complete the scheme, we never
955  * let the ring have more than 2 slots of (unsent) data and adjust the
956  * interrupt registers to cause an interrupt at every slot.
957  */
958 static u_int8_t
959 itjc_xdu(struct l1_softc *sc, l1_bchan_state_t *chan, dma_tx_context_t *ctx,
960 u_int16_t *dst_p, u_int16_t *dst_end_p, u_int8_t tx_restart)
961 {
962         u_int8_t        xdu;
963
964         u_int16_t       dst_end,
965                         dst,
966                         dma,
967                         dma_l,
968                         dma_h,
969                         xdu_l,
970                         xdu_h;
971
972         itjc_bus_setup(sc);
973
974         /*
975          * Since the hardware is running, be conservative and assume
976          * the pointer location has a `fuzy' error factor.
977          */
978         dma   = itjc_get_dma_offset(ctx, TIGER_DMA_WR_CURR_ADDR);
979         dma_l = dma;
980         dma_h = itjc_ring_add(dma, 1);
981
982         dst_end = itjc_ring_sub(dma_l, ITJC_RING_SLOT_WORDS);
983
984         if (ctx->state != ITJC_TS_ACTIVE)
985         {
986                 xdu = (ctx->state == ITJC_TS_AFTER_XDU);
987                 dst = itjc_ring_add(dma_h, 4);
988                 goto done;
989         }
990
991         /*
992          * Check for xmit underruns.
993          */
994         xdu_l = dst = ctx->next_write; 
995         xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
996
997         if (xdu_l < xdu_h)
998                 xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
999                         || (xdu_l <= dma_h && dma_h < xdu_h);
1000         else
1001                 xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1002                         || (xdu_l <= dma_h || dma_h < xdu_h);
1003
1004         if (xdu)
1005         {
1006                 ctx->state = ITJC_TS_AFTER_XDU;
1007
1008                 dst = itjc_ring_add(dma_h, 4);
1009         }
1010         else if (tx_restart)
1011         {
1012                 /*
1013                  * See if we still can restart from immediately
1014                  * after the last frame sent. It's a XDU test but
1015                  * using the real data end on the comparsions. We
1016                  * don't consider XDU an error here because we were
1017                  * just trying to avoid send a filling gap between
1018                  * frames. If it's already sent no harm is done.
1019                  */
1020                 xdu_l = dst = ctx->next_frame; 
1021                 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1022
1023                 if (xdu_l < xdu_h)
1024                         xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
1025                                 || (xdu_l <= dma_h && dma_h < xdu_h);
1026                 else
1027                         xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1028                                 || (xdu_l <= dma_h || dma_h < xdu_h);
1029
1030                 if (xdu)
1031                         dst = itjc_ring_add(dma_h, 4);
1032
1033                 xdu = 0;
1034         }
1035
1036 done:
1037         if (dst_p != NULL)
1038                 *dst_p = dst;
1039         
1040         if (dst_end_p != NULL)
1041                 *dst_end_p = dst_end;
1042
1043         ctx->next_write = dst_end;
1044
1045         return xdu;
1046 }
1047
1048
1049 #define itjc_rotate_hdlc_flag(blevel)                                   \
1050         ((u_int8_t)(0x7E7E >> (8 - (u_int8_t)((blevel) >> 8))))
1051
1052
1053 static void
1054 itjc_dma_rx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1055 dma_rx_context_t *ctx)
1056 {
1057         u_int8_t        *ring,
1058                         *dst,
1059                         *dst_end,
1060                         flag,
1061                         blevel;
1062
1063         u_int16_t       dma,
1064                         src,
1065                         tmp2,
1066                         tmp,
1067                         len,
1068                         crc,
1069                         ib;
1070         
1071         itjc_bus_setup(sc);
1072
1073
1074         if (ctx->state == ITJC_RS_IDLE)
1075                 return;
1076
1077         ring = ctx->ring;
1078         dma = itjc_get_dma_offset(ctx, TIGER_DMA_RD_CURR_ADDR);
1079         dma = itjc_ring_sub(dma, 1);
1080         src = ctx->next_read;
1081
1082         if (chan->bprot == BPROT_NONE)
1083         {
1084                 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_CURR);
1085
1086                 while (src != dma)
1087                 {
1088                         if (dst == NULL)
1089                                 dst = itjc_get_rx_mbuf(chan, &dst_end, 
1090                                         ITJC_MB_NEW);
1091
1092                         *dst++ = ring[src];
1093                         src = itjc_ring_add(src, 1);
1094
1095                         if (dst >= dst_end)
1096                         {
1097                                 itjc_put_rx_mbuf(sc, chan, BCH_MAX_DATALEN);
1098                                 dst = dst_end = NULL;
1099                         }
1100                 }
1101                 ctx->next_read = src;
1102                 itjc_save_rx_mbuf(chan, dst);
1103                 return;
1104         }
1105
1106         blevel = ctx->hdlc_blevel;
1107         flag   = ctx->hdlc_flag;
1108         len    = ctx->hdlc_len;
1109         tmp    = ctx->hdlc_tmp;
1110         crc    = ctx->hdlc_crc;
1111         ib     = ctx->hdlc_ib;
1112
1113         dst = itjc_get_rx_mbuf(chan, NULL, ITJC_MB_CURR);
1114
1115         while (src != dma)
1116         {
1117                 HDLC_DECODE(*dst++, len, tmp, tmp2, blevel, ib, crc, flag,
1118                 {/* rdd */
1119                         tmp2 = ring[src];
1120                         src = itjc_ring_add(src, 1);
1121                 },
1122                 {/* nfr */
1123                         if (dst != NULL)
1124                                 panic("itjc_dma_rx_intr: nfrcmd with "
1125                                         "valid current frame");
1126
1127                         dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_NEW);
1128                         len = dst_end - dst;
1129                 },
1130                 {/* cfr */
1131                         len = BCH_MAX_DATALEN - len;
1132
1133                         if ((!len) || (len > BCH_MAX_DATALEN))
1134                         {
1135                                 /*
1136                                  * NOTE: frames without any data, only crc
1137                                  * field, should be silently discared.
1138                                  */
1139                                 NDBGL1(L1_S_MSG, "itjc_dma_rx_intr: "
1140                                         "bad frame (len=%d, unit=%d)",
1141                                         len, sc->sc_unit);
1142
1143                                 itjc_free_rx_mbuf(chan);
1144
1145                                 goto s0;
1146                         }
1147
1148                         if (crc)
1149                         {
1150                                 NDBGL1(L1_S_ERR,
1151                                         "CRC (crc=0x%04x, len=%d, unit=%d)",
1152                                         crc, len, sc->sc_unit);
1153
1154                                 itjc_free_rx_mbuf(chan);
1155
1156                                 goto s0;
1157                         }
1158
1159                         itjc_put_rx_mbuf(sc, chan, len);
1160
1161                 s0:
1162                         dst = NULL;
1163                         len = 0;
1164                 },
1165                 {/* rab */
1166                         NDBGL1(L1_S_ERR, "Read Abort (unit=%d)", sc->sc_unit);
1167
1168                         itjc_free_rx_mbuf(chan);
1169                         dst = NULL;
1170                         len = 0;
1171                 },
1172                 {/* rdo */
1173                         NDBGL1(L1_S_ERR, "RDO (unit=%d) dma=%d src=%d",
1174                                 sc->sc_unit, dma, src);
1175
1176                         itjc_free_rx_mbuf(chan);
1177                         dst = NULL;
1178                         len = 0;
1179                 },
1180                 continue,
1181                 d);
1182         }
1183
1184         itjc_save_rx_mbuf(chan, dst);
1185
1186         ctx->next_read  = src;
1187         ctx->hdlc_blevel= blevel;
1188         ctx->hdlc_flag  = flag;
1189         ctx->hdlc_len   = len;
1190         ctx->hdlc_tmp   = tmp;
1191         ctx->hdlc_crc   = crc;
1192         ctx->hdlc_ib    = ib;
1193 }
1194
1195
1196 /*
1197  * The HDLC side of itjc_dma_tx_intr. We made a separate function
1198  * to improve readability and (perhaps) help the compiler with
1199  * register allocation.
1200  */
1201 static void
1202 itjc_hdlc_encode(struct l1_softc *sc, l1_bchan_state_t *chan,
1203 dma_tx_context_t * ctx)
1204 {
1205         u_int8_t        *ring,
1206                         *src,
1207                         xdu,
1208                         flag,
1209                         flag_byte,
1210                         tx_restart;
1211
1212         u_int16_t       saved_len,
1213                         dst_end,
1214                         dst_end1,
1215                         dst,
1216                         filled,
1217                         blevel,
1218                         tmp2,
1219                         len,
1220                         crc,
1221                         ib;
1222
1223         u_int32_t       tmp;
1224
1225
1226         saved_len = len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1227
1228         filled = ctx->filled;
1229         flag   = ctx->hdlc_flag;
1230
1231         if (src == NULL && flag == 2 && filled >= ITJC_RING_WORDS)
1232                 return;
1233
1234         tx_restart = (flag == 2 && src != NULL);
1235         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, tx_restart);
1236
1237         ring   = ctx->ring;
1238
1239         ib     = ctx->hdlc_ib;
1240         crc    = ctx->hdlc_crc;
1241         tmp    = ctx->hdlc_tmp;
1242         blevel = ctx->hdlc_blevel;
1243
1244         if (xdu)
1245         {
1246                 if (flag != 2)
1247                 {
1248                         NDBGL1(L1_H_XFRERR, "XDU");
1249                         ++chan->stat_XDU;
1250
1251                         /*
1252                          * Abort the current frame and 
1253                          * prepare for a full restart.
1254                          */
1255                         itjc_free_tx_mbufs(chan);
1256                         saved_len = len = filled = 0;
1257                         flag = (u_int8_t)-2;
1258                 }
1259                 else if (filled < ITJC_RING_SLOT_WORDS)
1260                 {
1261                         /*
1262                          * A little garbage may have been retransmitted.
1263                          * Send an abort before any new data.
1264                          */
1265                         filled = 0;
1266                         flag = (u_int8_t)-2;
1267                 }
1268         }
1269
1270         if (flag != 3)
1271                 len = 0;
1272
1273         while (dst != dst_end)
1274         {
1275                 HDLC_ENCODE(
1276                 *src++, len, tmp, tmp2, blevel, ib, crc, flag,
1277                 {/* gfr */
1278                         if ((len = saved_len) == 0)
1279                                 len = itjc_get_tx_mbuf(sc, chan, &src,
1280                                         ITJC_MB_NEW);
1281
1282                         if (len == 0)
1283                         {
1284                                 ctx->next_frame = dst;
1285
1286                                 flag_byte = itjc_rotate_hdlc_flag(blevel);
1287
1288                                 for (dst_end1 = itjc_ring_sub(dst_end, 1);
1289                                 dst != dst_end1;
1290                                 dst = itjc_ring_add(dst, 1))
1291                                 {
1292                                         ring[dst] = flag_byte;
1293                                         ++filled;
1294                                 }
1295                         }
1296                         else
1297                                 filled = 0;
1298
1299                         ctx->state = ITJC_TS_ACTIVE;
1300                 },
1301                 {/* nmb */
1302                         saved_len = 0;
1303                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1304                 },
1305                 {/* wrd */
1306                         ring[dst] = (u_int8_t)tmp;
1307                         dst = itjc_ring_add(dst, 1);
1308                 },
1309                 d1);
1310         }
1311
1312         ctx->hdlc_blevel = blevel;
1313         ctx->hdlc_flag   = flag;
1314         ctx->hdlc_tmp    = tmp;
1315         ctx->hdlc_crc    = crc;
1316         ctx->hdlc_ib     = ib;
1317
1318         ctx->filled = filled;
1319         ctx->next_write = dst;
1320
1321         itjc_save_tx_mbuf(chan, src, len);
1322 }
1323
1324
1325 static void
1326 itjc_dma_tx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1327 dma_tx_context_t * ctx)
1328 {
1329         u_int8_t        *data_end,
1330                         *ring,
1331                         *src,
1332                         xdu;
1333
1334         u_int16_t       dst,
1335                         dst_end,
1336                         filled,
1337                         len;
1338
1339
1340         if (ctx->state == ITJC_TS_IDLE)
1341                 goto done;
1342
1343         if (chan->bprot != BPROT_NONE)
1344         {
1345                 itjc_hdlc_encode(sc, chan, ctx);
1346                 goto done;
1347         }
1348
1349         ring   = ctx->ring;
1350         filled = ctx->filled;
1351
1352         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1353
1354         if (len == 0 && filled >= ITJC_RING_WORDS)
1355                 goto done;
1356
1357         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, len != 0);
1358
1359         if (xdu && filled < ITJC_RING_WORDS)
1360         {
1361                 NDBGL1(L1_H_XFRERR, "XDU");
1362                 ++chan->stat_XDU;
1363                 filled = 0;
1364         }
1365
1366         if (len == 0)
1367                 goto fill_ring;
1368
1369         ctx->state = ITJC_TS_ACTIVE;
1370
1371         data_end = src + len;
1372         while (dst != dst_end)
1373         {
1374                 ring[dst] = *src++; --len;
1375
1376                 dst = itjc_ring_add(dst, 1);
1377
1378                 if (src >= data_end)
1379                 {
1380                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1381                         if (len == 0)
1382                                 len = itjc_get_tx_mbuf(sc, chan,
1383                                          &src, ITJC_MB_NEW);
1384
1385                         if (len == 0)
1386                         {
1387                                 data_end = NULL;
1388                                 break;
1389                         }
1390                         data_end = src + len;
1391                 }
1392         }
1393
1394         itjc_save_tx_mbuf(chan, src, len);
1395
1396         filled = 0;
1397
1398 fill_ring:
1399         ctx->next_frame = dst;
1400
1401         for (; dst != dst_end; dst = itjc_ring_add(dst, 1))
1402         {
1403                 ring[dst] = ITJC_TEL_SILENCE_BYTE;
1404                 ++filled;
1405         }
1406
1407         ctx->next_write = dst;
1408         ctx->filled = filled;
1409
1410 done:
1411 }
1412
1413
1414 /*---------------------------------------------------------------------------*
1415  *      NetJet fifo read/write routines.
1416  *---------------------------------------------------------------------------*/
1417
1418 static void
1419 itjc_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1420 {
1421         itjc_bus_setup(sc);
1422
1423         if (what != ISIC_WHAT_ISAC)
1424                 panic("itjc_write_fifo: Trying to read from HSCX fifo.\n");
1425
1426         itjc_set_pib_addr_msb(0);
1427         itjc_read_multi_1(PIB_OFFSET, buf, size);
1428 }
1429
1430
1431 static void
1432 itjc_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1433 {
1434         itjc_bus_setup(sc);
1435
1436         if (what != ISIC_WHAT_ISAC)
1437                 panic("itjc_write_fifo: Trying to write to HSCX fifo.\n");
1438
1439         itjc_set_pib_addr_msb(0);
1440         itjc_write_multi_1(PIB_OFFSET, buf, size);
1441 }
1442
1443
1444 /*---------------------------------------------------------------------------*
1445  *      Read an ISAC register.
1446  *---------------------------------------------------------------------------*/
1447 static u_int8_t
1448 itjc_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
1449 {
1450         itjc_bus_setup(sc);
1451
1452         if (what != ISIC_WHAT_ISAC)
1453         {
1454                 panic("itjc_read_reg: what(%d) != ISIC_WHAT_ISAC\n",
1455                         what);
1456                 return 0;
1457         }
1458
1459         itjc_set_pib_addr_msb(offs);
1460         return itjc_read_1(itjc_pib_2_pci(offs));
1461 }
1462
1463
1464 /*---------------------------------------------------------------------------*
1465  *      Write an ISAC register.
1466  *---------------------------------------------------------------------------*/
1467 static void
1468 itjc_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
1469 {
1470         itjc_bus_setup(sc);
1471
1472         if (what != ISIC_WHAT_ISAC)
1473         {
1474                 panic("itjc_write_reg: what(%d) != ISIC_WHAT_ISAC\n",
1475                         what);
1476                 return;
1477         }
1478
1479         itjc_set_pib_addr_msb(offs);
1480         itjc_write_1(itjc_pib_2_pci(offs), data);
1481 }
1482
1483
1484 /*---------------------------------------------------------------------------*
1485  *      itjc_probe - probe for a card.
1486  *---------------------------------------------------------------------------*/
1487 static int itjc_probe(device_t dev)
1488 {
1489         u_int16_t       vid = pci_get_vendor(dev),
1490                         did = pci_get_device(dev);
1491
1492         if ((vid == PCI_TJNET_VID) && (did == PCI_TJ300_DID))
1493         {
1494                 device_set_desc(dev, "NetJet-S");
1495                 return 0;
1496         }
1497
1498         return ENXIO;
1499 }
1500
1501
1502 /*---------------------------------------------------------------------------*
1503  *      itjc_attach - attach a (previously probed) card.
1504  *---------------------------------------------------------------------------*/
1505 int
1506 itjc_attach(device_t dev)
1507 {
1508         bus_space_handle_t      h;
1509         bus_space_tag_t         t; 
1510
1511         struct l1_softc         *sc = device_get_softc(dev);
1512
1513         u_int16_t               vid = pci_get_vendor(dev),
1514                                 did = pci_get_device(dev);
1515
1516         int                     unit = device_get_unit(dev),
1517                                 s = splimp(),
1518                                 res_init_level = 0,
1519                                 error = 0;
1520
1521         void                    *ih = 0;
1522
1523         dma_context_t           *ctx = &dma_context[unit];
1524
1525         bzero(sc, sizeof(struct l1_softc));
1526
1527         /* Probably not really required. */
1528         if (unit > ITJC_MAXUNIT)
1529         {
1530                 printf("itjc%d: Error, unit > ITJC_MAXUNIT!\n", unit);
1531                 splx(s);
1532                 return ENXIO;
1533         }
1534
1535         if (!(vid == PCI_TJNET_VID && did == PCI_TJ300_DID))
1536         {
1537                 printf("itjc%d: unknown device (%04X,%04X)!\n", unit, vid, did);
1538                 goto fail;
1539         }
1540
1541         itjc_scp[unit] = sc;
1542
1543         sc->sc_resources.io_rid[0] = PCIR_MAPS+0;
1544         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
1545                 &sc->sc_resources.io_rid[0], 0, ~0, 1, RF_ACTIVE);
1546
1547         if (sc->sc_resources.io_base[0] == NULL)
1548         {
1549                 printf("itjc%d: couldn't map IO port\n", unit);
1550                 error = ENXIO;
1551                 goto fail;
1552         }
1553
1554         h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1555         t = rman_get_bustag(sc->sc_resources.io_base[0]); 
1556
1557         ++res_init_level;
1558
1559         /* Allocate interrupt. */
1560         sc->sc_resources.irq_rid = 0;
1561         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
1562                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
1563
1564         if (sc->sc_resources.irq == NULL)
1565         {
1566                 printf("itjc%d: couldn't map interrupt\n", unit);
1567                 error = ENXIO;
1568                 goto fail;
1569         }
1570
1571         ++res_init_level;
1572
1573         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
1574                          itjc_intr, sc, &ih);
1575
1576         if (error)
1577         {
1578                 printf("itjc%d: couldn't set up irq handler\n", unit);
1579                 error = ENXIO;
1580                 goto fail;
1581         }
1582
1583         /*
1584          * Reset the ASIC & the ISAC.
1585          */
1586         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1587
1588         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1589
1590         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1591                 TIGER_SELF_ADDR_DMA | TIGER_PIB_3_CYCLES);
1592
1593         DELAY(SEC_DELAY/100); /* ... and more 10 to recover. */
1594
1595         /*
1596          * First part of DMA initialization. Create & map the memory
1597          * pool that will be used to bear the rx & tx ring buffers.
1598          */
1599         ctx->state = ITJC_DS_LOADING;
1600
1601         error = bus_dma_tag_create(
1602                 NULL,                                   /* parent */
1603                 4,                                      /* alignment*/
1604                 0,                                      /* boundary*/
1605                 BUS_SPACE_MAXADDR_32BIT,                /* lowaddr*/    
1606                 BUS_SPACE_MAXADDR,                      /* highaddr*/
1607                 NULL,                                   /* filter*/
1608                 NULL,                                   /* filterarg*/
1609                 ITJC_DMA_POOL_BYTES,                    /* maxsize*/
1610                 1,                                      /* nsegments*/
1611                 ITJC_DMA_POOL_BYTES,                    /* maxsegsz*/
1612                 BUS_DMA_ALLOCNOW | BUS_DMAMEM_NOSYNC,   /* flags*/
1613                 &ctx->tag);
1614
1615         if (error)
1616         {
1617                 printf("itjc%d: couldn't create bus DMA tag.\n", unit);
1618                 goto fail;
1619         }
1620
1621         ++res_init_level;
1622
1623         error = bus_dmamem_alloc(
1624                 ctx->tag,                               /* DMA tag */
1625                 (void **)&ctx->pool,    /* KV addr of the allocated memory */
1626                 BUS_DMA_NOWAIT | BUS_DMAMEM_NOSYNC,     /* flags */
1627                 &ctx->map);                             /* KV <-> PCI map */
1628
1629         if (error)
1630                 goto fail;
1631
1632         /*
1633          * Load the KV <-> PCI map so the device sees the same
1634          * memory segment as pointed by pool. Note: since the
1635          * load may happen assyncronously (completion indicated by
1636          * the execution of the callback function) we have to
1637          * delay the initialization of the DMA engine to a moment we
1638          * actually have the proper bus addresses to feed the Tiger
1639          * and our DMA control blocks. This will be done in
1640          * itjc_bchannel_setup via a call to itjc_dma_start.
1641          */
1642         bus_dmamap_load(
1643                 ctx->tag,               /* DMA tag */
1644                 ctx->map,               /* DMA map */
1645                 ctx->pool,              /* KV addr of buffer */
1646                 ITJC_DMA_POOL_BYTES,    /* buffer size */
1647                 itjc_map_callback,      /* this receive the bus addr/error */
1648                 ctx,                    /* callback aux arg */
1649                 0);                     /* flags */
1650
1651         ++res_init_level;
1652
1653         /*
1654          * Setup the AUX port so we can talk to the ISAC.
1655          */
1656         itjc_write_1(TIGER_AUX_PORT_CNTL, TIGER_AUX_NJ_DEFAULT);
1657         itjc_write_1(TIGER_INT1_MASK, TIGER_ISAC_INT);
1658
1659         /*
1660          * From now on, almost like a `normal' ISIC driver.
1661          */
1662
1663         sc->sc_unit = unit;
1664
1665         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
1666
1667         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
1668         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
1669
1670         /* setup access routines */
1671
1672         sc->clearirq = NULL;
1673         sc->readreg = itjc_read_reg;
1674         sc->writereg = itjc_write_reg;
1675
1676         sc->readfifo = itjc_read_fifo;
1677         sc->writefifo = itjc_write_fifo;
1678
1679         /* setup card type */
1680         
1681         sc->sc_cardtyp = CARD_TYPEP_NETJET_S;
1682
1683         /* setup IOM bus type */
1684         
1685         sc->sc_bustyp = BUS_TYPE_IOM2;
1686
1687         /* set up some other miscellaneous things */
1688         sc->sc_ipac = 0;
1689         sc->sc_bfifolen = 2 * ITJC_RING_SLOT_WORDS;
1690
1691         printf("itjc%d: ISAC 2186 Version 1.1 (IOM-2)\n", unit);
1692
1693         /* init the ISAC */
1694         itjc_isac_init(sc);
1695
1696         /* init the "HSCX" */
1697         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
1698         
1699         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
1700
1701         /* can't use the normal B-Channel stuff */
1702         itjc_init_linktab(sc);
1703
1704         /* set trace level */
1705
1706         sc->sc_trace = TRACE_OFF;
1707
1708         sc->sc_state = ISAC_IDLE;
1709
1710         sc->sc_ibuf = NULL;
1711         sc->sc_ib = NULL;
1712         sc->sc_ilen = 0;
1713
1714         sc->sc_obuf = NULL;
1715         sc->sc_op = NULL;
1716         sc->sc_ol = 0;
1717         sc->sc_freeflag = 0;
1718
1719         sc->sc_obuf2 = NULL;
1720         sc->sc_freeflag2 = 0;
1721
1722 #if defined(__FreeBSD__) && __FreeBSD__ >=3
1723         callout_handle_init(&sc->sc_T3_callout);
1724         callout_handle_init(&sc->sc_T4_callout);        
1725 #endif
1726         
1727         /* init higher protocol layers */
1728         
1729         i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_ATTACH, 
1730                 sc->sc_cardtyp, &itjc_l1mux_func);
1731
1732         splx(s);
1733         return 0;
1734
1735   fail:
1736         switch (res_init_level)
1737         {
1738         case 5:
1739                 bus_dmamap_unload(ctx->tag, ctx->map);
1740                 /* FALL TRHU */
1741
1742         case 4:
1743                 bus_dmamem_free(ctx->tag, ctx->pool, ctx->map);
1744                 bus_dmamap_destroy(ctx->tag, ctx->map);
1745                 /* FALL TRHU */
1746
1747         case 3:
1748                 bus_dma_tag_destroy(ctx->tag);
1749                 /* FALL TRHU */
1750
1751         case 2:
1752                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
1753                 /* FALL TRHU */
1754
1755         case 1:
1756                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+0,
1757                         sc->sc_resources.io_base[0]);
1758                 /* FALL TRHU */
1759
1760         case 0:
1761         }
1762
1763         itjc_scp[unit] = NULL;
1764
1765         splx(s);
1766         return error;
1767 }
1768
1769
1770 /*---------------------------------------------------------------------------*
1771  *      itjc_intr - main interrupt service routine.
1772  *---------------------------------------------------------------------------*/
1773 static void
1774 itjc_intr(void *xsc)
1775 {
1776         struct l1_softc         *sc     = xsc;
1777         l1_bchan_state_t        *chan   = &sc->sc_chan[0];
1778         dma_context_t           *dma    = &dma_context[sc->sc_unit];
1779         dma_rx_context_t        *rxc    = &dma_rx_context[sc->sc_unit][0];
1780         dma_tx_context_t        *txc    = &dma_tx_context[sc->sc_unit][0];
1781
1782         itjc_bus_setup(sc);
1783
1784         /* Honor interrupts from successfully configured cards only. */
1785         if (dma->state < ITJC_DS_STOPPED)
1786                 return;
1787
1788         /* First, we check the ISAC... */
1789         if (! (itjc_read_1(TIGER_AUX_PORT_DATA) & TIGER_ISAC_INT_MASK))
1790         {
1791                 itjc_write_1(TIGER_INT1_STATUS, TIGER_ISAC_INT);
1792                 NDBGL1(L1_H_IRQ, "ISAC");
1793                 itjc_isac_intr(sc);
1794         }
1795
1796         /* ... after what we always have a look at the DMA rings. */
1797
1798         NDBGL1(L1_H_IRQ, "Tiger");
1799
1800         itjc_read_1(TIGER_INT0_STATUS);
1801         itjc_write_1(TIGER_INT0_STATUS, TIGER_TARGET_ABORT_INT
1802                 | TIGER_MASTER_ABORT_INT | TIGER_RD_END_INT
1803                 | TIGER_RD_INT_INT       | TIGER_WR_END_INT | TIGER_WR_INT_INT);
1804
1805         itjc_dma_rx_intr(sc, chan, rxc);
1806         itjc_dma_tx_intr(sc, chan, txc);
1807
1808         ++chan; ++rxc; ++txc;
1809
1810         itjc_dma_rx_intr(sc, chan, rxc);
1811         itjc_dma_tx_intr(sc, chan, txc);
1812 }
1813
1814
1815 /*---------------------------------------------------------------------------*
1816  *      itjc_bchannel_setup - (Re)initialize and start/stop a Bchannel.
1817  *---------------------------------------------------------------------------*/
1818 static void
1819 itjc_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1820 {
1821 #ifdef __FreeBSD__
1822         struct l1_softc         *sc     = itjc_scp[unit];
1823 #else
1824         struct l1_softc         *sc     = isic_find_sc(unit);
1825 #endif
1826         l1_bchan_state_t        *chan   = &sc->sc_chan[h_chan];
1827         int                     s       = SPLI4B();
1828                 
1829         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1830                 unit, h_chan, activate ? "activate" : "deactivate");
1831
1832         /*
1833          * If we are deactivating the channel, we have to stop
1834          * the DMA before we reset the channel control structures.
1835          */
1836         if (! activate)
1837                 itjc_bchannel_dma_setup(sc, h_chan, activate); 
1838
1839         /* general part */
1840
1841         chan->state = HSCX_IDLE;
1842
1843         chan->unit = sc->sc_unit;       /* unit number */
1844         chan->channel = h_chan;         /* B channel */
1845         chan->bprot = bprot;            /* B channel protocol */
1846
1847         /* receiver part */
1848
1849         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1850
1851         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1852
1853         chan->rxcount = 0;              /* reset rx counter */
1854         
1855         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1856
1857         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1858         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1859         chan->in_len = 0;               /* reset mbuf data len */
1860         
1861         /* transmitter part */
1862
1863         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1864
1865         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1866         
1867         chan->txcount = 0;              /* reset tx counter */
1868         
1869         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1870
1871         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1872         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */    
1873         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1874         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1875
1876         /*
1877          * Only setup & start the DMA after all other channel
1878          * control structures are in place.
1879          */
1880         if (activate)
1881                 itjc_bchannel_dma_setup(sc, h_chan, activate); 
1882
1883         splx(s);
1884 }
1885
1886
1887 /*---------------------------------------------------------------------------*
1888  *      itjc_bchannel_start - Signal us we have more data to send.
1889  *---------------------------------------------------------------------------*/
1890 static void
1891 itjc_bchannel_start(int unit, int h_chan)
1892 {
1893 #if Buggy_code
1894         /*
1895          * I disabled this routine because it was causing crashes when
1896          * this driver was used with the ISP (kernel SPPP) protocol driver.
1897          * The scenario is reproductible:
1898          *      Use the -link1 (dial on demand) ifconfig option.
1899          *      Start an interactive  TCP connection to somewhere.
1900          *      Wait until the PPP connection times out and is dropped.
1901          *      Try to send something on the TCP connection.
1902          *      The machine will print some garbage and halt or reboot
1903          *      (no panic messages).
1904          *
1905          * I've nailed down the problem to the fact that this routine
1906          * was being called before the B channel had been setup again.
1907          *
1908          * For now, I don't have a good solution other than this one.
1909          * But, don't despair. The impact of it is unnoticeable.
1910          */
1911
1912 #ifdef __FreeBSD__
1913         struct l1_softc  *sc    = itjc_scp[unit];
1914 #else
1915         struct l1_softc  *sc    = isic_find_sc(unit);
1916 #endif
1917         l1_bchan_state_t *chan  = &sc->sc_chan[h_chan];
1918
1919         int              s      = SPLI4B();
1920
1921         dma_tx_context_t *txc   = &dma_tx_context[unit][h_chan];
1922
1923         if (chan->state & HSCX_TX_ACTIVE)
1924         {
1925                 splx(s);
1926                 return;
1927         }
1928
1929         itjc_dma_tx_intr(sc, chan, txc);
1930
1931         splx(s);
1932 #endif
1933 }
1934
1935
1936 /*---------------------------------------------------------------------------*
1937  *      itjc_shutdown - Stop the driver and reset the card.
1938  *---------------------------------------------------------------------------*/
1939 static void
1940 itjc_shutdown(device_t dev)
1941 {
1942         struct l1_softc *sc = device_get_softc(dev);
1943
1944         itjc_bus_setup(sc);
1945
1946         /*
1947          * Stop the DMA the nice and easy way.
1948          */
1949         itjc_bchannel_setup(sc->sc_unit, 0, BPROT_NONE, 0);
1950         itjc_bchannel_setup(sc->sc_unit, 1, BPROT_NONE, 0);
1951
1952         /*
1953          * Reset the card.
1954          */
1955         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1956
1957         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1958
1959         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1960                 TIGER_SELF_ADDR_DMA | TIGER_LATCH_DMA_INT | TIGER_PIB_3_CYCLES);
1961
1962         DELAY(SEC_DELAY/100); /* ... and more 10 to recover */
1963 }
1964
1965
1966 /*---------------------------------------------------------------------------*
1967  *      itjc_ret_linktab - Return the address of itjc drivers linktab.
1968  *---------------------------------------------------------------------------*/
1969 isdn_link_t *
1970 itjc_ret_linktab(int unit, int channel)
1971 {
1972 #ifdef __FreeBSD__
1973         struct l1_softc         *sc = itjc_scp[unit];
1974 #else
1975         struct l1_softc         *sc = isic_find_sc(unit);
1976 #endif
1977         l1_bchan_state_t        *chan = &sc->sc_chan[channel];
1978
1979         return(&chan->isic_isdn_linktab);
1980 }
1981  
1982 /*---------------------------------------------------------------------------*
1983  *      itjc_set_linktab - Set the driver linktab in the b channel softc.
1984  *---------------------------------------------------------------------------*/
1985 void
1986 itjc_set_linktab(int unit, int channel, drvr_link_t *dlt)
1987 {
1988 #ifdef __FreeBSD__
1989         struct l1_softc *sc     = itjc_scp[unit];
1990 #else
1991         struct l1_softc *sc     = isic_find_sc(unit);
1992 #endif
1993         l1_bchan_state_t *chan  = &sc->sc_chan[channel];
1994
1995         chan->isic_drvr_linktab = dlt;
1996 }
1997
1998
1999 /*---------------------------------------------------------------------------*
2000  *      itjc_init_linktab - Initialize our local linktab.
2001  *---------------------------------------------------------------------------*/
2002 static void
2003 itjc_init_linktab(struct l1_softc *sc)
2004 {
2005         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
2006         isdn_link_t *lt = &chan->isic_isdn_linktab;
2007
2008         /* make sure the hardware driver is known to layer 4 */
2009         /* avoid overwriting if already set */
2010         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
2011         {
2012                 ctrl_types[CTRL_PASSIVE].set_linktab = itjc_set_linktab;
2013                 ctrl_types[CTRL_PASSIVE].get_linktab = itjc_ret_linktab;
2014         }
2015
2016         /* local setup */
2017         lt->unit = sc->sc_unit;
2018         lt->channel = HSCX_CH_A;
2019         lt->bch_config = itjc_bchannel_setup;
2020         lt->bch_tx_start = itjc_bchannel_start;
2021         lt->bch_stat = itjc_bchannel_stat;
2022         lt->tx_queue = &chan->tx_queue;
2023
2024         /* used by non-HDLC data transfers, i.e. telephony drivers */
2025         lt->rx_queue = &chan->rx_queue;
2026
2027         /* used by HDLC data transfers, i.e. ipr and isp drivers */     
2028         lt->rx_mbuf = &chan->in_mbuf;   
2029                                                 
2030         chan = &sc->sc_chan[HSCX_CH_B];
2031         lt = &chan->isic_isdn_linktab;
2032
2033         lt->unit = sc->sc_unit;
2034         lt->channel = HSCX_CH_B;
2035         lt->bch_config = itjc_bchannel_setup;
2036         lt->bch_tx_start = itjc_bchannel_start;
2037         lt->bch_stat = itjc_bchannel_stat;
2038         lt->tx_queue = &chan->tx_queue;
2039
2040         /* used by non-HDLC data transfers, i.e. telephony drivers */
2041         lt->rx_queue = &chan->rx_queue;
2042
2043         /* used by HDLC data transfers, i.e. ipr and isp drivers */     
2044         lt->rx_mbuf = &chan->in_mbuf;   
2045 }
2046
2047
2048 /*---------------------------------------------------------------------------*
2049  *      itjc_bchannel_stat - Collect link statistics for a given B channel.
2050  *---------------------------------------------------------------------------*/
2051 static void
2052 itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
2053 {
2054 #ifdef __FreeBSD__
2055         struct l1_softc *sc = itjc_scp[unit];
2056 #else
2057         struct l1_softc *sc = isic_find_sc(unit);
2058 #endif
2059         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
2060         int s;
2061
2062         s = SPLI4B();
2063         
2064         bsp->outbytes = chan->txcount;
2065         bsp->inbytes = chan->rxcount;
2066
2067         chan->txcount = 0;
2068         chan->rxcount = 0;
2069
2070         splx(s);
2071 }
2072
2073
2074 /*---------------------------------------------------------------------------*
2075  *      Netjet - ISAC interrupt routine.
2076  *---------------------------------------------------------------------------*/
2077 static void
2078 itjc_isac_intr(struct l1_softc *sc)
2079 {
2080         register u_char irq_stat;
2081
2082         do
2083         {
2084                 /* get isac irq status */
2085                 irq_stat = ISAC_READ(I_ISTA);
2086
2087                 if(irq_stat)
2088                         itjc_isac_irq(sc, irq_stat); /* isac handler */
2089         }
2090         while(irq_stat);
2091
2092         ISAC_WRITE(I_MASK, 0xff);
2093
2094         DELAY(100);
2095
2096         ISAC_WRITE(I_MASK, ISAC_IMASK);
2097 }
2098
2099
2100 /*---------------------------------------------------------------------------*
2101  *      itjc_recover - Try to recover from ISAC irq lockup.
2102  *---------------------------------------------------------------------------*/
2103 void
2104 itjc_recover(struct l1_softc *sc)
2105 {
2106         u_char byte;
2107         
2108         /* get isac irq status */
2109
2110         byte = ISAC_READ(I_ISTA);
2111
2112         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
2113         
2114         if(byte & ISAC_ISTA_EXI)
2115                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
2116
2117         if(byte & ISAC_ISTA_CISQ)
2118         {
2119                 byte = ISAC_READ(I_CIRR);
2120         
2121                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
2122                 
2123                 if(byte & ISAC_CIRR_SQC)
2124                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
2125         }
2126
2127         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
2128
2129         ISAC_WRITE(I_MASK, 0xff);       
2130         DELAY(100);
2131         ISAC_WRITE(I_MASK, ISAC_IMASK);
2132 }
2133
2134 #endif /* NITJC > 0 */