1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is an invariant value to which pseudo reg N is equivalent.
100 eliminate_regs_in_insn uses this to replace pseudos in particular
102 rtx *reg_equiv_invariant;
104 /* Element N is a memory location to which pseudo reg N is equivalent,
105 prior to any register elimination (such as frame pointer to stack
106 pointer). Depending on whether or not it is a valid address, this value
107 is transferred to either reg_equiv_address or reg_equiv_mem. */
108 rtx *reg_equiv_memory_loc;
110 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
111 collector can keep track of what is inside. */
112 varray_type reg_equiv_memory_loc_varray;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
129 int reg_equiv_init_size;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Indicate whether the register's current value is one that is not
152 safe to retain across a call, even for registers that are normally
154 static HARD_REG_SET reg_reloaded_call_part_clobbered;
156 /* Number of spill-regs so far; number of valid elements of spill_regs. */
159 /* In parallel with spill_regs, contains REG rtx's for those regs.
160 Holds the last rtx used for any given reg, or 0 if it has never
161 been used for spilling yet. This rtx is reused, provided it has
163 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
165 /* In parallel with spill_regs, contains nonzero for a spill reg
166 that was stored after the last time it was used.
167 The precise value is the insn generated to do the store. */
168 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
170 /* This is the register that was stored with spill_reg_store. This is a
171 copy of reload_out / reload_out_reg when the value was stored; if
172 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
173 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
175 /* This table is the inverse mapping of spill_regs:
176 indexed by hard reg number,
177 it contains the position of that reg in spill_regs,
178 or -1 for something that is not in spill_regs.
180 ?!? This is no longer accurate. */
181 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
183 /* This reg set indicates registers that can't be used as spill registers for
184 the currently processed insn. These are the hard registers which are live
185 during the insn, but not allocated to pseudos, as well as fixed
187 static HARD_REG_SET bad_spill_regs;
189 /* These are the hard registers that can't be used as spill register for any
190 insn. This includes registers used for user variables and registers that
191 we can't eliminate. A register that appears in this set also can't be used
192 to retry register allocation. */
193 static HARD_REG_SET bad_spill_regs_global;
195 /* Describes order of use of registers for reloading
196 of spilled pseudo-registers. `n_spills' is the number of
197 elements that are actually valid; new ones are added at the end.
199 Both spill_regs and spill_reg_order are used on two occasions:
200 once during find_reload_regs, where they keep track of the spill registers
201 for a single insn, but also during reload_as_needed where they show all
202 the registers ever used by reload. For the latter case, the information
203 is calculated during finish_spills. */
204 static short spill_regs[FIRST_PSEUDO_REGISTER];
206 /* This vector of reg sets indicates, for each pseudo, which hard registers
207 may not be used for retrying global allocation because the register was
208 formerly spilled from one of them. If we allowed reallocating a pseudo to
209 a register that it was already allocated to, reload might not
211 static HARD_REG_SET *pseudo_previous_regs;
213 /* This vector of reg sets indicates, for each pseudo, which hard
214 registers may not be used for retrying global allocation because they
215 are used as spill registers during one of the insns in which the
217 static HARD_REG_SET *pseudo_forbidden_regs;
219 /* All hard regs that have been used as spill registers for any insn are
220 marked in this set. */
221 static HARD_REG_SET used_spill_regs;
223 /* Index of last register assigned as a spill register. We allocate in
224 a round-robin fashion. */
225 static int last_spill_reg;
227 /* Nonzero if indirect addressing is supported on the machine; this means
228 that spilling (REG n) does not require reloading it into a register in
229 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
230 value indicates the level of indirect addressing supported, e.g., two
231 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
233 static char spill_indirect_levels;
235 /* Nonzero if indirect addressing is supported when the innermost MEM is
236 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
237 which these are valid is the same as spill_indirect_levels, above. */
238 char indirect_symref_ok;
240 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
241 char double_reg_address_ok;
243 /* Record the stack slot for each spilled hard register. */
244 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
246 /* Width allocated so far for that stack slot. */
247 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
249 /* Record which pseudos needed to be spilled. */
250 static regset_head spilled_pseudos;
252 /* Used for communication between order_regs_for_reload and count_pseudo.
253 Used to avoid counting one pseudo twice. */
254 static regset_head pseudos_counted;
256 /* First uid used by insns created by reload in this function.
257 Used in find_equiv_reg. */
258 int reload_first_uid;
260 /* Flag set by local-alloc or global-alloc if anything is live in
261 a call-clobbered reg across calls. */
262 int caller_save_needed;
264 /* Set to 1 while reload_as_needed is operating.
265 Required by some machines to handle any generated moves differently. */
266 int reload_in_progress = 0;
268 /* These arrays record the insn_code of insns that may be needed to
269 perform input and output reloads of special objects. They provide a
270 place to pass a scratch register. */
271 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
272 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
274 /* This obstack is used for allocation of rtl during register elimination.
275 The allocated storage can be freed once find_reloads has processed the
277 static struct obstack reload_obstack;
279 /* Points to the beginning of the reload_obstack. All insn_chain structures
280 are allocated first. */
281 static char *reload_startobj;
283 /* The point after all insn_chain structures. Used to quickly deallocate
284 memory allocated in copy_reloads during calculate_needs_all_insns. */
285 static char *reload_firstobj;
287 /* This points before all local rtl generated by register elimination.
288 Used to quickly free all memory after processing one insn. */
289 static char *reload_insn_firstobj;
291 /* List of insn_chain instructions, one for every insn that reload needs to
293 struct insn_chain *reload_insn_chain;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 HOST_WIDE_INT offset; /* Current offset between the two regs. */
312 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the difference of the
358 number of the label and the first label number. We can't offset the
359 pointer itself as this can cause problems on machines with segmented
360 memory. The first table is an array of flags that records whether we
361 have yet encountered a label and the second table is an array of arrays,
362 one entry in the latter array for each elimination. */
364 static int first_label_num;
365 static char *offsets_known_at;
366 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
368 /* Number of labels in the current function. */
370 static int num_labels;
372 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
373 static void maybe_fix_stack_asms (void);
374 static void copy_reloads (struct insn_chain *);
375 static void calculate_needs_all_insns (int);
376 static int find_reg (struct insn_chain *, int);
377 static void find_reload_regs (struct insn_chain *);
378 static void select_reload_regs (void);
379 static void delete_caller_save_insns (void);
381 static void spill_failure (rtx, enum reg_class);
382 static void count_spilled_pseudo (int, int, int);
383 static void delete_dead_insn (rtx);
384 static void alter_reg (int, int);
385 static void set_label_offsets (rtx, rtx, int);
386 static void check_eliminable_occurrences (rtx);
387 static void elimination_effects (rtx, enum machine_mode);
388 static int eliminate_regs_in_insn (rtx, int);
389 static void update_eliminable_offsets (void);
390 static void mark_not_eliminable (rtx, rtx, void *);
391 static void set_initial_elim_offsets (void);
392 static bool verify_initial_elim_offsets (void);
393 static void set_initial_label_offsets (void);
394 static void set_offsets_for_label (rtx);
395 static void init_elim_table (void);
396 static void update_eliminables (HARD_REG_SET *);
397 static void spill_hard_reg (unsigned int, int);
398 static int finish_spills (int);
399 static void scan_paradoxical_subregs (rtx);
400 static void count_pseudo (int);
401 static void order_regs_for_reload (struct insn_chain *);
402 static void reload_as_needed (int);
403 static void forget_old_reloads_1 (rtx, rtx, void *);
404 static int reload_reg_class_lower (const void *, const void *);
405 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
407 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
409 static int reload_reg_free_p (unsigned int, int, enum reload_type);
410 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
412 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
414 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
415 static int allocate_reload_reg (struct insn_chain *, int, int);
416 static int conflicts_with_override (rtx);
417 static void failed_reload (rtx, int);
418 static int set_reload_reg (int, int);
419 static void choose_reload_regs_init (struct insn_chain *, rtx *);
420 static void choose_reload_regs (struct insn_chain *);
421 static void merge_assigned_reloads (rtx);
422 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
424 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
426 static void do_input_reload (struct insn_chain *, struct reload *, int);
427 static void do_output_reload (struct insn_chain *, struct reload *, int);
428 static bool inherit_piecemeal_p (int, int);
429 static void emit_reload_insns (struct insn_chain *);
430 static void delete_output_reload (rtx, int, int);
431 static void delete_address_reloads (rtx, rtx);
432 static void delete_address_reloads_1 (rtx, rtx, rtx);
433 static rtx inc_for_reload (rtx, rtx, rtx, int);
435 static void add_auto_inc_notes (rtx, rtx);
437 static void copy_eh_notes (rtx, rtx);
438 static int reloads_conflict (int, int);
439 static rtx gen_reload (rtx, rtx, int, enum reload_type);
440 static rtx emit_insn_if_valid_for_reload (rtx);
442 /* Initialize the reload pass once per compilation. */
449 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
450 Set spill_indirect_levels to the number of levels such addressing is
451 permitted, zero if it is not permitted at all. */
454 = gen_rtx_MEM (Pmode,
457 LAST_VIRTUAL_REGISTER + 1),
459 spill_indirect_levels = 0;
461 while (memory_address_p (QImode, tem))
463 spill_indirect_levels++;
464 tem = gen_rtx_MEM (Pmode, tem);
467 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
469 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
470 indirect_symref_ok = memory_address_p (QImode, tem);
472 /* See if reg+reg is a valid (and offsettable) address. */
474 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
476 tem = gen_rtx_PLUS (Pmode,
477 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
478 gen_rtx_REG (Pmode, i));
480 /* This way, we make sure that reg+reg is an offsettable address. */
481 tem = plus_constant (tem, 4);
483 if (memory_address_p (QImode, tem))
485 double_reg_address_ok = 1;
490 /* Initialize obstack for our rtl allocation. */
491 gcc_obstack_init (&reload_obstack);
492 reload_startobj = obstack_alloc (&reload_obstack, 0);
494 INIT_REG_SET (&spilled_pseudos);
495 INIT_REG_SET (&pseudos_counted);
496 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
499 /* List of insn chains that are currently unused. */
500 static struct insn_chain *unused_insn_chains = 0;
502 /* Allocate an empty insn_chain structure. */
504 new_insn_chain (void)
506 struct insn_chain *c;
508 if (unused_insn_chains == 0)
510 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
511 INIT_REG_SET (&c->live_throughout);
512 INIT_REG_SET (&c->dead_or_set);
516 c = unused_insn_chains;
517 unused_insn_chains = c->next;
519 c->is_caller_save_insn = 0;
520 c->need_operand_change = 0;
526 /* Small utility function to set all regs in hard reg set TO which are
527 allocated to pseudos in regset FROM. */
530 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
533 reg_set_iterator rsi;
535 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
537 int r = reg_renumber[regno];
542 /* reload_combine uses the information from
543 BASIC_BLOCK->global_live_at_start, which might still
544 contain registers that have not actually been allocated
545 since they have an equivalence. */
546 gcc_assert (reload_completed);
550 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
552 SET_HARD_REG_BIT (*to, r + nregs);
557 /* Replace all pseudos found in LOC with their corresponding
561 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
574 unsigned int regno = REGNO (x);
576 if (regno < FIRST_PSEUDO_REGISTER)
579 x = eliminate_regs (x, mem_mode, usage);
583 replace_pseudos_in (loc, mem_mode, usage);
587 if (reg_equiv_constant[regno])
588 *loc = reg_equiv_constant[regno];
589 else if (reg_equiv_mem[regno])
590 *loc = reg_equiv_mem[regno];
591 else if (reg_equiv_address[regno])
592 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
595 gcc_assert (!REG_P (regno_reg_rtx[regno])
596 || REGNO (regno_reg_rtx[regno]) != regno);
597 *loc = regno_reg_rtx[regno];
602 else if (code == MEM)
604 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
608 /* Process each of our operands recursively. */
609 fmt = GET_RTX_FORMAT (code);
610 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
612 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
613 else if (*fmt == 'E')
614 for (j = 0; j < XVECLEN (x, i); j++)
615 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
619 /* Global variables used by reload and its subroutines. */
621 /* Set during calculate_needs if an insn needs register elimination. */
622 static int something_needs_elimination;
623 /* Set during calculate_needs if an insn needs an operand changed. */
624 static int something_needs_operands_changed;
626 /* Nonzero means we couldn't get enough spill regs. */
629 /* Main entry point for the reload pass.
631 FIRST is the first insn of the function being compiled.
633 GLOBAL nonzero means we were called from global_alloc
634 and should attempt to reallocate any pseudoregs that we
635 displace from hard regs we will use for reloads.
636 If GLOBAL is zero, we do not have enough information to do that,
637 so any pseudo reg that is spilled must go to the stack.
639 Return value is nonzero if reload failed
640 and we must not do any more for this function. */
643 reload (rtx first, int global)
647 struct elim_table *ep;
650 /* Make sure even insns with volatile mem refs are recognizable. */
655 reload_firstobj = obstack_alloc (&reload_obstack, 0);
657 /* Make sure that the last insn in the chain
658 is not something that needs reloading. */
659 emit_note (NOTE_INSN_DELETED);
661 /* Enable find_equiv_reg to distinguish insns made by reload. */
662 reload_first_uid = get_max_uid ();
664 #ifdef SECONDARY_MEMORY_NEEDED
665 /* Initialize the secondary memory table. */
666 clear_secondary_mem ();
669 /* We don't have a stack slot for any spill reg yet. */
670 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
671 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
673 /* Initialize the save area information for caller-save, in case some
677 /* Compute which hard registers are now in use
678 as homes for pseudo registers.
679 This is done here rather than (eg) in global_alloc
680 because this point is reached even if not optimizing. */
681 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
684 /* A function that receives a nonlocal goto must save all call-saved
686 if (current_function_has_nonlocal_label)
687 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
688 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
689 regs_ever_live[i] = 1;
691 /* Find all the pseudo registers that didn't get hard regs
692 but do have known equivalent constants or memory slots.
693 These include parameters (known equivalent to parameter slots)
694 and cse'd or loop-moved constant memory addresses.
696 Record constant equivalents in reg_equiv_constant
697 so they will be substituted by find_reloads.
698 Record memory equivalents in reg_mem_equiv so they can
699 be substituted eventually by altering the REG-rtx's. */
701 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
702 reg_equiv_invariant = xcalloc (max_regno, sizeof (rtx));
703 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
704 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
705 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
706 reg_old_renumber = xcalloc (max_regno, sizeof (short));
707 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
708 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
709 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
711 CLEAR_HARD_REG_SET (bad_spill_regs_global);
713 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
714 to. Also find all paradoxical subregs and find largest such for
717 num_eliminable_invariants = 0;
718 for (insn = first; insn; insn = NEXT_INSN (insn))
720 rtx set = single_set (insn);
722 /* We may introduce USEs that we want to remove at the end, so
723 we'll mark them with QImode. Make sure there are no
724 previously-marked insns left by say regmove. */
725 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
726 && GET_MODE (insn) != VOIDmode)
727 PUT_MODE (insn, VOIDmode);
730 scan_paradoxical_subregs (PATTERN (insn));
732 if (set != 0 && REG_P (SET_DEST (set)))
734 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
740 i = REGNO (SET_DEST (set));
743 if (i <= LAST_VIRTUAL_REGISTER)
746 if (! function_invariant_p (x)
748 /* A function invariant is often CONSTANT_P but may
749 include a register. We promise to only pass
750 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
752 && LEGITIMATE_PIC_OPERAND_P (x)))
754 /* It can happen that a REG_EQUIV note contains a MEM
755 that is not a legitimate memory operand. As later
756 stages of reload assume that all addresses found
757 in the reg_equiv_* arrays were originally legitimate,
758 we ignore such REG_EQUIV notes. */
759 if (memory_operand (x, VOIDmode))
761 /* Always unshare the equivalence, so we can
762 substitute into this insn without touching the
764 reg_equiv_memory_loc[i] = copy_rtx (x);
766 else if (function_invariant_p (x))
768 if (GET_CODE (x) == PLUS)
770 /* This is PLUS of frame pointer and a constant,
771 and might be shared. Unshare it. */
772 reg_equiv_invariant[i] = copy_rtx (x);
773 num_eliminable_invariants++;
775 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
777 reg_equiv_invariant[i] = x;
778 num_eliminable_invariants++;
780 else if (LEGITIMATE_CONSTANT_P (x))
781 reg_equiv_constant[i] = x;
784 reg_equiv_memory_loc[i]
785 = force_const_mem (GET_MODE (SET_DEST (set)), x);
786 if (! reg_equiv_memory_loc[i])
787 reg_equiv_init[i] = NULL_RTX;
792 reg_equiv_init[i] = NULL_RTX;
797 reg_equiv_init[i] = NULL_RTX;
802 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
803 if (reg_equiv_init[i])
805 fprintf (dump_file, "init_insns for %u: ", i);
806 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
807 fprintf (dump_file, "\n");
812 first_label_num = get_first_label_num ();
813 num_labels = max_label_num () - first_label_num;
815 /* Allocate the tables used to store offset information at labels. */
816 /* We used to use alloca here, but the size of what it would try to
817 allocate would occasionally cause it to exceed the stack limit and
818 cause a core dump. */
819 offsets_known_at = xmalloc (num_labels);
820 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
822 /* Alter each pseudo-reg rtx to contain its hard reg number.
823 Assign stack slots to the pseudos that lack hard regs or equivalents.
824 Do not touch virtual registers. */
826 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
829 /* If we have some registers we think can be eliminated, scan all insns to
830 see if there is an insn that sets one of these registers to something
831 other than itself plus a constant. If so, the register cannot be
832 eliminated. Doing this scan here eliminates an extra pass through the
833 main reload loop in the most common case where register elimination
835 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
837 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
839 maybe_fix_stack_asms ();
841 insns_need_reload = 0;
842 something_needs_elimination = 0;
844 /* Initialize to -1, which means take the first spill register. */
847 /* Spill any hard regs that we know we can't eliminate. */
848 CLEAR_HARD_REG_SET (used_spill_regs);
849 /* There can be multiple ways to eliminate a register;
850 they should be listed adjacently.
851 Elimination for any register fails only if all possible ways fail. */
852 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
855 int can_eliminate = 0;
858 can_eliminate |= ep->can_eliminate;
861 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
863 spill_hard_reg (from, 1);
866 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
867 if (frame_pointer_needed)
868 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
870 finish_spills (global);
872 /* From now on, we may need to generate moves differently. We may also
873 allow modifications of insns which cause them to not be recognized.
874 Any such modifications will be cleaned up during reload itself. */
875 reload_in_progress = 1;
877 /* This loop scans the entire function each go-round
878 and repeats until one repetition spills no additional hard regs. */
881 int something_changed;
884 HOST_WIDE_INT starting_frame_size;
886 /* Round size of stack frame to stack_alignment_needed. This must be done
887 here because the stack size may be a part of the offset computation
888 for register elimination, and there might have been new stack slots
889 created in the last iteration of this loop. */
890 if (cfun->stack_alignment_needed)
891 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
893 starting_frame_size = get_frame_size ();
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
923 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
925 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
927 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
929 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
930 else if (CONSTANT_P (XEXP (x, 0))
931 || (REG_P (XEXP (x, 0))
932 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
933 || (GET_CODE (XEXP (x, 0)) == PLUS
934 && REG_P (XEXP (XEXP (x, 0), 0))
935 && (REGNO (XEXP (XEXP (x, 0), 0))
936 < FIRST_PSEUDO_REGISTER)
937 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
938 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
941 /* Make a new stack slot. Then indicate that something
942 changed so we go back and recompute offsets for
943 eliminable registers because the allocation of memory
944 below might change some offset. reg_equiv_{mem,address}
945 will be set up for this pseudo on the next pass around
947 reg_equiv_memory_loc[i] = 0;
948 reg_equiv_init[i] = 0;
953 if (caller_save_needed)
956 /* If we allocated another stack slot, redo elimination bookkeeping. */
957 if (starting_frame_size != get_frame_size ())
960 if (caller_save_needed)
962 save_call_clobbered_regs ();
963 /* That might have allocated new insn_chain structures. */
964 reload_firstobj = obstack_alloc (&reload_obstack, 0);
967 calculate_needs_all_insns (global);
969 CLEAR_REG_SET (&spilled_pseudos);
972 something_changed = 0;
974 /* If we allocated any new memory locations, make another pass
975 since it might have changed elimination offsets. */
976 if (starting_frame_size != get_frame_size ())
977 something_changed = 1;
979 /* Even if the frame size remained the same, we might still have
980 changed elimination offsets, e.g. if find_reloads called
981 force_const_mem requiring the back end to allocate a constant
982 pool base register that needs to be saved on the stack. */
983 else if (!verify_initial_elim_offsets ())
984 something_changed = 1;
987 HARD_REG_SET to_spill;
988 CLEAR_HARD_REG_SET (to_spill);
989 update_eliminables (&to_spill);
990 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
991 if (TEST_HARD_REG_BIT (to_spill, i))
993 spill_hard_reg (i, 1);
996 /* Regardless of the state of spills, if we previously had
997 a register that we thought we could eliminate, but now can
998 not eliminate, we must run another pass.
1000 Consider pseudos which have an entry in reg_equiv_* which
1001 reference an eliminable register. We must make another pass
1002 to update reg_equiv_* so that we do not substitute in the
1003 old value from when we thought the elimination could be
1005 something_changed = 1;
1009 select_reload_regs ();
1013 if (insns_need_reload != 0 || did_spill)
1014 something_changed |= finish_spills (global);
1016 if (! something_changed)
1019 if (caller_save_needed)
1020 delete_caller_save_insns ();
1022 obstack_free (&reload_obstack, reload_firstobj);
1025 /* If global-alloc was run, notify it of any register eliminations we have
1028 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1029 if (ep->can_eliminate)
1030 mark_elimination (ep->from, ep->to);
1032 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1033 If that insn didn't set the register (i.e., it copied the register to
1034 memory), just delete that insn instead of the equivalencing insn plus
1035 anything now dead. If we call delete_dead_insn on that insn, we may
1036 delete the insn that actually sets the register if the register dies
1037 there and that is incorrect. */
1039 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1041 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1044 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1046 rtx equiv_insn = XEXP (list, 0);
1048 /* If we already deleted the insn or if it may trap, we can't
1049 delete it. The latter case shouldn't happen, but can
1050 if an insn has a variable address, gets a REG_EH_REGION
1051 note added to it, and then gets converted into a load
1052 from a constant address. */
1053 if (NOTE_P (equiv_insn)
1054 || can_throw_internal (equiv_insn))
1056 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1057 delete_dead_insn (equiv_insn);
1059 SET_INSN_DELETED (equiv_insn);
1064 /* Use the reload registers where necessary
1065 by generating move instructions to move the must-be-register
1066 values into or out of the reload registers. */
1068 if (insns_need_reload != 0 || something_needs_elimination
1069 || something_needs_operands_changed)
1071 HOST_WIDE_INT old_frame_size = get_frame_size ();
1073 reload_as_needed (global);
1075 gcc_assert (old_frame_size == get_frame_size ());
1077 gcc_assert (verify_initial_elim_offsets ());
1080 /* If we were able to eliminate the frame pointer, show that it is no
1081 longer live at the start of any basic block. If it ls live by
1082 virtue of being in a pseudo, that pseudo will be marked live
1083 and hence the frame pointer will be known to be live via that
1086 if (! frame_pointer_needed)
1088 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1089 HARD_FRAME_POINTER_REGNUM);
1091 /* Come here (with failure set nonzero) if we can't get enough spill
1095 CLEAR_REG_SET (&spilled_pseudos);
1096 reload_in_progress = 0;
1098 /* Now eliminate all pseudo regs by modifying them into
1099 their equivalent memory references.
1100 The REG-rtx's for the pseudos are modified in place,
1101 so all insns that used to refer to them now refer to memory.
1103 For a reg that has a reg_equiv_address, all those insns
1104 were changed by reloading so that no insns refer to it any longer;
1105 but the DECL_RTL of a variable decl may refer to it,
1106 and if so this causes the debugging info to mention the variable. */
1108 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1112 if (reg_equiv_mem[i])
1113 addr = XEXP (reg_equiv_mem[i], 0);
1115 if (reg_equiv_address[i])
1116 addr = reg_equiv_address[i];
1120 if (reg_renumber[i] < 0)
1122 rtx reg = regno_reg_rtx[i];
1124 REG_USERVAR_P (reg) = 0;
1125 PUT_CODE (reg, MEM);
1126 XEXP (reg, 0) = addr;
1127 if (reg_equiv_memory_loc[i])
1128 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1131 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1132 MEM_ATTRS (reg) = 0;
1134 MEM_NOTRAP_P (reg) = 1;
1136 else if (reg_equiv_mem[i])
1137 XEXP (reg_equiv_mem[i], 0) = addr;
1141 /* We must set reload_completed now since the cleanup_subreg_operands call
1142 below will re-recognize each insn and reload may have generated insns
1143 which are only valid during and after reload. */
1144 reload_completed = 1;
1146 /* Make a pass over all the insns and delete all USEs which we inserted
1147 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1148 notes. Delete all CLOBBER insns, except those that refer to the return
1149 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1150 from misarranging variable-array code, and simplify (subreg (reg))
1151 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1152 are no longer useful or accurate. Strip and regenerate REG_INC notes
1153 that may have been moved around. */
1155 for (insn = first; insn; insn = NEXT_INSN (insn))
1161 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1162 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1164 if ((GET_CODE (PATTERN (insn)) == USE
1165 /* We mark with QImode USEs introduced by reload itself. */
1166 && (GET_MODE (insn) == QImode
1167 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1168 || (GET_CODE (PATTERN (insn)) == CLOBBER
1169 && (!MEM_P (XEXP (PATTERN (insn), 0))
1170 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1171 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1172 && XEXP (XEXP (PATTERN (insn), 0), 0)
1173 != stack_pointer_rtx))
1174 && (!REG_P (XEXP (PATTERN (insn), 0))
1175 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1181 /* Some CLOBBERs may survive until here and still reference unassigned
1182 pseudos with const equivalent, which may in turn cause ICE in later
1183 passes if the reference remains in place. */
1184 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1185 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1186 VOIDmode, PATTERN (insn));
1188 /* Discard obvious no-ops, even without -O. This optimization
1189 is fast and doesn't interfere with debugging. */
1190 if (NONJUMP_INSN_P (insn)
1191 && GET_CODE (PATTERN (insn)) == SET
1192 && REG_P (SET_SRC (PATTERN (insn)))
1193 && REG_P (SET_DEST (PATTERN (insn)))
1194 && (REGNO (SET_SRC (PATTERN (insn)))
1195 == REGNO (SET_DEST (PATTERN (insn)))))
1201 pnote = ®_NOTES (insn);
1204 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1205 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1206 || REG_NOTE_KIND (*pnote) == REG_INC
1207 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1208 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1209 *pnote = XEXP (*pnote, 1);
1211 pnote = &XEXP (*pnote, 1);
1215 add_auto_inc_notes (insn, PATTERN (insn));
1218 /* And simplify (subreg (reg)) if it appears as an operand. */
1219 cleanup_subreg_operands (insn);
1222 /* If we are doing stack checking, give a warning if this function's
1223 frame size is larger than we expect. */
1224 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1226 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1227 static int verbose_warned = 0;
1229 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1230 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1231 size += UNITS_PER_WORD;
1233 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1235 warning (0, "frame size too large for reliable stack checking");
1236 if (! verbose_warned)
1238 warning (0, "try reducing the number of local variables");
1244 /* Indicate that we no longer have known memory locations or constants. */
1245 if (reg_equiv_constant)
1246 free (reg_equiv_constant);
1247 if (reg_equiv_invariant)
1248 free (reg_equiv_invariant);
1249 reg_equiv_constant = 0;
1250 reg_equiv_invariant = 0;
1251 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1252 reg_equiv_memory_loc = 0;
1254 if (offsets_known_at)
1255 free (offsets_known_at);
1259 free (reg_equiv_mem);
1261 free (reg_equiv_address);
1262 free (reg_max_ref_width);
1263 free (reg_old_renumber);
1264 free (pseudo_previous_regs);
1265 free (pseudo_forbidden_regs);
1267 CLEAR_HARD_REG_SET (used_spill_regs);
1268 for (i = 0; i < n_spills; i++)
1269 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1271 /* Free all the insn_chain structures at once. */
1272 obstack_free (&reload_obstack, reload_startobj);
1273 unused_insn_chains = 0;
1274 fixup_abnormal_edges ();
1276 /* Replacing pseudos with their memory equivalents might have
1277 created shared rtx. Subsequent passes would get confused
1278 by this, so unshare everything here. */
1279 unshare_all_rtl_again (first);
1281 #ifdef STACK_BOUNDARY
1282 /* init_emit has set the alignment of the hard frame pointer
1283 to STACK_BOUNDARY. It is very likely no longer valid if
1284 the hard frame pointer was used for register allocation. */
1285 if (!frame_pointer_needed)
1286 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1292 /* Yet another special case. Unfortunately, reg-stack forces people to
1293 write incorrect clobbers in asm statements. These clobbers must not
1294 cause the register to appear in bad_spill_regs, otherwise we'll call
1295 fatal_insn later. We clear the corresponding regnos in the live
1296 register sets to avoid this.
1297 The whole thing is rather sick, I'm afraid. */
1300 maybe_fix_stack_asms (void)
1303 const char *constraints[MAX_RECOG_OPERANDS];
1304 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1305 struct insn_chain *chain;
1307 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1310 HARD_REG_SET clobbered, allowed;
1313 if (! INSN_P (chain->insn)
1314 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1316 pat = PATTERN (chain->insn);
1317 if (GET_CODE (pat) != PARALLEL)
1320 CLEAR_HARD_REG_SET (clobbered);
1321 CLEAR_HARD_REG_SET (allowed);
1323 /* First, make a mask of all stack regs that are clobbered. */
1324 for (i = 0; i < XVECLEN (pat, 0); i++)
1326 rtx t = XVECEXP (pat, 0, i);
1327 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1328 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1331 /* Get the operand values and constraints out of the insn. */
1332 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1333 constraints, operand_mode);
1335 /* For every operand, see what registers are allowed. */
1336 for (i = 0; i < noperands; i++)
1338 const char *p = constraints[i];
1339 /* For every alternative, we compute the class of registers allowed
1340 for reloading in CLS, and merge its contents into the reg set
1342 int cls = (int) NO_REGS;
1348 if (c == '\0' || c == ',' || c == '#')
1350 /* End of one alternative - mark the regs in the current
1351 class, and reset the class. */
1352 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1358 } while (c != '\0' && c != ',');
1366 case '=': case '+': case '*': case '%': case '?': case '!':
1367 case '0': case '1': case '2': case '3': case '4': case 'm':
1368 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1369 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1370 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1375 cls = (int) reg_class_subunion[cls]
1376 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1381 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1385 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1386 cls = (int) reg_class_subunion[cls]
1387 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1389 cls = (int) reg_class_subunion[cls]
1390 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1392 p += CONSTRAINT_LEN (c, p);
1395 /* Those of the registers which are clobbered, but allowed by the
1396 constraints, must be usable as reload registers. So clear them
1397 out of the life information. */
1398 AND_HARD_REG_SET (allowed, clobbered);
1399 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1400 if (TEST_HARD_REG_BIT (allowed, i))
1402 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1403 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1410 /* Copy the global variables n_reloads and rld into the corresponding elts
1413 copy_reloads (struct insn_chain *chain)
1415 chain->n_reloads = n_reloads;
1416 chain->rld = obstack_alloc (&reload_obstack,
1417 n_reloads * sizeof (struct reload));
1418 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1419 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1422 /* Walk the chain of insns, and determine for each whether it needs reloads
1423 and/or eliminations. Build the corresponding insns_need_reload list, and
1424 set something_needs_elimination as appropriate. */
1426 calculate_needs_all_insns (int global)
1428 struct insn_chain **pprev_reload = &insns_need_reload;
1429 struct insn_chain *chain, *next = 0;
1431 something_needs_elimination = 0;
1433 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1434 for (chain = reload_insn_chain; chain != 0; chain = next)
1436 rtx insn = chain->insn;
1440 /* Clear out the shortcuts. */
1441 chain->n_reloads = 0;
1442 chain->need_elim = 0;
1443 chain->need_reload = 0;
1444 chain->need_operand_change = 0;
1446 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1447 include REG_LABEL), we need to see what effects this has on the
1448 known offsets at labels. */
1450 if (LABEL_P (insn) || JUMP_P (insn)
1451 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1452 set_label_offsets (insn, insn, 0);
1456 rtx old_body = PATTERN (insn);
1457 int old_code = INSN_CODE (insn);
1458 rtx old_notes = REG_NOTES (insn);
1459 int did_elimination = 0;
1460 int operands_changed = 0;
1461 rtx set = single_set (insn);
1463 /* Skip insns that only set an equivalence. */
1464 if (set && REG_P (SET_DEST (set))
1465 && reg_renumber[REGNO (SET_DEST (set))] < 0
1466 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1467 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1468 && reg_equiv_init[REGNO (SET_DEST (set))])
1471 /* If needed, eliminate any eliminable registers. */
1472 if (num_eliminable || num_eliminable_invariants)
1473 did_elimination = eliminate_regs_in_insn (insn, 0);
1475 /* Analyze the instruction. */
1476 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1477 global, spill_reg_order);
1479 /* If a no-op set needs more than one reload, this is likely
1480 to be something that needs input address reloads. We
1481 can't get rid of this cleanly later, and it is of no use
1482 anyway, so discard it now.
1483 We only do this when expensive_optimizations is enabled,
1484 since this complements reload inheritance / output
1485 reload deletion, and it can make debugging harder. */
1486 if (flag_expensive_optimizations && n_reloads > 1)
1488 rtx set = single_set (insn);
1490 && SET_SRC (set) == SET_DEST (set)
1491 && REG_P (SET_SRC (set))
1492 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1495 /* Delete it from the reload chain. */
1497 chain->prev->next = next;
1499 reload_insn_chain = next;
1501 next->prev = chain->prev;
1502 chain->next = unused_insn_chains;
1503 unused_insn_chains = chain;
1508 update_eliminable_offsets ();
1510 /* Remember for later shortcuts which insns had any reloads or
1511 register eliminations. */
1512 chain->need_elim = did_elimination;
1513 chain->need_reload = n_reloads > 0;
1514 chain->need_operand_change = operands_changed;
1516 /* Discard any register replacements done. */
1517 if (did_elimination)
1519 obstack_free (&reload_obstack, reload_insn_firstobj);
1520 PATTERN (insn) = old_body;
1521 INSN_CODE (insn) = old_code;
1522 REG_NOTES (insn) = old_notes;
1523 something_needs_elimination = 1;
1526 something_needs_operands_changed |= operands_changed;
1530 copy_reloads (chain);
1531 *pprev_reload = chain;
1532 pprev_reload = &chain->next_need_reload;
1539 /* Comparison function for qsort to decide which of two reloads
1540 should be handled first. *P1 and *P2 are the reload numbers. */
1543 reload_reg_class_lower (const void *r1p, const void *r2p)
1545 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1548 /* Consider required reloads before optional ones. */
1549 t = rld[r1].optional - rld[r2].optional;
1553 /* Count all solitary classes before non-solitary ones. */
1554 t = ((reg_class_size[(int) rld[r2].class] == 1)
1555 - (reg_class_size[(int) rld[r1].class] == 1));
1559 /* Aside from solitaires, consider all multi-reg groups first. */
1560 t = rld[r2].nregs - rld[r1].nregs;
1564 /* Consider reloads in order of increasing reg-class number. */
1565 t = (int) rld[r1].class - (int) rld[r2].class;
1569 /* If reloads are equally urgent, sort by reload number,
1570 so that the results of qsort leave nothing to chance. */
1574 /* The cost of spilling each hard reg. */
1575 static int spill_cost[FIRST_PSEUDO_REGISTER];
1577 /* When spilling multiple hard registers, we use SPILL_COST for the first
1578 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1579 only the first hard reg for a multi-reg pseudo. */
1580 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1582 /* Update the spill cost arrays, considering that pseudo REG is live. */
1585 count_pseudo (int reg)
1587 int freq = REG_FREQ (reg);
1588 int r = reg_renumber[reg];
1591 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1592 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1595 SET_REGNO_REG_SET (&pseudos_counted, reg);
1597 gcc_assert (r >= 0);
1599 spill_add_cost[r] += freq;
1601 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1603 spill_cost[r + nregs] += freq;
1606 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1607 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1610 order_regs_for_reload (struct insn_chain *chain)
1613 HARD_REG_SET used_by_pseudos;
1614 HARD_REG_SET used_by_pseudos2;
1615 reg_set_iterator rsi;
1617 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1619 memset (spill_cost, 0, sizeof spill_cost);
1620 memset (spill_add_cost, 0, sizeof spill_add_cost);
1622 /* Count number of uses of each hard reg by pseudo regs allocated to it
1623 and then order them by decreasing use. First exclude hard registers
1624 that are live in or across this insn. */
1626 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1627 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1628 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1629 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1631 /* Now find out which pseudos are allocated to it, and update
1633 CLEAR_REG_SET (&pseudos_counted);
1635 EXECUTE_IF_SET_IN_REG_SET
1636 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1640 EXECUTE_IF_SET_IN_REG_SET
1641 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1645 CLEAR_REG_SET (&pseudos_counted);
1648 /* Vector of reload-numbers showing the order in which the reloads should
1650 static short reload_order[MAX_RELOADS];
1652 /* This is used to keep track of the spill regs used in one insn. */
1653 static HARD_REG_SET used_spill_regs_local;
1655 /* We decided to spill hard register SPILLED, which has a size of
1656 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1657 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1658 update SPILL_COST/SPILL_ADD_COST. */
1661 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1663 int r = reg_renumber[reg];
1664 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1666 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1667 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1670 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1672 spill_add_cost[r] -= REG_FREQ (reg);
1674 spill_cost[r + nregs] -= REG_FREQ (reg);
1677 /* Find reload register to use for reload number ORDER. */
1680 find_reg (struct insn_chain *chain, int order)
1682 int rnum = reload_order[order];
1683 struct reload *rl = rld + rnum;
1684 int best_cost = INT_MAX;
1688 HARD_REG_SET not_usable;
1689 HARD_REG_SET used_by_other_reload;
1690 reg_set_iterator rsi;
1692 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1693 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1694 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1696 CLEAR_HARD_REG_SET (used_by_other_reload);
1697 for (k = 0; k < order; k++)
1699 int other = reload_order[k];
1701 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1702 for (j = 0; j < rld[other].nregs; j++)
1703 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1706 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1708 unsigned int regno = i;
1710 if (! TEST_HARD_REG_BIT (not_usable, regno)
1711 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1712 && HARD_REGNO_MODE_OK (regno, rl->mode))
1714 int this_cost = spill_cost[regno];
1716 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1718 for (j = 1; j < this_nregs; j++)
1720 this_cost += spill_add_cost[regno + j];
1721 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1722 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1727 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1729 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1731 if (this_cost < best_cost
1732 /* Among registers with equal cost, prefer caller-saved ones, or
1733 use REG_ALLOC_ORDER if it is defined. */
1734 || (this_cost == best_cost
1735 #ifdef REG_ALLOC_ORDER
1736 && (inv_reg_alloc_order[regno]
1737 < inv_reg_alloc_order[best_reg])
1739 && call_used_regs[regno]
1740 && ! call_used_regs[best_reg]
1745 best_cost = this_cost;
1753 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1755 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1756 rl->regno = best_reg;
1758 EXECUTE_IF_SET_IN_REG_SET
1759 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1761 count_spilled_pseudo (best_reg, rl->nregs, j);
1764 EXECUTE_IF_SET_IN_REG_SET
1765 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1767 count_spilled_pseudo (best_reg, rl->nregs, j);
1770 for (i = 0; i < rl->nregs; i++)
1772 gcc_assert (spill_cost[best_reg + i] == 0);
1773 gcc_assert (spill_add_cost[best_reg + i] == 0);
1774 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1779 /* Find more reload regs to satisfy the remaining need of an insn, which
1781 Do it by ascending class number, since otherwise a reg
1782 might be spilled for a big class and might fail to count
1783 for a smaller class even though it belongs to that class. */
1786 find_reload_regs (struct insn_chain *chain)
1790 /* In order to be certain of getting the registers we need,
1791 we must sort the reloads into order of increasing register class.
1792 Then our grabbing of reload registers will parallel the process
1793 that provided the reload registers. */
1794 for (i = 0; i < chain->n_reloads; i++)
1796 /* Show whether this reload already has a hard reg. */
1797 if (chain->rld[i].reg_rtx)
1799 int regno = REGNO (chain->rld[i].reg_rtx);
1800 chain->rld[i].regno = regno;
1802 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1805 chain->rld[i].regno = -1;
1806 reload_order[i] = i;
1809 n_reloads = chain->n_reloads;
1810 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1812 CLEAR_HARD_REG_SET (used_spill_regs_local);
1815 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1817 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1819 /* Compute the order of preference for hard registers to spill. */
1821 order_regs_for_reload (chain);
1823 for (i = 0; i < n_reloads; i++)
1825 int r = reload_order[i];
1827 /* Ignore reloads that got marked inoperative. */
1828 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1829 && ! rld[r].optional
1830 && rld[r].regno == -1)
1831 if (! find_reg (chain, i))
1833 spill_failure (chain->insn, rld[r].class);
1839 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1840 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1842 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1846 select_reload_regs (void)
1848 struct insn_chain *chain;
1850 /* Try to satisfy the needs for each insn. */
1851 for (chain = insns_need_reload; chain != 0;
1852 chain = chain->next_need_reload)
1853 find_reload_regs (chain);
1856 /* Delete all insns that were inserted by emit_caller_save_insns during
1859 delete_caller_save_insns (void)
1861 struct insn_chain *c = reload_insn_chain;
1865 while (c != 0 && c->is_caller_save_insn)
1867 struct insn_chain *next = c->next;
1870 if (c == reload_insn_chain)
1871 reload_insn_chain = next;
1875 next->prev = c->prev;
1877 c->prev->next = next;
1878 c->next = unused_insn_chains;
1879 unused_insn_chains = c;
1887 /* Handle the failure to find a register to spill.
1888 INSN should be one of the insns which needed this particular spill reg. */
1891 spill_failure (rtx insn, enum reg_class class)
1893 if (asm_noperands (PATTERN (insn)) >= 0)
1894 error_for_asm (insn, "can't find a register in class %qs while "
1895 "reloading %<asm%>",
1896 reg_class_names[class]);
1899 error ("unable to find a register to spill in class %qs",
1900 reg_class_names[class]);
1901 fatal_insn ("this is the insn:", insn);
1905 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1906 data that is dead in INSN. */
1909 delete_dead_insn (rtx insn)
1911 rtx prev = prev_real_insn (insn);
1914 /* If the previous insn sets a register that dies in our insn, delete it
1916 if (prev && GET_CODE (PATTERN (prev)) == SET
1917 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1918 && reg_mentioned_p (prev_dest, PATTERN (insn))
1919 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1920 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1921 delete_dead_insn (prev);
1923 SET_INSN_DELETED (insn);
1926 /* Modify the home of pseudo-reg I.
1927 The new home is present in reg_renumber[I].
1929 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1930 or it may be -1, meaning there is none or it is not relevant.
1931 This is used so that all pseudos spilled from a given hard reg
1932 can share one stack slot. */
1935 alter_reg (int i, int from_reg)
1937 /* When outputting an inline function, this can happen
1938 for a reg that isn't actually used. */
1939 if (regno_reg_rtx[i] == 0)
1942 /* If the reg got changed to a MEM at rtl-generation time,
1944 if (!REG_P (regno_reg_rtx[i]))
1947 /* Modify the reg-rtx to contain the new hard reg
1948 number or else to contain its pseudo reg number. */
1949 REGNO (regno_reg_rtx[i])
1950 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1952 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1953 allocate a stack slot for it. */
1955 if (reg_renumber[i] < 0
1956 && REG_N_REFS (i) > 0
1957 && reg_equiv_constant[i] == 0
1958 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1959 && reg_equiv_memory_loc[i] == 0)
1962 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1963 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1966 /* Each pseudo reg has an inherent size which comes from its own mode,
1967 and a total size which provides room for paradoxical subregs
1968 which refer to the pseudo reg in wider modes.
1970 We can use a slot already allocated if it provides both
1971 enough inherent space and enough total space.
1972 Otherwise, we allocate a new slot, making sure that it has no less
1973 inherent space, and no less total space, then the previous slot. */
1976 /* No known place to spill from => no slot to reuse. */
1977 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1978 inherent_size == total_size ? 0 : -1);
1979 if (BYTES_BIG_ENDIAN)
1980 /* Cancel the big-endian correction done in assign_stack_local.
1981 Get the address of the beginning of the slot.
1982 This is so we can do a big-endian correction unconditionally
1984 adjust = inherent_size - total_size;
1986 /* Nothing can alias this slot except this pseudo. */
1987 set_mem_alias_set (x, new_alias_set ());
1990 /* Reuse a stack slot if possible. */
1991 else if (spill_stack_slot[from_reg] != 0
1992 && spill_stack_slot_width[from_reg] >= total_size
1993 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1995 x = spill_stack_slot[from_reg];
1997 /* Allocate a bigger slot. */
2000 /* Compute maximum size needed, both for inherent size
2001 and for total size. */
2002 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2005 if (spill_stack_slot[from_reg])
2007 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2009 mode = GET_MODE (spill_stack_slot[from_reg]);
2010 if (spill_stack_slot_width[from_reg] > total_size)
2011 total_size = spill_stack_slot_width[from_reg];
2014 /* Make a slot with that size. */
2015 x = assign_stack_local (mode, total_size,
2016 inherent_size == total_size ? 0 : -1);
2019 /* All pseudos mapped to this slot can alias each other. */
2020 if (spill_stack_slot[from_reg])
2021 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2023 set_mem_alias_set (x, new_alias_set ());
2025 if (BYTES_BIG_ENDIAN)
2027 /* Cancel the big-endian correction done in assign_stack_local.
2028 Get the address of the beginning of the slot.
2029 This is so we can do a big-endian correction unconditionally
2031 adjust = GET_MODE_SIZE (mode) - total_size;
2034 = adjust_address_nv (x, mode_for_size (total_size
2040 spill_stack_slot[from_reg] = stack_slot;
2041 spill_stack_slot_width[from_reg] = total_size;
2044 /* On a big endian machine, the "address" of the slot
2045 is the address of the low part that fits its inherent mode. */
2046 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2047 adjust += (total_size - inherent_size);
2049 /* If we have any adjustment to make, or if the stack slot is the
2050 wrong mode, make a new stack slot. */
2051 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2053 /* If we have a decl for the original register, set it for the
2054 memory. If this is a shared MEM, make a copy. */
2055 if (REG_EXPR (regno_reg_rtx[i])
2056 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2058 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2060 /* We can do this only for the DECLs home pseudo, not for
2061 any copies of it, since otherwise when the stack slot
2062 is reused, nonoverlapping_memrefs_p might think they
2064 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2066 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2069 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2073 /* Save the stack slot for later. */
2074 reg_equiv_memory_loc[i] = x;
2078 /* Mark the slots in regs_ever_live for the hard regs
2079 used by pseudo-reg number REGNO. */
2082 mark_home_live (int regno)
2086 i = reg_renumber[regno];
2089 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2091 regs_ever_live[i++] = 1;
2094 /* This function handles the tracking of elimination offsets around branches.
2096 X is a piece of RTL being scanned.
2098 INSN is the insn that it came from, if any.
2100 INITIAL_P is nonzero if we are to set the offset to be the initial
2101 offset and zero if we are setting the offset of the label to be the
2105 set_label_offsets (rtx x, rtx insn, int initial_p)
2107 enum rtx_code code = GET_CODE (x);
2110 struct elim_table *p;
2115 if (LABEL_REF_NONLOCAL_P (x))
2120 /* ... fall through ... */
2123 /* If we know nothing about this label, set the desired offsets. Note
2124 that this sets the offset at a label to be the offset before a label
2125 if we don't know anything about the label. This is not correct for
2126 the label after a BARRIER, but is the best guess we can make. If
2127 we guessed wrong, we will suppress an elimination that might have
2128 been possible had we been able to guess correctly. */
2130 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2132 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2133 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2134 = (initial_p ? reg_eliminate[i].initial_offset
2135 : reg_eliminate[i].offset);
2136 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2139 /* Otherwise, if this is the definition of a label and it is
2140 preceded by a BARRIER, set our offsets to the known offset of
2144 && (tem = prev_nonnote_insn (insn)) != 0
2146 set_offsets_for_label (insn);
2148 /* If neither of the above cases is true, compare each offset
2149 with those previously recorded and suppress any eliminations
2150 where the offsets disagree. */
2152 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2153 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2154 != (initial_p ? reg_eliminate[i].initial_offset
2155 : reg_eliminate[i].offset))
2156 reg_eliminate[i].can_eliminate = 0;
2161 set_label_offsets (PATTERN (insn), insn, initial_p);
2163 /* ... fall through ... */
2167 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2168 and hence must have all eliminations at their initial offsets. */
2169 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2170 if (REG_NOTE_KIND (tem) == REG_LABEL)
2171 set_label_offsets (XEXP (tem, 0), insn, 1);
2177 /* Each of the labels in the parallel or address vector must be
2178 at their initial offsets. We want the first field for PARALLEL
2179 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2181 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2182 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2187 /* We only care about setting PC. If the source is not RETURN,
2188 IF_THEN_ELSE, or a label, disable any eliminations not at
2189 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2190 isn't one of those possibilities. For branches to a label,
2191 call ourselves recursively.
2193 Note that this can disable elimination unnecessarily when we have
2194 a non-local goto since it will look like a non-constant jump to
2195 someplace in the current function. This isn't a significant
2196 problem since such jumps will normally be when all elimination
2197 pairs are back to their initial offsets. */
2199 if (SET_DEST (x) != pc_rtx)
2202 switch (GET_CODE (SET_SRC (x)))
2209 set_label_offsets (SET_SRC (x), insn, initial_p);
2213 tem = XEXP (SET_SRC (x), 1);
2214 if (GET_CODE (tem) == LABEL_REF)
2215 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2216 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2219 tem = XEXP (SET_SRC (x), 2);
2220 if (GET_CODE (tem) == LABEL_REF)
2221 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2222 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2230 /* If we reach here, all eliminations must be at their initial
2231 offset because we are doing a jump to a variable address. */
2232 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2233 if (p->offset != p->initial_offset)
2234 p->can_eliminate = 0;
2242 /* Scan X and replace any eliminable registers (such as fp) with a
2243 replacement (such as sp), plus an offset.
2245 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2246 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2247 MEM, we are allowed to replace a sum of a register and the constant zero
2248 with the register, which we cannot do outside a MEM. In addition, we need
2249 to record the fact that a register is referenced outside a MEM.
2251 If INSN is an insn, it is the insn containing X. If we replace a REG
2252 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2253 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2254 the REG is being modified.
2256 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2257 That's used when we eliminate in expressions stored in notes.
2258 This means, do not set ref_outside_mem even if the reference
2261 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2262 replacements done assuming all offsets are at their initial values. If
2263 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2264 encounter, return the actual location so that find_reloads will do
2265 the proper thing. */
2268 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2269 bool may_use_invariant)
2271 enum rtx_code code = GET_CODE (x);
2272 struct elim_table *ep;
2279 if (! current_function_decl)
2301 /* First handle the case where we encounter a bare register that
2302 is eliminable. Replace it with a PLUS. */
2303 if (regno < FIRST_PSEUDO_REGISTER)
2305 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2307 if (ep->from_rtx == x && ep->can_eliminate)
2308 return plus_constant (ep->to_rtx, ep->previous_offset);
2311 else if (reg_renumber && reg_renumber[regno] < 0
2312 && reg_equiv_invariant && reg_equiv_invariant[regno])
2314 if (may_use_invariant)
2315 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2316 mem_mode, insn, true);
2317 /* There exists at least one use of REGNO that cannot be
2318 eliminated. Prevent the defining insn from being deleted. */
2319 reg_equiv_init[regno] = NULL_RTX;
2320 alter_reg (regno, -1);
2324 /* You might think handling MINUS in a manner similar to PLUS is a
2325 good idea. It is not. It has been tried multiple times and every
2326 time the change has had to have been reverted.
2328 Other parts of reload know a PLUS is special (gen_reload for example)
2329 and require special code to handle code a reloaded PLUS operand.
2331 Also consider backends where the flags register is clobbered by a
2332 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2333 lea instruction comes to mind). If we try to reload a MINUS, we
2334 may kill the flags register that was holding a useful value.
2336 So, please before trying to handle MINUS, consider reload as a
2337 whole instead of this little section as well as the backend issues. */
2339 /* If this is the sum of an eliminable register and a constant, rework
2341 if (REG_P (XEXP (x, 0))
2342 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2343 && CONSTANT_P (XEXP (x, 1)))
2345 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2347 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2349 /* The only time we want to replace a PLUS with a REG (this
2350 occurs when the constant operand of the PLUS is the negative
2351 of the offset) is when we are inside a MEM. We won't want
2352 to do so at other times because that would change the
2353 structure of the insn in a way that reload can't handle.
2354 We special-case the commonest situation in
2355 eliminate_regs_in_insn, so just replace a PLUS with a
2356 PLUS here, unless inside a MEM. */
2357 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2358 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2361 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2362 plus_constant (XEXP (x, 1),
2363 ep->previous_offset));
2366 /* If the register is not eliminable, we are done since the other
2367 operand is a constant. */
2371 /* If this is part of an address, we want to bring any constant to the
2372 outermost PLUS. We will do this by doing register replacement in
2373 our operands and seeing if a constant shows up in one of them.
2375 Note that there is no risk of modifying the structure of the insn,
2376 since we only get called for its operands, thus we are either
2377 modifying the address inside a MEM, or something like an address
2378 operand of a load-address insn. */
2381 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2382 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2384 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2386 /* If one side is a PLUS and the other side is a pseudo that
2387 didn't get a hard register but has a reg_equiv_constant,
2388 we must replace the constant here since it may no longer
2389 be in the position of any operand. */
2390 if (GET_CODE (new0) == PLUS && REG_P (new1)
2391 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2392 && reg_renumber[REGNO (new1)] < 0
2393 && reg_equiv_constant != 0
2394 && reg_equiv_constant[REGNO (new1)] != 0)
2395 new1 = reg_equiv_constant[REGNO (new1)];
2396 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2397 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2398 && reg_renumber[REGNO (new0)] < 0
2399 && reg_equiv_constant[REGNO (new0)] != 0)
2400 new0 = reg_equiv_constant[REGNO (new0)];
2402 new = form_sum (new0, new1);
2404 /* As above, if we are not inside a MEM we do not want to
2405 turn a PLUS into something else. We might try to do so here
2406 for an addition of 0 if we aren't optimizing. */
2407 if (! mem_mode && GET_CODE (new) != PLUS)
2408 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2416 /* If this is the product of an eliminable register and a
2417 constant, apply the distribute law and move the constant out
2418 so that we have (plus (mult ..) ..). This is needed in order
2419 to keep load-address insns valid. This case is pathological.
2420 We ignore the possibility of overflow here. */
2421 if (REG_P (XEXP (x, 0))
2422 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2423 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2424 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2426 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2429 /* Refs inside notes don't count for this purpose. */
2430 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2431 || GET_CODE (insn) == INSN_LIST)))
2432 ep->ref_outside_mem = 1;
2435 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2436 ep->previous_offset * INTVAL (XEXP (x, 1)));
2439 /* ... fall through ... */
2443 /* See comments before PLUS about handling MINUS. */
2445 case DIV: case UDIV:
2446 case MOD: case UMOD:
2447 case AND: case IOR: case XOR:
2448 case ROTATERT: case ROTATE:
2449 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2451 case GE: case GT: case GEU: case GTU:
2452 case LE: case LT: case LEU: case LTU:
2454 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2455 rtx new1 = XEXP (x, 1)
2456 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2458 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2459 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2464 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2467 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2468 if (new != XEXP (x, 0))
2470 /* If this is a REG_DEAD note, it is not valid anymore.
2471 Using the eliminated version could result in creating a
2472 REG_DEAD note for the stack or frame pointer. */
2473 if (GET_MODE (x) == REG_DEAD)
2475 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2478 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2482 /* ... fall through ... */
2485 /* Now do eliminations in the rest of the chain. If this was
2486 an EXPR_LIST, this might result in allocating more memory than is
2487 strictly needed, but it simplifies the code. */
2490 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2491 if (new != XEXP (x, 1))
2493 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2501 case STRICT_LOW_PART:
2503 case SIGN_EXTEND: case ZERO_EXTEND:
2504 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2505 case FLOAT: case FIX:
2506 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2514 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2515 if (new != XEXP (x, 0))
2516 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2520 /* Similar to above processing, but preserve SUBREG_BYTE.
2521 Convert (subreg (mem)) to (mem) if not paradoxical.
2522 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2523 pseudo didn't get a hard reg, we must replace this with the
2524 eliminated version of the memory location because push_reload
2525 may do the replacement in certain circumstances. */
2526 if (REG_P (SUBREG_REG (x))
2527 && (GET_MODE_SIZE (GET_MODE (x))
2528 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2529 && reg_equiv_memory_loc != 0
2530 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2532 new = SUBREG_REG (x);
2535 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2537 if (new != SUBREG_REG (x))
2539 int x_size = GET_MODE_SIZE (GET_MODE (x));
2540 int new_size = GET_MODE_SIZE (GET_MODE (new));
2543 && ((x_size < new_size
2544 #ifdef WORD_REGISTER_OPERATIONS
2545 /* On these machines, combine can create rtl of the form
2546 (set (subreg:m1 (reg:m2 R) 0) ...)
2547 where m1 < m2, and expects something interesting to
2548 happen to the entire word. Moreover, it will use the
2549 (reg:m2 R) later, expecting all bits to be preserved.
2550 So if the number of words is the same, preserve the
2551 subreg so that push_reload can see it. */
2552 && ! ((x_size - 1) / UNITS_PER_WORD
2553 == (new_size -1 ) / UNITS_PER_WORD)
2556 || x_size == new_size)
2558 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2560 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2566 /* Our only special processing is to pass the mode of the MEM to our
2567 recursive call and copy the flags. While we are here, handle this
2568 case more efficiently. */
2570 replace_equiv_address_nv (x,
2571 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2575 /* Handle insn_list USE that a call to a pure function may generate. */
2576 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2577 if (new != XEXP (x, 0))
2578 return gen_rtx_USE (GET_MODE (x), new);
2590 /* Process each of our operands recursively. If any have changed, make a
2592 fmt = GET_RTX_FORMAT (code);
2593 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2597 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2598 if (new != XEXP (x, i) && ! copied)
2600 rtx new_x = rtx_alloc (code);
2601 memcpy (new_x, x, RTX_SIZE (code));
2607 else if (*fmt == 'E')
2610 for (j = 0; j < XVECLEN (x, i); j++)
2612 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2613 if (new != XVECEXP (x, i, j) && ! copied_vec)
2615 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2619 rtx new_x = rtx_alloc (code);
2620 memcpy (new_x, x, RTX_SIZE (code));
2624 XVEC (x, i) = new_v;
2627 XVECEXP (x, i, j) = new;
2636 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2638 return eliminate_regs_1 (x, mem_mode, insn, false);
2641 /* Scan rtx X for modifications of elimination target registers. Update
2642 the table of eliminables to reflect the changed state. MEM_MODE is
2643 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2646 elimination_effects (rtx x, enum machine_mode mem_mode)
2648 enum rtx_code code = GET_CODE (x);
2649 struct elim_table *ep;
2673 /* First handle the case where we encounter a bare register that
2674 is eliminable. Replace it with a PLUS. */
2675 if (regno < FIRST_PSEUDO_REGISTER)
2677 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2679 if (ep->from_rtx == x && ep->can_eliminate)
2682 ep->ref_outside_mem = 1;
2687 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2688 && reg_equiv_constant[regno]
2689 && ! function_invariant_p (reg_equiv_constant[regno]))
2690 elimination_effects (reg_equiv_constant[regno], mem_mode);
2699 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2700 if (ep->to_rtx == XEXP (x, 0))
2702 int size = GET_MODE_SIZE (mem_mode);
2704 /* If more bytes than MEM_MODE are pushed, account for them. */
2705 #ifdef PUSH_ROUNDING
2706 if (ep->to_rtx == stack_pointer_rtx)
2707 size = PUSH_ROUNDING (size);
2709 if (code == PRE_DEC || code == POST_DEC)
2711 else if (code == PRE_INC || code == POST_INC)
2713 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2714 && GET_CODE (XEXP (x, 1)) == PLUS
2715 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2716 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2717 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2720 /* These two aren't unary operators. */
2721 if (code == POST_MODIFY || code == PRE_MODIFY)
2724 /* Fall through to generic unary operation case. */
2725 case STRICT_LOW_PART:
2727 case SIGN_EXTEND: case ZERO_EXTEND:
2728 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2729 case FLOAT: case FIX:
2730 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2738 elimination_effects (XEXP (x, 0), mem_mode);
2742 if (REG_P (SUBREG_REG (x))
2743 && (GET_MODE_SIZE (GET_MODE (x))
2744 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2745 && reg_equiv_memory_loc != 0
2746 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2749 elimination_effects (SUBREG_REG (x), mem_mode);
2753 /* If using a register that is the source of an eliminate we still
2754 think can be performed, note it cannot be performed since we don't
2755 know how this register is used. */
2756 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2757 if (ep->from_rtx == XEXP (x, 0))
2758 ep->can_eliminate = 0;
2760 elimination_effects (XEXP (x, 0), mem_mode);
2764 /* If clobbering a register that is the replacement register for an
2765 elimination we still think can be performed, note that it cannot
2766 be performed. Otherwise, we need not be concerned about it. */
2767 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2768 if (ep->to_rtx == XEXP (x, 0))
2769 ep->can_eliminate = 0;
2771 elimination_effects (XEXP (x, 0), mem_mode);
2775 /* Check for setting a register that we know about. */
2776 if (REG_P (SET_DEST (x)))
2778 /* See if this is setting the replacement register for an
2781 If DEST is the hard frame pointer, we do nothing because we
2782 assume that all assignments to the frame pointer are for
2783 non-local gotos and are being done at a time when they are valid
2784 and do not disturb anything else. Some machines want to
2785 eliminate a fake argument pointer (or even a fake frame pointer)
2786 with either the real frame or the stack pointer. Assignments to
2787 the hard frame pointer must not prevent this elimination. */
2789 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2791 if (ep->to_rtx == SET_DEST (x)
2792 && SET_DEST (x) != hard_frame_pointer_rtx)
2794 /* If it is being incremented, adjust the offset. Otherwise,
2795 this elimination can't be done. */
2796 rtx src = SET_SRC (x);
2798 if (GET_CODE (src) == PLUS
2799 && XEXP (src, 0) == SET_DEST (x)
2800 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2801 ep->offset -= INTVAL (XEXP (src, 1));
2803 ep->can_eliminate = 0;
2807 elimination_effects (SET_DEST (x), 0);
2808 elimination_effects (SET_SRC (x), 0);
2812 /* Our only special processing is to pass the mode of the MEM to our
2814 elimination_effects (XEXP (x, 0), GET_MODE (x));
2821 fmt = GET_RTX_FORMAT (code);
2822 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2825 elimination_effects (XEXP (x, i), mem_mode);
2826 else if (*fmt == 'E')
2827 for (j = 0; j < XVECLEN (x, i); j++)
2828 elimination_effects (XVECEXP (x, i, j), mem_mode);
2832 /* Descend through rtx X and verify that no references to eliminable registers
2833 remain. If any do remain, mark the involved register as not
2837 check_eliminable_occurrences (rtx x)
2846 code = GET_CODE (x);
2848 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2850 struct elim_table *ep;
2852 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2853 if (ep->from_rtx == x)
2854 ep->can_eliminate = 0;
2858 fmt = GET_RTX_FORMAT (code);
2859 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2862 check_eliminable_occurrences (XEXP (x, i));
2863 else if (*fmt == 'E')
2866 for (j = 0; j < XVECLEN (x, i); j++)
2867 check_eliminable_occurrences (XVECEXP (x, i, j));
2872 /* Scan INSN and eliminate all eliminable registers in it.
2874 If REPLACE is nonzero, do the replacement destructively. Also
2875 delete the insn as dead it if it is setting an eliminable register.
2877 If REPLACE is zero, do all our allocations in reload_obstack.
2879 If no eliminations were done and this insn doesn't require any elimination
2880 processing (these are not identical conditions: it might be updating sp,
2881 but not referencing fp; this needs to be seen during reload_as_needed so
2882 that the offset between fp and sp can be taken into consideration), zero
2883 is returned. Otherwise, 1 is returned. */
2886 eliminate_regs_in_insn (rtx insn, int replace)
2888 int icode = recog_memoized (insn);
2889 rtx old_body = PATTERN (insn);
2890 int insn_is_asm = asm_noperands (old_body) >= 0;
2891 rtx old_set = single_set (insn);
2895 rtx substed_operand[MAX_RECOG_OPERANDS];
2896 rtx orig_operand[MAX_RECOG_OPERANDS];
2897 struct elim_table *ep;
2898 rtx plus_src, plus_cst_src;
2900 if (! insn_is_asm && icode < 0)
2902 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2903 || GET_CODE (PATTERN (insn)) == CLOBBER
2904 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2905 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2906 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2910 if (old_set != 0 && REG_P (SET_DEST (old_set))
2911 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2913 /* Check for setting an eliminable register. */
2914 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2915 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2917 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2918 /* If this is setting the frame pointer register to the
2919 hardware frame pointer register and this is an elimination
2920 that will be done (tested above), this insn is really
2921 adjusting the frame pointer downward to compensate for
2922 the adjustment done before a nonlocal goto. */
2923 if (ep->from == FRAME_POINTER_REGNUM
2924 && ep->to == HARD_FRAME_POINTER_REGNUM)
2926 rtx base = SET_SRC (old_set);
2927 rtx base_insn = insn;
2928 HOST_WIDE_INT offset = 0;
2930 while (base != ep->to_rtx)
2932 rtx prev_insn, prev_set;
2934 if (GET_CODE (base) == PLUS
2935 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2937 offset += INTVAL (XEXP (base, 1));
2938 base = XEXP (base, 0);
2940 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2941 && (prev_set = single_set (prev_insn)) != 0
2942 && rtx_equal_p (SET_DEST (prev_set), base))
2944 base = SET_SRC (prev_set);
2945 base_insn = prev_insn;
2951 if (base == ep->to_rtx)
2954 = plus_constant (ep->to_rtx, offset - ep->offset);
2956 new_body = old_body;
2959 new_body = copy_insn (old_body);
2960 if (REG_NOTES (insn))
2961 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2963 PATTERN (insn) = new_body;
2964 old_set = single_set (insn);
2966 /* First see if this insn remains valid when we
2967 make the change. If not, keep the INSN_CODE
2968 the same and let reload fit it up. */
2969 validate_change (insn, &SET_SRC (old_set), src, 1);
2970 validate_change (insn, &SET_DEST (old_set),
2972 if (! apply_change_group ())
2974 SET_SRC (old_set) = src;
2975 SET_DEST (old_set) = ep->to_rtx;
2984 /* In this case this insn isn't serving a useful purpose. We
2985 will delete it in reload_as_needed once we know that this
2986 elimination is, in fact, being done.
2988 If REPLACE isn't set, we can't delete this insn, but needn't
2989 process it since it won't be used unless something changes. */
2992 delete_dead_insn (insn);
3000 /* We allow one special case which happens to work on all machines we
3001 currently support: a single set with the source or a REG_EQUAL
3002 note being a PLUS of an eliminable register and a constant. */
3003 plus_src = plus_cst_src = 0;
3004 if (old_set && REG_P (SET_DEST (old_set)))
3006 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3007 plus_src = SET_SRC (old_set);
3008 /* First see if the source is of the form (plus (...) CST). */
3010 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3011 plus_cst_src = plus_src;
3012 else if (REG_P (SET_SRC (old_set))
3015 /* Otherwise, see if we have a REG_EQUAL note of the form
3016 (plus (...) CST). */
3018 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3020 if (REG_NOTE_KIND (links) == REG_EQUAL
3021 && GET_CODE (XEXP (links, 0)) == PLUS
3022 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3024 plus_cst_src = XEXP (links, 0);
3030 /* Check that the first operand of the PLUS is a hard reg or
3031 the lowpart subreg of one. */
3034 rtx reg = XEXP (plus_cst_src, 0);
3035 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3036 reg = SUBREG_REG (reg);
3038 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3044 rtx reg = XEXP (plus_cst_src, 0);
3045 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3047 if (GET_CODE (reg) == SUBREG)
3048 reg = SUBREG_REG (reg);
3050 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3051 if (ep->from_rtx == reg && ep->can_eliminate)
3053 rtx to_rtx = ep->to_rtx;
3054 offset += ep->offset;
3056 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3057 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3062 /* We assume here that if we need a PARALLEL with
3063 CLOBBERs for this assignment, we can do with the
3064 MATCH_SCRATCHes that add_clobbers allocates.
3065 There's not much we can do if that doesn't work. */
3066 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3070 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3073 rtvec vec = rtvec_alloc (num_clobbers + 1);
3075 vec->elem[0] = PATTERN (insn);
3076 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3077 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3079 gcc_assert (INSN_CODE (insn) >= 0);
3081 /* If we have a nonzero offset, and the source is already
3082 a simple REG, the following transformation would
3083 increase the cost of the insn by replacing a simple REG
3084 with (plus (reg sp) CST). So try only when we already
3085 had a PLUS before. */
3088 new_body = old_body;
3091 new_body = copy_insn (old_body);
3092 if (REG_NOTES (insn))
3093 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3095 PATTERN (insn) = new_body;
3096 old_set = single_set (insn);
3098 XEXP (SET_SRC (old_set), 0) = to_rtx;
3099 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3105 /* This can't have an effect on elimination offsets, so skip right
3111 /* Determine the effects of this insn on elimination offsets. */
3112 elimination_effects (old_body, 0);
3114 /* Eliminate all eliminable registers occurring in operands that
3115 can be handled by reload. */
3116 extract_insn (insn);
3117 for (i = 0; i < recog_data.n_operands; i++)
3119 orig_operand[i] = recog_data.operand[i];
3120 substed_operand[i] = recog_data.operand[i];
3122 /* For an asm statement, every operand is eliminable. */
3123 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3125 bool is_set_src, in_plus;
3127 /* Check for setting a register that we know about. */
3128 if (recog_data.operand_type[i] != OP_IN
3129 && REG_P (orig_operand[i]))
3131 /* If we are assigning to a register that can be eliminated, it
3132 must be as part of a PARALLEL, since the code above handles
3133 single SETs. We must indicate that we can no longer
3134 eliminate this reg. */
3135 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3137 if (ep->from_rtx == orig_operand[i])
3138 ep->can_eliminate = 0;
3141 /* Companion to the above plus substitution, we can allow
3142 invariants as the source of a plain move. */
3144 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3148 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3149 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3153 = eliminate_regs_1 (recog_data.operand[i], 0,
3154 replace ? insn : NULL_RTX,
3155 is_set_src || in_plus);
3156 if (substed_operand[i] != orig_operand[i])
3158 /* Terminate the search in check_eliminable_occurrences at
3160 *recog_data.operand_loc[i] = 0;
3162 /* If an output operand changed from a REG to a MEM and INSN is an
3163 insn, write a CLOBBER insn. */
3164 if (recog_data.operand_type[i] != OP_IN
3165 && REG_P (orig_operand[i])
3166 && MEM_P (substed_operand[i])
3168 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3173 for (i = 0; i < recog_data.n_dups; i++)
3174 *recog_data.dup_loc[i]
3175 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3177 /* If any eliminable remain, they aren't eliminable anymore. */
3178 check_eliminable_occurrences (old_body);
3180 /* Substitute the operands; the new values are in the substed_operand
3182 for (i = 0; i < recog_data.n_operands; i++)
3183 *recog_data.operand_loc[i] = substed_operand[i];
3184 for (i = 0; i < recog_data.n_dups; i++)
3185 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3187 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3188 re-recognize the insn. We do this in case we had a simple addition
3189 but now can do this as a load-address. This saves an insn in this
3191 If re-recognition fails, the old insn code number will still be used,
3192 and some register operands may have changed into PLUS expressions.
3193 These will be handled by find_reloads by loading them into a register
3198 /* If we aren't replacing things permanently and we changed something,
3199 make another copy to ensure that all the RTL is new. Otherwise
3200 things can go wrong if find_reload swaps commutative operands
3201 and one is inside RTL that has been copied while the other is not. */
3202 new_body = old_body;
3205 new_body = copy_insn (old_body);
3206 if (REG_NOTES (insn))
3207 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3209 PATTERN (insn) = new_body;
3211 /* If we had a move insn but now we don't, rerecognize it. This will
3212 cause spurious re-recognition if the old move had a PARALLEL since
3213 the new one still will, but we can't call single_set without
3214 having put NEW_BODY into the insn and the re-recognition won't
3215 hurt in this rare case. */
3216 /* ??? Why this huge if statement - why don't we just rerecognize the
3220 && ((REG_P (SET_SRC (old_set))
3221 && (GET_CODE (new_body) != SET
3222 || !REG_P (SET_SRC (new_body))))
3223 /* If this was a load from or store to memory, compare
3224 the MEM in recog_data.operand to the one in the insn.
3225 If they are not equal, then rerecognize the insn. */
3227 && ((MEM_P (SET_SRC (old_set))
3228 && SET_SRC (old_set) != recog_data.operand[1])
3229 || (MEM_P (SET_DEST (old_set))
3230 && SET_DEST (old_set) != recog_data.operand[0])))
3231 /* If this was an add insn before, rerecognize. */
3232 || GET_CODE (SET_SRC (old_set)) == PLUS))
3234 int new_icode = recog (PATTERN (insn), insn, 0);
3236 INSN_CODE (insn) = new_icode;
3240 /* Restore the old body. If there were any changes to it, we made a copy
3241 of it while the changes were still in place, so we'll correctly return
3242 a modified insn below. */
3245 /* Restore the old body. */
3246 for (i = 0; i < recog_data.n_operands; i++)
3247 *recog_data.operand_loc[i] = orig_operand[i];
3248 for (i = 0; i < recog_data.n_dups; i++)
3249 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3252 /* Update all elimination pairs to reflect the status after the current
3253 insn. The changes we make were determined by the earlier call to
3254 elimination_effects.
3256 We also detect cases where register elimination cannot be done,
3257 namely, if a register would be both changed and referenced outside a MEM
3258 in the resulting insn since such an insn is often undefined and, even if
3259 not, we cannot know what meaning will be given to it. Note that it is
3260 valid to have a register used in an address in an insn that changes it
3261 (presumably with a pre- or post-increment or decrement).
3263 If anything changes, return nonzero. */
3265 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3267 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3268 ep->can_eliminate = 0;
3270 ep->ref_outside_mem = 0;
3272 if (ep->previous_offset != ep->offset)
3277 /* If we changed something, perform elimination in REG_NOTES. This is
3278 needed even when REPLACE is zero because a REG_DEAD note might refer
3279 to a register that we eliminate and could cause a different number
3280 of spill registers to be needed in the final reload pass than in
3282 if (val && REG_NOTES (insn) != 0)
3284 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3289 /* Loop through all elimination pairs.
3290 Recalculate the number not at initial offset.
3292 Compute the maximum offset (minimum offset if the stack does not
3293 grow downward) for each elimination pair. */
3296 update_eliminable_offsets (void)
3298 struct elim_table *ep;
3300 num_not_at_initial_offset = 0;
3301 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3303 ep->previous_offset = ep->offset;
3304 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3305 num_not_at_initial_offset++;
3309 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3310 replacement we currently believe is valid, mark it as not eliminable if X
3311 modifies DEST in any way other than by adding a constant integer to it.
3313 If DEST is the frame pointer, we do nothing because we assume that
3314 all assignments to the hard frame pointer are nonlocal gotos and are being
3315 done at a time when they are valid and do not disturb anything else.
3316 Some machines want to eliminate a fake argument pointer with either the
3317 frame or stack pointer. Assignments to the hard frame pointer must not
3318 prevent this elimination.
3320 Called via note_stores from reload before starting its passes to scan
3321 the insns of the function. */
3324 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3328 /* A SUBREG of a hard register here is just changing its mode. We should
3329 not see a SUBREG of an eliminable hard register, but check just in
3331 if (GET_CODE (dest) == SUBREG)
3332 dest = SUBREG_REG (dest);
3334 if (dest == hard_frame_pointer_rtx)
3337 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3338 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3339 && (GET_CODE (x) != SET
3340 || GET_CODE (SET_SRC (x)) != PLUS
3341 || XEXP (SET_SRC (x), 0) != dest
3342 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3344 reg_eliminate[i].can_eliminate_previous
3345 = reg_eliminate[i].can_eliminate = 0;
3350 /* Verify that the initial elimination offsets did not change since the
3351 last call to set_initial_elim_offsets. This is used to catch cases
3352 where something illegal happened during reload_as_needed that could
3353 cause incorrect code to be generated if we did not check for it. */
3356 verify_initial_elim_offsets (void)
3360 if (!num_eliminable)
3363 #ifdef ELIMINABLE_REGS
3365 struct elim_table *ep;
3367 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3369 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3370 if (t != ep->initial_offset)
3375 INITIAL_FRAME_POINTER_OFFSET (t);
3376 if (t != reg_eliminate[0].initial_offset)
3383 /* Reset all offsets on eliminable registers to their initial values. */
3386 set_initial_elim_offsets (void)
3388 struct elim_table *ep = reg_eliminate;
3390 #ifdef ELIMINABLE_REGS
3391 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3393 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3394 ep->previous_offset = ep->offset = ep->initial_offset;
3397 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3398 ep->previous_offset = ep->offset = ep->initial_offset;
3401 num_not_at_initial_offset = 0;
3404 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3407 set_initial_eh_label_offset (rtx label)
3409 set_label_offsets (label, NULL_RTX, 1);
3412 /* Initialize the known label offsets.
3413 Set a known offset for each forced label to be at the initial offset
3414 of each elimination. We do this because we assume that all
3415 computed jumps occur from a location where each elimination is
3416 at its initial offset.
3417 For all other labels, show that we don't know the offsets. */
3420 set_initial_label_offsets (void)
3423 memset (offsets_known_at, 0, num_labels);
3425 for (x = forced_labels; x; x = XEXP (x, 1))
3427 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3429 for_each_eh_label (set_initial_eh_label_offset);
3432 /* Set all elimination offsets to the known values for the code label given
3436 set_offsets_for_label (rtx insn)
3439 int label_nr = CODE_LABEL_NUMBER (insn);
3440 struct elim_table *ep;
3442 num_not_at_initial_offset = 0;
3443 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3445 ep->offset = ep->previous_offset
3446 = offsets_at[label_nr - first_label_num][i];
3447 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3448 num_not_at_initial_offset++;
3452 /* See if anything that happened changes which eliminations are valid.
3453 For example, on the SPARC, whether or not the frame pointer can
3454 be eliminated can depend on what registers have been used. We need
3455 not check some conditions again (such as flag_omit_frame_pointer)
3456 since they can't have changed. */
3459 update_eliminables (HARD_REG_SET *pset)
3461 int previous_frame_pointer_needed = frame_pointer_needed;
3462 struct elim_table *ep;
3464 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3465 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3466 #ifdef ELIMINABLE_REGS
3467 || ! CAN_ELIMINATE (ep->from, ep->to)
3470 ep->can_eliminate = 0;
3472 /* Look for the case where we have discovered that we can't replace
3473 register A with register B and that means that we will now be
3474 trying to replace register A with register C. This means we can
3475 no longer replace register C with register B and we need to disable
3476 such an elimination, if it exists. This occurs often with A == ap,
3477 B == sp, and C == fp. */
3479 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3481 struct elim_table *op;
3484 if (! ep->can_eliminate && ep->can_eliminate_previous)
3486 /* Find the current elimination for ep->from, if there is a
3488 for (op = reg_eliminate;
3489 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3490 if (op->from == ep->from && op->can_eliminate)
3496 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3498 for (op = reg_eliminate;
3499 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3500 if (op->from == new_to && op->to == ep->to)
3501 op->can_eliminate = 0;
3505 /* See if any registers that we thought we could eliminate the previous
3506 time are no longer eliminable. If so, something has changed and we
3507 must spill the register. Also, recompute the number of eliminable
3508 registers and see if the frame pointer is needed; it is if there is
3509 no elimination of the frame pointer that we can perform. */
3511 frame_pointer_needed = 1;
3512 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3514 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3515 && ep->to != HARD_FRAME_POINTER_REGNUM)
3516 frame_pointer_needed = 0;
3518 if (! ep->can_eliminate && ep->can_eliminate_previous)
3520 ep->can_eliminate_previous = 0;
3521 SET_HARD_REG_BIT (*pset, ep->from);
3526 /* If we didn't need a frame pointer last time, but we do now, spill
3527 the hard frame pointer. */
3528 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3529 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3532 /* Initialize the table of registers to eliminate. */
3535 init_elim_table (void)
3537 struct elim_table *ep;
3538 #ifdef ELIMINABLE_REGS
3539 const struct elim_table_1 *ep1;
3543 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3545 /* Does this function require a frame pointer? */
3547 frame_pointer_needed = (! flag_omit_frame_pointer
3548 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3549 and restore sp for alloca. So we can't eliminate
3550 the frame pointer in that case. At some point,
3551 we should improve this by emitting the
3552 sp-adjusting insns for this case. */
3553 || (current_function_calls_alloca
3554 && EXIT_IGNORE_STACK)
3555 || current_function_accesses_prior_frames
3556 || FRAME_POINTER_REQUIRED);
3560 #ifdef ELIMINABLE_REGS
3561 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3562 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3564 ep->from = ep1->from;
3566 ep->can_eliminate = ep->can_eliminate_previous
3567 = (CAN_ELIMINATE (ep->from, ep->to)
3568 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3571 reg_eliminate[0].from = reg_eliminate_1[0].from;
3572 reg_eliminate[0].to = reg_eliminate_1[0].to;
3573 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3574 = ! frame_pointer_needed;
3577 /* Count the number of eliminable registers and build the FROM and TO
3578 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3579 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3580 We depend on this. */
3581 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3583 num_eliminable += ep->can_eliminate;
3584 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3585 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3589 /* Kick all pseudos out of hard register REGNO.
3591 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3592 because we found we can't eliminate some register. In the case, no pseudos
3593 are allowed to be in the register, even if they are only in a block that
3594 doesn't require spill registers, unlike the case when we are spilling this
3595 hard reg to produce another spill register.
3597 Return nonzero if any pseudos needed to be kicked out. */
3600 spill_hard_reg (unsigned int regno, int cant_eliminate)
3606 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3607 regs_ever_live[regno] = 1;
3610 /* Spill every pseudo reg that was allocated to this reg
3611 or to something that overlaps this reg. */
3613 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3614 if (reg_renumber[i] >= 0
3615 && (unsigned int) reg_renumber[i] <= regno
3616 && ((unsigned int) reg_renumber[i]
3617 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3618 [PSEUDO_REGNO_MODE (i)]
3620 SET_REGNO_REG_SET (&spilled_pseudos, i);
3623 /* After find_reload_regs has been run for all insn that need reloads,
3624 and/or spill_hard_regs was called, this function is used to actually
3625 spill pseudo registers and try to reallocate them. It also sets up the
3626 spill_regs array for use by choose_reload_regs. */
3629 finish_spills (int global)
3631 struct insn_chain *chain;
3632 int something_changed = 0;
3634 reg_set_iterator rsi;
3636 /* Build the spill_regs array for the function. */
3637 /* If there are some registers still to eliminate and one of the spill regs
3638 wasn't ever used before, additional stack space may have to be
3639 allocated to store this register. Thus, we may have changed the offset
3640 between the stack and frame pointers, so mark that something has changed.
3642 One might think that we need only set VAL to 1 if this is a call-used
3643 register. However, the set of registers that must be saved by the
3644 prologue is not identical to the call-used set. For example, the
3645 register used by the call insn for the return PC is a call-used register,
3646 but must be saved by the prologue. */
3649 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3650 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3652 spill_reg_order[i] = n_spills;
3653 spill_regs[n_spills++] = i;
3654 if (num_eliminable && ! regs_ever_live[i])
3655 something_changed = 1;
3656 regs_ever_live[i] = 1;
3659 spill_reg_order[i] = -1;
3661 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3663 /* Record the current hard register the pseudo is allocated to in
3664 pseudo_previous_regs so we avoid reallocating it to the same
3665 hard reg in a later pass. */
3666 gcc_assert (reg_renumber[i] >= 0);
3668 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3669 /* Mark it as no longer having a hard register home. */
3670 reg_renumber[i] = -1;
3671 /* We will need to scan everything again. */
3672 something_changed = 1;
3675 /* Retry global register allocation if possible. */
3678 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3679 /* For every insn that needs reloads, set the registers used as spill
3680 regs in pseudo_forbidden_regs for every pseudo live across the
3682 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3684 EXECUTE_IF_SET_IN_REG_SET
3685 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3687 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3688 chain->used_spill_regs);
3690 EXECUTE_IF_SET_IN_REG_SET
3691 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3693 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3694 chain->used_spill_regs);
3698 /* Retry allocating the spilled pseudos. For each reg, merge the
3699 various reg sets that indicate which hard regs can't be used,
3700 and call retry_global_alloc.
3701 We change spill_pseudos here to only contain pseudos that did not
3702 get a new hard register. */
3703 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3704 if (reg_old_renumber[i] != reg_renumber[i])
3706 HARD_REG_SET forbidden;
3707 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3708 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3709 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3710 retry_global_alloc (i, forbidden);
3711 if (reg_renumber[i] >= 0)
3712 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3716 /* Fix up the register information in the insn chain.
3717 This involves deleting those of the spilled pseudos which did not get
3718 a new hard register home from the live_{before,after} sets. */
3719 for (chain = reload_insn_chain; chain; chain = chain->next)
3721 HARD_REG_SET used_by_pseudos;
3722 HARD_REG_SET used_by_pseudos2;
3724 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3725 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3727 /* Mark any unallocated hard regs as available for spills. That
3728 makes inheritance work somewhat better. */
3729 if (chain->need_reload)
3731 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3732 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3733 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3735 /* Save the old value for the sanity test below. */
3736 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3738 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3739 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3740 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3741 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3743 /* Make sure we only enlarge the set. */
3744 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3750 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3751 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3753 int regno = reg_renumber[i];
3754 if (reg_old_renumber[i] == regno)
3757 alter_reg (i, reg_old_renumber[i]);
3758 reg_old_renumber[i] = regno;
3762 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3764 fprintf (dump_file, " Register %d now in %d.\n\n",
3765 i, reg_renumber[i]);
3769 return something_changed;
3772 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3775 scan_paradoxical_subregs (rtx x)
3779 enum rtx_code code = GET_CODE (x);
3789 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3797 if (REG_P (SUBREG_REG (x))
3798 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3799 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3800 = GET_MODE_SIZE (GET_MODE (x));
3807 fmt = GET_RTX_FORMAT (code);
3808 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3811 scan_paradoxical_subregs (XEXP (x, i));
3812 else if (fmt[i] == 'E')
3815 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3816 scan_paradoxical_subregs (XVECEXP (x, i, j));
3821 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3822 examine all of the reload insns between PREV and NEXT exclusive, and
3823 annotate all that may trap. */
3826 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3828 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3829 unsigned int trap_count;
3835 if (may_trap_p (PATTERN (insn)))
3839 remove_note (insn, note);
3843 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3844 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3848 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3852 /* Reload pseudo-registers into hard regs around each insn as needed.
3853 Additional register load insns are output before the insn that needs it
3854 and perhaps store insns after insns that modify the reloaded pseudo reg.
3856 reg_last_reload_reg and reg_reloaded_contents keep track of
3857 which registers are already available in reload registers.
3858 We update these for the reloads that we perform,
3859 as the insns are scanned. */
3862 reload_as_needed (int live_known)
3864 struct insn_chain *chain;
3865 #if defined (AUTO_INC_DEC)
3870 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3871 memset (spill_reg_store, 0, sizeof spill_reg_store);
3872 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3873 reg_has_output_reload = xmalloc (max_regno);
3874 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3875 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3877 set_initial_elim_offsets ();
3879 for (chain = reload_insn_chain; chain; chain = chain->next)
3882 rtx insn = chain->insn;
3883 rtx old_next = NEXT_INSN (insn);
3885 /* If we pass a label, copy the offsets from the label information
3886 into the current offsets of each elimination. */
3888 set_offsets_for_label (insn);
3890 else if (INSN_P (insn))
3892 rtx oldpat = copy_rtx (PATTERN (insn));
3894 /* If this is a USE and CLOBBER of a MEM, ensure that any
3895 references to eliminable registers have been removed. */
3897 if ((GET_CODE (PATTERN (insn)) == USE
3898 || GET_CODE (PATTERN (insn)) == CLOBBER)
3899 && MEM_P (XEXP (PATTERN (insn), 0)))
3900 XEXP (XEXP (PATTERN (insn), 0), 0)
3901 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3902 GET_MODE (XEXP (PATTERN (insn), 0)),
3905 /* If we need to do register elimination processing, do so.
3906 This might delete the insn, in which case we are done. */
3907 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3909 eliminate_regs_in_insn (insn, 1);
3912 update_eliminable_offsets ();
3917 /* If need_elim is nonzero but need_reload is zero, one might think
3918 that we could simply set n_reloads to 0. However, find_reloads
3919 could have done some manipulation of the insn (such as swapping
3920 commutative operands), and these manipulations are lost during
3921 the first pass for every insn that needs register elimination.
3922 So the actions of find_reloads must be redone here. */
3924 if (! chain->need_elim && ! chain->need_reload
3925 && ! chain->need_operand_change)
3927 /* First find the pseudo regs that must be reloaded for this insn.
3928 This info is returned in the tables reload_... (see reload.h).
3929 Also modify the body of INSN by substituting RELOAD
3930 rtx's for those pseudo regs. */
3933 memset (reg_has_output_reload, 0, max_regno);
3934 CLEAR_HARD_REG_SET (reg_is_output_reload);
3936 find_reloads (insn, 1, spill_indirect_levels, live_known,
3942 rtx next = NEXT_INSN (insn);
3945 prev = PREV_INSN (insn);
3947 /* Now compute which reload regs to reload them into. Perhaps
3948 reusing reload regs from previous insns, or else output
3949 load insns to reload them. Maybe output store insns too.
3950 Record the choices of reload reg in reload_reg_rtx. */
3951 choose_reload_regs (chain);
3953 /* Merge any reloads that we didn't combine for fear of
3954 increasing the number of spill registers needed but now
3955 discover can be safely merged. */
3956 if (SMALL_REGISTER_CLASSES)
3957 merge_assigned_reloads (insn);
3959 /* Generate the insns to reload operands into or out of
3960 their reload regs. */
3961 emit_reload_insns (chain);
3963 /* Substitute the chosen reload regs from reload_reg_rtx
3964 into the insn's body (or perhaps into the bodies of other
3965 load and store insn that we just made for reloading
3966 and that we moved the structure into). */
3967 subst_reloads (insn);
3969 /* Adjust the exception region notes for loads and stores. */
3970 if (flag_non_call_exceptions && !CALL_P (insn))
3971 fixup_eh_region_note (insn, prev, next);
3973 /* If this was an ASM, make sure that all the reload insns
3974 we have generated are valid. If not, give an error
3976 if (asm_noperands (PATTERN (insn)) >= 0)
3977 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3978 if (p != insn && INSN_P (p)
3979 && GET_CODE (PATTERN (p)) != USE
3980 && (recog_memoized (p) < 0
3981 || (extract_insn (p), ! constrain_operands (1))))
3983 error_for_asm (insn,
3984 "%<asm%> operand requires "
3985 "impossible reload");
3990 if (num_eliminable && chain->need_elim)
3991 update_eliminable_offsets ();
3993 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3994 is no longer validly lying around to save a future reload.
3995 Note that this does not detect pseudos that were reloaded
3996 for this insn in order to be stored in
3997 (obeying register constraints). That is correct; such reload
3998 registers ARE still valid. */
3999 note_stores (oldpat, forget_old_reloads_1, NULL);
4001 /* There may have been CLOBBER insns placed after INSN. So scan
4002 between INSN and NEXT and use them to forget old reloads. */
4003 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4004 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4005 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4008 /* Likewise for regs altered by auto-increment in this insn.
4009 REG_INC notes have been changed by reloading:
4010 find_reloads_address_1 records substitutions for them,
4011 which have been performed by subst_reloads above. */
4012 for (i = n_reloads - 1; i >= 0; i--)
4014 rtx in_reg = rld[i].in_reg;
4017 enum rtx_code code = GET_CODE (in_reg);
4018 /* PRE_INC / PRE_DEC will have the reload register ending up
4019 with the same value as the stack slot, but that doesn't
4020 hold true for POST_INC / POST_DEC. Either we have to
4021 convert the memory access to a true POST_INC / POST_DEC,
4022 or we can't use the reload register for inheritance. */
4023 if ((code == POST_INC || code == POST_DEC)
4024 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4025 REGNO (rld[i].reg_rtx))
4026 /* Make sure it is the inc/dec pseudo, and not
4027 some other (e.g. output operand) pseudo. */
4028 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4029 == REGNO (XEXP (in_reg, 0))))
4032 rtx reload_reg = rld[i].reg_rtx;
4033 enum machine_mode mode = GET_MODE (reload_reg);
4037 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4039 /* We really want to ignore REG_INC notes here, so
4040 use PATTERN (p) as argument to reg_set_p . */
4041 if (reg_set_p (reload_reg, PATTERN (p)))
4043 n = count_occurrences (PATTERN (p), reload_reg, 0);
4048 n = validate_replace_rtx (reload_reg,
4049 gen_rtx_fmt_e (code,
4054 /* We must also verify that the constraints
4055 are met after the replacement. */
4058 n = constrain_operands (1);
4062 /* If the constraints were not met, then
4063 undo the replacement. */
4066 validate_replace_rtx (gen_rtx_fmt_e (code,
4079 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4081 /* Mark this as having an output reload so that the
4082 REG_INC processing code below won't invalidate
4083 the reload for inheritance. */
4084 SET_HARD_REG_BIT (reg_is_output_reload,
4085 REGNO (reload_reg));
4086 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4089 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4092 else if ((code == PRE_INC || code == PRE_DEC)
4093 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4094 REGNO (rld[i].reg_rtx))
4095 /* Make sure it is the inc/dec pseudo, and not
4096 some other (e.g. output operand) pseudo. */
4097 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4098 == REGNO (XEXP (in_reg, 0))))
4100 SET_HARD_REG_BIT (reg_is_output_reload,
4101 REGNO (rld[i].reg_rtx));
4102 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4106 /* If a pseudo that got a hard register is auto-incremented,
4107 we must purge records of copying it into pseudos without
4109 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4110 if (REG_NOTE_KIND (x) == REG_INC)
4112 /* See if this pseudo reg was reloaded in this insn.
4113 If so, its last-reload info is still valid
4114 because it is based on this insn's reload. */
4115 for (i = 0; i < n_reloads; i++)
4116 if (rld[i].out == XEXP (x, 0))
4120 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4124 /* A reload reg's contents are unknown after a label. */
4126 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4128 /* Don't assume a reload reg is still good after a call insn
4129 if it is a call-used reg, or if it contains a value that will
4130 be partially clobbered by the call. */
4131 else if (CALL_P (insn))
4133 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4134 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4139 free (reg_last_reload_reg);
4140 free (reg_has_output_reload);
4143 /* Discard all record of any value reloaded from X,
4144 or reloaded in X from someplace else;
4145 unless X is an output reload reg of the current insn.
4147 X may be a hard reg (the reload reg)
4148 or it may be a pseudo reg that was reloaded from. */
4151 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4152 void *data ATTRIBUTE_UNUSED)
4157 /* note_stores does give us subregs of hard regs,
4158 subreg_regno_offset requires a hard reg. */
4159 while (GET_CODE (x) == SUBREG)
4161 /* We ignore the subreg offset when calculating the regno,
4162 because we are using the entire underlying hard register
4172 if (regno >= FIRST_PSEUDO_REGISTER)
4178 nr = hard_regno_nregs[regno][GET_MODE (x)];
4179 /* Storing into a spilled-reg invalidates its contents.
4180 This can happen if a block-local pseudo is allocated to that reg
4181 and it wasn't spilled because this block's total need is 0.
4182 Then some insn might have an optional reload and use this reg. */
4183 for (i = 0; i < nr; i++)
4184 /* But don't do this if the reg actually serves as an output
4185 reload reg in the current instruction. */
4187 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4189 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4190 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4191 spill_reg_store[regno + i] = 0;
4195 /* Since value of X has changed,
4196 forget any value previously copied from it. */
4199 /* But don't forget a copy if this is the output reload
4200 that establishes the copy's validity. */
4201 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4202 reg_last_reload_reg[regno + nr] = 0;
4205 /* The following HARD_REG_SETs indicate when each hard register is
4206 used for a reload of various parts of the current insn. */
4208 /* If reg is unavailable for all reloads. */
4209 static HARD_REG_SET reload_reg_unavailable;
4210 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4211 static HARD_REG_SET reload_reg_used;
4212 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4213 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4214 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4215 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4216 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4217 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4218 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4219 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4220 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4221 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4222 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4223 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4224 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4225 static HARD_REG_SET reload_reg_used_in_op_addr;
4226 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4227 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4228 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4229 static HARD_REG_SET reload_reg_used_in_insn;
4230 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4231 static HARD_REG_SET reload_reg_used_in_other_addr;
4233 /* If reg is in use as a reload reg for any sort of reload. */
4234 static HARD_REG_SET reload_reg_used_at_all;
4236 /* If reg is use as an inherited reload. We just mark the first register
4238 static HARD_REG_SET reload_reg_used_for_inherit;
4240 /* Records which hard regs are used in any way, either as explicit use or
4241 by being allocated to a pseudo during any point of the current insn. */
4242 static HARD_REG_SET reg_used_in_insn;
4244 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4245 TYPE. MODE is used to indicate how many consecutive regs are
4249 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4250 enum machine_mode mode)
4252 unsigned int nregs = hard_regno_nregs[regno][mode];
4255 for (i = regno; i < nregs + regno; i++)
4260 SET_HARD_REG_BIT (reload_reg_used, i);
4263 case RELOAD_FOR_INPUT_ADDRESS:
4264 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4267 case RELOAD_FOR_INPADDR_ADDRESS:
4268 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4271 case RELOAD_FOR_OUTPUT_ADDRESS:
4272 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4275 case RELOAD_FOR_OUTADDR_ADDRESS:
4276 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4279 case RELOAD_FOR_OPERAND_ADDRESS:
4280 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4283 case RELOAD_FOR_OPADDR_ADDR:
4284 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4287 case RELOAD_FOR_OTHER_ADDRESS:
4288 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4291 case RELOAD_FOR_INPUT:
4292 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4295 case RELOAD_FOR_OUTPUT:
4296 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4299 case RELOAD_FOR_INSN:
4300 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4304 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4308 /* Similarly, but show REGNO is no longer in use for a reload. */
4311 clear_reload_reg_in_use (unsigned int regno, int opnum,
4312 enum reload_type type, enum machine_mode mode)
4314 unsigned int nregs = hard_regno_nregs[regno][mode];
4315 unsigned int start_regno, end_regno, r;
4317 /* A complication is that for some reload types, inheritance might
4318 allow multiple reloads of the same types to share a reload register.
4319 We set check_opnum if we have to check only reloads with the same
4320 operand number, and check_any if we have to check all reloads. */
4321 int check_opnum = 0;
4323 HARD_REG_SET *used_in_set;
4328 used_in_set = &reload_reg_used;
4331 case RELOAD_FOR_INPUT_ADDRESS:
4332 used_in_set = &reload_reg_used_in_input_addr[opnum];
4335 case RELOAD_FOR_INPADDR_ADDRESS:
4337 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4340 case RELOAD_FOR_OUTPUT_ADDRESS:
4341 used_in_set = &reload_reg_used_in_output_addr[opnum];
4344 case RELOAD_FOR_OUTADDR_ADDRESS:
4346 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4349 case RELOAD_FOR_OPERAND_ADDRESS:
4350 used_in_set = &reload_reg_used_in_op_addr;
4353 case RELOAD_FOR_OPADDR_ADDR:
4355 used_in_set = &reload_reg_used_in_op_addr_reload;
4358 case RELOAD_FOR_OTHER_ADDRESS:
4359 used_in_set = &reload_reg_used_in_other_addr;
4363 case RELOAD_FOR_INPUT:
4364 used_in_set = &reload_reg_used_in_input[opnum];
4367 case RELOAD_FOR_OUTPUT:
4368 used_in_set = &reload_reg_used_in_output[opnum];
4371 case RELOAD_FOR_INSN:
4372 used_in_set = &reload_reg_used_in_insn;
4377 /* We resolve conflicts with remaining reloads of the same type by
4378 excluding the intervals of reload registers by them from the
4379 interval of freed reload registers. Since we only keep track of
4380 one set of interval bounds, we might have to exclude somewhat
4381 more than what would be necessary if we used a HARD_REG_SET here.
4382 But this should only happen very infrequently, so there should
4383 be no reason to worry about it. */
4385 start_regno = regno;
4386 end_regno = regno + nregs;
4387 if (check_opnum || check_any)
4389 for (i = n_reloads - 1; i >= 0; i--)
4391 if (rld[i].when_needed == type
4392 && (check_any || rld[i].opnum == opnum)
4395 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4396 unsigned int conflict_end
4398 + hard_regno_nregs[conflict_start][rld[i].mode]);
4400 /* If there is an overlap with the first to-be-freed register,
4401 adjust the interval start. */
4402 if (conflict_start <= start_regno && conflict_end > start_regno)
4403 start_regno = conflict_end;
4404 /* Otherwise, if there is a conflict with one of the other
4405 to-be-freed registers, adjust the interval end. */
4406 if (conflict_start > start_regno && conflict_start < end_regno)
4407 end_regno = conflict_start;
4412 for (r = start_regno; r < end_regno; r++)
4413 CLEAR_HARD_REG_BIT (*used_in_set, r);
4416 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4417 specified by OPNUM and TYPE. */
4420 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4424 /* In use for a RELOAD_OTHER means it's not available for anything. */
4425 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4426 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4432 /* In use for anything means we can't use it for RELOAD_OTHER. */
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4434 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4435 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4436 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4439 for (i = 0; i < reload_n_operands; i++)
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4441 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4450 case RELOAD_FOR_INPUT:
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4452 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4458 /* If it is used for some other input, can't use it. */
4459 for (i = 0; i < reload_n_operands; i++)
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4463 /* If it is used in a later operand's address, can't use it. */
4464 for (i = opnum + 1; i < reload_n_operands; i++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4471 case RELOAD_FOR_INPUT_ADDRESS:
4472 /* Can't use a register if it is used for an input address for this
4473 operand or used as an input in an earlier one. */
4474 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4475 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4478 for (i = 0; i < opnum; i++)
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4484 case RELOAD_FOR_INPADDR_ADDRESS:
4485 /* Can't use a register if it is used for an input address
4486 for this operand or used as an input in an earlier
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4491 for (i = 0; i < opnum; i++)
4492 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4497 case RELOAD_FOR_OUTPUT_ADDRESS:
4498 /* Can't use a register if it is used for an output address for this
4499 operand or used as an output in this or a later operand. Note
4500 that multiple output operands are emitted in reverse order, so
4501 the conflicting ones are those with lower indices. */
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4505 for (i = 0; i <= opnum; i++)
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4511 case RELOAD_FOR_OUTADDR_ADDRESS:
4512 /* Can't use a register if it is used for an output address
4513 for this operand or used as an output in this or a
4514 later operand. Note that multiple output operands are
4515 emitted in reverse order, so the conflicting ones are
4516 those with lower indices. */
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4520 for (i = 0; i <= opnum; i++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4526 case RELOAD_FOR_OPERAND_ADDRESS:
4527 for (i = 0; i < reload_n_operands; i++)
4528 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4531 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4532 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4534 case RELOAD_FOR_OPADDR_ADDR:
4535 for (i = 0; i < reload_n_operands; i++)
4536 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4539 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4541 case RELOAD_FOR_OUTPUT:
4542 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4543 outputs, or an operand address for this or an earlier output.
4544 Note that multiple output operands are emitted in reverse order,
4545 so the conflicting ones are those with higher indices. */
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4549 for (i = 0; i < reload_n_operands; i++)
4550 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4553 for (i = opnum; i < reload_n_operands; i++)
4554 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4555 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4560 case RELOAD_FOR_INSN:
4561 for (i = 0; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4566 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4567 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4569 case RELOAD_FOR_OTHER_ADDRESS:
4570 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4577 /* Return 1 if the value in reload reg REGNO, as used by a reload
4578 needed for the part of the insn specified by OPNUM and TYPE,
4579 is still available in REGNO at the end of the insn.
4581 We can assume that the reload reg was already tested for availability
4582 at the time it is needed, and we should not check this again,
4583 in case the reg has already been marked in use. */
4586 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4593 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4594 its value must reach the end. */
4597 /* If this use is for part of the insn,
4598 its value reaches if no subsequent part uses the same register.
4599 Just like the above function, don't try to do this with lots
4602 case RELOAD_FOR_OTHER_ADDRESS:
4603 /* Here we check for everything else, since these don't conflict
4604 with anything else and everything comes later. */
4606 for (i = 0; i < reload_n_operands; i++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4611 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4612 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4615 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4616 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4617 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4618 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4620 case RELOAD_FOR_INPUT_ADDRESS:
4621 case RELOAD_FOR_INPADDR_ADDRESS:
4622 /* Similar, except that we check only for this and subsequent inputs
4623 and the address of only subsequent inputs and we do not need
4624 to check for RELOAD_OTHER objects since they are known not to
4627 for (i = opnum; i < reload_n_operands; i++)
4628 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4631 for (i = opnum + 1; i < reload_n_operands; i++)
4632 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4633 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4636 for (i = 0; i < reload_n_operands; i++)
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4638 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4645 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4646 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4647 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4649 case RELOAD_FOR_INPUT:
4650 /* Similar to input address, except we start at the next operand for
4651 both input and input address and we do not check for
4652 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4655 for (i = opnum + 1; i < reload_n_operands; i++)
4656 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4657 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4658 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4661 /* ... fall through ... */
4663 case RELOAD_FOR_OPERAND_ADDRESS:
4664 /* Check outputs and their addresses. */
4666 for (i = 0; i < reload_n_operands; i++)
4667 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4668 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4669 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4672 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4674 case RELOAD_FOR_OPADDR_ADDR:
4675 for (i = 0; i < reload_n_operands; i++)
4676 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4677 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4678 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4681 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4682 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4683 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4685 case RELOAD_FOR_INSN:
4686 /* These conflict with other outputs with RELOAD_OTHER. So
4687 we need only check for output addresses. */
4689 opnum = reload_n_operands;
4691 /* ... fall through ... */
4693 case RELOAD_FOR_OUTPUT:
4694 case RELOAD_FOR_OUTPUT_ADDRESS:
4695 case RELOAD_FOR_OUTADDR_ADDRESS:
4696 /* We already know these can't conflict with a later output. So the
4697 only thing to check are later output addresses.
4698 Note that multiple output operands are emitted in reverse order,
4699 so the conflicting ones are those with lower indices. */
4700 for (i = 0; i < opnum; i++)
4701 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4702 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4712 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4715 This function uses the same algorithm as reload_reg_free_p above. */
4718 reloads_conflict (int r1, int r2)
4720 enum reload_type r1_type = rld[r1].when_needed;
4721 enum reload_type r2_type = rld[r2].when_needed;
4722 int r1_opnum = rld[r1].opnum;
4723 int r2_opnum = rld[r2].opnum;
4725 /* RELOAD_OTHER conflicts with everything. */
4726 if (r2_type == RELOAD_OTHER)
4729 /* Otherwise, check conflicts differently for each type. */
4733 case RELOAD_FOR_INPUT:
4734 return (r2_type == RELOAD_FOR_INSN
4735 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4736 || r2_type == RELOAD_FOR_OPADDR_ADDR
4737 || r2_type == RELOAD_FOR_INPUT
4738 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4739 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4740 && r2_opnum > r1_opnum));
4742 case RELOAD_FOR_INPUT_ADDRESS:
4743 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4744 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4746 case RELOAD_FOR_INPADDR_ADDRESS:
4747 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4748 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4750 case RELOAD_FOR_OUTPUT_ADDRESS:
4751 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4752 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4754 case RELOAD_FOR_OUTADDR_ADDRESS:
4755 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4756 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4758 case RELOAD_FOR_OPERAND_ADDRESS:
4759 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4760 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4762 case RELOAD_FOR_OPADDR_ADDR:
4763 return (r2_type == RELOAD_FOR_INPUT
4764 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4766 case RELOAD_FOR_OUTPUT:
4767 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4768 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4769 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4770 && r2_opnum >= r1_opnum));
4772 case RELOAD_FOR_INSN:
4773 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4774 || r2_type == RELOAD_FOR_INSN
4775 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4777 case RELOAD_FOR_OTHER_ADDRESS:
4778 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4788 /* Indexed by reload number, 1 if incoming value
4789 inherited from previous insns. */
4790 static char reload_inherited[MAX_RELOADS];
4792 /* For an inherited reload, this is the insn the reload was inherited from,
4793 if we know it. Otherwise, this is 0. */
4794 static rtx reload_inheritance_insn[MAX_RELOADS];
4796 /* If nonzero, this is a place to get the value of the reload,
4797 rather than using reload_in. */
4798 static rtx reload_override_in[MAX_RELOADS];
4800 /* For each reload, the hard register number of the register used,
4801 or -1 if we did not need a register for this reload. */
4802 static int reload_spill_index[MAX_RELOADS];
4804 /* Subroutine of free_for_value_p, used to check a single register.
4805 START_REGNO is the starting regno of the full reload register
4806 (possibly comprising multiple hard registers) that we are considering. */
4809 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4810 enum reload_type type, rtx value, rtx out,
4811 int reloadnum, int ignore_address_reloads)
4814 /* Set if we see an input reload that must not share its reload register
4815 with any new earlyclobber, but might otherwise share the reload
4816 register with an output or input-output reload. */
4817 int check_earlyclobber = 0;
4821 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4824 if (out == const0_rtx)
4830 /* We use some pseudo 'time' value to check if the lifetimes of the
4831 new register use would overlap with the one of a previous reload
4832 that is not read-only or uses a different value.
4833 The 'time' used doesn't have to be linear in any shape or form, just
4835 Some reload types use different 'buckets' for each operand.
4836 So there are MAX_RECOG_OPERANDS different time values for each
4838 We compute TIME1 as the time when the register for the prospective
4839 new reload ceases to be live, and TIME2 for each existing
4840 reload as the time when that the reload register of that reload
4842 Where there is little to be gained by exact lifetime calculations,
4843 we just make conservative assumptions, i.e. a longer lifetime;
4844 this is done in the 'default:' cases. */
4847 case RELOAD_FOR_OTHER_ADDRESS:
4848 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4849 time1 = copy ? 0 : 1;
4852 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4854 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4855 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4856 respectively, to the time values for these, we get distinct time
4857 values. To get distinct time values for each operand, we have to
4858 multiply opnum by at least three. We round that up to four because
4859 multiply by four is often cheaper. */
4860 case RELOAD_FOR_INPADDR_ADDRESS:
4861 time1 = opnum * 4 + 2;
4863 case RELOAD_FOR_INPUT_ADDRESS:
4864 time1 = opnum * 4 + 3;
4866 case RELOAD_FOR_INPUT:
4867 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4868 executes (inclusive). */
4869 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4871 case RELOAD_FOR_OPADDR_ADDR:
4873 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4874 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4876 case RELOAD_FOR_OPERAND_ADDRESS:
4877 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4879 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4881 case RELOAD_FOR_OUTADDR_ADDRESS:
4882 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4884 case RELOAD_FOR_OUTPUT_ADDRESS:
4885 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4888 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4891 for (i = 0; i < n_reloads; i++)
4893 rtx reg = rld[i].reg_rtx;
4894 if (reg && REG_P (reg)
4895 && ((unsigned) regno - true_regnum (reg)
4896 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4899 rtx other_input = rld[i].in;
4901 /* If the other reload loads the same input value, that
4902 will not cause a conflict only if it's loading it into
4903 the same register. */
4904 if (true_regnum (reg) != start_regno)
4905 other_input = NULL_RTX;
4906 if (! other_input || ! rtx_equal_p (other_input, value)
4907 || rld[i].out || out)
4910 switch (rld[i].when_needed)
4912 case RELOAD_FOR_OTHER_ADDRESS:
4915 case RELOAD_FOR_INPADDR_ADDRESS:
4916 /* find_reloads makes sure that a
4917 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4918 by at most one - the first -
4919 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4920 address reload is inherited, the address address reload
4921 goes away, so we can ignore this conflict. */
4922 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4923 && ignore_address_reloads
4924 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4925 Then the address address is still needed to store
4926 back the new address. */
4927 && ! rld[reloadnum].out)
4929 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4930 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4932 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4933 && ignore_address_reloads
4934 /* Unless we are reloading an auto_inc expression. */
4935 && ! rld[reloadnum].out)
4937 time2 = rld[i].opnum * 4 + 2;
4939 case RELOAD_FOR_INPUT_ADDRESS:
4940 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4941 && ignore_address_reloads
4942 && ! rld[reloadnum].out)
4944 time2 = rld[i].opnum * 4 + 3;
4946 case RELOAD_FOR_INPUT:
4947 time2 = rld[i].opnum * 4 + 4;
4948 check_earlyclobber = 1;
4950 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4951 == MAX_RECOG_OPERAND * 4 */
4952 case RELOAD_FOR_OPADDR_ADDR:
4953 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4954 && ignore_address_reloads
4955 && ! rld[reloadnum].out)
4957 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4959 case RELOAD_FOR_OPERAND_ADDRESS:
4960 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4961 check_earlyclobber = 1;
4963 case RELOAD_FOR_INSN:
4964 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4966 case RELOAD_FOR_OUTPUT:
4967 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4968 instruction is executed. */
4969 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4971 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4972 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4974 case RELOAD_FOR_OUTADDR_ADDRESS:
4975 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4976 && ignore_address_reloads
4977 && ! rld[reloadnum].out)
4979 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4981 case RELOAD_FOR_OUTPUT_ADDRESS:
4982 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4985 /* If there is no conflict in the input part, handle this
4986 like an output reload. */
4987 if (! rld[i].in || rtx_equal_p (other_input, value))
4989 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4990 /* Earlyclobbered outputs must conflict with inputs. */
4991 if (earlyclobber_operand_p (rld[i].out))
4992 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4997 /* RELOAD_OTHER might be live beyond instruction execution,
4998 but this is not obvious when we set time2 = 1. So check
4999 here if there might be a problem with the new reload
5000 clobbering the register used by the RELOAD_OTHER. */
5008 && (! rld[i].in || rld[i].out
5009 || ! rtx_equal_p (other_input, value)))
5010 || (out && rld[reloadnum].out_reg
5011 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5017 /* Earlyclobbered outputs must conflict with inputs. */
5018 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5024 /* Return 1 if the value in reload reg REGNO, as used by a reload
5025 needed for the part of the insn specified by OPNUM and TYPE,
5026 may be used to load VALUE into it.
5028 MODE is the mode in which the register is used, this is needed to
5029 determine how many hard regs to test.
5031 Other read-only reloads with the same value do not conflict
5032 unless OUT is nonzero and these other reloads have to live while
5033 output reloads live.
5034 If OUT is CONST0_RTX, this is a special case: it means that the
5035 test should not be for using register REGNO as reload register, but
5036 for copying from register REGNO into the reload register.
5038 RELOADNUM is the number of the reload we want to load this value for;
5039 a reload does not conflict with itself.
5041 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5042 reloads that load an address for the very reload we are considering.
5044 The caller has to make sure that there is no conflict with the return
5048 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5049 enum reload_type type, rtx value, rtx out, int reloadnum,
5050 int ignore_address_reloads)
5052 int nregs = hard_regno_nregs[regno][mode];
5054 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5055 value, out, reloadnum,
5056 ignore_address_reloads))
5061 /* Return nonzero if the rtx X is invariant over the current function. */
5062 /* ??? Actually, the places where we use this expect exactly what is
5063 tested here, and not everything that is function invariant. In
5064 particular, the frame pointer and arg pointer are special cased;
5065 pic_offset_table_rtx is not, and we must not spill these things to
5069 function_invariant_p (rtx x)
5073 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5075 if (GET_CODE (x) == PLUS
5076 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5077 && CONSTANT_P (XEXP (x, 1)))
5082 /* Determine whether the reload reg X overlaps any rtx'es used for
5083 overriding inheritance. Return nonzero if so. */
5086 conflicts_with_override (rtx x)
5089 for (i = 0; i < n_reloads; i++)
5090 if (reload_override_in[i]
5091 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5096 /* Give an error message saying we failed to find a reload for INSN,
5097 and clear out reload R. */
5099 failed_reload (rtx insn, int r)
5101 if (asm_noperands (PATTERN (insn)) < 0)
5102 /* It's the compiler's fault. */
5103 fatal_insn ("could not find a spill register", insn);
5105 /* It's the user's fault; the operand's mode and constraint
5106 don't match. Disable this reload so we don't crash in final. */
5107 error_for_asm (insn,
5108 "%<asm%> operand constraint incompatible with operand size");
5112 rld[r].optional = 1;
5113 rld[r].secondary_p = 1;
5116 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5117 for reload R. If it's valid, get an rtx for it. Return nonzero if
5120 set_reload_reg (int i, int r)
5123 rtx reg = spill_reg_rtx[i];
5125 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5126 spill_reg_rtx[i] = reg
5127 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5129 regno = true_regnum (reg);
5131 /* Detect when the reload reg can't hold the reload mode.
5132 This used to be one `if', but Sequent compiler can't handle that. */
5133 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5135 enum machine_mode test_mode = VOIDmode;
5137 test_mode = GET_MODE (rld[r].in);
5138 /* If rld[r].in has VOIDmode, it means we will load it
5139 in whatever mode the reload reg has: to wit, rld[r].mode.
5140 We have already tested that for validity. */
5141 /* Aside from that, we need to test that the expressions
5142 to reload from or into have modes which are valid for this
5143 reload register. Otherwise the reload insns would be invalid. */
5144 if (! (rld[r].in != 0 && test_mode != VOIDmode
5145 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5146 if (! (rld[r].out != 0
5147 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5149 /* The reg is OK. */
5152 /* Mark as in use for this insn the reload regs we use
5154 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5155 rld[r].when_needed, rld[r].mode);
5157 rld[r].reg_rtx = reg;
5158 reload_spill_index[r] = spill_regs[i];
5165 /* Find a spill register to use as a reload register for reload R.
5166 LAST_RELOAD is nonzero if this is the last reload for the insn being
5169 Set rld[R].reg_rtx to the register allocated.
5171 We return 1 if successful, or 0 if we couldn't find a spill reg and
5172 we didn't change anything. */
5175 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5180 /* If we put this reload ahead, thinking it is a group,
5181 then insist on finding a group. Otherwise we can grab a
5182 reg that some other reload needs.
5183 (That can happen when we have a 68000 DATA_OR_FP_REG
5184 which is a group of data regs or one fp reg.)
5185 We need not be so restrictive if there are no more reloads
5188 ??? Really it would be nicer to have smarter handling
5189 for that kind of reg class, where a problem like this is normal.
5190 Perhaps those classes should be avoided for reloading
5191 by use of more alternatives. */
5193 int force_group = rld[r].nregs > 1 && ! last_reload;
5195 /* If we want a single register and haven't yet found one,
5196 take any reg in the right class and not in use.
5197 If we want a consecutive group, here is where we look for it.
5199 We use two passes so we can first look for reload regs to
5200 reuse, which are already in use for other reloads in this insn,
5201 and only then use additional registers.
5202 I think that maximizing reuse is needed to make sure we don't
5203 run out of reload regs. Suppose we have three reloads, and
5204 reloads A and B can share regs. These need two regs.
5205 Suppose A and B are given different regs.
5206 That leaves none for C. */
5207 for (pass = 0; pass < 2; pass++)
5209 /* I is the index in spill_regs.
5210 We advance it round-robin between insns to use all spill regs
5211 equally, so that inherited reloads have a chance
5212 of leapfrogging each other. */
5216 for (count = 0; count < n_spills; count++)
5218 int class = (int) rld[r].class;
5224 regnum = spill_regs[i];
5226 if ((reload_reg_free_p (regnum, rld[r].opnum,
5229 /* We check reload_reg_used to make sure we
5230 don't clobber the return register. */
5231 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5232 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5233 rld[r].when_needed, rld[r].in,
5235 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5236 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5237 /* Look first for regs to share, then for unshared. But
5238 don't share regs used for inherited reloads; they are
5239 the ones we want to preserve. */
5241 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5243 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5246 int nr = hard_regno_nregs[regnum][rld[r].mode];
5247 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5248 (on 68000) got us two FP regs. If NR is 1,
5249 we would reject both of them. */
5252 /* If we need only one reg, we have already won. */
5255 /* But reject a single reg if we demand a group. */
5260 /* Otherwise check that as many consecutive regs as we need
5261 are available here. */
5264 int regno = regnum + nr - 1;
5265 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5266 && spill_reg_order[regno] >= 0
5267 && reload_reg_free_p (regno, rld[r].opnum,
5268 rld[r].when_needed)))
5277 /* If we found something on pass 1, omit pass 2. */
5278 if (count < n_spills)
5282 /* We should have found a spill register by now. */
5283 if (count >= n_spills)
5286 /* I is the index in SPILL_REG_RTX of the reload register we are to
5287 allocate. Get an rtx for it and find its register number. */
5289 return set_reload_reg (i, r);
5292 /* Initialize all the tables needed to allocate reload registers.
5293 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5294 is the array we use to restore the reg_rtx field for every reload. */
5297 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5301 for (i = 0; i < n_reloads; i++)
5302 rld[i].reg_rtx = save_reload_reg_rtx[i];
5304 memset (reload_inherited, 0, MAX_RELOADS);
5305 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5306 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5308 CLEAR_HARD_REG_SET (reload_reg_used);
5309 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5310 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5311 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5312 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5313 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5315 CLEAR_HARD_REG_SET (reg_used_in_insn);
5318 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5319 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5320 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5321 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5322 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5323 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5326 for (i = 0; i < reload_n_operands; i++)
5328 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5329 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5330 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5331 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5332 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5333 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5336 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5338 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5340 for (i = 0; i < n_reloads; i++)
5341 /* If we have already decided to use a certain register,
5342 don't use it in another way. */
5344 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5345 rld[i].when_needed, rld[i].mode);
5348 /* Assign hard reg targets for the pseudo-registers we must reload
5349 into hard regs for this insn.
5350 Also output the instructions to copy them in and out of the hard regs.
5352 For machines with register classes, we are responsible for
5353 finding a reload reg in the proper class. */
5356 choose_reload_regs (struct insn_chain *chain)
5358 rtx insn = chain->insn;
5360 unsigned int max_group_size = 1;
5361 enum reg_class group_class = NO_REGS;
5362 int pass, win, inheritance;
5364 rtx save_reload_reg_rtx[MAX_RELOADS];
5366 /* In order to be certain of getting the registers we need,
5367 we must sort the reloads into order of increasing register class.
5368 Then our grabbing of reload registers will parallel the process
5369 that provided the reload registers.
5371 Also note whether any of the reloads wants a consecutive group of regs.
5372 If so, record the maximum size of the group desired and what
5373 register class contains all the groups needed by this insn. */
5375 for (j = 0; j < n_reloads; j++)
5377 reload_order[j] = j;
5378 reload_spill_index[j] = -1;
5380 if (rld[j].nregs > 1)
5382 max_group_size = MAX (rld[j].nregs, max_group_size);
5384 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5387 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5391 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5393 /* If -O, try first with inheritance, then turning it off.
5394 If not -O, don't do inheritance.
5395 Using inheritance when not optimizing leads to paradoxes
5396 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5397 because one side of the comparison might be inherited. */
5399 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5401 choose_reload_regs_init (chain, save_reload_reg_rtx);
5403 /* Process the reloads in order of preference just found.
5404 Beyond this point, subregs can be found in reload_reg_rtx.
5406 This used to look for an existing reloaded home for all of the
5407 reloads, and only then perform any new reloads. But that could lose
5408 if the reloads were done out of reg-class order because a later
5409 reload with a looser constraint might have an old home in a register
5410 needed by an earlier reload with a tighter constraint.
5412 To solve this, we make two passes over the reloads, in the order
5413 described above. In the first pass we try to inherit a reload
5414 from a previous insn. If there is a later reload that needs a
5415 class that is a proper subset of the class being processed, we must
5416 also allocate a spill register during the first pass.
5418 Then make a second pass over the reloads to allocate any reloads
5419 that haven't been given registers yet. */
5421 for (j = 0; j < n_reloads; j++)
5423 int r = reload_order[j];
5424 rtx search_equiv = NULL_RTX;
5426 /* Ignore reloads that got marked inoperative. */
5427 if (rld[r].out == 0 && rld[r].in == 0
5428 && ! rld[r].secondary_p)
5431 /* If find_reloads chose to use reload_in or reload_out as a reload
5432 register, we don't need to chose one. Otherwise, try even if it
5433 found one since we might save an insn if we find the value lying
5435 Try also when reload_in is a pseudo without a hard reg. */
5436 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5437 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5438 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5439 && !MEM_P (rld[r].in)
5440 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5443 #if 0 /* No longer needed for correct operation.
5444 It might give better code, or might not; worth an experiment? */
5445 /* If this is an optional reload, we can't inherit from earlier insns
5446 until we are sure that any non-optional reloads have been allocated.
5447 The following code takes advantage of the fact that optional reloads
5448 are at the end of reload_order. */
5449 if (rld[r].optional != 0)
5450 for (i = 0; i < j; i++)
5451 if ((rld[reload_order[i]].out != 0
5452 || rld[reload_order[i]].in != 0
5453 || rld[reload_order[i]].secondary_p)
5454 && ! rld[reload_order[i]].optional
5455 && rld[reload_order[i]].reg_rtx == 0)
5456 allocate_reload_reg (chain, reload_order[i], 0);
5459 /* First see if this pseudo is already available as reloaded
5460 for a previous insn. We cannot try to inherit for reloads
5461 that are smaller than the maximum number of registers needed
5462 for groups unless the register we would allocate cannot be used
5465 We could check here to see if this is a secondary reload for
5466 an object that is already in a register of the desired class.
5467 This would avoid the need for the secondary reload register.
5468 But this is complex because we can't easily determine what
5469 objects might want to be loaded via this reload. So let a
5470 register be allocated here. In `emit_reload_insns' we suppress
5471 one of the loads in the case described above. */
5477 enum machine_mode mode = VOIDmode;
5481 else if (REG_P (rld[r].in))
5483 regno = REGNO (rld[r].in);
5484 mode = GET_MODE (rld[r].in);
5486 else if (REG_P (rld[r].in_reg))
5488 regno = REGNO (rld[r].in_reg);
5489 mode = GET_MODE (rld[r].in_reg);
5491 else if (GET_CODE (rld[r].in_reg) == SUBREG
5492 && REG_P (SUBREG_REG (rld[r].in_reg)))
5494 byte = SUBREG_BYTE (rld[r].in_reg);
5495 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5496 if (regno < FIRST_PSEUDO_REGISTER)
5497 regno = subreg_regno (rld[r].in_reg);
5498 mode = GET_MODE (rld[r].in_reg);
5501 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5502 || GET_CODE (rld[r].in_reg) == PRE_DEC
5503 || GET_CODE (rld[r].in_reg) == POST_INC
5504 || GET_CODE (rld[r].in_reg) == POST_DEC)
5505 && REG_P (XEXP (rld[r].in_reg, 0)))
5507 regno = REGNO (XEXP (rld[r].in_reg, 0));
5508 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5509 rld[r].out = rld[r].in;
5513 /* This won't work, since REGNO can be a pseudo reg number.
5514 Also, it takes much more hair to keep track of all the things
5515 that can invalidate an inherited reload of part of a pseudoreg. */
5516 else if (GET_CODE (rld[r].in) == SUBREG
5517 && REG_P (SUBREG_REG (rld[r].in)))
5518 regno = subreg_regno (rld[r].in);
5521 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5523 enum reg_class class = rld[r].class, last_class;
5524 rtx last_reg = reg_last_reload_reg[regno];
5525 enum machine_mode need_mode;
5527 i = REGNO (last_reg);
5528 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5529 last_class = REGNO_REG_CLASS (i);
5535 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5536 + byte * BITS_PER_UNIT,
5537 GET_MODE_CLASS (mode));
5539 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5540 >= GET_MODE_SIZE (need_mode))
5541 #ifdef CANNOT_CHANGE_MODE_CLASS
5542 /* Verify that the register in "i" can be obtained
5544 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5545 GET_MODE (last_reg),
5548 && reg_reloaded_contents[i] == regno
5549 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5550 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5551 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5552 /* Even if we can't use this register as a reload
5553 register, we might use it for reload_override_in,
5554 if copying it to the desired class is cheap
5556 || ((REGISTER_MOVE_COST (mode, last_class, class)
5557 < MEMORY_MOVE_COST (mode, class, 1))
5558 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5559 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5563 #ifdef SECONDARY_MEMORY_NEEDED
5564 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5569 && (rld[r].nregs == max_group_size
5570 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5572 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5573 rld[r].when_needed, rld[r].in,
5576 /* If a group is needed, verify that all the subsequent
5577 registers still have their values intact. */
5578 int nr = hard_regno_nregs[i][rld[r].mode];
5581 for (k = 1; k < nr; k++)
5582 if (reg_reloaded_contents[i + k] != regno
5583 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5591 last_reg = (GET_MODE (last_reg) == mode
5592 ? last_reg : gen_rtx_REG (mode, i));
5595 for (k = 0; k < nr; k++)
5596 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5599 /* We found a register that contains the
5600 value we need. If this register is the
5601 same as an `earlyclobber' operand of the
5602 current insn, just mark it as a place to
5603 reload from since we can't use it as the
5604 reload register itself. */
5606 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5607 if (reg_overlap_mentioned_for_reload_p
5608 (reg_last_reload_reg[regno],
5609 reload_earlyclobbers[i1]))
5612 if (i1 != n_earlyclobbers
5613 || ! (free_for_value_p (i, rld[r].mode,
5615 rld[r].when_needed, rld[r].in,
5617 /* Don't use it if we'd clobber a pseudo reg. */
5618 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5620 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5621 /* Don't clobber the frame pointer. */
5622 || (i == HARD_FRAME_POINTER_REGNUM
5623 && frame_pointer_needed
5625 /* Don't really use the inherited spill reg
5626 if we need it wider than we've got it. */
5627 || (GET_MODE_SIZE (rld[r].mode)
5628 > GET_MODE_SIZE (mode))
5631 /* If find_reloads chose reload_out as reload
5632 register, stay with it - that leaves the
5633 inherited register for subsequent reloads. */
5634 || (rld[r].out && rld[r].reg_rtx
5635 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5637 if (! rld[r].optional)
5639 reload_override_in[r] = last_reg;
5640 reload_inheritance_insn[r]
5641 = reg_reloaded_insn[i];
5647 /* We can use this as a reload reg. */
5648 /* Mark the register as in use for this part of
5650 mark_reload_reg_in_use (i,
5654 rld[r].reg_rtx = last_reg;
5655 reload_inherited[r] = 1;
5656 reload_inheritance_insn[r]
5657 = reg_reloaded_insn[i];
5658 reload_spill_index[r] = i;
5659 for (k = 0; k < nr; k++)
5660 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5668 /* Here's another way to see if the value is already lying around. */
5671 && ! reload_inherited[r]
5673 && (CONSTANT_P (rld[r].in)
5674 || GET_CODE (rld[r].in) == PLUS
5675 || REG_P (rld[r].in)
5676 || MEM_P (rld[r].in))
5677 && (rld[r].nregs == max_group_size
5678 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5679 search_equiv = rld[r].in;
5680 /* If this is an output reload from a simple move insn, look
5681 if an equivalence for the input is available. */
5682 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5684 rtx set = single_set (insn);
5687 && rtx_equal_p (rld[r].out, SET_DEST (set))
5688 && CONSTANT_P (SET_SRC (set)))
5689 search_equiv = SET_SRC (set);
5695 = find_equiv_reg (search_equiv, insn, rld[r].class,
5696 -1, NULL, 0, rld[r].mode);
5702 regno = REGNO (equiv);
5705 /* This must be a SUBREG of a hard register.
5706 Make a new REG since this might be used in an
5707 address and not all machines support SUBREGs
5709 gcc_assert (GET_CODE (equiv) == SUBREG);
5710 regno = subreg_regno (equiv);
5711 equiv = gen_rtx_REG (rld[r].mode, regno);
5712 /* If we choose EQUIV as the reload register, but the
5713 loop below decides to cancel the inheritance, we'll
5714 end up reloading EQUIV in rld[r].mode, not the mode
5715 it had originally. That isn't safe when EQUIV isn't
5716 available as a spill register since its value might
5717 still be live at this point. */
5718 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5719 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5724 /* If we found a spill reg, reject it unless it is free
5725 and of the desired class. */
5729 int bad_for_class = 0;
5730 int max_regno = regno + rld[r].nregs;
5732 for (i = regno; i < max_regno; i++)
5734 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5736 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5741 && ! free_for_value_p (regno, rld[r].mode,
5742 rld[r].opnum, rld[r].when_needed,
5743 rld[r].in, rld[r].out, r, 1))
5748 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5751 /* We found a register that contains the value we need.
5752 If this register is the same as an `earlyclobber' operand
5753 of the current insn, just mark it as a place to reload from
5754 since we can't use it as the reload register itself. */
5757 for (i = 0; i < n_earlyclobbers; i++)
5758 if (reg_overlap_mentioned_for_reload_p (equiv,
5759 reload_earlyclobbers[i]))
5761 if (! rld[r].optional)
5762 reload_override_in[r] = equiv;
5767 /* If the equiv register we have found is explicitly clobbered
5768 in the current insn, it depends on the reload type if we
5769 can use it, use it for reload_override_in, or not at all.
5770 In particular, we then can't use EQUIV for a
5771 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5775 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5776 switch (rld[r].when_needed)
5778 case RELOAD_FOR_OTHER_ADDRESS:
5779 case RELOAD_FOR_INPADDR_ADDRESS:
5780 case RELOAD_FOR_INPUT_ADDRESS:
5781 case RELOAD_FOR_OPADDR_ADDR:
5784 case RELOAD_FOR_INPUT:
5785 case RELOAD_FOR_OPERAND_ADDRESS:
5786 if (! rld[r].optional)
5787 reload_override_in[r] = equiv;
5793 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5794 switch (rld[r].when_needed)
5796 case RELOAD_FOR_OTHER_ADDRESS:
5797 case RELOAD_FOR_INPADDR_ADDRESS:
5798 case RELOAD_FOR_INPUT_ADDRESS:
5799 case RELOAD_FOR_OPADDR_ADDR:
5800 case RELOAD_FOR_OPERAND_ADDRESS:
5801 case RELOAD_FOR_INPUT:
5804 if (! rld[r].optional)
5805 reload_override_in[r] = equiv;
5813 /* If we found an equivalent reg, say no code need be generated
5814 to load it, and use it as our reload reg. */
5816 && (regno != HARD_FRAME_POINTER_REGNUM
5817 || !frame_pointer_needed))
5819 int nr = hard_regno_nregs[regno][rld[r].mode];
5821 rld[r].reg_rtx = equiv;
5822 reload_inherited[r] = 1;
5824 /* If reg_reloaded_valid is not set for this register,
5825 there might be a stale spill_reg_store lying around.
5826 We must clear it, since otherwise emit_reload_insns
5827 might delete the store. */
5828 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5829 spill_reg_store[regno] = NULL_RTX;
5830 /* If any of the hard registers in EQUIV are spill
5831 registers, mark them as in use for this insn. */
5832 for (k = 0; k < nr; k++)
5834 i = spill_reg_order[regno + k];
5837 mark_reload_reg_in_use (regno, rld[r].opnum,
5840 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5847 /* If we found a register to use already, or if this is an optional
5848 reload, we are done. */
5849 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5853 /* No longer needed for correct operation. Might or might
5854 not give better code on the average. Want to experiment? */
5856 /* See if there is a later reload that has a class different from our
5857 class that intersects our class or that requires less register
5858 than our reload. If so, we must allocate a register to this
5859 reload now, since that reload might inherit a previous reload
5860 and take the only available register in our class. Don't do this
5861 for optional reloads since they will force all previous reloads
5862 to be allocated. Also don't do this for reloads that have been
5865 for (i = j + 1; i < n_reloads; i++)
5867 int s = reload_order[i];
5869 if ((rld[s].in == 0 && rld[s].out == 0
5870 && ! rld[s].secondary_p)
5874 if ((rld[s].class != rld[r].class
5875 && reg_classes_intersect_p (rld[r].class,
5877 || rld[s].nregs < rld[r].nregs)
5884 allocate_reload_reg (chain, r, j == n_reloads - 1);
5888 /* Now allocate reload registers for anything non-optional that
5889 didn't get one yet. */
5890 for (j = 0; j < n_reloads; j++)
5892 int r = reload_order[j];
5894 /* Ignore reloads that got marked inoperative. */
5895 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5898 /* Skip reloads that already have a register allocated or are
5900 if (rld[r].reg_rtx != 0 || rld[r].optional)
5903 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5907 /* If that loop got all the way, we have won. */
5914 /* Loop around and try without any inheritance. */
5919 /* First undo everything done by the failed attempt
5920 to allocate with inheritance. */
5921 choose_reload_regs_init (chain, save_reload_reg_rtx);
5923 /* Some sanity tests to verify that the reloads found in the first
5924 pass are identical to the ones we have now. */
5925 gcc_assert (chain->n_reloads == n_reloads);
5927 for (i = 0; i < n_reloads; i++)
5929 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5931 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5932 for (j = 0; j < n_spills; j++)
5933 if (spill_regs[j] == chain->rld[i].regno)
5934 if (! set_reload_reg (j, i))
5935 failed_reload (chain->insn, i);
5939 /* If we thought we could inherit a reload, because it seemed that
5940 nothing else wanted the same reload register earlier in the insn,
5941 verify that assumption, now that all reloads have been assigned.
5942 Likewise for reloads where reload_override_in has been set. */
5944 /* If doing expensive optimizations, do one preliminary pass that doesn't
5945 cancel any inheritance, but removes reloads that have been needed only
5946 for reloads that we know can be inherited. */
5947 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5949 for (j = 0; j < n_reloads; j++)
5951 int r = reload_order[j];
5953 if (reload_inherited[r] && rld[r].reg_rtx)
5954 check_reg = rld[r].reg_rtx;
5955 else if (reload_override_in[r]
5956 && (REG_P (reload_override_in[r])
5957 || GET_CODE (reload_override_in[r]) == SUBREG))
5958 check_reg = reload_override_in[r];
5961 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5962 rld[r].opnum, rld[r].when_needed, rld[r].in,
5963 (reload_inherited[r]
5964 ? rld[r].out : const0_rtx),
5969 reload_inherited[r] = 0;
5970 reload_override_in[r] = 0;
5972 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5973 reload_override_in, then we do not need its related
5974 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5975 likewise for other reload types.
5976 We handle this by removing a reload when its only replacement
5977 is mentioned in reload_in of the reload we are going to inherit.
5978 A special case are auto_inc expressions; even if the input is
5979 inherited, we still need the address for the output. We can
5980 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5981 If we succeeded removing some reload and we are doing a preliminary
5982 pass just to remove such reloads, make another pass, since the
5983 removal of one reload might allow us to inherit another one. */
5985 && rld[r].out != rld[r].in
5986 && remove_address_replacements (rld[r].in) && pass)
5991 /* Now that reload_override_in is known valid,
5992 actually override reload_in. */
5993 for (j = 0; j < n_reloads; j++)
5994 if (reload_override_in[j])
5995 rld[j].in = reload_override_in[j];
5997 /* If this reload won't be done because it has been canceled or is
5998 optional and not inherited, clear reload_reg_rtx so other
5999 routines (such as subst_reloads) don't get confused. */
6000 for (j = 0; j < n_reloads; j++)
6001 if (rld[j].reg_rtx != 0
6002 && ((rld[j].optional && ! reload_inherited[j])
6003 || (rld[j].in == 0 && rld[j].out == 0
6004 && ! rld[j].secondary_p)))
6006 int regno = true_regnum (rld[j].reg_rtx);
6008 if (spill_reg_order[regno] >= 0)
6009 clear_reload_reg_in_use (regno, rld[j].opnum,
6010 rld[j].when_needed, rld[j].mode);
6012 reload_spill_index[j] = -1;
6015 /* Record which pseudos and which spill regs have output reloads. */
6016 for (j = 0; j < n_reloads; j++)
6018 int r = reload_order[j];
6020 i = reload_spill_index[r];
6022 /* I is nonneg if this reload uses a register.
6023 If rld[r].reg_rtx is 0, this is an optional reload
6024 that we opted to ignore. */
6025 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6026 && rld[r].reg_rtx != 0)
6028 int nregno = REGNO (rld[r].out_reg);
6031 if (nregno < FIRST_PSEUDO_REGISTER)
6032 nr = hard_regno_nregs[nregno][rld[r].mode];
6035 reg_has_output_reload[nregno + nr] = 1;
6039 nr = hard_regno_nregs[i][rld[r].mode];
6041 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6044 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6045 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6046 || rld[r].when_needed == RELOAD_FOR_INSN);
6051 /* Deallocate the reload register for reload R. This is called from
6052 remove_address_replacements. */
6055 deallocate_reload_reg (int r)
6059 if (! rld[r].reg_rtx)
6061 regno = true_regnum (rld[r].reg_rtx);
6063 if (spill_reg_order[regno] >= 0)
6064 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6066 reload_spill_index[r] = -1;
6069 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6070 reloads of the same item for fear that we might not have enough reload
6071 registers. However, normally they will get the same reload register
6072 and hence actually need not be loaded twice.
6074 Here we check for the most common case of this phenomenon: when we have
6075 a number of reloads for the same object, each of which were allocated
6076 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6077 reload, and is not modified in the insn itself. If we find such,
6078 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6079 This will not increase the number of spill registers needed and will
6080 prevent redundant code. */
6083 merge_assigned_reloads (rtx insn)
6087 /* Scan all the reloads looking for ones that only load values and
6088 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6089 assigned and not modified by INSN. */
6091 for (i = 0; i < n_reloads; i++)
6093 int conflicting_input = 0;
6094 int max_input_address_opnum = -1;
6095 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6097 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6098 || rld[i].out != 0 || rld[i].reg_rtx == 0
6099 || reg_set_p (rld[i].reg_rtx, insn))
6102 /* Look at all other reloads. Ensure that the only use of this
6103 reload_reg_rtx is in a reload that just loads the same value
6104 as we do. Note that any secondary reloads must be of the identical
6105 class since the values, modes, and result registers are the
6106 same, so we need not do anything with any secondary reloads. */
6108 for (j = 0; j < n_reloads; j++)
6110 if (i == j || rld[j].reg_rtx == 0
6111 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6115 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6116 && rld[j].opnum > max_input_address_opnum)
6117 max_input_address_opnum = rld[j].opnum;
6119 /* If the reload regs aren't exactly the same (e.g, different modes)
6120 or if the values are different, we can't merge this reload.
6121 But if it is an input reload, we might still merge
6122 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6124 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6125 || rld[j].out != 0 || rld[j].in == 0
6126 || ! rtx_equal_p (rld[i].in, rld[j].in))
6128 if (rld[j].when_needed != RELOAD_FOR_INPUT
6129 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6130 || rld[i].opnum > rld[j].opnum)
6131 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6133 conflicting_input = 1;
6134 if (min_conflicting_input_opnum > rld[j].opnum)
6135 min_conflicting_input_opnum = rld[j].opnum;
6139 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6140 we, in fact, found any matching reloads. */
6143 && max_input_address_opnum <= min_conflicting_input_opnum)
6145 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6147 for (j = 0; j < n_reloads; j++)
6148 if (i != j && rld[j].reg_rtx != 0
6149 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6150 && (! conflicting_input
6151 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6152 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6154 rld[i].when_needed = RELOAD_OTHER;
6156 reload_spill_index[j] = -1;
6157 transfer_replacements (i, j);
6160 /* If this is now RELOAD_OTHER, look for any reloads that load
6161 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6162 if they were for inputs, RELOAD_OTHER for outputs. Note that
6163 this test is equivalent to looking for reloads for this operand
6165 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6166 share registers with a RELOAD_FOR_INPUT, so we can not change it
6167 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6168 do not modify RELOAD_FOR_OUTPUT. */
6170 if (rld[i].when_needed == RELOAD_OTHER)
6171 for (j = 0; j < n_reloads; j++)
6173 && rld[j].when_needed != RELOAD_OTHER
6174 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6175 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6176 && (! conflicting_input
6177 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6178 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6179 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6185 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6186 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6187 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6189 /* Check to see if we accidentally converted two
6190 reloads that use the same reload register with
6191 different inputs to the same type. If so, the
6192 resulting code won't work. */
6194 for (k = 0; k < j; k++)
6195 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6196 || rld[k].when_needed != rld[j].when_needed
6197 || !rtx_equal_p (rld[k].reg_rtx,
6199 || rtx_equal_p (rld[k].in,
6206 /* These arrays are filled by emit_reload_insns and its subroutines. */
6207 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6208 static rtx other_input_address_reload_insns = 0;
6209 static rtx other_input_reload_insns = 0;
6210 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6211 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6212 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6213 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6214 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6215 static rtx operand_reload_insns = 0;
6216 static rtx other_operand_reload_insns = 0;
6217 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6219 /* Values to be put in spill_reg_store are put here first. */
6220 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6221 static HARD_REG_SET reg_reloaded_died;
6223 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6224 has the number J. OLD contains the value to be used as input. */
6227 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6230 rtx insn = chain->insn;
6231 rtx reloadreg = rl->reg_rtx;
6232 rtx oldequiv_reg = 0;
6235 enum machine_mode mode;
6238 /* Determine the mode to reload in.
6239 This is very tricky because we have three to choose from.
6240 There is the mode the insn operand wants (rl->inmode).
6241 There is the mode of the reload register RELOADREG.
6242 There is the intrinsic mode of the operand, which we could find
6243 by stripping some SUBREGs.
6244 It turns out that RELOADREG's mode is irrelevant:
6245 we can change that arbitrarily.
6247 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6248 then the reload reg may not support QImode moves, so use SImode.
6249 If foo is in memory due to spilling a pseudo reg, this is safe,
6250 because the QImode value is in the least significant part of a
6251 slot big enough for a SImode. If foo is some other sort of
6252 memory reference, then it is impossible to reload this case,
6253 so previous passes had better make sure this never happens.
6255 Then consider a one-word union which has SImode and one of its
6256 members is a float, being fetched as (SUBREG:SF union:SI).
6257 We must fetch that as SFmode because we could be loading into
6258 a float-only register. In this case OLD's mode is correct.
6260 Consider an immediate integer: it has VOIDmode. Here we need
6261 to get a mode from something else.
6263 In some cases, there is a fourth mode, the operand's
6264 containing mode. If the insn specifies a containing mode for
6265 this operand, it overrides all others.
6267 I am not sure whether the algorithm here is always right,
6268 but it does the right things in those cases. */
6270 mode = GET_MODE (old);
6271 if (mode == VOIDmode)
6274 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6275 /* If we need a secondary register for this operation, see if
6276 the value is already in a register in that class. Don't
6277 do this if the secondary register will be used as a scratch
6280 if (rl->secondary_in_reload >= 0
6281 && rl->secondary_in_icode == CODE_FOR_nothing
6284 = find_equiv_reg (old, insn,
6285 rld[rl->secondary_in_reload].class,
6289 /* If reloading from memory, see if there is a register
6290 that already holds the same value. If so, reload from there.
6291 We can pass 0 as the reload_reg_p argument because
6292 any other reload has either already been emitted,
6293 in which case find_equiv_reg will see the reload-insn,
6294 or has yet to be emitted, in which case it doesn't matter
6295 because we will use this equiv reg right away. */
6297 if (oldequiv == 0 && optimize
6300 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6301 && reg_renumber[REGNO (old)] < 0)))
6302 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6306 unsigned int regno = true_regnum (oldequiv);
6308 /* Don't use OLDEQUIV if any other reload changes it at an
6309 earlier stage of this insn or at this stage. */
6310 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6311 rl->in, const0_rtx, j, 0))
6314 /* If it is no cheaper to copy from OLDEQUIV into the
6315 reload register than it would be to move from memory,
6316 don't use it. Likewise, if we need a secondary register
6320 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6321 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6323 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6324 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6325 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6329 #ifdef SECONDARY_MEMORY_NEEDED
6330 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6338 /* delete_output_reload is only invoked properly if old contains
6339 the original pseudo register. Since this is replaced with a
6340 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6341 find the pseudo in RELOAD_IN_REG. */
6343 && reload_override_in[j]
6344 && REG_P (rl->in_reg))
6351 else if (REG_P (oldequiv))
6352 oldequiv_reg = oldequiv;
6353 else if (GET_CODE (oldequiv) == SUBREG)
6354 oldequiv_reg = SUBREG_REG (oldequiv);
6356 /* If we are reloading from a register that was recently stored in
6357 with an output-reload, see if we can prove there was
6358 actually no need to store the old value in it. */
6360 if (optimize && REG_P (oldequiv)
6361 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6362 && spill_reg_store[REGNO (oldequiv)]
6364 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6365 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6367 delete_output_reload (insn, j, REGNO (oldequiv));
6369 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6370 then load RELOADREG from OLDEQUIV. Note that we cannot use
6371 gen_lowpart_common since it can do the wrong thing when
6372 RELOADREG has a multi-word mode. Note that RELOADREG
6373 must always be a REG here. */
6375 if (GET_MODE (reloadreg) != mode)
6376 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6377 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6378 oldequiv = SUBREG_REG (oldequiv);
6379 if (GET_MODE (oldequiv) != VOIDmode
6380 && mode != GET_MODE (oldequiv))
6381 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6383 /* Switch to the right place to emit the reload insns. */
6384 switch (rl->when_needed)
6387 where = &other_input_reload_insns;
6389 case RELOAD_FOR_INPUT:
6390 where = &input_reload_insns[rl->opnum];
6392 case RELOAD_FOR_INPUT_ADDRESS:
6393 where = &input_address_reload_insns[rl->opnum];
6395 case RELOAD_FOR_INPADDR_ADDRESS:
6396 where = &inpaddr_address_reload_insns[rl->opnum];
6398 case RELOAD_FOR_OUTPUT_ADDRESS:
6399 where = &output_address_reload_insns[rl->opnum];
6401 case RELOAD_FOR_OUTADDR_ADDRESS:
6402 where = &outaddr_address_reload_insns[rl->opnum];
6404 case RELOAD_FOR_OPERAND_ADDRESS:
6405 where = &operand_reload_insns;
6407 case RELOAD_FOR_OPADDR_ADDR:
6408 where = &other_operand_reload_insns;
6410 case RELOAD_FOR_OTHER_ADDRESS:
6411 where = &other_input_address_reload_insns;
6417 push_to_sequence (*where);
6419 /* Auto-increment addresses must be reloaded in a special way. */
6420 if (rl->out && ! rl->out_reg)
6422 /* We are not going to bother supporting the case where a
6423 incremented register can't be copied directly from
6424 OLDEQUIV since this seems highly unlikely. */
6425 gcc_assert (rl->secondary_in_reload < 0);
6427 if (reload_inherited[j])
6428 oldequiv = reloadreg;
6430 old = XEXP (rl->in_reg, 0);
6432 if (optimize && REG_P (oldequiv)
6433 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6434 && spill_reg_store[REGNO (oldequiv)]
6436 && (dead_or_set_p (insn,
6437 spill_reg_stored_to[REGNO (oldequiv)])
6438 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6440 delete_output_reload (insn, j, REGNO (oldequiv));
6442 /* Prevent normal processing of this reload. */
6444 /* Output a special code sequence for this case. */
6445 new_spill_reg_store[REGNO (reloadreg)]
6446 = inc_for_reload (reloadreg, oldequiv, rl->out,
6450 /* If we are reloading a pseudo-register that was set by the previous
6451 insn, see if we can get rid of that pseudo-register entirely
6452 by redirecting the previous insn into our reload register. */
6454 else if (optimize && REG_P (old)
6455 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6456 && dead_or_set_p (insn, old)
6457 /* This is unsafe if some other reload
6458 uses the same reg first. */
6459 && ! conflicts_with_override (reloadreg)
6460 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6461 rl->when_needed, old, rl->out, j, 0))
6463 rtx temp = PREV_INSN (insn);
6464 while (temp && NOTE_P (temp))
6465 temp = PREV_INSN (temp);
6467 && NONJUMP_INSN_P (temp)
6468 && GET_CODE (PATTERN (temp)) == SET
6469 && SET_DEST (PATTERN (temp)) == old
6470 /* Make sure we can access insn_operand_constraint. */
6471 && asm_noperands (PATTERN (temp)) < 0
6472 /* This is unsafe if operand occurs more than once in current
6473 insn. Perhaps some occurrences aren't reloaded. */
6474 && count_occurrences (PATTERN (insn), old, 0) == 1)
6476 rtx old = SET_DEST (PATTERN (temp));
6477 /* Store into the reload register instead of the pseudo. */
6478 SET_DEST (PATTERN (temp)) = reloadreg;
6480 /* Verify that resulting insn is valid. */
6481 extract_insn (temp);
6482 if (constrain_operands (1))
6484 /* If the previous insn is an output reload, the source is
6485 a reload register, and its spill_reg_store entry will
6486 contain the previous destination. This is now
6488 if (REG_P (SET_SRC (PATTERN (temp)))
6489 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6491 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6492 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6495 /* If these are the only uses of the pseudo reg,
6496 pretend for GDB it lives in the reload reg we used. */
6497 if (REG_N_DEATHS (REGNO (old)) == 1
6498 && REG_N_SETS (REGNO (old)) == 1)
6500 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6501 alter_reg (REGNO (old), -1);
6507 SET_DEST (PATTERN (temp)) = old;
6512 /* We can't do that, so output an insn to load RELOADREG. */
6514 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6515 /* If we have a secondary reload, pick up the secondary register
6516 and icode, if any. If OLDEQUIV and OLD are different or
6517 if this is an in-out reload, recompute whether or not we
6518 still need a secondary register and what the icode should
6519 be. If we still need a secondary register and the class or
6520 icode is different, go back to reloading from OLD if using
6521 OLDEQUIV means that we got the wrong type of register. We
6522 cannot have different class or icode due to an in-out reload
6523 because we don't make such reloads when both the input and
6524 output need secondary reload registers. */
6526 if (! special && rl->secondary_in_reload >= 0)
6528 rtx second_reload_reg = 0;
6529 int secondary_reload = rl->secondary_in_reload;
6530 rtx real_oldequiv = oldequiv;
6533 enum insn_code icode;
6535 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6536 and similarly for OLD.
6537 See comments in get_secondary_reload in reload.c. */
6538 /* If it is a pseudo that cannot be replaced with its
6539 equivalent MEM, we must fall back to reload_in, which
6540 will have all the necessary substitutions registered.
6541 Likewise for a pseudo that can't be replaced with its
6542 equivalent constant.
6544 Take extra care for subregs of such pseudos. Note that
6545 we cannot use reg_equiv_mem in this case because it is
6546 not in the right mode. */
6549 if (GET_CODE (tmp) == SUBREG)
6550 tmp = SUBREG_REG (tmp);
6552 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6553 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6554 || reg_equiv_constant[REGNO (tmp)] != 0))
6556 if (! reg_equiv_mem[REGNO (tmp)]
6557 || num_not_at_initial_offset
6558 || GET_CODE (oldequiv) == SUBREG)
6559 real_oldequiv = rl->in;
6561 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6565 if (GET_CODE (tmp) == SUBREG)
6566 tmp = SUBREG_REG (tmp);
6568 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6569 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6570 || reg_equiv_constant[REGNO (tmp)] != 0))
6572 if (! reg_equiv_mem[REGNO (tmp)]
6573 || num_not_at_initial_offset
6574 || GET_CODE (old) == SUBREG)
6577 real_old = reg_equiv_mem[REGNO (tmp)];
6580 second_reload_reg = rld[secondary_reload].reg_rtx;
6581 icode = rl->secondary_in_icode;
6583 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6584 || (rl->in != 0 && rl->out != 0))
6586 enum reg_class new_class
6587 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6588 mode, real_oldequiv);
6590 if (new_class == NO_REGS)
6591 second_reload_reg = 0;
6594 enum insn_code new_icode;
6595 enum machine_mode new_mode;
6597 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6598 REGNO (second_reload_reg)))
6599 oldequiv = old, real_oldequiv = real_old;
6602 new_icode = reload_in_optab[(int) mode];
6603 if (new_icode != CODE_FOR_nothing
6604 && ((insn_data[(int) new_icode].operand[0].predicate
6605 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6607 || (insn_data[(int) new_icode].operand[1].predicate
6608 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6609 (real_oldequiv, mode)))))
6610 new_icode = CODE_FOR_nothing;
6612 if (new_icode == CODE_FOR_nothing)
6615 new_mode = insn_data[(int) new_icode].operand[2].mode;
6617 if (GET_MODE (second_reload_reg) != new_mode)
6619 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6621 oldequiv = old, real_oldequiv = real_old;
6624 = reload_adjust_reg_for_mode (second_reload_reg,
6631 /* If we still need a secondary reload register, check
6632 to see if it is being used as a scratch or intermediate
6633 register and generate code appropriately. If we need
6634 a scratch register, use REAL_OLDEQUIV since the form of
6635 the insn may depend on the actual address if it is
6638 if (second_reload_reg)
6640 if (icode != CODE_FOR_nothing)
6642 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6643 second_reload_reg));
6648 /* See if we need a scratch register to load the
6649 intermediate register (a tertiary reload). */
6650 enum insn_code tertiary_icode
6651 = rld[secondary_reload].secondary_in_icode;
6653 if (tertiary_icode != CODE_FOR_nothing)
6655 rtx third_reload_reg
6656 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6658 emit_insn ((GEN_FCN (tertiary_icode)
6659 (second_reload_reg, real_oldequiv,
6660 third_reload_reg)));
6663 gen_reload (second_reload_reg, real_oldequiv,
6667 oldequiv = second_reload_reg;
6673 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6675 rtx real_oldequiv = oldequiv;
6677 if ((REG_P (oldequiv)
6678 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6679 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6680 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6681 || (GET_CODE (oldequiv) == SUBREG
6682 && REG_P (SUBREG_REG (oldequiv))
6683 && (REGNO (SUBREG_REG (oldequiv))
6684 >= FIRST_PSEUDO_REGISTER)
6685 && ((reg_equiv_memory_loc
6686 [REGNO (SUBREG_REG (oldequiv))] != 0)
6687 || (reg_equiv_constant
6688 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6689 || (CONSTANT_P (oldequiv)
6690 && (PREFERRED_RELOAD_CLASS (oldequiv,
6691 REGNO_REG_CLASS (REGNO (reloadreg)))
6693 real_oldequiv = rl->in;
6694 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6698 if (flag_non_call_exceptions)
6699 copy_eh_notes (insn, get_insns ());
6701 /* End this sequence. */
6702 *where = get_insns ();
6705 /* Update reload_override_in so that delete_address_reloads_1
6706 can see the actual register usage. */
6708 reload_override_in[j] = oldequiv;
6711 /* Generate insns to for the output reload RL, which is for the insn described
6712 by CHAIN and has the number J. */
6714 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6717 rtx reloadreg = rl->reg_rtx;
6718 rtx insn = chain->insn;
6721 enum machine_mode mode = GET_MODE (old);
6724 if (rl->when_needed == RELOAD_OTHER)
6727 push_to_sequence (output_reload_insns[rl->opnum]);
6729 /* Determine the mode to reload in.
6730 See comments above (for input reloading). */
6732 if (mode == VOIDmode)
6734 /* VOIDmode should never happen for an output. */
6735 if (asm_noperands (PATTERN (insn)) < 0)
6736 /* It's the compiler's fault. */
6737 fatal_insn ("VOIDmode on an output", insn);
6738 error_for_asm (insn, "output operand is constant in %<asm%>");
6739 /* Prevent crash--use something we know is valid. */
6741 old = gen_rtx_REG (mode, REGNO (reloadreg));
6744 if (GET_MODE (reloadreg) != mode)
6745 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6747 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6749 /* If we need two reload regs, set RELOADREG to the intermediate
6750 one, since it will be stored into OLD. We might need a secondary
6751 register only for an input reload, so check again here. */
6753 if (rl->secondary_out_reload >= 0)
6757 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6758 && reg_equiv_mem[REGNO (old)] != 0)
6759 real_old = reg_equiv_mem[REGNO (old)];
6761 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6765 rtx second_reloadreg = reloadreg;
6766 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6768 /* See if RELOADREG is to be used as a scratch register
6769 or as an intermediate register. */
6770 if (rl->secondary_out_icode != CODE_FOR_nothing)
6772 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6773 (real_old, second_reloadreg, reloadreg)));
6778 /* See if we need both a scratch and intermediate reload
6781 int secondary_reload = rl->secondary_out_reload;
6782 enum insn_code tertiary_icode
6783 = rld[secondary_reload].secondary_out_icode;
6785 if (GET_MODE (reloadreg) != mode)
6786 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6788 if (tertiary_icode != CODE_FOR_nothing)
6791 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6794 /* Copy primary reload reg to secondary reload reg.
6795 (Note that these have been swapped above, then
6796 secondary reload reg to OLD using our insn.) */
6798 /* If REAL_OLD is a paradoxical SUBREG, remove it
6799 and try to put the opposite SUBREG on
6801 if (GET_CODE (real_old) == SUBREG
6802 && (GET_MODE_SIZE (GET_MODE (real_old))
6803 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6804 && 0 != (tem = gen_lowpart_common
6805 (GET_MODE (SUBREG_REG (real_old)),
6807 real_old = SUBREG_REG (real_old), reloadreg = tem;
6809 gen_reload (reloadreg, second_reloadreg,
6810 rl->opnum, rl->when_needed);
6811 emit_insn ((GEN_FCN (tertiary_icode)
6812 (real_old, reloadreg, third_reloadreg)));
6817 /* Copy between the reload regs here and then to
6820 gen_reload (reloadreg, second_reloadreg,
6821 rl->opnum, rl->when_needed);
6827 /* Output the last reload insn. */
6832 /* Don't output the last reload if OLD is not the dest of
6833 INSN and is in the src and is clobbered by INSN. */
6834 if (! flag_expensive_optimizations
6836 || !(set = single_set (insn))
6837 || rtx_equal_p (old, SET_DEST (set))
6838 || !reg_mentioned_p (old, SET_SRC (set))
6839 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6840 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6841 gen_reload (old, reloadreg, rl->opnum,
6845 /* Look at all insns we emitted, just to be safe. */
6846 for (p = get_insns (); p; p = NEXT_INSN (p))
6849 rtx pat = PATTERN (p);
6851 /* If this output reload doesn't come from a spill reg,
6852 clear any memory of reloaded copies of the pseudo reg.
6853 If this output reload comes from a spill reg,
6854 reg_has_output_reload will make this do nothing. */
6855 note_stores (pat, forget_old_reloads_1, NULL);
6857 if (reg_mentioned_p (rl->reg_rtx, pat))
6859 rtx set = single_set (insn);
6860 if (reload_spill_index[j] < 0
6862 && SET_SRC (set) == rl->reg_rtx)
6864 int src = REGNO (SET_SRC (set));
6866 reload_spill_index[j] = src;
6867 SET_HARD_REG_BIT (reg_is_output_reload, src);
6868 if (find_regno_note (insn, REG_DEAD, src))
6869 SET_HARD_REG_BIT (reg_reloaded_died, src);
6871 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6873 int s = rl->secondary_out_reload;
6874 set = single_set (p);
6875 /* If this reload copies only to the secondary reload
6876 register, the secondary reload does the actual
6878 if (s >= 0 && set == NULL_RTX)
6879 /* We can't tell what function the secondary reload
6880 has and where the actual store to the pseudo is
6881 made; leave new_spill_reg_store alone. */
6884 && SET_SRC (set) == rl->reg_rtx
6885 && SET_DEST (set) == rld[s].reg_rtx)
6887 /* Usually the next instruction will be the
6888 secondary reload insn; if we can confirm
6889 that it is, setting new_spill_reg_store to
6890 that insn will allow an extra optimization. */
6891 rtx s_reg = rld[s].reg_rtx;
6892 rtx next = NEXT_INSN (p);
6893 rld[s].out = rl->out;
6894 rld[s].out_reg = rl->out_reg;
6895 set = single_set (next);
6896 if (set && SET_SRC (set) == s_reg
6897 && ! new_spill_reg_store[REGNO (s_reg)])
6899 SET_HARD_REG_BIT (reg_is_output_reload,
6901 new_spill_reg_store[REGNO (s_reg)] = next;
6905 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6910 if (rl->when_needed == RELOAD_OTHER)
6912 emit_insn (other_output_reload_insns[rl->opnum]);
6913 other_output_reload_insns[rl->opnum] = get_insns ();
6916 output_reload_insns[rl->opnum] = get_insns ();
6918 if (flag_non_call_exceptions)
6919 copy_eh_notes (insn, get_insns ());
6924 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6925 and has the number J. */
6927 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6929 rtx insn = chain->insn;
6930 rtx old = (rl->in && MEM_P (rl->in)
6931 ? rl->in_reg : rl->in);
6934 /* AUTO_INC reloads need to be handled even if inherited. We got an
6935 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6936 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6937 && ! rtx_equal_p (rl->reg_rtx, old)
6938 && rl->reg_rtx != 0)
6939 emit_input_reload_insns (chain, rld + j, old, j);
6941 /* When inheriting a wider reload, we have a MEM in rl->in,
6942 e.g. inheriting a SImode output reload for
6943 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6944 if (optimize && reload_inherited[j] && rl->in
6946 && MEM_P (rl->in_reg)
6947 && reload_spill_index[j] >= 0
6948 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6949 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6951 /* If we are reloading a register that was recently stored in with an
6952 output-reload, see if we can prove there was
6953 actually no need to store the old value in it. */
6956 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6957 that there may be multiple uses of the previous output reload.
6958 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6959 && rl->when_needed == RELOAD_FOR_INPUT
6960 && (reload_inherited[j] || reload_override_in[j])
6962 && REG_P (rl->reg_rtx)
6963 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6965 /* There doesn't seem to be any reason to restrict this to pseudos
6966 and doing so loses in the case where we are copying from a
6967 register of the wrong class. */
6968 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6969 >= FIRST_PSEUDO_REGISTER)
6971 /* The insn might have already some references to stackslots
6972 replaced by MEMs, while reload_out_reg still names the
6974 && (dead_or_set_p (insn,
6975 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6976 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6978 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6981 /* Do output reloading for reload RL, which is for the insn described by
6982 CHAIN and has the number J.
6983 ??? At some point we need to support handling output reloads of
6984 JUMP_INSNs or insns that set cc0. */
6986 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6989 rtx insn = chain->insn;
6990 /* If this is an output reload that stores something that is
6991 not loaded in this same reload, see if we can eliminate a previous
6993 rtx pseudo = rl->out_reg;
6998 && ! rtx_equal_p (rl->in_reg, pseudo)
6999 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7000 && reg_last_reload_reg[REGNO (pseudo)])
7002 int pseudo_no = REGNO (pseudo);
7003 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7005 /* We don't need to test full validity of last_regno for
7006 inherit here; we only want to know if the store actually
7007 matches the pseudo. */
7008 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7009 && reg_reloaded_contents[last_regno] == pseudo_no
7010 && spill_reg_store[last_regno]
7011 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7012 delete_output_reload (insn, j, last_regno);
7017 || rl->reg_rtx == old
7018 || rl->reg_rtx == 0)
7021 /* An output operand that dies right away does need a reload,
7022 but need not be copied from it. Show the new location in the
7024 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7025 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7027 XEXP (note, 0) = rl->reg_rtx;
7030 /* Likewise for a SUBREG of an operand that dies. */
7031 else if (GET_CODE (old) == SUBREG
7032 && REG_P (SUBREG_REG (old))
7033 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7036 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7040 else if (GET_CODE (old) == SCRATCH)
7041 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7042 but we don't want to make an output reload. */
7045 /* If is a JUMP_INSN, we can't support output reloads yet. */
7046 gcc_assert (!JUMP_P (insn));
7048 emit_output_reload_insns (chain, rld + j, j);
7051 /* Reload number R reloads from or to a group of hard registers starting at
7052 register REGNO. Return true if it can be treated for inheritance purposes
7053 like a group of reloads, each one reloading a single hard register.
7054 The caller has already checked that the spill register and REGNO use
7055 the same number of registers to store the reload value. */
7058 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7060 #ifdef CANNOT_CHANGE_MODE_CLASS
7061 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7062 GET_MODE (rld[r].reg_rtx),
7063 reg_raw_mode[reload_spill_index[r]])
7064 && !REG_CANNOT_CHANGE_MODE_P (regno,
7065 GET_MODE (rld[r].reg_rtx),
7066 reg_raw_mode[regno]));
7072 /* Output insns to reload values in and out of the chosen reload regs. */
7075 emit_reload_insns (struct insn_chain *chain)
7077 rtx insn = chain->insn;
7081 CLEAR_HARD_REG_SET (reg_reloaded_died);
7083 for (j = 0; j < reload_n_operands; j++)
7084 input_reload_insns[j] = input_address_reload_insns[j]
7085 = inpaddr_address_reload_insns[j]
7086 = output_reload_insns[j] = output_address_reload_insns[j]
7087 = outaddr_address_reload_insns[j]
7088 = other_output_reload_insns[j] = 0;
7089 other_input_address_reload_insns = 0;
7090 other_input_reload_insns = 0;
7091 operand_reload_insns = 0;
7092 other_operand_reload_insns = 0;
7094 /* Dump reloads into the dump file. */
7097 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7098 debug_reload_to_stream (dump_file);
7101 /* Now output the instructions to copy the data into and out of the
7102 reload registers. Do these in the order that the reloads were reported,
7103 since reloads of base and index registers precede reloads of operands
7104 and the operands may need the base and index registers reloaded. */
7106 for (j = 0; j < n_reloads; j++)
7109 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7110 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7112 do_input_reload (chain, rld + j, j);
7113 do_output_reload (chain, rld + j, j);
7116 /* Now write all the insns we made for reloads in the order expected by
7117 the allocation functions. Prior to the insn being reloaded, we write
7118 the following reloads:
7120 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7122 RELOAD_OTHER reloads.
7124 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7125 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7126 RELOAD_FOR_INPUT reload for the operand.
7128 RELOAD_FOR_OPADDR_ADDRS reloads.
7130 RELOAD_FOR_OPERAND_ADDRESS reloads.
7132 After the insn being reloaded, we write the following:
7134 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7135 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7136 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7137 reloads for the operand. The RELOAD_OTHER output reloads are
7138 output in descending order by reload number. */
7140 emit_insn_before (other_input_address_reload_insns, insn);
7141 emit_insn_before (other_input_reload_insns, insn);
7143 for (j = 0; j < reload_n_operands; j++)
7145 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7146 emit_insn_before (input_address_reload_insns[j], insn);
7147 emit_insn_before (input_reload_insns[j], insn);
7150 emit_insn_before (other_operand_reload_insns, insn);
7151 emit_insn_before (operand_reload_insns, insn);
7153 for (j = 0; j < reload_n_operands; j++)
7155 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7156 x = emit_insn_after (output_address_reload_insns[j], x);
7157 x = emit_insn_after (output_reload_insns[j], x);
7158 emit_insn_after (other_output_reload_insns[j], x);
7161 /* For all the spill regs newly reloaded in this instruction,
7162 record what they were reloaded from, so subsequent instructions
7163 can inherit the reloads.
7165 Update spill_reg_store for the reloads of this insn.
7166 Copy the elements that were updated in the loop above. */
7168 for (j = 0; j < n_reloads; j++)
7170 int r = reload_order[j];
7171 int i = reload_spill_index[r];
7173 /* If this is a non-inherited input reload from a pseudo, we must
7174 clear any memory of a previous store to the same pseudo. Only do
7175 something if there will not be an output reload for the pseudo
7177 if (rld[r].in_reg != 0
7178 && ! (reload_inherited[r] || reload_override_in[r]))
7180 rtx reg = rld[r].in_reg;
7182 if (GET_CODE (reg) == SUBREG)
7183 reg = SUBREG_REG (reg);
7186 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7187 && ! reg_has_output_reload[REGNO (reg)])
7189 int nregno = REGNO (reg);
7191 if (reg_last_reload_reg[nregno])
7193 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7195 if (reg_reloaded_contents[last_regno] == nregno)
7196 spill_reg_store[last_regno] = 0;
7201 /* I is nonneg if this reload used a register.
7202 If rld[r].reg_rtx is 0, this is an optional reload
7203 that we opted to ignore. */
7205 if (i >= 0 && rld[r].reg_rtx != 0)
7207 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7209 int part_reaches_end = 0;
7210 int all_reaches_end = 1;
7212 /* For a multi register reload, we need to check if all or part
7213 of the value lives to the end. */
7214 for (k = 0; k < nr; k++)
7216 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7217 rld[r].when_needed))
7218 part_reaches_end = 1;
7220 all_reaches_end = 0;
7223 /* Ignore reloads that don't reach the end of the insn in
7225 if (all_reaches_end)
7227 /* First, clear out memory of what used to be in this spill reg.
7228 If consecutive registers are used, clear them all. */
7230 for (k = 0; k < nr; k++)
7232 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7233 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7236 /* Maybe the spill reg contains a copy of reload_out. */
7238 && (REG_P (rld[r].out)
7242 || REG_P (rld[r].out_reg)))
7244 rtx out = (REG_P (rld[r].out)
7248 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7249 int nregno = REGNO (out);
7250 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7251 : hard_regno_nregs[nregno]
7252 [GET_MODE (rld[r].reg_rtx)]);
7255 spill_reg_store[i] = new_spill_reg_store[i];
7256 spill_reg_stored_to[i] = out;
7257 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7259 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7261 && inherit_piecemeal_p (r, nregno));
7263 /* If NREGNO is a hard register, it may occupy more than
7264 one register. If it does, say what is in the
7265 rest of the registers assuming that both registers
7266 agree on how many words the object takes. If not,
7267 invalidate the subsequent registers. */
7269 if (nregno < FIRST_PSEUDO_REGISTER)
7270 for (k = 1; k < nnr; k++)
7271 reg_last_reload_reg[nregno + k]
7273 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7276 /* Now do the inverse operation. */
7277 for (k = 0; k < nr; k++)
7279 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7280 reg_reloaded_contents[i + k]
7281 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7284 reg_reloaded_insn[i + k] = insn;
7285 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7286 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7287 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7291 /* Maybe the spill reg contains a copy of reload_in. Only do
7292 something if there will not be an output reload for
7293 the register being reloaded. */
7294 else if (rld[r].out_reg == 0
7296 && ((REG_P (rld[r].in)
7297 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7298 && ! reg_has_output_reload[REGNO (rld[r].in)])
7299 || (REG_P (rld[r].in_reg)
7300 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7301 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7308 if (REG_P (rld[r].in)
7309 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7311 else if (REG_P (rld[r].in_reg))
7314 in = XEXP (rld[r].in_reg, 0);
7315 nregno = REGNO (in);
7317 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7318 : hard_regno_nregs[nregno]
7319 [GET_MODE (rld[r].reg_rtx)]);
7321 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7323 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7325 && inherit_piecemeal_p (r, nregno));
7327 if (nregno < FIRST_PSEUDO_REGISTER)
7328 for (k = 1; k < nnr; k++)
7329 reg_last_reload_reg[nregno + k]
7331 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7334 /* Unless we inherited this reload, show we haven't
7335 recently done a store.
7336 Previous stores of inherited auto_inc expressions
7337 also have to be discarded. */
7338 if (! reload_inherited[r]
7339 || (rld[r].out && ! rld[r].out_reg))
7340 spill_reg_store[i] = 0;
7342 for (k = 0; k < nr; k++)
7344 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7345 reg_reloaded_contents[i + k]
7346 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7349 reg_reloaded_insn[i + k] = insn;
7350 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7351 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7352 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7357 /* However, if part of the reload reaches the end, then we must
7358 invalidate the old info for the part that survives to the end. */
7359 else if (part_reaches_end)
7361 for (k = 0; k < nr; k++)
7362 if (reload_reg_reaches_end_p (i + k,
7364 rld[r].when_needed))
7365 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7369 /* The following if-statement was #if 0'd in 1.34 (or before...).
7370 It's reenabled in 1.35 because supposedly nothing else
7371 deals with this problem. */
7373 /* If a register gets output-reloaded from a non-spill register,
7374 that invalidates any previous reloaded copy of it.
7375 But forget_old_reloads_1 won't get to see it, because
7376 it thinks only about the original insn. So invalidate it here. */
7377 if (i < 0 && rld[r].out != 0
7378 && (REG_P (rld[r].out)
7379 || (MEM_P (rld[r].out)
7380 && REG_P (rld[r].out_reg))))
7382 rtx out = (REG_P (rld[r].out)
7383 ? rld[r].out : rld[r].out_reg);
7384 int nregno = REGNO (out);
7385 if (nregno >= FIRST_PSEUDO_REGISTER)
7387 rtx src_reg, store_insn = NULL_RTX;
7389 reg_last_reload_reg[nregno] = 0;
7391 /* If we can find a hard register that is stored, record
7392 the storing insn so that we may delete this insn with
7393 delete_output_reload. */
7394 src_reg = rld[r].reg_rtx;
7396 /* If this is an optional reload, try to find the source reg
7397 from an input reload. */
7400 rtx set = single_set (insn);
7401 if (set && SET_DEST (set) == rld[r].out)
7405 src_reg = SET_SRC (set);
7407 for (k = 0; k < n_reloads; k++)
7409 if (rld[k].in == src_reg)
7411 src_reg = rld[k].reg_rtx;
7418 store_insn = new_spill_reg_store[REGNO (src_reg)];
7419 if (src_reg && REG_P (src_reg)
7420 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7422 int src_regno = REGNO (src_reg);
7423 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7424 /* The place where to find a death note varies with
7425 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7426 necessarily checked exactly in the code that moves
7427 notes, so just check both locations. */
7428 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7429 if (! note && store_insn)
7430 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7433 spill_reg_store[src_regno + nr] = store_insn;
7434 spill_reg_stored_to[src_regno + nr] = out;
7435 reg_reloaded_contents[src_regno + nr] = nregno;
7436 reg_reloaded_insn[src_regno + nr] = store_insn;
7437 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7438 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7439 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7440 GET_MODE (src_reg)))
7441 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7443 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7445 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7447 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7449 reg_last_reload_reg[nregno] = src_reg;
7450 /* We have to set reg_has_output_reload here, or else
7451 forget_old_reloads_1 will clear reg_last_reload_reg
7453 reg_has_output_reload[nregno] = 1;
7458 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7460 while (num_regs-- > 0)
7461 reg_last_reload_reg[nregno + num_regs] = 0;
7465 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7468 /* Go through the motions to emit INSN and test if it is strictly valid.
7469 Return the emitted insn if valid, else return NULL. */
7472 emit_insn_if_valid_for_reload (rtx insn)
7474 rtx last = get_last_insn ();
7477 insn = emit_insn (insn);
7478 code = recog_memoized (insn);
7482 extract_insn (insn);
7483 /* We want constrain operands to treat this insn strictly in its
7484 validity determination, i.e., the way it would after reload has
7486 if (constrain_operands (1))
7490 delete_insns_since (last);
7494 /* Emit code to perform a reload from IN (which may be a reload register) to
7495 OUT (which may also be a reload register). IN or OUT is from operand
7496 OPNUM with reload type TYPE.
7498 Returns first insn emitted. */
7501 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7503 rtx last = get_last_insn ();
7506 /* If IN is a paradoxical SUBREG, remove it and try to put the
7507 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7508 if (GET_CODE (in) == SUBREG
7509 && (GET_MODE_SIZE (GET_MODE (in))
7510 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7511 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7512 in = SUBREG_REG (in), out = tem;
7513 else if (GET_CODE (out) == SUBREG
7514 && (GET_MODE_SIZE (GET_MODE (out))
7515 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7516 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7517 out = SUBREG_REG (out), in = tem;
7519 /* How to do this reload can get quite tricky. Normally, we are being
7520 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7521 register that didn't get a hard register. In that case we can just
7522 call emit_move_insn.
7524 We can also be asked to reload a PLUS that adds a register or a MEM to
7525 another register, constant or MEM. This can occur during frame pointer
7526 elimination and while reloading addresses. This case is handled by
7527 trying to emit a single insn to perform the add. If it is not valid,
7528 we use a two insn sequence.
7530 Or we can be asked to reload an unary operand that was a fragment of
7531 an addressing mode, into a register. If it isn't recognized as-is,
7532 we try making the unop operand and the reload-register the same:
7533 (set reg:X (unop:X expr:Y))
7534 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7536 Finally, we could be called to handle an 'o' constraint by putting
7537 an address into a register. In that case, we first try to do this
7538 with a named pattern of "reload_load_address". If no such pattern
7539 exists, we just emit a SET insn and hope for the best (it will normally
7540 be valid on machines that use 'o').
7542 This entire process is made complex because reload will never
7543 process the insns we generate here and so we must ensure that
7544 they will fit their constraints and also by the fact that parts of
7545 IN might be being reloaded separately and replaced with spill registers.
7546 Because of this, we are, in some sense, just guessing the right approach
7547 here. The one listed above seems to work.
7549 ??? At some point, this whole thing needs to be rethought. */
7551 if (GET_CODE (in) == PLUS
7552 && (REG_P (XEXP (in, 0))
7553 || GET_CODE (XEXP (in, 0)) == SUBREG
7554 || MEM_P (XEXP (in, 0)))
7555 && (REG_P (XEXP (in, 1))
7556 || GET_CODE (XEXP (in, 1)) == SUBREG
7557 || CONSTANT_P (XEXP (in, 1))
7558 || MEM_P (XEXP (in, 1))))
7560 /* We need to compute the sum of a register or a MEM and another
7561 register, constant, or MEM, and put it into the reload
7562 register. The best possible way of doing this is if the machine
7563 has a three-operand ADD insn that accepts the required operands.
7565 The simplest approach is to try to generate such an insn and see if it
7566 is recognized and matches its constraints. If so, it can be used.
7568 It might be better not to actually emit the insn unless it is valid,
7569 but we need to pass the insn as an operand to `recog' and
7570 `extract_insn' and it is simpler to emit and then delete the insn if
7571 not valid than to dummy things up. */
7573 rtx op0, op1, tem, insn;
7576 op0 = find_replacement (&XEXP (in, 0));
7577 op1 = find_replacement (&XEXP (in, 1));
7579 /* Since constraint checking is strict, commutativity won't be
7580 checked, so we need to do that here to avoid spurious failure
7581 if the add instruction is two-address and the second operand
7582 of the add is the same as the reload reg, which is frequently
7583 the case. If the insn would be A = B + A, rearrange it so
7584 it will be A = A + B as constrain_operands expects. */
7586 if (REG_P (XEXP (in, 1))
7587 && REGNO (out) == REGNO (XEXP (in, 1)))
7588 tem = op0, op0 = op1, op1 = tem;
7590 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7591 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7593 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7597 /* If that failed, we must use a conservative two-insn sequence.
7599 Use a move to copy one operand into the reload register. Prefer
7600 to reload a constant, MEM or pseudo since the move patterns can
7601 handle an arbitrary operand. If OP1 is not a constant, MEM or
7602 pseudo and OP1 is not a valid operand for an add instruction, then
7605 After reloading one of the operands into the reload register, add
7606 the reload register to the output register.
7608 If there is another way to do this for a specific machine, a
7609 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7612 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7614 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7616 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7617 || (code != CODE_FOR_nothing
7618 && ! ((*insn_data[code].operand[2].predicate)
7619 (op1, insn_data[code].operand[2].mode))))
7620 tem = op0, op0 = op1, op1 = tem;
7622 gen_reload (out, op0, opnum, type);
7624 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7625 This fixes a problem on the 32K where the stack pointer cannot
7626 be used as an operand of an add insn. */
7628 if (rtx_equal_p (op0, op1))
7631 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7634 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7636 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7640 /* If that failed, copy the address register to the reload register.
7641 Then add the constant to the reload register. */
7643 gen_reload (out, op1, opnum, type);
7644 insn = emit_insn (gen_add2_insn (out, op0));
7645 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7648 #ifdef SECONDARY_MEMORY_NEEDED
7649 /* If we need a memory location to do the move, do it that way. */
7650 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7651 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7652 && (REG_P (out) || GET_CODE (out) == SUBREG)
7653 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7654 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7655 REGNO_REG_CLASS (reg_or_subregno (out)),
7658 /* Get the memory to use and rewrite both registers to its mode. */
7659 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7661 if (GET_MODE (loc) != GET_MODE (out))
7662 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7664 if (GET_MODE (loc) != GET_MODE (in))
7665 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7667 gen_reload (loc, in, opnum, type);
7668 gen_reload (out, loc, opnum, type);
7671 else if (REG_P (out) && UNARY_P (in))
7678 op1 = find_replacement (&XEXP (in, 0));
7679 if (op1 != XEXP (in, 0))
7680 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7682 /* First, try a plain SET. */
7683 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7687 /* If that failed, move the inner operand to the reload
7688 register, and try the same unop with the inner expression
7689 replaced with the reload register. */
7691 if (GET_MODE (op1) != GET_MODE (out))
7692 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7696 gen_reload (out_moded, op1, opnum, type);
7699 = gen_rtx_SET (VOIDmode, out,
7700 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7702 insn = emit_insn_if_valid_for_reload (insn);
7706 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7710 fatal_insn ("Failure trying to reload:", set);
7712 /* If IN is a simple operand, use gen_move_insn. */
7713 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7714 emit_insn (gen_move_insn (out, in));
7716 #ifdef HAVE_reload_load_address
7717 else if (HAVE_reload_load_address)
7718 emit_insn (gen_reload_load_address (out, in));
7721 /* Otherwise, just write (set OUT IN) and hope for the best. */
7723 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7725 /* Return the first insn emitted.
7726 We can not just return get_last_insn, because there may have
7727 been multiple instructions emitted. Also note that gen_move_insn may
7728 emit more than one insn itself, so we can not assume that there is one
7729 insn emitted per emit_insn_before call. */
7731 return last ? NEXT_INSN (last) : get_insns ();
7734 /* Delete a previously made output-reload whose result we now believe
7735 is not needed. First we double-check.
7737 INSN is the insn now being processed.
7738 LAST_RELOAD_REG is the hard register number for which we want to delete
7739 the last output reload.
7740 J is the reload-number that originally used REG. The caller has made
7741 certain that reload J doesn't use REG any longer for input. */
7744 delete_output_reload (rtx insn, int j, int last_reload_reg)
7746 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7747 rtx reg = spill_reg_stored_to[last_reload_reg];
7750 int n_inherited = 0;
7754 /* It is possible that this reload has been only used to set another reload
7755 we eliminated earlier and thus deleted this instruction too. */
7756 if (INSN_DELETED_P (output_reload_insn))
7759 /* Get the raw pseudo-register referred to. */
7761 while (GET_CODE (reg) == SUBREG)
7762 reg = SUBREG_REG (reg);
7763 substed = reg_equiv_memory_loc[REGNO (reg)];
7765 /* This is unsafe if the operand occurs more often in the current
7766 insn than it is inherited. */
7767 for (k = n_reloads - 1; k >= 0; k--)
7769 rtx reg2 = rld[k].in;
7772 if (MEM_P (reg2) || reload_override_in[k])
7773 reg2 = rld[k].in_reg;
7775 if (rld[k].out && ! rld[k].out_reg)
7776 reg2 = XEXP (rld[k].in_reg, 0);
7778 while (GET_CODE (reg2) == SUBREG)
7779 reg2 = SUBREG_REG (reg2);
7780 if (rtx_equal_p (reg2, reg))
7782 if (reload_inherited[k] || reload_override_in[k] || k == j)
7785 reg2 = rld[k].out_reg;
7788 while (GET_CODE (reg2) == SUBREG)
7789 reg2 = XEXP (reg2, 0);
7790 if (rtx_equal_p (reg2, reg))
7797 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7799 n_occurrences += count_occurrences (PATTERN (insn),
7800 eliminate_regs (substed, 0,
7802 if (n_occurrences > n_inherited)
7805 /* If the pseudo-reg we are reloading is no longer referenced
7806 anywhere between the store into it and here,
7807 and we're within the same basic block, then the value can only
7808 pass through the reload reg and end up here.
7809 Otherwise, give up--return. */
7810 for (i1 = NEXT_INSN (output_reload_insn);
7811 i1 != insn; i1 = NEXT_INSN (i1))
7813 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7815 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7816 && reg_mentioned_p (reg, PATTERN (i1)))
7818 /* If this is USE in front of INSN, we only have to check that
7819 there are no more references than accounted for by inheritance. */
7820 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7822 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7823 i1 = NEXT_INSN (i1);
7825 if (n_occurrences <= n_inherited && i1 == insn)
7831 /* We will be deleting the insn. Remove the spill reg information. */
7832 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7834 spill_reg_store[last_reload_reg + k] = 0;
7835 spill_reg_stored_to[last_reload_reg + k] = 0;
7838 /* The caller has already checked that REG dies or is set in INSN.
7839 It has also checked that we are optimizing, and thus some
7840 inaccuracies in the debugging information are acceptable.
7841 So we could just delete output_reload_insn. But in some cases
7842 we can improve the debugging information without sacrificing
7843 optimization - maybe even improving the code: See if the pseudo
7844 reg has been completely replaced with reload regs. If so, delete
7845 the store insn and forget we had a stack slot for the pseudo. */
7846 if (rld[j].out != rld[j].in
7847 && REG_N_DEATHS (REGNO (reg)) == 1
7848 && REG_N_SETS (REGNO (reg)) == 1
7849 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7850 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7854 /* We know that it was used only between here and the beginning of
7855 the current basic block. (We also know that the last use before
7856 INSN was the output reload we are thinking of deleting, but never
7857 mind that.) Search that range; see if any ref remains. */
7858 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7860 rtx set = single_set (i2);
7862 /* Uses which just store in the pseudo don't count,
7863 since if they are the only uses, they are dead. */
7864 if (set != 0 && SET_DEST (set) == reg)
7869 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7870 && reg_mentioned_p (reg, PATTERN (i2)))
7872 /* Some other ref remains; just delete the output reload we
7874 delete_address_reloads (output_reload_insn, insn);
7875 delete_insn (output_reload_insn);
7880 /* Delete the now-dead stores into this pseudo. Note that this
7881 loop also takes care of deleting output_reload_insn. */
7882 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7884 rtx set = single_set (i2);
7886 if (set != 0 && SET_DEST (set) == reg)
7888 delete_address_reloads (i2, insn);
7896 /* For the debugging info, say the pseudo lives in this reload reg. */
7897 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7898 alter_reg (REGNO (reg), -1);
7902 delete_address_reloads (output_reload_insn, insn);
7903 delete_insn (output_reload_insn);
7907 /* We are going to delete DEAD_INSN. Recursively delete loads of
7908 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7909 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7911 delete_address_reloads (rtx dead_insn, rtx current_insn)
7913 rtx set = single_set (dead_insn);
7914 rtx set2, dst, prev, next;
7917 rtx dst = SET_DEST (set);
7919 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7921 /* If we deleted the store from a reloaded post_{in,de}c expression,
7922 we can delete the matching adds. */
7923 prev = PREV_INSN (dead_insn);
7924 next = NEXT_INSN (dead_insn);
7925 if (! prev || ! next)
7927 set = single_set (next);
7928 set2 = single_set (prev);
7930 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7931 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7932 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7934 dst = SET_DEST (set);
7935 if (! rtx_equal_p (dst, SET_DEST (set2))
7936 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7937 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7938 || (INTVAL (XEXP (SET_SRC (set), 1))
7939 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7941 delete_related_insns (prev);
7942 delete_related_insns (next);
7945 /* Subfunction of delete_address_reloads: process registers found in X. */
7947 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7949 rtx prev, set, dst, i2;
7951 enum rtx_code code = GET_CODE (x);
7955 const char *fmt = GET_RTX_FORMAT (code);
7956 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7959 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7960 else if (fmt[i] == 'E')
7962 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7963 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7970 if (spill_reg_order[REGNO (x)] < 0)
7973 /* Scan backwards for the insn that sets x. This might be a way back due
7975 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7977 code = GET_CODE (prev);
7978 if (code == CODE_LABEL || code == JUMP_INSN)
7982 if (reg_set_p (x, PATTERN (prev)))
7984 if (reg_referenced_p (x, PATTERN (prev)))
7987 if (! prev || INSN_UID (prev) < reload_first_uid)
7989 /* Check that PREV only sets the reload register. */
7990 set = single_set (prev);
7993 dst = SET_DEST (set);
7995 || ! rtx_equal_p (dst, x))
7997 if (! reg_set_p (dst, PATTERN (dead_insn)))
7999 /* Check if DST was used in a later insn -
8000 it might have been inherited. */
8001 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8007 if (reg_referenced_p (dst, PATTERN (i2)))
8009 /* If there is a reference to the register in the current insn,
8010 it might be loaded in a non-inherited reload. If no other
8011 reload uses it, that means the register is set before
8013 if (i2 == current_insn)
8015 for (j = n_reloads - 1; j >= 0; j--)
8016 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8017 || reload_override_in[j] == dst)
8019 for (j = n_reloads - 1; j >= 0; j--)
8020 if (rld[j].in && rld[j].reg_rtx == dst)
8029 /* If DST is still live at CURRENT_INSN, check if it is used for
8030 any reload. Note that even if CURRENT_INSN sets DST, we still
8031 have to check the reloads. */
8032 if (i2 == current_insn)
8034 for (j = n_reloads - 1; j >= 0; j--)
8035 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8036 || reload_override_in[j] == dst)
8038 /* ??? We can't finish the loop here, because dst might be
8039 allocated to a pseudo in this block if no reload in this
8040 block needs any of the classes containing DST - see
8041 spill_hard_reg. There is no easy way to tell this, so we
8042 have to scan till the end of the basic block. */
8044 if (reg_set_p (dst, PATTERN (i2)))
8048 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8049 reg_reloaded_contents[REGNO (dst)] = -1;
8053 /* Output reload-insns to reload VALUE into RELOADREG.
8054 VALUE is an autoincrement or autodecrement RTX whose operand
8055 is a register or memory location;
8056 so reloading involves incrementing that location.
8057 IN is either identical to VALUE, or some cheaper place to reload from.
8059 INC_AMOUNT is the number to increment or decrement by (always positive).
8060 This cannot be deduced from VALUE.
8062 Return the instruction that stores into RELOADREG. */
8065 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8067 /* REG or MEM to be copied and incremented. */
8068 rtx incloc = XEXP (value, 0);
8069 /* Nonzero if increment after copying. */
8070 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8076 rtx real_in = in == value ? XEXP (in, 0) : in;
8078 /* No hard register is equivalent to this register after
8079 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8080 we could inc/dec that register as well (maybe even using it for
8081 the source), but I'm not sure it's worth worrying about. */
8083 reg_last_reload_reg[REGNO (incloc)] = 0;
8085 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8086 inc_amount = -inc_amount;
8088 inc = GEN_INT (inc_amount);
8090 /* If this is post-increment, first copy the location to the reload reg. */
8091 if (post && real_in != reloadreg)
8092 emit_insn (gen_move_insn (reloadreg, real_in));
8096 /* See if we can directly increment INCLOC. Use a method similar to
8097 that in gen_reload. */
8099 last = get_last_insn ();
8100 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8101 gen_rtx_PLUS (GET_MODE (incloc),
8104 code = recog_memoized (add_insn);
8107 extract_insn (add_insn);
8108 if (constrain_operands (1))
8110 /* If this is a pre-increment and we have incremented the value
8111 where it lives, copy the incremented value to RELOADREG to
8112 be used as an address. */
8115 emit_insn (gen_move_insn (reloadreg, incloc));
8120 delete_insns_since (last);
8123 /* If couldn't do the increment directly, must increment in RELOADREG.
8124 The way we do this depends on whether this is pre- or post-increment.
8125 For pre-increment, copy INCLOC to the reload register, increment it
8126 there, then save back. */
8130 if (in != reloadreg)
8131 emit_insn (gen_move_insn (reloadreg, real_in));
8132 emit_insn (gen_add2_insn (reloadreg, inc));
8133 store = emit_insn (gen_move_insn (incloc, reloadreg));
8138 Because this might be a jump insn or a compare, and because RELOADREG
8139 may not be available after the insn in an input reload, we must do
8140 the incrementation before the insn being reloaded for.
8142 We have already copied IN to RELOADREG. Increment the copy in
8143 RELOADREG, save that back, then decrement RELOADREG so it has
8144 the original value. */
8146 emit_insn (gen_add2_insn (reloadreg, inc));
8147 store = emit_insn (gen_move_insn (incloc, reloadreg));
8148 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8156 add_auto_inc_notes (rtx insn, rtx x)
8158 enum rtx_code code = GET_CODE (x);
8162 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8165 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8169 /* Scan all the operand sub-expressions. */
8170 fmt = GET_RTX_FORMAT (code);
8171 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8174 add_auto_inc_notes (insn, XEXP (x, i));
8175 else if (fmt[i] == 'E')
8176 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8177 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8182 /* Copy EH notes from an insn to its reloads. */
8184 copy_eh_notes (rtx insn, rtx x)
8186 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8189 for (; x != 0; x = NEXT_INSN (x))
8191 if (may_trap_p (PATTERN (x)))
8193 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8199 /* This is used by reload pass, that does emit some instructions after
8200 abnormal calls moving basic block end, but in fact it wants to emit
8201 them on the edge. Looks for abnormal call edges, find backward the
8202 proper call and fix the damage.
8204 Similar handle instructions throwing exceptions internally. */
8206 fixup_abnormal_edges (void)
8208 bool inserted = false;
8216 /* Look for cases we are interested in - calls or instructions causing
8218 FOR_EACH_EDGE (e, ei, bb->succs)
8220 if (e->flags & EDGE_ABNORMAL_CALL)
8222 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8223 == (EDGE_ABNORMAL | EDGE_EH))
8226 if (e && !CALL_P (BB_END (bb))
8227 && !can_throw_internal (BB_END (bb)))
8231 /* Get past the new insns generated. Allow notes, as the insns
8232 may be already deleted. */
8234 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8235 && !can_throw_internal (insn)
8236 && insn != BB_HEAD (bb))
8237 insn = PREV_INSN (insn);
8239 if (CALL_P (insn) || can_throw_internal (insn))
8243 stop = NEXT_INSN (BB_END (bb));
8245 insn = NEXT_INSN (insn);
8247 FOR_EACH_EDGE (e, ei, bb->succs)
8248 if (e->flags & EDGE_FALLTHRU)
8251 while (insn && insn != stop)
8253 next = NEXT_INSN (insn);
8258 /* Sometimes there's still the return value USE.
8259 If it's placed after a trapping call (i.e. that
8260 call is the last insn anyway), we have no fallthru
8261 edge. Simply delete this use and don't try to insert
8262 on the non-existent edge. */
8263 if (GET_CODE (PATTERN (insn)) != USE)
8265 /* We're not deleting it, we're moving it. */
8266 INSN_DELETED_P (insn) = 0;
8267 PREV_INSN (insn) = NULL_RTX;
8268 NEXT_INSN (insn) = NULL_RTX;
8270 insert_insn_on_edge (insn, e);
8278 /* It may be that we don't find any such trapping insn. In this
8279 case we discovered quite late that the insn that had been
8280 marked as can_throw_internal in fact couldn't trap at all.
8281 So we should in fact delete the EH edges out of the block. */
8283 purge_dead_edges (bb);
8287 /* We've possibly turned single trapping insn into multiple ones. */
8288 if (flag_non_call_exceptions)
8291 blocks = sbitmap_alloc (last_basic_block);
8292 sbitmap_ones (blocks);
8293 find_many_sub_basic_blocks (blocks);
8297 commit_edge_insertions ();
8299 #ifdef ENABLE_CHECKING
8300 /* Verify that we didn't turn one trapping insn into many, and that
8301 we found and corrected all of the problems wrt fixups on the
8303 verify_flow_info ();