1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
35 * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.14 2006/10/25 20:55:57 dillon Exp $
39 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
40 * 1000mbps; all we need to negotiate here is full or half duplex.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/socket.h>
49 #include <machine/clock.h>
52 #include <net/if_media.h>
53 #include <net/if_arp.h>
59 #include "brgphyreg.h"
60 #include <dev/netif/bge/if_bgereg.h>
62 #include "miibus_if.h"
64 static int brgphy_probe(device_t);
65 static int brgphy_attach(device_t);
67 static const struct mii_phydesc brgphys[] = {
68 MII_PHYDESC(xxBROADCOM, BCM5400),
69 MII_PHYDESC(xxBROADCOM, BCM5401),
70 MII_PHYDESC(xxBROADCOM, BCM5411),
71 MII_PHYDESC(xxBROADCOM, BCM5421),
72 MII_PHYDESC(xxBROADCOM, BCM54K2),
73 MII_PHYDESC(xxBROADCOM, BCM5462),
75 MII_PHYDESC(xxBROADCOM, BCM5701),
76 MII_PHYDESC(xxBROADCOM, BCM5703),
77 MII_PHYDESC(xxBROADCOM, BCM5704),
78 MII_PHYDESC(xxBROADCOM, BCM5705),
80 MII_PHYDESC(xxBROADCOM, BCM5714),
81 MII_PHYDESC(xxBROADCOM, BCM5750),
82 MII_PHYDESC(xxBROADCOM, BCM5752),
83 MII_PHYDESC(xxBROADCOM, BCM5780),
85 MII_PHYDESC(xxBROADCOM, BCM5706C),
86 MII_PHYDESC(xxBROADCOM, BCM5708C),
91 static device_method_t brgphy_methods[] = {
92 /* device interface */
93 DEVMETHOD(device_probe, brgphy_probe),
94 DEVMETHOD(device_attach, brgphy_attach),
95 DEVMETHOD(device_detach, ukphy_detach),
96 DEVMETHOD(device_shutdown, bus_generic_shutdown),
100 static devclass_t brgphy_devclass;
102 static driver_t brgphy_driver = {
105 sizeof(struct mii_softc)
108 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
110 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
111 static void brgphy_status(struct mii_softc *);
112 static int brgphy_mii_phy_auto(struct mii_softc *, int);
113 static void brgphy_reset(struct mii_softc *);
114 static void brgphy_loop(struct mii_softc *);
116 static void brgphy_load_dspcode(struct mii_softc *);
117 static void brgphy_bcm5401_dspcode(struct mii_softc *);
118 static void brgphy_bcm5411_dspcode(struct mii_softc *);
119 static void brgphy_bcm5421_dspcode(struct mii_softc *);
120 static void brgphy_bcm54k2_dspcode(struct mii_softc *);
121 static void brgphy_bcm5703_dspcode(struct mii_softc *);
122 static void brgphy_bcm5704_dspcode(struct mii_softc *);
123 static void brgphy_bcm5750_dspcode(struct mii_softc *);
126 brgphy_probe(device_t dev)
128 struct mii_attach_args *ma = device_get_ivars(dev);
129 const struct mii_phydesc *mpd;
131 mpd = mii_phy_match(ma, brgphys);
133 device_set_desc(dev, mpd->mpd_name);
140 brgphy_attach(device_t dev)
142 struct mii_softc *sc;
143 struct mii_attach_args *ma;
144 struct mii_data *mii;
146 sc = device_get_softc(dev);
147 ma = device_get_ivars(dev);
148 mii_softc_init(sc, ma);
149 sc->mii_dev = device_get_parent(dev);
150 mii = device_get_softc(sc->mii_dev);
151 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
153 sc->mii_inst = mii->mii_instance;
154 sc->mii_service = brgphy_service;
155 sc->mii_reset = brgphy_reset;
158 sc->mii_flags |= MIIF_NOISOLATE;
163 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
165 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
168 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
174 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
175 if (sc->mii_capabilities & BMSR_EXTSTAT)
176 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
178 device_printf(dev, " ");
179 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
180 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
181 mii_phy_add_media(sc);
183 printf("no media present");
186 MIIBUS_MEDIAINIT(sc->mii_dev);
191 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
193 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
199 * If we're not polling our PHY instance, just return.
201 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
207 * If the media indicates a different PHY instance,
210 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
211 reg = PHY_READ(sc, MII_BMCR);
212 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
217 * If the interface is not up, don't do anything.
219 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
222 brgphy_reset(sc); /* XXX hardware bug work-around */
224 switch (IFM_SUBTYPE(ife->ifm_media)) {
228 * If we're already in auto mode, just return.
230 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
233 brgphy_mii_phy_auto(sc, 1);
236 speed = BRGPHY_S1000;
245 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
246 speed |= BRGPHY_BMCR_FDX;
247 gig = BRGPHY_1000CTL_AFD;
249 gig = BRGPHY_1000CTL_AHD;
252 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
253 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
254 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
256 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
259 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
260 PHY_WRITE(sc, BRGPHY_MII_BMCR,
261 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
263 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
267 * When settning the link manually, one side must
268 * be the master and the other the slave. However
269 * ifmedia doesn't give us a good way to specify
270 * this, so we fake it by using one of the LINK
271 * flags. If LINK0 is set, we program the PHY to
272 * be a master, otherwise it's a slave.
274 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
275 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
276 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
278 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
279 gig|BRGPHY_1000CTL_MSE);
284 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
295 * If we're not currently selected, just return.
297 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
301 * Is the interface even up?
303 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
307 * Only used for autonegotiation.
309 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
313 * Check to see if we have link. If we do, we don't
314 * need to restart the autonegotiation process. Read
315 * the BMSR twice in case it's latched.
317 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
318 if (reg & BRGPHY_AUXSTS_LINK)
322 * Only retry autonegotiation every 5 seconds.
324 if (++sc->mii_ticks <= sc->mii_anegticks)
328 if (brgphy_mii_phy_auto(sc, 0) == EJUSTRETURN)
333 /* Update the media status. */
337 * Callback if something changed. Note that we need to poke
338 * the DSP on the Broadcom PHYs if the media changes.
340 if (sc->mii_media_active != mii->mii_media_active ||
341 sc->mii_media_status != mii->mii_media_status ||
342 cmd == MII_MEDIACHG) {
343 switch (sc->mii_model) {
344 case MII_MODEL_BROADCOM_BCM5400:
345 case MII_MODEL_xxBROADCOM_BCM5401:
346 case MII_MODEL_xxBROADCOM_BCM5411:
347 brgphy_load_dspcode(sc);
351 mii_phy_update(sc, cmd);
356 brgphy_status(struct mii_softc *sc)
358 struct mii_data *mii = sc->mii_pdata;
359 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
362 mii->mii_media_status = IFM_AVALID;
363 mii->mii_media_active = IFM_ETHER;
365 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
366 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
367 mii->mii_media_status |= IFM_ACTIVE;
369 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
371 if (bmcr & BRGPHY_BMCR_LOOP)
372 mii->mii_media_active |= IFM_LOOP;
374 if (bmcr & BRGPHY_BMCR_AUTOEN) {
375 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
376 /* Erg, still trying, I guess... */
377 mii->mii_media_active |= IFM_NONE;
381 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
382 BRGPHY_AUXSTS_AN_RES) {
383 case BRGPHY_RES_1000FD:
384 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
386 case BRGPHY_RES_1000HD:
387 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
389 case BRGPHY_RES_100FD:
390 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
392 case BRGPHY_RES_100T4:
393 mii->mii_media_active |= IFM_100_T4;
395 case BRGPHY_RES_100HD:
396 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
398 case BRGPHY_RES_10FD:
399 mii->mii_media_active |= IFM_10_T | IFM_FDX;
401 case BRGPHY_RES_10HD:
402 mii->mii_media_active |= IFM_10_T | IFM_HDX;
405 mii->mii_media_active |= IFM_NONE;
411 mii->mii_media_active = ife->ifm_media;
416 brgphy_mii_phy_auto(struct mii_softc *sc, int waitfor)
418 int bmsr, ktcr = 0, i;
420 if ((sc->mii_flags & MIIF_DOINGAUTO) == 0) {
423 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
424 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
425 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
426 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
427 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
429 PHY_WRITE(sc, BRGPHY_MII_ANAR,
430 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
432 PHY_WRITE(sc, BRGPHY_MII_BMCR,
433 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
434 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
438 /* Wait 500ms for it to complete. */
439 for (i = 0; i < 500; i++) {
440 if ((bmsr = PHY_READ(sc, BRGPHY_MII_BMSR)) &
447 * Don't need to worry about clearing MIIF_DOINGAUTO.
448 * If that's set, a timeout is pending, and it will
455 * Just let it finish asynchronously. This is for the benefit of
456 * the tick handler driving autonegotiation. Don't want 500ms
457 * delays all the time while the system is running!
459 if ((sc->mii_flags & MIIF_DOINGAUTO) == 0) {
460 sc->mii_flags |= MIIF_DOINGAUTO;
461 callout_reset(&sc->mii_auto_ch, hz >> 1,
462 mii_phy_auto_timeout, sc);
465 return (EJUSTRETURN);
469 brgphy_loop(struct mii_softc *sc)
474 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
475 for (i = 0; i < 15000; i++) {
476 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
477 if (!(bmsr & BRGPHY_BMSR_LINK))
484 brgphy_reset(struct mii_softc *sc)
488 struct bge_softc *bge_sc;
492 ifp = sc->mii_pdata->mii_ifp;
493 bge_sc = ifp->if_softc;
495 brgphy_load_dspcode(sc);
498 * Don't enable Ethernet@WireSpeed for the 5700 or 5705
499 * other than A0 and A1 chips. Make sure we only do this
500 * test on "bge" NICs, since other drivers may use this
501 * same PHY subdriver.
503 if (strncmp(ifp->if_xname, "bge", 3) == 0 &&
504 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
505 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
506 (bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
507 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A1))))
510 /* Enable Ethernet@WireSpeed. */
511 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
512 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
513 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
515 /* Enable Link LED on Dell boxes */
516 if (bge_sc->bge_no_3_led) {
517 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
518 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
519 & ~BRGPHY_PHY_EXTCTL_3_LED);
523 /* Turn off tap power management on 5401. */
525 brgphy_bcm5401_dspcode(struct mii_softc *sc)
527 static const struct {
531 { BRGPHY_MII_AUXCTL, 0x0c20 },
532 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
533 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
534 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
535 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
536 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
537 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
538 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
539 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
540 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
541 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
546 for (i = 0; dspcode[i].reg != 0; i++)
547 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
551 /* Setting some undocumented voltage */
553 brgphy_bcm5411_dspcode(struct mii_softc *sc)
555 static const struct {
566 for (i = 0; dspcode[i].reg != 0; i++)
567 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
571 brgphy_bcm5421_dspcode(struct mii_softc *sc)
575 /* Set Class A mode */
576 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
577 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
578 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
580 /* Set FFE gamma override to -0.125 */
581 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
582 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
583 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
584 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
585 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
586 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
590 brgphy_bcm54k2_dspcode(struct mii_softc *sc)
592 static const struct {
602 for (i = 0; dspcode[i].reg != 0; i++)
603 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
607 brgphy_bcm5703_dspcode(struct mii_softc *sc)
609 static const struct {
613 { BRGPHY_MII_AUXCTL, 0x0c00 },
614 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
615 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
620 for (i = 0; dspcode[i].reg != 0; i++)
621 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
625 brgphy_bcm5704_dspcode(struct mii_softc *sc)
627 static const struct {
631 { BRGPHY_MII_AUXCTL, 0x0c00 },
632 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
633 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
634 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
635 { BRGPHY_MII_DSP_RW_PORT, 0x0323 },
636 { BRGPHY_MII_AUXCTL, 0x0400 },
643 for (i = 0; dspcode[i].reg != 0; i++)
644 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
648 brgphy_bcm5750_dspcode(struct mii_softc *sc)
650 static const struct {
654 { BRGPHY_MII_AUXCTL, 0x0c00 },
655 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
656 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
657 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
658 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
659 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
660 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
661 { BRGPHY_MII_AUXCTL, 0x0400 },
666 for (i = 0; dspcode[i].reg != 0; i++)
667 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
671 brgphy_load_dspcode(struct mii_softc *sc)
673 switch (sc->mii_model) {
674 case MII_MODEL_BROADCOM_BCM5400:
675 brgphy_bcm5401_dspcode(sc);
677 case MII_MODEL_BROADCOM_BCM5401:
678 if (sc->mii_rev == 1 || sc->mii_rev == 3)
679 brgphy_bcm5401_dspcode(sc);
681 case MII_MODEL_BROADCOM_BCM5411:
682 brgphy_bcm5411_dspcode(sc);
684 case MII_MODEL_xxBROADCOM_BCM5421:
685 brgphy_bcm5421_dspcode(sc);
687 case MII_MODEL_xxBROADCOM_BCM54K2:
688 brgphy_bcm54k2_dspcode(sc);
690 case MII_MODEL_xxBROADCOM_BCM5703:
691 brgphy_bcm5703_dspcode(sc);
693 case MII_MODEL_xxBROADCOM_BCM5704:
694 brgphy_bcm5704_dspcode(sc);
696 case MII_MODEL_xxBROADCOM_BCM5705:
697 case MII_MODEL_xxBROADCOM_BCM5750:
698 case MII_MODEL_xxBROADCOM_BCM5714:
699 case MII_MODEL_xxBROADCOM_BCM5780:
700 case MII_MODEL_xxBROADCOM_BCM5752:
701 case MII_MODEL_xxBROADCOM_BCM5706C:
702 case MII_MODEL_xxBROADCOM_BCM5708C:
703 brgphy_bcm5750_dspcode(sc);