1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi_drm/i915_drm.h>
34 #include <uapi_drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/kref.h>
50 #include <linux/kconfig.h>
51 #include <linux/pm_qos.h>
52 #include <linux/delay.h>
53 #include "intel_guc.h"
55 #define CONFIG_DRM_FBDEV_EMULATION 1
56 #define CONFIG_DRM_I915_KMS 1
57 #define CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT 1
61 /* General customization:
64 #define DRIVER_NAME "i915"
65 #define DRIVER_DESC "Intel Graphics"
66 #define DRIVER_DATE "20151010"
69 /* Many gcc seem to no see through this and fall over :( */
71 #define WARN_ON(x) ({ \
72 bool __i915_warn_cond = (x); \
73 if (__builtin_constant_p(__i915_warn_cond)) \
74 BUILD_BUG_ON(__i915_warn_cond); \
75 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
77 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
81 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
83 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
84 (long) (x), __func__);
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) { \
96 if (i915.verbose_state_checks) \
101 unlikely(__ret_warn_on); \
104 #define I915_STATE_WARN_ON(condition) ({ \
105 int __ret_warn_on = !!(condition); \
106 if (unlikely(__ret_warn_on)) { \
107 if (i915.verbose_state_checks) \
108 WARN(1, "WARN_ON(" #condition ")\n"); \
110 DRM_ERROR("WARN_ON(" #condition ")\n"); \
112 unlikely(__ret_warn_on); \
115 static inline const char *yesno(bool v)
117 return v ? "yes" : "no";
126 I915_MAX_PIPES = _PIPE_EDP
128 #define pipe_name(p) ((p) + 'A')
137 #define transcoder_name(t) ((t) + 'A')
140 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
141 * number of planes per CRTC. Not all platforms really have this many planes,
142 * which means some arrays of size I915_MAX_PLANES may have unused entries
143 * between the topmost sprite plane and the cursor plane.
152 #define plane_name(p) ((p) + 'A')
154 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
164 #define port_name(p) ((p) + 'A')
166 #define I915_NUM_PHYS_VLV 2
178 enum intel_display_power_domain {
182 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
183 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
184 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
185 POWER_DOMAIN_TRANSCODER_A,
186 POWER_DOMAIN_TRANSCODER_B,
187 POWER_DOMAIN_TRANSCODER_C,
188 POWER_DOMAIN_TRANSCODER_EDP,
189 POWER_DOMAIN_PORT_DDI_A_2_LANES,
190 POWER_DOMAIN_PORT_DDI_A_4_LANES,
191 POWER_DOMAIN_PORT_DDI_B_2_LANES,
192 POWER_DOMAIN_PORT_DDI_B_4_LANES,
193 POWER_DOMAIN_PORT_DDI_C_2_LANES,
194 POWER_DOMAIN_PORT_DDI_C_4_LANES,
195 POWER_DOMAIN_PORT_DDI_D_2_LANES,
196 POWER_DOMAIN_PORT_DDI_D_4_LANES,
197 POWER_DOMAIN_PORT_DDI_E_2_LANES,
198 POWER_DOMAIN_PORT_DSI,
199 POWER_DOMAIN_PORT_CRT,
200 POWER_DOMAIN_PORT_OTHER,
214 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
215 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
216 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
217 #define POWER_DOMAIN_TRANSCODER(tran) \
218 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
219 (tran) + POWER_DOMAIN_TRANSCODER_A)
223 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
235 #define for_each_hpd_pin(__pin) \
236 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
238 struct i915_hotplug {
239 struct work_struct hotplug_work;
242 unsigned long last_jiffies;
247 HPD_MARK_DISABLED = 2
249 } stats[HPD_NUM_PINS];
251 struct delayed_work reenable_work;
253 struct intel_digital_port *irq_port[I915_MAX_PORTS];
256 struct work_struct dig_port_work;
259 * if we get a HPD irq from DP and a HPD irq from non-DP
260 * the non-DP HPD could block the workqueue on a mode config
261 * mutex getting, that userspace may have taken. However
262 * userspace is waiting on the DP workqueue to run which is
263 * blocked behind the non-DP one.
265 struct workqueue_struct *dp_wq;
268 #define I915_GEM_GPU_DOMAINS \
269 (I915_GEM_DOMAIN_RENDER | \
270 I915_GEM_DOMAIN_SAMPLER | \
271 I915_GEM_DOMAIN_COMMAND | \
272 I915_GEM_DOMAIN_INSTRUCTION | \
273 I915_GEM_DOMAIN_VERTEX)
275 #define for_each_pipe(__dev_priv, __p) \
276 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
277 #define for_each_plane(__dev_priv, __pipe, __p) \
279 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
281 #define for_each_sprite(__dev_priv, __p, __s) \
283 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
286 #define for_each_crtc(dev, crtc) \
287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
289 #define for_each_intel_plane(dev, intel_plane) \
290 list_for_each_entry(intel_plane, \
291 &dev->mode_config.plane_list, \
294 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
295 list_for_each_entry(intel_plane, \
296 &(dev)->mode_config.plane_list, \
298 if ((intel_plane)->pipe == (intel_crtc)->pipe)
300 #define for_each_intel_crtc(dev, intel_crtc) \
301 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
303 #define for_each_intel_encoder(dev, intel_encoder) \
304 list_for_each_entry(intel_encoder, \
305 &(dev)->mode_config.encoder_list, \
308 #define for_each_intel_connector(dev, intel_connector) \
309 list_for_each_entry(intel_connector, \
310 &dev->mode_config.connector_list, \
313 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
314 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
315 if ((intel_encoder)->base.crtc == (__crtc))
317 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
318 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
319 if ((intel_connector)->base.encoder == (__encoder))
321 #define for_each_power_domain(domain, mask) \
322 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
323 if ((1 << (domain)) & (mask))
325 struct drm_i915_private;
326 struct i915_mm_struct;
327 struct i915_mmu_object;
329 struct drm_i915_file_private {
330 struct drm_i915_private *dev_priv;
331 struct drm_file *file;
334 struct spinlock lock;
335 struct list_head request_list;
336 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
337 * chosen to prevent the CPU getting more than a frame ahead of the GPU
338 * (when using lax throttling for the frontbuffer). We also use it to
339 * offer free GPU waitboosts for severely congested workloads.
341 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
343 struct idr context_idr;
345 struct intel_rps_client {
346 struct list_head link;
350 struct intel_engine_cs *bsd_ring;
354 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
355 /* real shared dpll ids must be >= 0 */
356 DPLL_ID_PCH_PLL_A = 0,
357 DPLL_ID_PCH_PLL_B = 1,
364 DPLL_ID_SKL_DPLL1 = 0,
365 DPLL_ID_SKL_DPLL2 = 1,
366 DPLL_ID_SKL_DPLL3 = 2,
368 #define I915_NUM_PLLS 3
370 struct intel_dpll_hw_state {
383 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
384 * lower part of ctrl1 and they get shifted into position when writing
385 * the register. This allows us to easily compare the state to share
389 /* HDMI only, 0 when used for DP */
390 uint32_t cfgcr1, cfgcr2;
393 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
397 struct intel_shared_dpll_config {
398 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
399 struct intel_dpll_hw_state hw_state;
402 struct intel_shared_dpll {
403 struct intel_shared_dpll_config config;
405 int active; /* count of number of active CRTCs (i.e. DPMS on) */
406 bool on; /* is the PLL actually active? Disabled during modeset */
408 /* should match the index in the dev_priv->shared_dplls array */
409 enum intel_dpll_id id;
410 /* The mode_set hook is optional and should be used together with the
411 * intel_prepare_shared_dpll function. */
412 void (*mode_set)(struct drm_i915_private *dev_priv,
413 struct intel_shared_dpll *pll);
414 void (*enable)(struct drm_i915_private *dev_priv,
415 struct intel_shared_dpll *pll);
416 void (*disable)(struct drm_i915_private *dev_priv,
417 struct intel_shared_dpll *pll);
418 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
419 struct intel_shared_dpll *pll,
420 struct intel_dpll_hw_state *hw_state);
428 /* Used by dp and fdi links */
429 struct intel_link_m_n {
437 void intel_link_compute_m_n(int bpp, int nlanes,
438 int pixel_clock, int link_clock,
439 struct intel_link_m_n *m_n);
441 /* Interface history:
444 * 1.2: Add Power Management
445 * 1.3: Add vblank support
446 * 1.4: Fix cmdbuffer path, add heap destroy
447 * 1.5: Add vblank pipe configuration
448 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
449 * - Support vertical blank on secondary display pipe
451 #define DRIVER_MAJOR 1
452 #define DRIVER_MINOR 6
453 #define DRIVER_PATCHLEVEL 0
455 #define WATCH_LISTS 0
457 struct opregion_header;
458 struct opregion_acpi;
459 struct opregion_swsci;
460 struct opregion_asle;
462 struct intel_opregion {
463 struct opregion_header *header;
464 struct opregion_acpi *acpi;
465 struct opregion_swsci *swsci;
466 u32 swsci_gbda_sub_functions;
467 u32 swsci_sbcb_sub_functions;
468 struct opregion_asle *asle;
471 struct work_struct asle_work;
473 #define OPREGION_SIZE (8*1024)
475 struct intel_overlay;
476 struct intel_overlay_error_state;
478 #define I915_FENCE_REG_NONE -1
479 #define I915_MAX_NUM_FENCES 32
480 /* 32 fences + sign bit for FENCE_REG_NONE */
481 #define I915_MAX_NUM_FENCE_BITS 6
483 struct drm_i915_fence_reg {
484 struct list_head lru_list;
485 struct drm_i915_gem_object *obj;
489 struct sdvo_device_mapping {
498 struct intel_display_error_state;
500 struct drm_i915_error_state {
509 /* Generic register state */
517 u32 error; /* gen6+ */
518 u32 err_int; /* gen7 */
519 u32 fault_data0; /* gen8, gen9 */
520 u32 fault_data1; /* gen8, gen9 */
526 u32 extra_instdone[I915_NUM_INSTDONE_REG];
527 u64 fence[I915_MAX_NUM_FENCES];
528 struct intel_overlay_error_state *overlay;
529 struct intel_display_error_state *display;
530 struct drm_i915_error_object *semaphore_obj;
532 struct drm_i915_error_ring {
534 /* Software tracked state */
537 enum intel_ring_hangcheck_action hangcheck_action;
540 /* our own tracking of ring head and tail */
544 u32 semaphore_seqno[I915_NUM_RINGS - 1];
563 u32 rc_psmi; /* sleep state */
564 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
566 struct drm_i915_error_object {
570 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
572 struct drm_i915_error_request {
587 char comm[TASK_COMM_LEN];
588 } ring[I915_NUM_RINGS];
590 struct drm_i915_error_buffer {
593 u32 rseqno[I915_NUM_RINGS], wseqno;
597 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
605 } **active_bo, **pinned_bo;
607 u32 *active_bo_count, *pinned_bo_count;
611 struct intel_connector;
612 struct intel_encoder;
613 struct intel_crtc_state;
614 struct intel_initial_plane_config;
619 struct drm_i915_display_funcs {
620 int (*get_display_clock_speed)(struct drm_device *dev);
621 int (*get_fifo_size)(struct drm_device *dev, int plane);
623 * find_dpll() - Find the best values for the PLL
624 * @limit: limits for the PLL
625 * @crtc: current CRTC
626 * @target: target frequency in kHz
627 * @refclk: reference clock frequency in kHz
628 * @match_clock: if provided, @best_clock P divider must
629 * match the P divider from @match_clock
630 * used for LVDS downclocking
631 * @best_clock: best PLL values found
633 * Returns true on success, false on failure.
635 bool (*find_dpll)(const struct intel_limit *limit,
636 struct intel_crtc_state *crtc_state,
637 int target, int refclk,
638 struct dpll *match_clock,
639 struct dpll *best_clock);
640 void (*update_wm)(struct drm_crtc *crtc);
641 void (*update_sprite_wm)(struct drm_plane *plane,
642 struct drm_crtc *crtc,
643 uint32_t sprite_width, uint32_t sprite_height,
644 int pixel_size, bool enable, bool scaled);
645 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
646 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
647 /* Returns the active state of the crtc, and if the crtc is active,
648 * fills out the pipe-config with the hw state. */
649 bool (*get_pipe_config)(struct intel_crtc *,
650 struct intel_crtc_state *);
651 void (*get_initial_plane_config)(struct intel_crtc *,
652 struct intel_initial_plane_config *);
653 int (*crtc_compute_clock)(struct intel_crtc *crtc,
654 struct intel_crtc_state *crtc_state);
655 void (*crtc_enable)(struct drm_crtc *crtc);
656 void (*crtc_disable)(struct drm_crtc *crtc);
657 void (*audio_codec_enable)(struct drm_connector *connector,
658 struct intel_encoder *encoder,
659 const struct drm_display_mode *adjusted_mode);
660 void (*audio_codec_disable)(struct intel_encoder *encoder);
661 void (*fdi_link_train)(struct drm_crtc *crtc);
662 void (*init_clock_gating)(struct drm_device *dev);
663 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
664 struct drm_framebuffer *fb,
665 struct drm_i915_gem_object *obj,
666 struct drm_i915_gem_request *req,
668 void (*update_primary_plane)(struct drm_crtc *crtc,
669 struct drm_framebuffer *fb,
671 void (*hpd_irq_setup)(struct drm_device *dev);
672 /* clock updates for mode set */
674 /* render clock increase/decrease */
675 /* display clock increase/decrease */
676 /* pll clock increase/decrease */
679 enum forcewake_domain_id {
680 FW_DOMAIN_ID_RENDER = 0,
681 FW_DOMAIN_ID_BLITTER,
687 enum forcewake_domains {
688 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
689 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
690 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
691 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
696 struct intel_uncore_funcs {
697 void (*force_wake_get)(struct drm_i915_private *dev_priv,
698 enum forcewake_domains domains);
699 void (*force_wake_put)(struct drm_i915_private *dev_priv,
700 enum forcewake_domains domains);
702 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
703 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
704 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
705 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
707 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
708 uint8_t val, bool trace);
709 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
710 uint16_t val, bool trace);
711 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
712 uint32_t val, bool trace);
713 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
714 uint64_t val, bool trace);
717 struct intel_uncore {
718 struct lock lock; /** lock is also taken in irq contexts. */
720 struct intel_uncore_funcs funcs;
723 enum forcewake_domains fw_domains;
725 struct intel_uncore_forcewake_domain {
726 struct drm_i915_private *i915;
727 enum forcewake_domain_id id;
729 struct timer_list timer;
736 } fw_domain[FW_DOMAIN_ID_COUNT];
739 /* Iterate over initialised fw domains */
740 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
741 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
742 (i__) < FW_DOMAIN_ID_COUNT; \
743 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
744 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
746 #define for_each_fw_domain(domain__, dev_priv__, i__) \
747 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
750 FW_UNINITIALIZED = 0,
757 uint32_t *dmc_payload;
758 uint32_t dmc_fw_size;
760 uint32_t mmioaddr[8];
761 uint32_t mmiodata[8];
762 enum csr_state state;
765 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
766 func(is_mobile) sep \
769 func(is_i945gm) sep \
771 func(need_gfx_hws) sep \
773 func(is_pineview) sep \
774 func(is_broadwater) sep \
775 func(is_crestline) sep \
776 func(is_ivybridge) sep \
777 func(is_valleyview) sep \
778 func(is_haswell) sep \
779 func(is_skylake) sep \
780 func(is_preliminary) sep \
782 func(has_pipe_cxsr) sep \
783 func(has_hotplug) sep \
784 func(cursor_needs_physical) sep \
785 func(has_overlay) sep \
786 func(overlay_needs_physical) sep \
787 func(supports_tv) sep \
792 #define DEFINE_FLAG(name) u8 name:1
793 #define SEP_SEMICOLON ;
795 struct intel_device_info {
796 u32 display_mmio_offset;
799 u8 num_sprites[I915_MAX_PIPES];
801 u8 ring_mask; /* Rings supported by the HW */
802 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
803 /* Register offsets for the various display pipes and transcoders */
804 int pipe_offsets[I915_MAX_TRANSCODERS];
805 int trans_offsets[I915_MAX_TRANSCODERS];
806 int palette_offsets[I915_MAX_PIPES];
807 int cursor_offsets[I915_MAX_PIPES];
809 /* Slice/subslice/EU info */
812 u8 subslice_per_slice;
815 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
818 u8 has_subslice_pg:1;
825 enum i915_cache_level {
827 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
828 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
829 caches, eg sampler/render caches, and the
830 large Last-Level-Cache. LLC is coherent with
831 the CPU, but L3 is only visible to the GPU. */
832 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
835 struct i915_ctx_hang_stats {
836 /* This context had batch pending when hang was declared */
837 unsigned batch_pending;
839 /* This context had batch active when hang was declared */
840 unsigned batch_active;
842 /* Time when this context was last blamed for a GPU reset */
843 unsigned long guilty_ts;
845 /* If the contexts causes a second GPU hang within this time,
846 * it is permanently banned from submitting any more work.
848 unsigned long ban_period_seconds;
850 /* This context is banned to submit more work */
854 /* This must match up with the value previously used for execbuf2.rsvd1. */
855 #define DEFAULT_CONTEXT_HANDLE 0
857 #define CONTEXT_NO_ZEROMAP (1<<0)
859 * struct intel_context - as the name implies, represents a context.
860 * @ref: reference count.
861 * @user_handle: userspace tracking identity for this context.
862 * @remap_slice: l3 row remapping information.
863 * @flags: context specific flags:
864 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
865 * @file_priv: filp associated with this context (NULL for global default
867 * @hang_stats: information about the role of this context in possible GPU
869 * @ppgtt: virtual memory space used by this context.
870 * @legacy_hw_ctx: render context backing object and whether it is correctly
871 * initialized (legacy ring submission mechanism only).
872 * @link: link in the global list of contexts.
874 * Contexts are memory images used by the hardware to store copies of their
877 struct intel_context {
881 struct drm_i915_private *i915;
883 struct drm_i915_file_private *file_priv;
884 struct i915_ctx_hang_stats hang_stats;
885 struct i915_hw_ppgtt *ppgtt;
887 /* Legacy ring buffer submission */
889 struct drm_i915_gem_object *rcs_state;
895 struct drm_i915_gem_object *state;
896 struct intel_ringbuffer *ringbuf;
898 } engine[I915_NUM_RINGS];
900 struct list_head link;
912 /* This is always the inner lock when overlapping with struct_mutex and
913 * it's the outer lock when overlapping with stolen_lock. */
915 unsigned long uncompressed_size;
918 unsigned int possible_framebuffer_bits;
919 unsigned int busy_bits;
920 struct intel_crtc *crtc;
923 struct drm_mm_node compressed_fb;
924 struct drm_mm_node *compressed_llb;
928 /* Tracks whether the HW is actually enabled, not whether the feature is
932 struct intel_fbc_work {
933 struct delayed_work work;
934 struct intel_crtc *crtc;
935 struct drm_framebuffer *fb;
939 FBC_OK, /* FBC is enabled */
940 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
941 FBC_NO_OUTPUT, /* no outputs enabled to compress */
942 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
943 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
944 FBC_MODE_TOO_LARGE, /* mode too large for compression */
945 FBC_BAD_PLANE, /* fbc not supported on plane */
946 FBC_NOT_TILED, /* buffer not tiled */
947 FBC_MULTIPLE_PIPES, /* more than one pipe active */
949 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
950 FBC_ROTATION, /* rotation is not supported */
951 FBC_IN_DBG_MASTER, /* kernel debugger is active */
952 FBC_BAD_STRIDE, /* stride is not supported */
953 FBC_PIXEL_RATE, /* pixel rate is too big */
954 FBC_PIXEL_FORMAT /* pixel format is invalid */
957 bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
958 void (*enable_fbc)(struct intel_crtc *crtc);
959 void (*disable_fbc)(struct drm_i915_private *dev_priv);
963 * HIGH_RR is the highest eDP panel refresh rate read from EDID
964 * LOW_RR is the lowest eDP panel refresh rate found from EDID
965 * parsing for same resolution.
967 enum drrs_refresh_rate_type {
970 DRRS_MAX_RR, /* RR count */
973 enum drrs_support_type {
974 DRRS_NOT_SUPPORTED = 0,
975 STATIC_DRRS_SUPPORT = 1,
976 SEAMLESS_DRRS_SUPPORT = 2
982 struct delayed_work work;
984 unsigned busy_frontbuffer_bits;
985 enum drrs_refresh_rate_type refresh_rate_type;
986 enum drrs_support_type type;
993 struct intel_dp *enabled;
995 struct delayed_work work;
996 unsigned busy_frontbuffer_bits;
1002 PCH_NONE = 0, /* No PCH present */
1003 PCH_IBX, /* Ibexpeak PCH */
1004 PCH_CPT, /* Cougarpoint PCH */
1005 PCH_LPT, /* Lynxpoint PCH */
1006 PCH_SPT, /* Sunrisepoint PCH */
1010 enum intel_sbi_destination {
1015 #define QUIRK_PIPEA_FORCE (1<<0)
1016 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1017 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1018 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1019 #define QUIRK_PIPEB_FORCE (1<<4)
1020 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1023 struct intel_fbc_work;
1025 struct intel_gmbus {
1026 struct i2c_adapter adapter;
1030 struct drm_i915_private *dev_priv;
1033 struct intel_iic_softc {
1034 struct drm_device *drm_dev;
1042 struct i915_suspend_saved_registers {
1045 u32 savePP_ON_DELAYS;
1046 u32 savePP_OFF_DELAYS;
1051 u32 saveFBC_CONTROL;
1052 u32 saveCACHE_MODE_0;
1053 u32 saveMI_ARB_STATE;
1057 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1058 u32 savePCH_PORT_HOTPLUG;
1062 struct vlv_s0ix_state {
1069 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1070 u32 media_max_req_count;
1071 u32 gfx_max_req_count;
1097 u32 rp_down_timeout;
1103 /* Display 1 CZ domain */
1108 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1110 /* GT SA CZ domain */
1117 /* Display 2 CZ domain */
1121 u32 clock_gate_dis2;
1124 struct intel_rps_ei {
1130 struct intel_gen6_power_mgmt {
1132 * work, interrupts_enabled and pm_iir are protected by
1133 * dev_priv->irq_lock
1135 struct work_struct work;
1136 bool interrupts_enabled;
1139 /* Frequencies are stored in potentially platform dependent multiples.
1140 * In other words, *_freq needs to be multiplied by X to be interesting.
1141 * Soft limits are those which are used for the dynamic reclocking done
1142 * by the driver (raise frequencies under heavy loads, and lower for
1143 * lighter loads). Hard limits are those imposed by the hardware.
1145 * A distinction is made for overclocking, which is never enabled by
1146 * default, and is considered to be above the hard limit if it's
1149 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1150 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1151 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1152 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1153 u8 min_freq; /* AKA RPn. Minimum frequency */
1154 u8 idle_freq; /* Frequency to request when we are idle */
1155 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1156 u8 rp1_freq; /* "less than" RP0 power/freqency */
1157 u8 rp0_freq; /* Non-overclocked max frequency. */
1159 u8 up_threshold; /* Current %busy required to uplock */
1160 u8 down_threshold; /* Current %busy required to downclock */
1163 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1165 struct lock client_lock;
1166 struct list_head clients;
1170 struct delayed_work delayed_resume_work;
1173 struct intel_rps_client semaphores, mmioflips;
1175 /* manual wa residency calculations */
1176 struct intel_rps_ei up_ei, down_ei;
1179 * Protects RPS/RC6 register access and PCU communication.
1180 * Must be taken after struct_mutex if nested. Note that
1181 * this lock may be held for long periods of time when
1182 * talking to hw - so only take it when talking to hw!
1184 struct lock hw_lock;
1187 /* defined intel_pm.c */
1188 extern struct lock mchdev_lock;
1190 struct intel_ilk_power_mgmt {
1198 unsigned long last_time1;
1199 unsigned long chipset_power;
1202 unsigned long gfx_power;
1209 struct drm_i915_private;
1210 struct i915_power_well;
1212 struct i915_power_well_ops {
1214 * Synchronize the well's hw state to match the current sw state, for
1215 * example enable/disable it based on the current refcount. Called
1216 * during driver init and resume time, possibly after first calling
1217 * the enable/disable handlers.
1219 void (*sync_hw)(struct drm_i915_private *dev_priv,
1220 struct i915_power_well *power_well);
1222 * Enable the well and resources that depend on it (for example
1223 * interrupts located on the well). Called after the 0->1 refcount
1226 void (*enable)(struct drm_i915_private *dev_priv,
1227 struct i915_power_well *power_well);
1229 * Disable the well and resources that depend on it. Called after
1230 * the 1->0 refcount transition.
1232 void (*disable)(struct drm_i915_private *dev_priv,
1233 struct i915_power_well *power_well);
1234 /* Returns the hw enabled state. */
1235 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1236 struct i915_power_well *power_well);
1239 /* Power well structure for haswell */
1240 struct i915_power_well {
1243 /* power well enable/disable usage count */
1245 /* cached hw enabled state */
1247 unsigned long domains;
1249 const struct i915_power_well_ops *ops;
1252 struct i915_power_domains {
1254 * Power wells needed for initialization at driver init and suspend
1255 * time are on. They are kept on until after the first modeset.
1259 int power_well_count;
1262 int domain_use_count[POWER_DOMAIN_NUM];
1263 struct i915_power_well *power_wells;
1266 #define MAX_L3_SLICES 2
1267 struct intel_l3_parity {
1268 u32 *remap_info[MAX_L3_SLICES];
1269 struct work_struct error_work;
1273 struct i915_gem_mm {
1274 /** Memory allocator for GTT stolen memory */
1275 struct drm_mm stolen;
1276 /** Protects the usage of the GTT stolen memory allocator. This is
1277 * always the inner lock when overlapping with struct_mutex. */
1278 struct lock stolen_lock;
1280 /** List of all objects in gtt_space. Used to restore gtt
1281 * mappings on resume */
1282 struct list_head bound_list;
1284 * List of objects which are not bound to the GTT (thus
1285 * are idle and not used by the GPU) but still have
1286 * (presumably uncached) pages still attached.
1288 struct list_head unbound_list;
1290 /** Usable portion of the GTT for GEM */
1291 unsigned long stolen_base; /* limited to low memory (32-bit) */
1293 /** PPGTT used for aliasing the PPGTT with the GTT */
1294 struct i915_hw_ppgtt *aliasing_ppgtt;
1296 struct notifier_block oom_notifier;
1298 struct shrinker shrinker;
1300 bool shrinker_no_lock_stealing;
1302 /** LRU list of objects with fence regs on them. */
1303 struct list_head fence_list;
1306 * We leave the user IRQ off as much as possible,
1307 * but this means that requests will finish and never
1308 * be retired once the system goes idle. Set a timer to
1309 * fire periodically while the ring is running. When it
1310 * fires, go retire requests.
1312 struct delayed_work retire_work;
1315 * When we detect an idle GPU, we want to turn on
1316 * powersaving features. So once we see that there
1317 * are no more requests outstanding and no more
1318 * arrive within a small period of time, we fire
1319 * off the idle_work.
1321 struct delayed_work idle_work;
1324 * Are we in a non-interruptible section of code like
1330 * Is the GPU currently considered idle, or busy executing userspace
1331 * requests? Whilst idle, we attempt to power down the hardware and
1332 * display clocks. In order to reduce the effect on performance, there
1333 * is a slight delay before we do so.
1337 /* the indicator for dispatch video commands on two BSD rings */
1338 int bsd_ring_dispatch_index;
1340 /** Bit 6 swizzling required for X tiling */
1341 uint32_t bit_6_swizzle_x;
1342 /** Bit 6 swizzling required for Y tiling */
1343 uint32_t bit_6_swizzle_y;
1345 /* accounting, useful for userland debugging */
1346 struct spinlock object_stat_lock;
1347 size_t object_memory;
1351 struct drm_i915_error_state_buf {
1352 struct drm_i915_private *i915;
1361 struct i915_error_state_file_priv {
1362 struct drm_device *dev;
1363 struct drm_i915_error_state *error;
1366 struct i915_gpu_error {
1367 /* For hangcheck timer */
1368 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1369 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1370 /* Hang gpu twice in this window and your context gets banned */
1371 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1373 struct workqueue_struct *hangcheck_wq;
1374 struct delayed_work hangcheck_work;
1376 /* For reset and error_state handling. */
1378 /* Protected by the above dev->gpu_error.lock. */
1379 struct drm_i915_error_state *first_error;
1381 unsigned long missed_irq_rings;
1384 * State variable controlling the reset flow and count
1386 * This is a counter which gets incremented when reset is triggered,
1387 * and again when reset has been handled. So odd values (lowest bit set)
1388 * means that reset is in progress and even values that
1389 * (reset_counter >> 1):th reset was successfully completed.
1391 * If reset is not completed succesfully, the I915_WEDGE bit is
1392 * set meaning that hardware is terminally sour and there is no
1393 * recovery. All waiters on the reset_queue will be woken when
1396 * This counter is used by the wait_seqno code to notice that reset
1397 * event happened and it needs to restart the entire ioctl (since most
1398 * likely the seqno it waited for won't ever signal anytime soon).
1400 * This is important for lock-free wait paths, where no contended lock
1401 * naturally enforces the correct ordering between the bail-out of the
1402 * waiter and the gpu reset work code.
1404 atomic_t reset_counter;
1406 #define I915_RESET_IN_PROGRESS_FLAG 1
1407 #define I915_WEDGED (1 << 31)
1410 * Waitqueue to signal when the reset has completed. Used by clients
1411 * that wait for dev_priv->mm.wedged to settle.
1413 wait_queue_head_t reset_queue;
1415 /* Userspace knobs for gpu hang simulation;
1416 * combines both a ring mask, and extra flags
1419 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1420 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1422 /* For missed irq/seqno simulation. */
1423 unsigned int test_irq_rings;
1425 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1426 bool reload_in_reset;
1429 enum modeset_restore {
1430 MODESET_ON_LID_OPEN,
1435 #define DP_AUX_A 0x40
1436 #define DP_AUX_B 0x10
1437 #define DP_AUX_C 0x20
1438 #define DP_AUX_D 0x30
1440 #define DDC_PIN_B 0x05
1441 #define DDC_PIN_C 0x04
1442 #define DDC_PIN_D 0x06
1444 struct ddi_vbt_port_info {
1446 * This is an index in the HDMI/DVI DDI buffer translation table.
1447 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1448 * populate this field.
1450 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1451 uint8_t hdmi_level_shift;
1453 uint8_t supports_dvi:1;
1454 uint8_t supports_hdmi:1;
1455 uint8_t supports_dp:1;
1457 uint8_t alternate_aux_channel;
1458 uint8_t alternate_ddc_pin;
1460 uint8_t dp_boost_level;
1461 uint8_t hdmi_boost_level;
1464 enum psr_lines_to_wait {
1465 PSR_0_LINES_TO_WAIT = 0,
1467 PSR_4_LINES_TO_WAIT,
1471 struct intel_vbt_data {
1472 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1473 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1476 unsigned int int_tv_support:1;
1477 unsigned int lvds_dither:1;
1478 unsigned int lvds_vbt:1;
1479 unsigned int int_crt_support:1;
1480 unsigned int lvds_use_ssc:1;
1481 unsigned int display_clock_mode:1;
1482 unsigned int fdi_rx_polarity_inverted:1;
1483 unsigned int has_mipi:1;
1485 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1487 enum drrs_support_type drrs_type;
1492 int edp_preemphasis;
1494 bool edp_initialized;
1497 struct edp_power_seq edp_pps;
1501 bool require_aux_wakeup;
1503 enum psr_lines_to_wait lines_to_wait;
1504 int tp1_wakeup_time;
1505 int tp2_tp3_wakeup_time;
1511 bool active_low_pwm;
1512 u8 min_brightness; /* min_brightness/255 of max */
1519 struct mipi_config *config;
1520 struct mipi_pps_data *pps;
1524 u8 *sequence[MIPI_SEQ_MAX];
1530 union child_device_config *child_dev;
1532 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1535 enum intel_ddb_partitioning {
1537 INTEL_DDB_PART_5_6, /* IVB+ */
1540 struct intel_wm_level {
1548 struct ilk_wm_values {
1549 uint32_t wm_pipe[3];
1551 uint32_t wm_lp_spr[3];
1552 uint32_t wm_linetime[3];
1554 enum intel_ddb_partitioning partitioning;
1557 struct vlv_pipe_wm {
1568 struct vlv_wm_values {
1569 struct vlv_pipe_wm pipe[3];
1570 struct vlv_sr_wm sr;
1580 struct skl_ddb_entry {
1581 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1584 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1586 return entry->end - entry->start;
1589 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1590 const struct skl_ddb_entry *e2)
1592 if (e1->start == e2->start && e1->end == e2->end)
1598 struct skl_ddb_allocation {
1599 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1600 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1601 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1604 struct skl_wm_values {
1605 bool dirty[I915_MAX_PIPES];
1606 struct skl_ddb_allocation ddb;
1607 uint32_t wm_linetime[I915_MAX_PIPES];
1608 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1609 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1612 struct skl_wm_level {
1613 bool plane_en[I915_MAX_PLANES];
1614 uint16_t plane_res_b[I915_MAX_PLANES];
1615 uint8_t plane_res_l[I915_MAX_PLANES];
1619 * This struct helps tracking the state needed for runtime PM, which puts the
1620 * device in PCI D3 state. Notice that when this happens, nothing on the
1621 * graphics device works, even register access, so we don't get interrupts nor
1624 * Every piece of our code that needs to actually touch the hardware needs to
1625 * either call intel_runtime_pm_get or call intel_display_power_get with the
1626 * appropriate power domain.
1628 * Our driver uses the autosuspend delay feature, which means we'll only really
1629 * suspend if we stay with zero refcount for a certain amount of time. The
1630 * default value is currently very conservative (see intel_runtime_pm_enable), but
1631 * it can be changed with the standard runtime PM files from sysfs.
1633 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1634 * goes back to false exactly before we reenable the IRQs. We use this variable
1635 * to check if someone is trying to enable/disable IRQs while they're supposed
1636 * to be disabled. This shouldn't happen and we'll print some error messages in
1639 * For more, read the Documentation/power/runtime_pm.txt.
1641 struct i915_runtime_pm {
1646 enum intel_pipe_crc_source {
1647 INTEL_PIPE_CRC_SOURCE_NONE,
1648 INTEL_PIPE_CRC_SOURCE_PLANE1,
1649 INTEL_PIPE_CRC_SOURCE_PLANE2,
1650 INTEL_PIPE_CRC_SOURCE_PF,
1651 INTEL_PIPE_CRC_SOURCE_PIPE,
1652 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1653 INTEL_PIPE_CRC_SOURCE_TV,
1654 INTEL_PIPE_CRC_SOURCE_DP_B,
1655 INTEL_PIPE_CRC_SOURCE_DP_C,
1656 INTEL_PIPE_CRC_SOURCE_DP_D,
1657 INTEL_PIPE_CRC_SOURCE_AUTO,
1658 INTEL_PIPE_CRC_SOURCE_MAX,
1661 struct intel_pipe_crc_entry {
1666 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1667 struct intel_pipe_crc {
1668 struct spinlock lock;
1669 bool opened; /* exclusive access to the result file */
1670 struct intel_pipe_crc_entry *entries;
1671 enum intel_pipe_crc_source source;
1673 wait_queue_head_t wq;
1676 struct i915_frontbuffer_tracking {
1680 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1687 struct i915_wa_reg {
1690 /* bitmask representing WA bits */
1694 #define I915_MAX_WA_REGS 16
1696 struct i915_workarounds {
1697 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1701 struct i915_virtual_gpu {
1705 struct i915_execbuffer_params {
1706 struct drm_device *dev;
1707 struct drm_file *file;
1708 uint32_t dispatch_flags;
1709 uint32_t args_batch_start_offset;
1710 uint64_t batch_obj_vm_offset;
1711 struct intel_engine_cs *ring;
1712 struct drm_i915_gem_object *batch_obj;
1713 struct intel_context *ctx;
1714 struct drm_i915_gem_request *request;
1717 struct drm_i915_private {
1718 struct drm_device *dev;
1719 struct kmem_cache *objects;
1720 struct kmem_cache *vmas;
1721 struct kmem_cache *requests;
1723 struct intel_device_info info;
1725 int relative_constants_mode;
1727 device_t *gmbus_bridge;
1728 device_t *bbbus_bridge;
1733 struct intel_uncore uncore;
1735 struct i915_virtual_gpu vgpu;
1737 struct intel_guc guc;
1739 struct intel_csr csr;
1741 /* Display CSR-related protection */
1742 struct lock csr_lock;
1746 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1747 * controller on different i2c buses. */
1748 struct lock gmbus_mutex;
1751 * Base address of the gmbus and gpio block.
1753 uint32_t gpio_mmio_base;
1755 /* MMIO base address for MIPI regs */
1756 uint32_t mipi_mmio_base;
1758 wait_queue_head_t gmbus_wait_queue;
1760 struct pci_dev *bridge_dev;
1761 struct intel_engine_cs ring[I915_NUM_RINGS];
1762 struct drm_i915_gem_object *semaphore_obj;
1763 uint32_t last_seqno, next_seqno;
1765 struct drm_dma_handle *status_page_dmah;
1766 struct resource *mch_res;
1769 /* protects the irq masks */
1770 struct lock irq_lock;
1772 /* protects the mmio flip data */
1773 struct spinlock mmio_flip_lock;
1775 bool display_irqs_enabled;
1777 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1778 struct pm_qos_request pm_qos;
1780 /* Sideband mailbox protection */
1781 struct lock sb_lock;
1783 /** Cached value of IMR to avoid reads in updating the bitfield */
1786 u32 de_irq_mask[I915_MAX_PIPES];
1791 u32 pipestat_irq_mask[I915_MAX_PIPES];
1793 struct i915_hotplug hotplug;
1794 struct i915_fbc fbc;
1795 struct i915_drrs drrs;
1796 struct intel_opregion opregion;
1797 struct intel_vbt_data vbt;
1799 bool preserve_bios_swizzle;
1802 struct intel_overlay *overlay;
1804 /* backlight registers and fields in struct intel_panel */
1805 struct lock backlight_lock;
1808 bool no_aux_handshake;
1810 /* protects panel power sequencer state */
1811 struct lock pps_mutex;
1813 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1814 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1815 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1817 unsigned int fsb_freq, mem_freq, is_ddr3;
1818 unsigned int skl_boot_cdclk;
1819 unsigned int cdclk_freq, max_cdclk_freq;
1820 unsigned int max_dotclk_freq;
1821 unsigned int hpll_freq;
1822 unsigned int czclk_freq;
1825 * wq - Driver workqueue for GEM.
1827 * NOTE: Work items scheduled here are not allowed to grab any modeset
1828 * locks, for otherwise the flushing done in the pageflip code will
1829 * result in deadlocks.
1831 struct workqueue_struct *wq;
1833 /* Display functions */
1834 struct drm_i915_display_funcs display;
1836 /* PCH chipset type */
1837 enum intel_pch pch_type;
1838 unsigned short pch_id;
1840 unsigned long quirks;
1842 enum modeset_restore modeset_restore;
1843 struct lock modeset_restore_lock;
1845 struct list_head vm_list; /* Global list of all address spaces */
1846 struct i915_gtt gtt; /* VM representing the global address space */
1848 struct i915_gem_mm mm;
1849 DECLARE_HASHTABLE(mm_structs, 7);
1850 struct lock mm_lock;
1852 /* Kernel Modesetting */
1854 struct sdvo_device_mapping sdvo_mappings[2];
1856 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1857 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1858 wait_queue_head_t pending_flip_queue;
1860 #ifdef CONFIG_DEBUG_FS
1861 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1864 int num_shared_dpll;
1865 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1866 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1868 struct i915_workarounds workarounds;
1870 /* Reclocking support */
1871 bool render_reclock_avail;
1873 struct i915_frontbuffer_tracking fb_tracking;
1877 bool mchbar_need_disable;
1879 struct intel_l3_parity l3_parity;
1881 /* Cannot be determined by PCIID. You must always read a register. */
1884 /* gen6+ rps state */
1885 struct intel_gen6_power_mgmt rps;
1887 /* ilk-only ips/rps state. Everything in here is protected by the global
1888 * mchdev_lock in intel_pm.c */
1889 struct intel_ilk_power_mgmt ips;
1891 struct i915_power_domains power_domains;
1893 struct i915_psr psr;
1895 struct i915_gpu_error gpu_error;
1897 struct drm_i915_gem_object *vlv_pctx;
1899 #ifdef CONFIG_DRM_FBDEV_EMULATION
1900 /* list of fbdev register on this device */
1901 struct intel_fbdev *fbdev;
1902 struct work_struct fbdev_suspend_work;
1905 struct drm_property *broadcast_rgb_property;
1906 struct drm_property *force_audio_property;
1908 /* hda/i915 audio component */
1909 struct i915_audio_component *audio_component;
1910 bool audio_component_registered;
1912 * av_mutex - mutex for audio/video sync
1915 struct lock av_mutex;
1917 uint32_t hw_context_size;
1918 struct list_head context_list;
1922 u32 chv_phy_control;
1925 struct i915_suspend_saved_registers regfile;
1926 struct vlv_s0ix_state vlv_s0ix_state;
1930 * Raw watermark latency values:
1931 * in 0.1us units for WM0,
1932 * in 0.5us units for WM1+.
1935 uint16_t pri_latency[5];
1937 uint16_t spr_latency[5];
1939 uint16_t cur_latency[5];
1941 * Raw watermark memory latency values
1942 * for SKL for all 8 levels
1945 uint16_t skl_latency[8];
1948 * The skl_wm_values structure is a bit too big for stack
1949 * allocation, so we keep the staging struct where we store
1950 * intermediate results here instead.
1952 struct skl_wm_values skl_results;
1954 /* current hardware state */
1956 struct ilk_wm_values hw;
1957 struct skl_wm_values skl_hw;
1958 struct vlv_wm_values vlv;
1964 struct i915_runtime_pm pm;
1966 uint32_t bios_vgacntr;
1968 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1970 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1971 struct drm_i915_gem_execbuffer2 *args,
1972 struct list_head *vmas);
1973 int (*init_rings)(struct drm_device *dev);
1974 void (*cleanup_ring)(struct intel_engine_cs *ring);
1975 void (*stop_ring)(struct intel_engine_cs *ring);
1978 bool edp_low_vswing;
1980 /* perform PHY state sanity checks? */
1981 bool chv_phy_assert[2];
1984 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1985 * will be rejected. Instead look for a better place.
1989 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1991 return dev->dev_private;
1994 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1999 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2001 return container_of(guc, struct drm_i915_private, guc);
2004 /* Iterate over initialised rings */
2005 #define for_each_ring(ring__, dev_priv__, i__) \
2006 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2007 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
2009 enum hdmi_force_audio {
2010 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2011 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2012 HDMI_AUDIO_AUTO, /* trust EDID */
2013 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2016 #define I915_GTT_OFFSET_NONE ((u32)-1)
2018 struct drm_i915_gem_object_ops {
2019 /* Interface between the GEM object and its backing storage.
2020 * get_pages() is called once prior to the use of the associated set
2021 * of pages before to binding them into the GTT, and put_pages() is
2022 * called after we no longer need them. As we expect there to be
2023 * associated cost with migrating pages between the backing storage
2024 * and making them available for the GPU (e.g. clflush), we may hold
2025 * onto the pages after they are no longer referenced by the GPU
2026 * in case they may be used again shortly (for example migrating the
2027 * pages to a different memory domain within the GTT). put_pages()
2028 * will therefore most likely be called when the object itself is
2029 * being released or under memory pressure (where we attempt to
2030 * reap pages for the shrinker).
2032 int (*get_pages)(struct drm_i915_gem_object *);
2033 void (*put_pages)(struct drm_i915_gem_object *);
2034 int (*dmabuf_export)(struct drm_i915_gem_object *);
2035 void (*release)(struct drm_i915_gem_object *);
2039 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2040 * considered to be the frontbuffer for the given plane interface-wise. This
2041 * doesn't mean that the hw necessarily already scans it out, but that any
2042 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2044 * We have one bit per pipe and per scanout plane type.
2046 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2047 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2048 #define INTEL_FRONTBUFFER_BITS \
2049 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2050 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2051 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2052 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2053 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2054 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2055 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2056 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2057 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2058 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2059 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2061 struct drm_i915_gem_object {
2062 struct drm_gem_object base;
2064 const struct drm_i915_gem_object_ops *ops;
2066 /** List of VMAs backed by this object */
2067 struct list_head vma_list;
2069 /** Stolen memory for this object, instead of being backed by shmem. */
2070 struct drm_mm_node *stolen;
2071 struct list_head global_list;
2073 struct list_head ring_list[I915_NUM_RINGS];
2074 /** Used in execbuf to temporarily hold a ref */
2075 struct list_head obj_exec_link;
2077 struct list_head batch_pool_link;
2080 * This is set if the object is on the active lists (has pending
2081 * rendering and so a non-zero seqno), and is not set if it i s on
2082 * inactive (ready to be unbound) list.
2084 unsigned int active:I915_NUM_RINGS;
2087 * This is set if the object has been written to since last bound
2090 unsigned int dirty:1;
2093 * Fence register bits (if any) for this object. Will be set
2094 * as needed when mapped into the GTT.
2095 * Protected by dev->struct_mutex.
2097 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2100 * Advice: are the backing pages purgeable?
2102 unsigned int madv:2;
2105 * Current tiling mode for the object.
2107 unsigned int tiling_mode:2;
2109 * Whether the tiling parameters for the currently associated fence
2110 * register have changed. Note that for the purposes of tracking
2111 * tiling changes we also treat the unfenced register, the register
2112 * slot that the object occupies whilst it executes a fenced
2113 * command (such as BLT on gen2/3), as a "fence".
2115 unsigned int fence_dirty:1;
2118 * Is the object at the current location in the gtt mappable and
2119 * fenceable? Used to avoid costly recalculations.
2121 unsigned int map_and_fenceable:1;
2124 * Whether the current gtt mapping needs to be mappable (and isn't just
2125 * mappable by accident). Track pin and fault separate for a more
2126 * accurate mappable working set.
2128 unsigned int fault_mappable:1;
2131 * Is the object to be mapped as read-only to the GPU
2132 * Only honoured if hardware has relevant pte bit
2134 unsigned long gt_ro:1;
2135 unsigned int cache_level:3;
2136 unsigned int cache_dirty:1;
2138 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2140 unsigned int pin_display;
2142 struct sg_table *pages;
2143 int pages_pin_count;
2145 struct scatterlist *sg;
2149 /* prime dma-buf support */
2150 void *dma_buf_vmapping;
2153 /** Breadcrumb of last rendering to the buffer.
2154 * There can only be one writer, but we allow for multiple readers.
2155 * If there is a writer that necessarily implies that all other
2156 * read requests are complete - but we may only be lazily clearing
2157 * the read requests. A read request is naturally the most recent
2158 * request on a ring, so we may have two different write and read
2159 * requests on one ring where the write request is older than the
2160 * read request. This allows for the CPU to read from an active
2161 * buffer by only waiting for the write to complete.
2163 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2164 struct drm_i915_gem_request *last_write_req;
2165 /** Breadcrumb of last fenced GPU access to the buffer. */
2166 struct drm_i915_gem_request *last_fenced_req;
2168 /** Current tiling stride for the object, if it's tiled. */
2171 /** References from framebuffers, locks out tiling changes. */
2172 unsigned long framebuffer_references;
2174 /** Record of address bit 17 of each page at last unbind. */
2175 unsigned long *bit_17;
2178 /** for phy allocated objects */
2179 struct drm_dma_handle *phys_handle;
2181 struct i915_gem_userptr {
2183 unsigned read_only :1;
2184 unsigned workers :4;
2185 #define I915_GEM_USERPTR_MAX_WORKERS 15
2187 struct i915_mm_struct *mm;
2188 struct i915_mmu_object *mmu_object;
2189 struct work_struct *work;
2193 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2195 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2196 struct drm_i915_gem_object *new,
2197 unsigned frontbuffer_bits);
2200 * Request queue structure.
2202 * The request queue allows us to note sequence numbers that have been emitted
2203 * and may be associated with active buffers to be retired.
2205 * By keeping this list, we can avoid having to do questionable sequence
2206 * number comparisons on buffer last_read|write_seqno. It also allows an
2207 * emission time to be associated with the request for tracking how far ahead
2208 * of the GPU the submission is.
2210 * The requests are reference counted, so upon creation they should have an
2211 * initial reference taken using kref_init
2213 struct drm_i915_gem_request {
2216 /** On Which ring this request was generated */
2217 struct drm_i915_private *i915;
2218 struct intel_engine_cs *ring;
2220 /** GEM sequence number associated with the previous request,
2221 * when the HWS breadcrumb is equal to this the GPU is processing
2226 /** GEM sequence number associated with this request,
2227 * when the HWS breadcrumb is equal or greater than this the GPU
2228 * has finished processing this request.
2232 /** Position in the ringbuffer of the start of the request */
2236 * Position in the ringbuffer of the start of the postfix.
2237 * This is required to calculate the maximum available ringbuffer
2238 * space without overwriting the postfix.
2242 /** Position in the ringbuffer of the end of the whole request */
2246 * Context and ring buffer related to this request
2247 * Contexts are refcounted, so when this request is associated with a
2248 * context, we must increment the context's refcount, to guarantee that
2249 * it persists while any request is linked to it. Requests themselves
2250 * are also refcounted, so the request will only be freed when the last
2251 * reference to it is dismissed, and the code in
2252 * i915_gem_request_free() will then decrement the refcount on the
2255 struct intel_context *ctx;
2256 struct intel_ringbuffer *ringbuf;
2258 /** Batch buffer related to this request if any (used for
2259 error state dump only) */
2260 struct drm_i915_gem_object *batch_obj;
2262 /** Time at which this request was emitted, in jiffies. */
2263 unsigned long emitted_jiffies;
2265 /** global list entry for this request */
2266 struct list_head list;
2268 struct drm_i915_file_private *file_priv;
2269 /** file_priv list entry for this request */
2270 struct list_head client_list;
2272 /** process identifier submitting this request */
2276 * The ELSP only accepts two elements at a time, so we queue
2277 * context/tail pairs on a given queue (ring->execlist_queue) until the
2278 * hardware is available. The queue serves a double purpose: we also use
2279 * it to keep track of the up to 2 contexts currently in the hardware
2280 * (usually one in execution and the other queued up by the GPU): We
2281 * only remove elements from the head of the queue when the hardware
2282 * informs us that an element has been completed.
2284 * All accesses to the queue are mediated by a spinlock
2285 * (ring->execlist_lock).
2288 /** Execlist link in the submission queue.*/
2289 struct list_head execlist_link;
2291 /** Execlists no. of times this request has been sent to the ELSP */
2296 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2297 struct intel_context *ctx,
2298 struct drm_i915_gem_request **req_out);
2299 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2300 void i915_gem_request_free(struct kref *req_ref);
2301 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2302 struct drm_file *file);
2304 static inline uint32_t
2305 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2307 return req ? req->seqno : 0;
2310 static inline struct intel_engine_cs *
2311 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2313 return req ? req->ring : NULL;
2316 static inline struct drm_i915_gem_request *
2317 i915_gem_request_reference(struct drm_i915_gem_request *req)
2320 kref_get(&req->ref);
2325 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2327 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2328 kref_put(&req->ref, i915_gem_request_free);
2332 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2334 struct drm_device *dev;
2339 dev = req->ring->dev;
2340 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2341 mutex_unlock(&dev->struct_mutex);
2344 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2345 struct drm_i915_gem_request *src)
2348 i915_gem_request_reference(src);
2351 i915_gem_request_unreference(*pdst);
2357 * XXX: i915_gem_request_completed should be here but currently needs the
2358 * definition of i915_seqno_passed() which is below. It will be moved in
2359 * a later patch when the call to i915_seqno_passed() is obsoleted...
2363 * A command that requires special handling by the command parser.
2365 struct drm_i915_cmd_descriptor {
2367 * Flags describing how the command parser processes the command.
2369 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2370 * a length mask if not set
2371 * CMD_DESC_SKIP: The command is allowed but does not follow the
2372 * standard length encoding for the opcode range in
2374 * CMD_DESC_REJECT: The command is never allowed
2375 * CMD_DESC_REGISTER: The command should be checked against the
2376 * register whitelist for the appropriate ring
2377 * CMD_DESC_MASTER: The command is allowed if the submitting process
2381 #define CMD_DESC_FIXED (1<<0)
2382 #define CMD_DESC_SKIP (1<<1)
2383 #define CMD_DESC_REJECT (1<<2)
2384 #define CMD_DESC_REGISTER (1<<3)
2385 #define CMD_DESC_BITMASK (1<<4)
2386 #define CMD_DESC_MASTER (1<<5)
2389 * The command's unique identification bits and the bitmask to get them.
2390 * This isn't strictly the opcode field as defined in the spec and may
2391 * also include type, subtype, and/or subop fields.
2399 * The command's length. The command is either fixed length (i.e. does
2400 * not include a length field) or has a length field mask. The flag
2401 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2402 * a length mask. All command entries in a command table must include
2403 * length information.
2411 * Describes where to find a register address in the command to check
2412 * against the ring's register whitelist. Only valid if flags has the
2413 * CMD_DESC_REGISTER bit set.
2415 * A non-zero step value implies that the command may access multiple
2416 * registers in sequence (e.g. LRI), in that case step gives the
2417 * distance in dwords between individual offset fields.
2425 #define MAX_CMD_DESC_BITMASKS 3
2427 * Describes command checks where a particular dword is masked and
2428 * compared against an expected value. If the command does not match
2429 * the expected value, the parser rejects it. Only valid if flags has
2430 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2433 * If the check specifies a non-zero condition_mask then the parser
2434 * only performs the check when the bits specified by condition_mask
2441 u32 condition_offset;
2443 } bits[MAX_CMD_DESC_BITMASKS];
2447 * A table of commands requiring special handling by the command parser.
2449 * Each ring has an array of tables. Each table consists of an array of command
2450 * descriptors, which must be sorted with command opcodes in ascending order.
2452 struct drm_i915_cmd_table {
2453 const struct drm_i915_cmd_descriptor *table;
2457 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2458 #define __I915__(p) ({ \
2459 const struct drm_i915_private *__p; \
2460 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2461 __p = (const struct drm_i915_private *)p; \
2462 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2463 __p = to_i915((const struct drm_device *)p); \
2466 #define INTEL_INFO(p) (&__I915__(p)->info)
2467 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2468 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2470 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2471 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2472 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2473 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2474 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2475 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2476 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2477 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2478 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2479 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2480 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2481 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2482 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2483 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2484 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2485 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2486 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2487 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2488 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2489 INTEL_DEVID(dev) == 0x0152 || \
2490 INTEL_DEVID(dev) == 0x015a)
2491 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2492 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2493 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2494 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2495 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2496 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2497 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2498 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2499 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2500 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2501 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2502 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2503 (INTEL_DEVID(dev) & 0xf) == 0xe))
2504 /* ULX machines are also considered ULT. */
2505 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2506 (INTEL_DEVID(dev) & 0xf) == 0xe)
2507 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2508 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2509 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2510 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2511 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2512 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2513 /* ULX machines are also considered ULT. */
2514 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2515 INTEL_DEVID(dev) == 0x0A1E)
2516 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2517 INTEL_DEVID(dev) == 0x1913 || \
2518 INTEL_DEVID(dev) == 0x1916 || \
2519 INTEL_DEVID(dev) == 0x1921 || \
2520 INTEL_DEVID(dev) == 0x1926)
2521 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2522 INTEL_DEVID(dev) == 0x1915 || \
2523 INTEL_DEVID(dev) == 0x191E)
2524 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2525 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2526 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2527 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2529 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2531 #define SKL_REVID_A0 (0x0)
2532 #define SKL_REVID_B0 (0x1)
2533 #define SKL_REVID_C0 (0x2)
2534 #define SKL_REVID_D0 (0x3)
2535 #define SKL_REVID_E0 (0x4)
2536 #define SKL_REVID_F0 (0x5)
2538 #define BXT_REVID_A0 (0x0)
2539 #define BXT_REVID_B0 (0x3)
2540 #define BXT_REVID_C0 (0x9)
2543 * The genX designation typically refers to the render engine, so render
2544 * capability related checks should use IS_GEN, while display and other checks
2545 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2548 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2549 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2550 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2551 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2552 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2553 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2554 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2555 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2557 #define RENDER_RING (1<<RCS)
2558 #define BSD_RING (1<<VCS)
2559 #define BLT_RING (1<<BCS)
2560 #define VEBOX_RING (1<<VECS)
2561 #define BSD2_RING (1<<VCS2)
2562 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2563 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2564 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2565 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2566 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2567 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2568 __I915__(dev)->ellc_size)
2569 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2571 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2572 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2573 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2574 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2575 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2577 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2578 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2580 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2581 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2583 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2584 * even when in MSI mode. This results in spurious interrupt warnings if the
2585 * legacy irq no. is shared with another device. The kernel then disables that
2586 * interrupt source and so prevents the other device from working properly.
2588 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2589 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2591 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2592 * rows, which changed the alignment requirements and fence programming.
2594 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2596 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2597 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2599 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2600 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2601 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2603 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2605 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2606 INTEL_INFO(dev)->gen >= 9)
2608 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2609 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2610 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2611 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2613 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2614 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2616 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2617 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2619 #define HAS_CSR(dev) (IS_GEN9(dev))
2621 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
2622 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
2624 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2625 INTEL_INFO(dev)->gen >= 8)
2627 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2628 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2630 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2631 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2632 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2633 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2634 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2635 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2636 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2637 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2638 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2640 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2641 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2642 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2643 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2644 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2645 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2646 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2647 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2649 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2651 /* DPF == dynamic parity feature */
2652 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2653 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2655 #define GT_FREQUENCY_MULTIPLIER 50
2656 #define GEN9_FREQ_SCALER 3
2658 #include "i915_trace.h"
2660 extern const struct drm_ioctl_desc i915_ioctls[];
2661 extern int i915_max_ioctl;
2663 extern int i915_suspend_switcheroo(device_t kdev);
2664 extern int i915_resume_switcheroo(struct drm_device *dev);
2667 struct i915_params {
2669 int panel_ignore_lid;
2671 int lvds_channel_mode;
2673 int vbt_sdvo_panel_type;
2677 int enable_execlists;
2679 unsigned int preliminary_hw_support;
2680 int disable_power_well;
2682 int invert_brightness;
2683 int enable_cmd_parser;
2684 /* leave bools at the end to not create holes */
2685 bool enable_hangcheck;
2687 bool prefault_disable;
2688 bool load_detect_test;
2690 bool disable_display;
2691 bool disable_vtd_wa;
2692 bool enable_guc_submission;
2696 bool verbose_state_checks;
2697 bool nuclear_pageflip;
2700 extern struct i915_params i915 __read_mostly;
2703 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2704 extern int i915_driver_unload(struct drm_device *);
2705 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2706 extern void i915_driver_lastclose(struct drm_device * dev);
2707 extern void i915_driver_preclose(struct drm_device *dev,
2708 struct drm_file *file);
2709 extern void i915_driver_postclose(struct drm_device *dev,
2710 struct drm_file *file);
2711 #ifdef CONFIG_COMPAT
2712 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2715 extern int intel_gpu_reset(struct drm_device *dev);
2716 extern bool intel_has_gpu_reset(struct drm_device *dev);
2717 extern int i915_reset(struct drm_device *dev);
2718 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2719 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2720 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2721 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2722 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2723 void i915_firmware_load_error_print(const char *fw_path, int err);
2725 /* intel_hotplug.c */
2726 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2727 void intel_hpd_init(struct drm_i915_private *dev_priv);
2728 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2729 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2730 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2733 void i915_queue_hangcheck(struct drm_device *dev);
2735 void i915_handle_error(struct drm_device *dev, bool wedged,
2736 const char *fmt, ...);
2738 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2739 int intel_irq_install(struct drm_i915_private *dev_priv);
2740 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2742 extern void intel_uncore_sanitize(struct drm_device *dev);
2743 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2744 bool restore_forcewake);
2745 extern void intel_uncore_init(struct drm_device *dev);
2746 extern void intel_uncore_check_errors(struct drm_device *dev);
2747 extern void intel_uncore_fini(struct drm_device *dev);
2748 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2749 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2750 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2751 enum forcewake_domains domains);
2752 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2753 enum forcewake_domains domains);
2754 /* Like above but the caller must manage the uncore.lock itself.
2755 * Must be used with I915_READ_FW and friends.
2757 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2758 enum forcewake_domains domains);
2759 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2760 enum forcewake_domains domains);
2761 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2762 static inline bool intel_vgpu_active(struct drm_device *dev)
2764 return to_i915(dev)->vgpu.active;
2768 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
2772 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
2775 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2776 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2777 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2781 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2783 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2784 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2785 uint32_t interrupt_mask,
2786 uint32_t enabled_irq_mask);
2787 #define ibx_enable_display_interrupt(dev_priv, bits) \
2788 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2789 #define ibx_disable_display_interrupt(dev_priv, bits) \
2790 ibx_display_interrupt_update((dev_priv), (bits), 0)
2793 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2794 struct drm_file *file_priv);
2795 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2796 struct drm_file *file_priv);
2797 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2798 struct drm_file *file_priv);
2799 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2800 struct drm_file *file_priv);
2801 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2802 struct drm_file *file_priv);
2803 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2804 struct drm_file *file_priv);
2805 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2806 struct drm_file *file_priv);
2807 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2808 struct drm_i915_gem_request *req);
2809 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2810 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2811 struct drm_i915_gem_execbuffer2 *args,
2812 struct list_head *vmas);
2813 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2814 struct drm_file *file_priv);
2815 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2816 struct drm_file *file_priv);
2817 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2818 struct drm_file *file_priv);
2819 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2820 struct drm_file *file);
2821 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2822 struct drm_file *file);
2823 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2824 struct drm_file *file_priv);
2825 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2826 struct drm_file *file_priv);
2827 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2828 struct drm_file *file_priv);
2829 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2830 struct drm_file *file_priv);
2831 int i915_gem_init_userptr(struct drm_device *dev);
2832 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2833 struct drm_file *file);
2834 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2835 struct drm_file *file_priv);
2836 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2837 struct drm_file *file_priv);
2838 void i915_gem_load(struct drm_device *dev);
2839 void *i915_gem_object_alloc(struct drm_device *dev);
2840 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2841 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2842 const struct drm_i915_gem_object_ops *ops);
2843 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2845 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2846 struct drm_device *dev, const void *data, size_t size);
2847 void i915_gem_free_object(struct drm_gem_object *obj);
2848 void i915_gem_vma_destroy(struct i915_vma *vma);
2850 /* Flags used by pin/bind&friends. */
2851 #define PIN_MAPPABLE (1<<0)
2852 #define PIN_NONBLOCK (1<<1)
2853 #define PIN_GLOBAL (1<<2)
2854 #define PIN_OFFSET_BIAS (1<<3)
2855 #define PIN_USER (1<<4)
2856 #define PIN_UPDATE (1<<5)
2857 #define PIN_ZONE_4G (1<<6)
2858 #define PIN_HIGH (1<<7)
2859 #define PIN_OFFSET_MASK (~4095)
2861 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2862 struct i915_address_space *vm,
2866 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2867 const struct i915_ggtt_view *view,
2871 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2873 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2874 int __must_check i915_vma_unbind(struct i915_vma *vma);
2876 * BEWARE: Do not use the function below unless you can _absolutely_
2877 * _guarantee_ VMA in question is _not in use_ anywhere.
2879 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2880 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2881 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2882 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2884 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2885 int *needs_clflush);
2887 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2889 static inline int __sg_page_count(struct scatterlist *sg)
2891 return sg->length >> PAGE_SHIFT;
2894 static inline struct vm_page *
2895 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2897 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2900 if (n < obj->get_page.last) {
2901 obj->get_page.sg = obj->pages->sgl;
2902 obj->get_page.last = 0;
2905 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2906 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2908 if (unlikely(sg_is_chain(obj->get_page.sg)))
2909 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2913 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2916 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2918 BUG_ON(obj->pages == NULL);
2919 obj->pages_pin_count++;
2921 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2923 BUG_ON(obj->pages_pin_count == 0);
2924 obj->pages_pin_count--;
2927 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2928 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2929 struct intel_engine_cs *to,
2930 struct drm_i915_gem_request **to_req);
2931 void i915_vma_move_to_active(struct i915_vma *vma,
2932 struct drm_i915_gem_request *req);
2933 int i915_gem_dumb_create(struct drm_file *file_priv,
2934 struct drm_device *dev,
2935 struct drm_mode_create_dumb *args);
2936 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2937 uint32_t handle, uint64_t *offset);
2939 * Returns true if seq1 is later than seq2.
2942 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2944 return (int32_t)(seq1 - seq2) >= 0;
2947 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
2948 bool lazy_coherency)
2950 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2951 return i915_seqno_passed(seqno, req->previous_seqno);
2954 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2955 bool lazy_coherency)
2957 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2958 return i915_seqno_passed(seqno, req->seqno);
2961 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2962 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2964 struct drm_i915_gem_request *
2965 i915_gem_find_active_request(struct intel_engine_cs *ring);
2967 bool i915_gem_retire_requests(struct drm_device *dev);
2968 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2969 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2970 bool interruptible);
2972 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2974 return unlikely(atomic_read(&error->reset_counter)
2975 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2978 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2980 return atomic_read(&error->reset_counter) & I915_WEDGED;
2983 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2985 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2988 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2990 return dev_priv->gpu_error.stop_rings == 0 ||
2991 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2994 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2996 return dev_priv->gpu_error.stop_rings == 0 ||
2997 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3000 void i915_gem_reset(struct drm_device *dev);
3001 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3002 int __must_check i915_gem_init(struct drm_device *dev);
3003 int i915_gem_init_rings(struct drm_device *dev);
3004 int __must_check i915_gem_init_hw(struct drm_device *dev);
3005 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3006 void i915_gem_init_swizzling(struct drm_device *dev);
3007 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3008 int __must_check i915_gpu_idle(struct drm_device *dev);
3009 int __must_check i915_gem_suspend(struct drm_device *dev);
3010 void __i915_add_request(struct drm_i915_gem_request *req,
3011 struct drm_i915_gem_object *batch_obj,
3013 #define i915_add_request(req) \
3014 __i915_add_request(req, NULL, true)
3015 #define i915_add_request_no_flush(req) \
3016 __i915_add_request(req, NULL, false)
3017 int __i915_wait_request(struct drm_i915_gem_request *req,
3018 unsigned reset_counter,
3021 struct intel_rps_client *rps);
3022 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3023 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres);
3025 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3028 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3031 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3033 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3035 struct intel_engine_cs *pipelined,
3036 struct drm_i915_gem_request **pipelined_request,
3037 const struct i915_ggtt_view *view);
3038 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3039 const struct i915_ggtt_view *view);
3040 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3042 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3043 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3046 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3048 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3049 int tiling_mode, bool fenced);
3051 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3052 enum i915_cache_level cache_level);
3055 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3056 struct dma_buf *dma_buf);
3058 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3059 struct drm_gem_object *gem_obj, int flags);
3062 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3063 const struct i915_ggtt_view *view);
3064 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3065 struct i915_address_space *vm);
3067 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3069 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3072 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3073 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3074 const struct i915_ggtt_view *view);
3075 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3076 struct i915_address_space *vm);
3078 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3079 struct i915_address_space *vm);
3081 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3082 struct i915_address_space *vm);
3084 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3085 const struct i915_ggtt_view *view);
3088 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3089 struct i915_address_space *vm);
3091 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3092 const struct i915_ggtt_view *view);
3094 static inline struct i915_vma *
3095 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3097 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3099 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3101 /* Some GGTT VM helpers */
3102 #define i915_obj_to_ggtt(obj) \
3103 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3104 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3106 struct i915_address_space *ggtt =
3107 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3111 static inline struct i915_hw_ppgtt *
3112 i915_vm_to_ppgtt(struct i915_address_space *vm)
3114 WARN_ON(i915_is_ggtt(vm));
3116 return container_of(vm, struct i915_hw_ppgtt, base);
3120 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3122 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3125 static inline unsigned long
3126 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3128 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3131 static inline int __must_check
3132 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3136 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3137 alignment, flags | PIN_GLOBAL);
3141 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3143 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3146 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3147 const struct i915_ggtt_view *view);
3149 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3151 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3154 /* i915_gem_fence.c */
3155 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3156 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3158 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3159 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3161 void i915_gem_restore_fences(struct drm_device *dev);
3163 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3164 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3165 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3167 /* i915_gem_context.c */
3168 int __must_check i915_gem_context_init(struct drm_device *dev);
3169 void i915_gem_context_fini(struct drm_device *dev);
3170 void i915_gem_context_reset(struct drm_device *dev);
3171 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3172 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3173 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3174 int i915_switch_context(struct drm_i915_gem_request *req);
3175 struct intel_context *
3176 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3177 void i915_gem_context_free(struct kref *ctx_ref);
3178 struct drm_i915_gem_object *
3179 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3180 static inline void i915_gem_context_reference(struct intel_context *ctx)
3182 kref_get(&ctx->ref);
3185 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3187 kref_put(&ctx->ref, i915_gem_context_free);
3190 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3192 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3195 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3196 struct drm_file *file);
3197 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3198 struct drm_file *file);
3199 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3200 struct drm_file *file_priv);
3201 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3202 struct drm_file *file_priv);
3204 /* i915_gem_evict.c */
3205 int __must_check i915_gem_evict_something(struct drm_device *dev,
3206 struct i915_address_space *vm,
3209 unsigned cache_level,
3210 unsigned long start,
3213 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3215 /* belongs in i915_gem_gtt.h */
3216 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3218 if (INTEL_INFO(dev)->gen < 6)
3219 intel_gtt_chipset_flush();
3222 /* i915_gem_stolen.c */
3223 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3224 struct drm_mm_node *node, u64 size,
3225 unsigned alignment);
3226 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3227 struct drm_mm_node *node, u64 size,
3228 unsigned alignment, u64 start,
3230 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3231 struct drm_mm_node *node);
3232 int i915_gem_init_stolen(struct drm_device *dev);
3233 void i915_gem_cleanup_stolen(struct drm_device *dev);
3234 struct drm_i915_gem_object *
3235 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3236 struct drm_i915_gem_object *
3237 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3242 /* i915_gem_shrinker.c */
3243 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3244 unsigned long target,
3246 #define I915_SHRINK_PURGEABLE 0x1
3247 #define I915_SHRINK_UNBOUND 0x2
3248 #define I915_SHRINK_BOUND 0x4
3249 #define I915_SHRINK_ACTIVE 0x8
3250 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3251 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3254 /* i915_gem_tiling.c */
3255 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3257 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3259 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3260 obj->tiling_mode != I915_TILING_NONE;
3263 /* i915_gem_debug.c */
3265 int i915_verify_lists(struct drm_device *dev);
3267 #define i915_verify_lists(dev) 0
3270 /* i915_debugfs.c */
3271 int i915_debugfs_init(struct drm_minor *minor);
3272 void i915_debugfs_cleanup(struct drm_minor *minor);
3273 #ifdef CONFIG_DEBUG_FS
3274 int i915_debugfs_connector_add(struct drm_connector *connector);
3275 void intel_display_crc_init(struct drm_device *dev);
3277 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3279 static inline void intel_display_crc_init(struct drm_device *dev) {}
3282 /* i915_gpu_error.c */
3284 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3285 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3286 const struct i915_error_state_file_priv *error);
3287 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3288 struct drm_i915_private *i915,
3289 size_t count, loff_t pos);
3290 static inline void i915_error_state_buf_release(
3291 struct drm_i915_error_state_buf *eb)
3295 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3296 const char *error_msg);
3297 void i915_error_state_get(struct drm_device *dev,
3298 struct i915_error_state_file_priv *error_priv);
3299 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3300 void i915_destroy_error_state(struct drm_device *dev);
3302 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3303 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3305 /* i915_cmd_parser.c */
3306 int i915_cmd_parser_get_version(void);
3307 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3308 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3309 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3310 int i915_parse_cmds(struct intel_engine_cs *ring,
3311 struct drm_i915_gem_object *batch_obj,
3312 struct drm_i915_gem_object *shadow_batch_obj,
3313 u32 batch_start_offset,
3317 /* i915_suspend.c */
3318 extern int i915_save_state(struct drm_device *dev);
3319 extern int i915_restore_state(struct drm_device *dev);
3322 void i915_setup_sysfs(struct drm_device *dev_priv);
3323 void i915_teardown_sysfs(struct drm_device *dev_priv);
3326 extern int intel_setup_gmbus(struct drm_device *dev);
3327 extern void intel_teardown_gmbus(struct drm_device *dev);
3328 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3331 extern struct i2c_adapter *
3332 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3333 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3334 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3335 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3337 struct intel_iic_softc *sc;
3338 sc = device_get_softc(device_get_parent(adapter));
3340 return sc->force_bit_dev;
3342 extern void intel_i2c_reset(struct drm_device *dev);
3344 /* intel_opregion.c */
3346 extern int intel_opregion_setup(struct drm_device *dev);
3347 extern void intel_opregion_init(struct drm_device *dev);
3348 extern void intel_opregion_fini(struct drm_device *dev);
3349 extern void intel_opregion_asle_intr(struct drm_device *dev);
3350 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3352 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3355 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3356 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3357 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3358 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3360 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3365 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3373 extern void intel_register_dsm_handler(void);
3374 extern void intel_unregister_dsm_handler(void);
3376 static inline void intel_register_dsm_handler(void) { return; }
3377 static inline void intel_unregister_dsm_handler(void) { return; }
3378 #endif /* CONFIG_ACPI */
3381 extern void intel_modeset_init_hw(struct drm_device *dev);
3382 extern void intel_modeset_init(struct drm_device *dev);
3383 extern void intel_modeset_gem_init(struct drm_device *dev);
3384 extern void intel_modeset_cleanup(struct drm_device *dev);
3385 extern void intel_connector_unregister(struct intel_connector *);
3386 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3387 extern void intel_display_resume(struct drm_device *dev);
3388 extern void i915_redisable_vga(struct drm_device *dev);
3389 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3390 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3391 extern void intel_init_pch_refclk(struct drm_device *dev);
3392 extern void intel_set_rps(struct drm_device *dev, u8 val);
3393 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3395 extern void intel_detect_pch(struct drm_device *dev);
3396 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3397 extern int intel_enable_rc6(const struct drm_device *dev);
3399 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3400 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3401 struct drm_file *file);
3402 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3403 struct drm_file *file);
3405 struct intel_device_info *i915_get_device_id(int device);
3408 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3409 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3410 struct intel_overlay_error_state *error);
3412 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3413 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3414 struct drm_device *dev,
3415 struct intel_display_error_state *error);
3417 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3418 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3420 /* intel_sideband.c */
3421 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3422 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3423 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3424 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3425 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3426 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3427 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3428 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3429 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3430 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3431 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3432 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3433 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3434 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg);
3435 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val);
3436 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3437 enum intel_sbi_destination destination);
3438 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3439 enum intel_sbi_destination destination);
3440 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3441 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3443 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3444 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3446 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3447 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3449 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3450 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3451 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3452 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3454 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3455 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3456 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3457 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3459 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3460 * will be implemented using 2 32-bit writes in an arbitrary order with
3461 * an arbitrary delay between them. This can cause the hardware to
3462 * act upon the intermediate value, possibly leading to corruption and
3463 * machine death. You have been warned.
3465 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3466 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3468 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3469 u32 upper, lower, old_upper, loop = 0; \
3470 upper = I915_READ(upper_reg); \
3472 old_upper = upper; \
3473 lower = I915_READ(lower_reg); \
3474 upper = I915_READ(upper_reg); \
3475 } while (upper != old_upper && loop++ < 2); \
3476 (u64)upper << 32 | lower; })
3478 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3479 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3481 /* These are untraced mmio-accessors that are only valid to be used inside
3482 * criticial sections inside IRQ handlers where forcewake is explicitly
3484 * Think twice, and think again, before using these.
3485 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3486 * intel_uncore_forcewake_irqunlock().
3488 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3489 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3490 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3492 /* "Broadcast RGB" property */
3493 #define INTEL_BROADCAST_RGB_AUTO 0
3494 #define INTEL_BROADCAST_RGB_FULL 1
3495 #define INTEL_BROADCAST_RGB_LIMITED 2
3497 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3499 if (IS_VALLEYVIEW(dev))
3500 return VLV_VGACNTRL;
3501 else if (INTEL_INFO(dev)->gen >= 5)
3502 return CPU_VGACNTRL;
3507 static inline void __user *to_user_ptr(u64 address)
3509 return (void __user *)(uintptr_t)address;
3512 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3514 unsigned long j = msecs_to_jiffies(m);
3516 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3519 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3521 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3524 static inline unsigned long
3525 timespec_to_jiffies_timeout(const struct timespec *value)
3527 unsigned long j = timespec_to_jiffies(value);
3529 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3533 * If you need to wait X milliseconds between events A and B, but event B
3534 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3535 * when event A happened, then just before event B you call this function and
3536 * pass the timestamp as the first argument, and X as the second argument.
3539 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3541 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3544 * Don't re-read the value of "jiffies" every time since it may change
3545 * behind our back and break the math.
3547 tmp_jiffies = jiffies;
3548 target_jiffies = timestamp_jiffies +
3549 msecs_to_jiffies_timeout(to_wait_ms);
3551 if (time_after(target_jiffies, tmp_jiffies)) {
3552 remaining_jiffies = target_jiffies - tmp_jiffies;
3554 while (remaining_jiffies)
3556 schedule_timeout_uninterruptible(remaining_jiffies);
3558 msleep(jiffies_to_msecs(remaining_jiffies));
3563 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3564 struct drm_i915_gem_request *req)
3566 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3567 i915_gem_request_assign(&ring->trace_irq_req, req);