2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
38 #include <sys/cpu_topology.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/lapic.h>
60 #include <machine_base/apic/ioapic.h>
61 #include <machine_base/acpica/acpi_md_cpu.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
68 #include <machine/clock.h>
70 #include <machine/md_var.h> /* setidt() */
71 #include <machine_base/icu/icu.h> /* IPIs */
72 #include <machine_base/icu/icu_var.h>
73 #include <machine_base/apic/ioapic_abi.h>
74 #include <machine/intr_machdep.h> /* IPIs */
76 #define WARMBOOT_TARGET 0
77 #define WARMBOOT_OFF (KERNBASE + 0x0467)
78 #define WARMBOOT_SEG (KERNBASE + 0x0469)
80 #define CMOS_REG (0x70)
81 #define CMOS_DATA (0x71)
82 #define BIOS_RESET (0x0f)
83 #define BIOS_WARM (0x0a)
86 * this code MUST be enabled here and in mpboot.s.
87 * it follows the very early stages of AP boot by placing values in CMOS ram.
88 * it NORMALLY will never be needed and thus the primitive method for enabling.
91 #if defined(CHECK_POINTS)
92 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
93 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
95 #define CHECK_INIT(D); \
96 CHECK_WRITE(0x34, (D)); \
97 CHECK_WRITE(0x35, (D)); \
98 CHECK_WRITE(0x36, (D)); \
99 CHECK_WRITE(0x37, (D)); \
100 CHECK_WRITE(0x38, (D)); \
101 CHECK_WRITE(0x39, (D));
103 #define CHECK_PRINT(S); \
104 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
113 #else /* CHECK_POINTS */
115 #define CHECK_INIT(D)
116 #define CHECK_PRINT(S)
118 #endif /* CHECK_POINTS */
121 * Values to send to the POST hardware.
123 #define MP_BOOTADDRESS_POST 0x10
124 #define MP_PROBE_POST 0x11
125 #define MPTABLE_PASS1_POST 0x12
127 #define MP_START_POST 0x13
128 #define MP_ENABLE_POST 0x14
129 #define MPTABLE_PASS2_POST 0x15
131 #define START_ALL_APS_POST 0x16
132 #define INSTALL_AP_TRAMP_POST 0x17
133 #define START_AP_POST 0x18
135 #define MP_ANNOUNCE_POST 0x19
137 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
138 int current_postcode;
140 /** XXX FIXME: what system files declare these??? */
141 extern struct region_descriptor r_gdt;
147 extern int64_t tsc_offsets[];
149 /* AP uses this during bootstrap. Do not staticize. */
153 struct pcb stoppcbs[MAXCPU];
155 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
158 * Local data and functions.
161 static u_int boot_address;
162 static int mp_finish;
163 static int mp_finish_lapic;
165 static int start_all_aps(u_int boot_addr);
167 static void install_ap_tramp(u_int boot_addr);
169 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
170 static int smitest(void);
171 static void mp_bsp_simple_setup(void);
173 /* which cpus have been started */
174 static cpumask_t smp_startup_mask = CPUMASK_INITIALIZER_ONLYONE;
175 /* which cpus have lapic been inited */
176 static cpumask_t smp_lapic_mask = CPUMASK_INITIALIZER_ONLYONE;
177 /* which cpus are ready for IPIs etc? */
178 cpumask_t smp_active_mask = CPUMASK_INITIALIZER_ONLYONE;
179 cpumask_t smp_finalize_mask = CPUMASK_INITIALIZER_ONLYONE;
181 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
182 static u_int bootMP_size;
183 static u_int report_invlpg_src;
184 SYSCTL_INT(_machdep, OID_AUTO, report_invlpg_src, CTLFLAG_RW,
185 &report_invlpg_src, 0, "");
186 static u_int report_invltlb_src;
187 SYSCTL_INT(_machdep, OID_AUTO, report_invltlb_src, CTLFLAG_RW,
188 &report_invltlb_src, 0, "");
189 static int optimized_invltlb;
190 SYSCTL_INT(_machdep, OID_AUTO, optimized_invltlb, CTLFLAG_RW,
191 &optimized_invltlb, 0, "");
193 /* Local data for detecting CPU TOPOLOGY */
194 static int core_bits = 0;
195 static int logical_CPU_bits = 0;
199 * Calculate usable address in base memory for AP trampoline code.
202 mp_bootaddress(u_int basemem)
204 POSTCODE(MP_BOOTADDRESS_POST);
206 bootMP_size = mptramp_end - mptramp_start;
207 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
208 if (((basemem * 1024) - boot_address) < bootMP_size)
209 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
210 /* 3 levels of page table pages */
211 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
213 return mptramp_pagetables;
217 * Print various information about the SMP system hardware and setup.
224 POSTCODE(MP_ANNOUNCE_POST);
226 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
227 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
228 for (x = 1; x <= naps; ++x)
229 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
232 kprintf(" Warning: APIC I/O disabled\n");
236 * AP cpu's call this to sync up protected mode.
238 * WARNING! %gs is not set up on entry. This routine sets up %gs.
244 int x, myid = bootAP;
246 struct mdglobaldata *md;
247 struct privatespace *ps;
249 ps = CPU_prvspace[myid];
251 gdt_segs[GPROC0_SEL].ssd_base =
252 (long) &ps->mdglobaldata.gd_common_tss;
253 ps->mdglobaldata.mi.gd_prvspace = ps;
255 /* We fill the 32-bit segment descriptors */
256 for (x = 0; x < NGDT; x++) {
257 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
258 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
260 /* And now a 64-bit one */
261 ssdtosyssd(&gdt_segs[GPROC0_SEL],
262 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
264 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
265 r_gdt.rd_base = (long) &gdt[myid * NGDT];
266 lgdt(&r_gdt); /* does magic intra-segment return */
268 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
269 wrmsr(MSR_FSBASE, 0); /* User value */
270 wrmsr(MSR_GSBASE, (u_int64_t)ps);
271 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
273 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]);
277 mdcpu->gd_currentldt = _default_ldt;
280 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
281 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
283 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
285 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
287 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
289 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
290 md->gd_common_tssd = *md->gd_tss_gdt;
292 /* double fault stack */
293 md->gd_common_tss.tss_ist1 =
294 (long)&md->mi.gd_prvspace->idlestack[
295 sizeof(md->mi.gd_prvspace->idlestack)];
300 * Set to a known state:
301 * Set by mpboot.s: CR0_PG, CR0_PE
302 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
305 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
308 /* Set up the fast syscall stuff */
309 msr = rdmsr(MSR_EFER) | EFER_SCE;
310 wrmsr(MSR_EFER, msr);
311 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
312 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
313 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
314 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
315 wrmsr(MSR_STAR, msr);
316 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
318 pmap_set_opt(); /* PSE/4MB pages, etc */
319 pmap_init_pat(); /* Page Attribute Table */
321 /* set up CPU registers and state */
324 /* set up SSE/NX registers */
327 /* set up FPU state on the AP */
330 /* disable the APIC, just to be SURE */
331 lapic->svr &= ~APIC_SVR_ENABLE;
334 /*******************************************************************
335 * local functions and data
339 * Start the SMP system
342 mp_start_aps(void *dummy __unused)
345 /* start each Application Processor */
346 start_all_aps(boot_address);
348 mp_bsp_simple_setup();
351 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL);
354 * start each AP in our list
357 start_all_aps(u_int boot_addr)
359 vm_offset_t va = boot_address + KERNBASE;
360 u_int64_t *pt4, *pt3, *pt2;
368 u_long mpbioswarmvec;
369 struct mdglobaldata *gd;
370 struct privatespace *ps;
373 POSTCODE(START_ALL_APS_POST);
375 /* install the AP 1st level boot code */
376 pmap_kenter(va, boot_address);
377 cpu_invlpg((void *)va); /* JG XXX */
378 bcopy(mptramp_start, (void *)va, bootMP_size);
380 /* Locate the page tables, they'll be below the trampoline */
381 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
382 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
383 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
385 /* Create the initial 1GB replicated page tables */
386 for (i = 0; i < 512; i++) {
387 /* Each slot of the level 4 pages points to the same level 3 page */
388 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
389 pt4[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
390 kernel_pmap.pmap_bits[PG_RW_IDX] |
391 kernel_pmap.pmap_bits[PG_U_IDX];
393 /* Each slot of the level 3 pages points to the same level 2 page */
394 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
395 pt3[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
396 kernel_pmap.pmap_bits[PG_RW_IDX] |
397 kernel_pmap.pmap_bits[PG_U_IDX];
399 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
400 pt2[i] = i * (2 * 1024 * 1024);
401 pt2[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
402 kernel_pmap.pmap_bits[PG_RW_IDX] |
403 kernel_pmap.pmap_bits[PG_PS_IDX] |
404 kernel_pmap.pmap_bits[PG_U_IDX];
407 /* save the current value of the warm-start vector */
408 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
409 outb(CMOS_REG, BIOS_RESET);
410 mpbiosreason = inb(CMOS_DATA);
412 /* setup a vector to our boot code */
413 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
414 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
415 outb(CMOS_REG, BIOS_RESET);
416 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
419 * If we have a TSC we can figure out the SMI interrupt rate.
420 * The SMI does not necessarily use a constant rate. Spend
421 * up to 250ms trying to figure it out.
424 if (cpu_feature & CPUID_TSC) {
425 set_apic_timer(275000);
426 smilast = read_apic_timer();
427 for (x = 0; x < 20 && read_apic_timer(); ++x) {
428 smicount = smitest();
429 if (smibest == 0 || smilast - smicount < smibest)
430 smibest = smilast - smicount;
433 if (smibest > 250000)
436 smibest = smibest * (int64_t)1000000 /
437 get_apic_timer_frequency();
441 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
442 1000000 / smibest, smibest);
445 for (x = 1; x <= naps; ++x) {
446 /* This is a bit verbose, it will go away soon. */
448 pssize = sizeof(struct privatespace);
449 ps = (void *)kmem_alloc(&kernel_map, pssize);
450 CPU_prvspace[x] = ps;
452 kprintf("ps %d %p %d\n", x, ps, pssize);
455 gd = &ps->mdglobaldata;
456 gd->mi.gd_prvspace = ps;
458 /* prime data page for it to use */
459 mi_gdinit(&gd->mi, x);
461 ipiq_size = sizeof(struct lwkt_ipiq) * (naps + 1);
462 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size);
463 bzero(gd->mi.gd_ipiq, ipiq_size);
465 gd->gd_acpi_id = CPUID_TO_ACPIID(gd->mi.gd_cpuid);
467 /* setup a vector to our boot code */
468 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
469 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
470 outb(CMOS_REG, BIOS_RESET);
471 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
474 * Setup the AP boot stack
476 bootSTK = &ps->idlestack[UPAGES * PAGE_SIZE - PAGE_SIZE];
479 /* attempt to start the Application Processor */
480 CHECK_INIT(99); /* setup checkpoints */
481 if (!start_ap(gd, boot_addr, smibest)) {
482 kprintf("\nAP #%d (PHY# %d) failed!\n",
483 x, CPUID_TO_APICID(x));
484 CHECK_PRINT("trace"); /* show checkpoints */
485 /* better panic as the AP may be running loose */
486 kprintf("panic y/n? [y] ");
492 CHECK_PRINT("trace"); /* show checkpoints */
495 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
498 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
499 for (shift = 0; (1 << shift) <= ncpus; ++shift)
502 ncpus2_shift = shift;
504 ncpus2_mask = ncpus2 - 1;
506 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
507 if ((1 << shift) < ncpus)
509 ncpus_fit = 1 << shift;
510 ncpus_fit_mask = ncpus_fit - 1;
512 /* build our map of 'other' CPUs */
513 mycpu->gd_other_cpus = smp_startup_mask;
514 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
516 gd = (struct mdglobaldata *)mycpu;
517 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid);
519 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
520 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size);
521 bzero(mycpu->gd_ipiq, ipiq_size);
523 /* restore the warmstart vector */
524 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
525 outb(CMOS_REG, BIOS_RESET);
526 outb(CMOS_DATA, mpbiosreason);
529 * NOTE! The idlestack for the BSP was setup by locore. Finish
530 * up, clean out the P==V mapping we did earlier.
535 * Wait all APs to finish initializing LAPIC
538 kprintf("SMP: Waiting APs LAPIC initialization\n");
539 if (cpu_feature & CPUID_TSC)
540 tsc0_offset = rdtsc();
545 while (CPUMASK_CMPMASKNEQ(smp_lapic_mask, smp_startup_mask)) {
548 if (cpu_feature & CPUID_TSC)
549 tsc0_offset = rdtsc();
551 while (try_mplock() == 0) {
556 /* number of APs actually started */
562 * load the 1st level AP boot code into base memory.
565 /* targets for relocation */
566 extern void bigJump(void);
567 extern void bootCodeSeg(void);
568 extern void bootDataSeg(void);
569 extern void MPentry(void);
571 extern u_int mp_gdtbase;
576 install_ap_tramp(u_int boot_addr)
579 int size = *(int *) ((u_long) & bootMP_size);
580 u_char *src = (u_char *) ((u_long) bootMP);
581 u_char *dst = (u_char *) boot_addr + KERNBASE;
582 u_int boot_base = (u_int) bootMP;
587 POSTCODE(INSTALL_AP_TRAMP_POST);
589 for (x = 0; x < size; ++x)
593 * modify addresses in code we just moved to basemem. unfortunately we
594 * need fairly detailed info about mpboot.s for this to work. changes
595 * to mpboot.s might require changes here.
598 /* boot code is located in KERNEL space */
599 dst = (u_char *) boot_addr + KERNBASE;
601 /* modify the lgdt arg */
602 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
603 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
605 /* modify the ljmp target for MPentry() */
606 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
607 *dst32 = ((u_int) MPentry - KERNBASE);
609 /* modify the target for boot code segment */
610 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
611 dst8 = (u_int8_t *) (dst16 + 1);
612 *dst16 = (u_int) boot_addr & 0xffff;
613 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
615 /* modify the target for boot data segment */
616 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
617 dst8 = (u_int8_t *) (dst16 + 1);
618 *dst16 = (u_int) boot_addr & 0xffff;
619 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
625 * This function starts the AP (application processor) identified
626 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
627 * to accomplish this. This is necessary because of the nuances
628 * of the different hardware we might encounter. It ain't pretty,
629 * but it seems to work.
631 * NOTE: eventually an AP gets to ap_init(), which is called just
632 * before the AP goes into the LWKT scheduler's idle loop.
635 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
639 u_long icr_lo, icr_hi;
641 POSTCODE(START_AP_POST);
643 /* get the PHYSICAL APIC ID# */
644 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
646 /* calculate the vector */
647 vector = (boot_addr >> 12) & 0xff;
649 /* We don't want anything interfering */
652 /* Make sure the target cpu sees everything */
656 * Try to detect when a SMI has occurred, wait up to 200ms.
658 * If a SMI occurs during an AP reset but before we issue
659 * the STARTUP command, the AP may brick. To work around
660 * this problem we hold off doing the AP startup until
661 * after we have detected the SMI. Hopefully another SMI
662 * will not occur before we finish the AP startup.
664 * Retries don't seem to help. SMIs have a window of opportunity
665 * and if USB->legacy keyboard emulation is enabled in the BIOS
666 * the interrupt rate can be quite high.
668 * NOTE: Don't worry about the L1 cache load, it might bloat
669 * ldelta a little but ndelta will be so huge when the SMI
670 * occurs the detection logic will still work fine.
673 set_apic_timer(200000);
678 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
679 * and running the target CPU. OR this INIT IPI might be latched (P5
680 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
683 * see apic/apicreg.h for icr bit definitions.
685 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
689 * Setup the address for the target AP. We can setup
690 * icr_hi once and then just trigger operations with
693 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
694 icr_hi |= (physical_cpu << 24);
695 icr_lo = lapic->icr_lo & 0xfff00000;
696 lapic->icr_hi = icr_hi;
699 * Do an INIT IPI: assert RESET
701 * Use edge triggered mode to assert INIT
703 lapic->icr_lo = icr_lo | 0x00004500;
704 while (lapic->icr_lo & APIC_DELSTAT_MASK)
708 * The spec calls for a 10ms delay but we may have to use a
709 * MUCH lower delay to avoid bricking an AP due to a fast SMI
710 * interrupt. We have other loops here too and dividing by 2
711 * doesn't seem to be enough even after subtracting 350us,
714 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
715 * interrupt was detected we use the full 10ms.
719 else if (smibest < 150 * 4 + 350)
721 else if ((smibest - 350) / 4 < 10000)
722 u_sleep((smibest - 350) / 4);
727 * Do an INIT IPI: deassert RESET
729 * Use level triggered mode to deassert. It is unclear
730 * why we need to do this.
732 lapic->icr_lo = icr_lo | 0x00008500;
733 while (lapic->icr_lo & APIC_DELSTAT_MASK)
735 u_sleep(150); /* wait 150us */
738 * Next we do a STARTUP IPI: the previous INIT IPI might still be
739 * latched, (P5 bug) this 1st STARTUP would then terminate
740 * immediately, and the previously started INIT IPI would continue. OR
741 * the previous INIT IPI has already run. and this STARTUP IPI will
742 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
745 lapic->icr_lo = icr_lo | 0x00000600 | vector;
746 while (lapic->icr_lo & APIC_DELSTAT_MASK)
748 u_sleep(200); /* wait ~200uS */
751 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
752 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
753 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
754 * recognized after hardware RESET or INIT IPI.
756 lapic->icr_lo = icr_lo | 0x00000600 | vector;
757 while (lapic->icr_lo & APIC_DELSTAT_MASK)
760 /* Resume normal operation */
763 /* wait for it to start, see ap_init() */
764 set_apic_timer(5000000);/* == 5 seconds */
765 while (read_apic_timer()) {
766 if (CPUMASK_TESTBIT(smp_startup_mask, gd->mi.gd_cpuid))
767 return 1; /* return SUCCESS */
770 return 0; /* return FAILURE */
785 while (read_apic_timer()) {
787 for (count = 0; count < 100; ++count)
788 ntsc = rdtsc(); /* force loop to occur */
790 ndelta = ntsc - ltsc;
793 if (ndelta > ldelta * 2)
796 ldelta = ntsc - ltsc;
799 return(read_apic_timer());
803 * Synchronously flush the TLB on all other CPU's. The current cpu's
804 * TLB is not flushed. If the caller wishes to flush the current cpu's
805 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
807 * This routine may be called concurrently from multiple cpus. When this
808 * happens, smp_invltlb() can wind up sticking around in the confirmation
809 * while() loop at the end as additional cpus are added to the global
810 * cpumask, until they are acknowledged by another IPI.
812 * NOTE: If for some reason we were unable to start all cpus we cannot
813 * safely use broadcast IPIs.
816 cpumask_t smp_smurf_mask;
817 static cpumask_t smp_invltlb_mask;
818 #define LOOPMASK (/* 32 * */ 16 * 128 * 1024 - 1)
820 cpumask_t smp_in_mask;
822 cpumask_t smp_invmask;
823 extern cpumask_t smp_idleinvl_mask;
824 extern cpumask_t smp_idleinvl_reqs;
827 * Atomically OR bits in *mask to smp_smurf_mask. Adjust *mask to remove
828 * bits that do not need to be IPId. These bits are still part of the command,
829 * but the target cpus have already been signalled and do not need to be
832 #include <sys/spinlock.h>
833 #include <sys/spinlock2.h>
837 smp_smurf_fetchset(cpumask_t *mask)
845 while (i < CPUMASK_ELEMENTS) {
846 obits = smp_smurf_mask.ary[i];
848 nbits = obits | mask->ary[i];
849 if (atomic_cmpset_long(&smp_smurf_mask.ary[i], obits, nbits)) {
850 omask.ary[i] = obits;
854 CPUMASK_NANDMASK(*mask, omask);
858 * This is a mechanism which guarantees that cpu_invltlb() will be executed
859 * on idle cpus without having to signal or wake them up. The invltlb will be
860 * executed when they wake up, prior to any scheduling or interrupt thread.
862 * (*mask) is modified to remove the cpus we successfully negotiate this
863 * function with. This function may only be used with semi-synchronous
864 * commands (typically invltlb's or semi-synchronous invalidations which
865 * are usually associated only with kernel memory).
868 smp_smurf_idleinvlclr(cpumask_t *mask)
870 if (optimized_invltlb) {
871 ATOMIC_CPUMASK_ORMASK(smp_idleinvl_reqs, *mask);
872 /* cpu_lfence() not needed */
873 CPUMASK_NANDMASK(*mask, smp_idleinvl_mask);
878 * Issue cpu_invltlb() across all cpus except the current cpu.
880 * This function will arrange to avoid idle cpus, but still gurantee that
881 * invltlb is run on them when they wake up prior to any scheduling or
887 struct mdglobaldata *md = mdcpu;
889 unsigned long rflags;
891 uint64_t tsc_base = rdtsc();
895 if (report_invltlb_src > 0) {
896 if (--report_invltlb_src <= 0)
901 * Disallow normal interrupts, set all active cpus except our own
902 * in the global smp_invltlb_mask.
904 ++md->mi.gd_cnt.v_smpinvltlb;
905 crit_enter_gd(&md->mi);
908 * Bits we want to set in smp_invltlb_mask. We do not want to signal
909 * our own cpu. Also try to remove bits associated with idle cpus
910 * that we can flag for auto-invltlb.
912 mask = smp_active_mask;
913 CPUMASK_NANDBIT(mask, md->mi.gd_cpuid);
914 smp_smurf_idleinvlclr(&mask);
916 rflags = read_rflags();
918 ATOMIC_CPUMASK_ORMASK(smp_invltlb_mask, mask);
921 * IPI non-idle cpus represented by mask. The omask calculation
922 * removes cpus from the mask which already have a Xinvltlb IPI
923 * pending (avoid double-queueing the IPI).
925 * We must disable real interrupts when setting the smurf flags or
926 * we might race a XINVLTLB before we manage to send the ipi's for
929 * NOTE: We are not signalling ourselves, mask already does NOT
930 * include our own cpu.
932 smp_smurf_fetchset(&mask);
935 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
936 * the critical section count on the target cpus.
938 CPUMASK_ORMASK(mask, md->mi.gd_cpumask);
939 if (CPUMASK_CMPMASKEQ(smp_startup_mask, mask)) {
940 all_but_self_ipi(XINVLTLB_OFFSET);
942 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask);
943 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
947 * Wait for acknowledgement by all cpus. smp_inval_intr() will
948 * temporarily enable interrupts to avoid deadlocking the lapic,
949 * and will also handle running cpu_invltlb() and remote invlpg
950 * command son our cpu if some other cpu requests it of us.
952 * WARNING! I originally tried to implement this as a hard loop
953 * checking only smp_invltlb_mask (and issuing a local
954 * cpu_invltlb() if requested), with interrupts enabled
955 * and without calling smp_inval_intr(). This DID NOT WORK.
956 * It resulted in weird races where smurf bits would get
957 * cleared without any action being taken.
960 CPUMASK_ASSZERO(mask);
961 while (CPUMASK_CMPMASKNEQ(smp_invltlb_mask, mask)) {
965 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) {
966 kprintf("smp_invltlb %d: waited too long %08jx "
969 smp_invltlb_mask.ary[0],
970 smp_idleinvl_mask.ary[0],
971 smp_idleinvl_reqs.ary[0]);
972 mdcpu->gd_xinvaltlb = 0;
973 smp_invlpg(&smp_active_mask);
975 if (++repeats > 10) {
976 kprintf("smp_invltlb: giving up\n");
977 CPUMASK_ASSZERO(smp_invltlb_mask);
982 write_rflags(rflags);
983 crit_exit_gd(&md->mi);
987 * Called from a critical section with interrupts hard-disabled.
988 * This function issues an XINVLTLB IPI and then executes any pending
989 * command on the current cpu before returning.
992 smp_invlpg(cpumask_t *cmdmask)
994 struct mdglobaldata *md = mdcpu;
997 if (report_invlpg_src > 0) {
998 if (--report_invlpg_src <= 0)
1003 * Disallow normal interrupts, set all active cpus in the pmap,
1004 * plus our own for completion processing (it might or might not
1005 * be part of the set).
1007 mask = smp_active_mask;
1008 CPUMASK_ANDMASK(mask, *cmdmask);
1009 CPUMASK_ORMASK(mask, md->mi.gd_cpumask);
1012 * Avoid double-queuing IPIs, which can deadlock us. We must disable
1013 * real interrupts when setting the smurf flags or we might race a
1014 * XINVLTLB before we manage to send the ipi's for the bits we set.
1016 * NOTE: We might be including our own cpu in the smurf mask.
1018 smp_smurf_fetchset(&mask);
1021 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
1022 * the critical section count on the target cpus.
1024 * We do not include our own cpu when issuing the IPI.
1026 if (CPUMASK_CMPMASKEQ(smp_startup_mask, mask)) {
1027 all_but_self_ipi(XINVLTLB_OFFSET);
1029 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask);
1030 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1034 * This will synchronously wait for our command to complete,
1035 * as well as process commands from other cpus. It also handles
1038 * (interrupts are disabled and we are in a critical section here)
1046 globaldata_t gd = mycpu;
1049 all_but_self_ipi(XSNIFF_OFFSET);
1050 gd->gd_sample_pc = smp_sniff;
1051 gd->gd_sample_sp = &dummy;
1055 * Called from Xinvltlb assembly with interrupts hard-disabled and in a
1056 * critical section. gd_intr_nesting_level may or may not be bumped
1057 * depending on entry.
1059 * THIS CODE IS INTENDED TO EXPLICITLY IGNORE THE CRITICAL SECTION COUNT.
1060 * THAT IS, THE INTERRUPT IS INTENDED TO FUNCTION EVEN WHEN MAINLINE CODE
1061 * IS IN A CRITICAL SECTION.
1064 smp_inval_intr(void)
1066 struct mdglobaldata *md = mdcpu;
1069 uint64_t tsc_base = rdtsc();
1074 * The idle code is in a critical section, but that doesn't stop
1075 * Xinvltlb from executing, so deal with the race which can occur
1076 * in that situation. Otherwise r-m-w operations by pmap_inval_intr()
1077 * may have problems.
1079 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, md->mi.gd_cpuid)) {
1080 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, md->mi.gd_cpuid);
1087 * This is a real mess. I'd like to just leave interrupts disabled
1088 * but it can cause the lapic to deadlock if too many interrupts queue
1089 * to it, due to the idiotic design of the lapic. So instead we have
1090 * to enter a critical section so normal interrupts are made pending
1091 * and track whether this one was reentered.
1093 if (md->gd_xinvaltlb) { /* reentrant on cpu */
1094 md->gd_xinvaltlb = 2;
1097 md->gd_xinvaltlb = 1;
1100 * Check only those cpus with active Xinvl* commands pending.
1102 * We are going to enable interrupts so make sure we are in a
1103 * critical section. This is necessary to avoid deadlocking
1104 * the lapic and to ensure that we execute our commands prior to
1105 * any nominal interrupt or preemption.
1107 * WARNING! It is very important that we only clear out but in
1108 * smp_smurf_mask once for each interrupt we take. In
1109 * this case, we clear it on initial entry and only loop
1110 * on the reentrancy detect (caused by another interrupt).
1112 cpumask = smp_invmask;
1116 ATOMIC_CPUMASK_ORBIT(smp_in_mask, md->mi.gd_cpuid);
1118 ATOMIC_CPUMASK_NANDBIT(smp_smurf_mask, md->mi.gd_cpuid);
1121 * Specific page request(s), and we can't return until all bits
1128 * Also execute any pending full invalidation request in
1131 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) {
1132 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask,
1139 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) {
1140 kprintf("smp_inval_intr %d inv=%08jx tlbm=%08jx "
1141 "idle=%08jx/%08jx\n",
1144 smp_invltlb_mask.ary[0],
1145 smp_idleinvl_mask.ary[0],
1146 smp_idleinvl_reqs.ary[0]);
1157 * We can only add bits to the cpumask to test during the
1158 * loop because the smp_invmask bit is cleared once the
1159 * originator completes the command (the targets may still
1160 * be cycling their own completions in this loop, afterwords).
1162 * lfence required prior to all tests as this Xinvltlb
1163 * interrupt could race the originator (already be in progress
1164 * wnen the originator decides to issue, due to an issue by
1168 CPUMASK_ORMASK(cpumask, smp_invmask);
1169 /*cpumask = smp_active_mask;*/ /* XXX */
1171 if (pmap_inval_intr(&cpumask, toolong) == 0) {
1173 * Clear our smurf mask to allow new IPIs, but deal
1174 * with potential races.
1180 * Test if someone sent us another invalidation IPI, break
1181 * out so we can take it to avoid deadlocking the lapic
1182 * interrupt queue (? stupid intel, amd).
1184 if (md->gd_xinvaltlb == 2)
1187 if (CPUMASK_TESTBIT(smp_smurf_mask, md->mi.gd_cpuid))
1193 * Full invalidation request
1195 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) {
1196 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask,
1203 ATOMIC_CPUMASK_NANDBIT(smp_in_mask, md->mi.gd_cpuid);
1206 * Check to see if another Xinvltlb interrupt occurred and loop up
1210 if (md->gd_xinvaltlb == 2) {
1211 md->gd_xinvaltlb = 1;
1214 md->gd_xinvaltlb = 0;
1218 cpu_wbinvd_on_all_cpus_callback(void *arg)
1224 * When called the executing CPU will send an IPI to all other CPUs
1225 * requesting that they halt execution.
1227 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1229 * - Signals all CPUs in map to stop.
1230 * - Waits for each to stop.
1237 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1238 * from executing at same time.
1241 stop_cpus(cpumask_t map)
1245 CPUMASK_ANDMASK(map, smp_active_mask);
1247 /* send the Xcpustop IPI to all CPUs in map */
1248 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1251 mask = stopped_cpus;
1252 CPUMASK_ANDMASK(mask, map);
1254 } while (CPUMASK_CMPMASKNEQ(mask, map));
1261 * Called by a CPU to restart stopped CPUs.
1263 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1265 * - Signals all CPUs in map to restart.
1266 * - Waits for each to restart.
1274 restart_cpus(cpumask_t map)
1278 /* signal other cpus to restart */
1280 CPUMASK_ANDMASK(mask, smp_active_mask);
1282 started_cpus = mask;
1285 /* wait for each to clear its bit */
1286 while (CPUMASK_CMPMASKNEQ(stopped_cpus, map))
1293 * This is called once the mpboot code has gotten us properly relocated
1294 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1295 * and when it returns the scheduler will call the real cpu_idle() main
1296 * loop for the idlethread. Interrupts are disabled on entry and should
1297 * remain disabled at return.
1305 * Adjust smp_startup_mask to signal the BSP that we have started
1306 * up successfully. Note that we do not yet hold the BGL. The BSP
1307 * is waiting for our signal.
1309 * We can't set our bit in smp_active_mask yet because we are holding
1310 * interrupts physically disabled and remote cpus could deadlock
1311 * trying to send us an IPI.
1313 ATOMIC_CPUMASK_ORBIT(smp_startup_mask, mycpu->gd_cpuid);
1317 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1318 * non-zero, then get the MP lock.
1320 * Note: We are in a critical section.
1322 * Note: we are the idle thread, we can only spin.
1324 * Note: The load fence is memory volatile and prevents the compiler
1325 * from improperly caching mp_finish_lapic, and the cpu from improperly
1328 while (mp_finish_lapic == 0) {
1333 while (try_mplock() == 0) {
1339 if (cpu_feature & CPUID_TSC) {
1341 * The BSP is constantly updating tsc0_offset, figure out
1342 * the relative difference to synchronize ktrdump.
1344 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1347 /* BSP may have changed PTD while we're waiting for the lock */
1350 /* Build our map of 'other' CPUs. */
1351 mycpu->gd_other_cpus = smp_startup_mask;
1352 ATOMIC_CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
1354 /* A quick check from sanity claus */
1355 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1356 if (mycpu->gd_cpuid != cpu_id) {
1357 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1358 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1359 cpu_id, (lapic->id & 0xff000000) >> 24);
1361 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1363 panic("cpuid mismatch! boom!!");
1366 /* Initialize AP's local APIC for irq's */
1369 /* LAPIC initialization is done */
1370 ATOMIC_CPUMASK_ORBIT(smp_lapic_mask, mycpu->gd_cpuid);
1374 /* Let BSP move onto the next initialization stage */
1379 * Interlock for finalization. Wait until mp_finish is non-zero,
1380 * then get the MP lock.
1382 * Note: We are in a critical section.
1384 * Note: we are the idle thread, we can only spin.
1386 * Note: The load fence is memory volatile and prevents the compiler
1387 * from improperly caching mp_finish, and the cpu from improperly
1390 while (mp_finish == 0) {
1395 /* BSP may have changed PTD while we're waiting for the lock */
1398 /* Set memory range attributes for this CPU to match the BSP */
1399 mem_range_AP_init();
1402 * Once we go active we must process any IPIQ messages that may
1403 * have been queued, because no actual IPI will occur until we
1404 * set our bit in the smp_active_mask. If we don't the IPI
1405 * message interlock could be left set which would also prevent
1408 * The idle loop doesn't expect the BGL to be held and while
1409 * lwkt_switch() normally cleans things up this is a special case
1410 * because we returning almost directly into the idle loop.
1412 * The idle thread is never placed on the runq, make sure
1413 * nothing we've done put it there.
1417 * Hold a critical section and allow real interrupts to occur. Zero
1418 * any spurious interrupts which have accumulated, then set our
1419 * smp_active_mask indicating that we are fully operational.
1422 __asm __volatile("sti; pause; pause"::);
1423 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1424 ATOMIC_CPUMASK_ORBIT(smp_active_mask, mycpu->gd_cpuid);
1427 * Wait until all cpus have set their smp_active_mask and have fully
1428 * operational interrupts before proceeding.
1430 * We need a final cpu_invltlb() because we would not have received
1431 * any until we set our bit in smp_active_mask.
1433 while (mp_finish == 1) {
1440 * Initialize per-cpu clocks and do other per-cpu initialization.
1441 * At this point code is expected to be able to use the full kernel
1444 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1447 * Since we may have cleaned up the interrupt triggers, manually
1448 * process any pending IPIs before exiting our critical section.
1449 * Once the critical section has exited, normal interrupt processing
1452 atomic_swap_int(&mycpu->gd_npoll, 0);
1453 lwkt_process_ipiq();
1457 * Final final, allow the waiting BSP to resume the boot process,
1458 * return 'into' the idle thread bootstrap.
1460 ATOMIC_CPUMASK_ORBIT(smp_finalize_mask, mycpu->gd_cpuid);
1461 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1465 * Get SMP fully working before we start initializing devices.
1472 kprintf("Finish MP startup\n");
1476 * Wait for the active mask to complete, after which all cpus will
1477 * be accepting interrupts.
1480 while (CPUMASK_CMPMASKNEQ(smp_active_mask, smp_startup_mask)) {
1486 * Wait for the finalization mask to complete, after which all cpus
1487 * have completely finished initializing and are entering or are in
1488 * their idle thread.
1490 * BSP should have received all required invltlbs but do another
1495 while (CPUMASK_CMPMASKNEQ(smp_finalize_mask, smp_startup_mask)) {
1500 while (try_mplock() == 0) {
1506 kprintf("Active CPU Mask: %016jx\n",
1507 (uintmax_t)CPUMASK_LOWMASK(smp_active_mask));
1511 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL);
1514 cpu_send_ipiq(int dcpu)
1516 if (CPUMASK_TESTBIT(smp_active_mask, dcpu))
1517 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1520 #if 0 /* single_apic_ipi_passive() not working yet */
1522 * Returns 0 on failure, 1 on success
1525 cpu_send_ipiq_passive(int dcpu)
1528 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) {
1529 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1530 APIC_DELMODE_FIXED);
1537 mp_bsp_simple_setup(void)
1539 struct mdglobaldata *gd;
1542 /* build our map of 'other' CPUs */
1543 mycpu->gd_other_cpus = smp_startup_mask;
1544 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
1546 gd = (struct mdglobaldata *)mycpu;
1547 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid);
1549 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
1550 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size);
1551 bzero(mycpu->gd_ipiq, ipiq_size);
1555 if (cpu_feature & CPUID_TSC)
1556 tsc0_offset = rdtsc();
1561 * CPU TOPOLOGY DETECTION FUNCTIONS
1564 /* Detect intel topology using CPUID
1565 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41
1568 detect_intel_topology(int count_htt_cores)
1572 int core_plus_logical_bits = 0;
1573 int cores_per_package;
1574 int logical_per_package;
1575 int logical_per_core;
1578 if (cpu_high >= 0xb) {
1581 } else if (cpu_high >= 0x4) {
1586 for (shift = 0; (1 << shift) < count_htt_cores; ++shift)
1588 logical_CPU_bits = 1 << shift;
1593 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p);
1595 /* if 0xb not supported - fallback to 0x4 */
1596 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) {
1600 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]);
1602 ecx_index = FUNC_B_THREAD_LEVEL + 1;
1604 cpuid_count(0xb, ecx_index, p);
1606 /* Check for the Core type in the implemented sub leaves. */
1607 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) {
1608 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]);
1614 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE);
1616 core_bits = core_plus_logical_bits - logical_CPU_bits;
1621 cpuid_count(0x4, 0, p);
1622 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1;
1624 logical_per_package = count_htt_cores;
1625 logical_per_core = logical_per_package / cores_per_package;
1627 for (shift = 0; (1 << shift) < logical_per_core; ++shift)
1629 logical_CPU_bits = shift;
1631 for (shift = 0; (1 << shift) < cores_per_package; ++shift)
1638 /* Detect AMD topology using CPUID
1639 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page
1642 detect_amd_topology(int count_htt_cores)
1645 if ((cpu_feature & CPUID_HTT)
1646 && (amd_feature2 & AMDID2_CMP)) {
1648 if (cpu_procinfo2 & AMDID_COREID_SIZE) {
1649 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE)
1650 >> AMDID_COREID_SIZE_SHIFT;
1652 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
1653 for (shift = 0; (1 << shift) < core_bits; ++shift)
1658 logical_CPU_bits = count_htt_cores >> core_bits;
1659 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift)
1661 logical_CPU_bits = shift;
1663 for (shift = 0; (1 << shift) < count_htt_cores; ++shift)
1666 logical_CPU_bits = 0;
1671 amd_get_compute_unit_id(void *arg)
1675 do_cpuid(0x8000001e, regs);
1676 cpu_node_t * mynode = get_cpu_node_by_cpuid(mycpuid);
1678 * AMD - CPUID Specification September 2010
1679 * page 34 - //ComputeUnitID = ebx[0:7]//
1681 mynode->compute_unit_id = regs[1] & 0xff;
1685 fix_amd_topology(void)
1689 if (cpu_vendor_id != CPU_VENDOR_AMD)
1691 if ((amd_feature2 & AMDID2_TOPOEXT) == 0)
1694 CPUMASK_ASSALLONES(mask);
1695 lwkt_cpusync_simple(mask, amd_get_compute_unit_id, NULL);
1697 kprintf("Compute unit iDS:\n");
1699 for (i = 0; i < ncpus; i++) {
1700 kprintf("%d-%d; \n",
1701 i, get_cpu_node_by_cpuid(i)->compute_unit_id);
1708 * - logical_CPU_bits
1710 * With the values above (for AMD or INTEL) we are able to generally
1711 * detect the CPU topology (number of cores for each level):
1712 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1713 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf
1716 detect_cpu_topology(void)
1718 static int topology_detected = 0;
1721 if (topology_detected)
1723 if ((cpu_feature & CPUID_HTT) == 0) {
1725 logical_CPU_bits = 0;
1728 count = (cpu_procinfo & CPUID_HTT_CORES) >> CPUID_HTT_CORE_SHIFT;
1730 if (cpu_vendor_id == CPU_VENDOR_INTEL)
1731 detect_intel_topology(count);
1732 else if (cpu_vendor_id == CPU_VENDOR_AMD)
1733 detect_amd_topology(count);
1734 topology_detected = 1;
1738 kprintf("Bits within APICID: logical_CPU_bits: %d; core_bits: %d\n",
1739 logical_CPU_bits, core_bits);
1742 /* Interface functions to calculate chip_ID,
1743 * core_number and logical_number
1744 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1747 get_chip_ID(int cpuid)
1749 return get_apicid_from_cpuid(cpuid) >>
1750 (logical_CPU_bits + core_bits);
1754 get_core_number_within_chip(int cpuid)
1756 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) &
1757 ( (1 << core_bits) -1);
1761 get_logical_CPU_number_within_core(int cpuid)
1763 return get_apicid_from_cpuid(cpuid) &
1764 ( (1 << logical_CPU_bits) -1);